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sdhci: add SDHCI_QUIRK_BROKEN_DMA quirk
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
14d836e7 4 * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
d129bceb
PO		 10 */
11
d129bceb
PO		 12#include <linux/delay.h>
13#include <linux/highmem.h>
14#include <linux/pci.h>
15#include <linux/dma-mapping.h>
16
17#include <linux/mmc/host.h>
d129bceb
PO		 18
19#include <asm/scatterlist.h>
20
21#include "sdhci.h"
22
23#define DRIVER_NAME "sdhci"
d129bceb 24
d129bceb 25#define DBG(f, x...) \
c6563178 26 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 27
67435274
PO		 28static unsigned int debug_nodma = 0;
29static unsigned int debug_forcedma = 0;
df673b22 30static unsigned int debug_quirks = 0;
67435274 31
645289dc 32#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
98608076 33#define SDHCI_QUIRK_FORCE_DMA (1<<1)
8a4da143
PO		 34/* Controller doesn't like some resets when there is no card inserted. */
35#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
9e9dc5f2 36#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
b8352260 37#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
7c168e3d 38#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
645289dc 39
d129bceb 40static const struct pci_device_id pci_ids[] __devinitdata = {
645289dc
PO		 41 {
42 .vendor = PCI_VENDOR_ID_RICOH,
43 .device = PCI_DEVICE_ID_RICOH_R5C822,
44 .subvendor = PCI_VENDOR_ID_IBM,
45 .subdevice = PCI_ANY_ID,
98608076
PO		 46 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
47 SDHCI_QUIRK_FORCE_DMA,
48 },
49
50 {
51 .vendor = PCI_VENDOR_ID_RICOH,
52 .device = PCI_DEVICE_ID_RICOH_R5C822,
53 .subvendor = PCI_ANY_ID,
54 .subdevice = PCI_ANY_ID,
8a4da143
PO		 55 .driver_data = SDHCI_QUIRK_FORCE_DMA |
56 SDHCI_QUIRK_NO_CARD_NO_RESET,
98608076
PO		 57 },
58
59 {
60 .vendor = PCI_VENDOR_ID_TI,
61 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
62 .subvendor = PCI_ANY_ID,
63 .subdevice = PCI_ANY_ID,
64 .driver_data = SDHCI_QUIRK_FORCE_DMA,
645289dc
PO		 65 },
66
9e9dc5f2
DS		 67 {
68 .vendor = PCI_VENDOR_ID_ENE,
69 .device = PCI_DEVICE_ID_ENE_CB712_SD,
70 .subvendor = PCI_ANY_ID,
71 .subdevice = PCI_ANY_ID,
7c168e3d
FT		 72 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
73 SDHCI_QUIRK_BROKEN_DMA,
9e9dc5f2
DS		 74 },
75
7de064eb
MK		 76 {
77 .vendor = PCI_VENDOR_ID_ENE,
78 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
79 .subvendor = PCI_ANY_ID,
80 .subdevice = PCI_ANY_ID,
7c168e3d
FT		 81 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
82 SDHCI_QUIRK_BROKEN_DMA,
7de064eb
MK		 83 },
84
b8352260
LD		 85 {
86 .vendor = PCI_VENDOR_ID_ENE,
87 .device = PCI_DEVICE_ID_ENE_CB714_SD,
88 .subvendor = PCI_ANY_ID,
89 .subdevice = PCI_ANY_ID,
90 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
91 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
92 },
93
94 {
95 .vendor = PCI_VENDOR_ID_ENE,
96 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
97 .subvendor = PCI_ANY_ID,
98 .subdevice = PCI_ANY_ID,
99 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
100 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
101 },
102
645289dc
PO		 103 { /* Generic SD host controller */
104 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
105 },
106
d129bceb
PO		 107 { /* end: all zeroes */ },
108};
109
110MODULE_DEVICE_TABLE(pci, pci_ids);
111
112static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
113static void sdhci_finish_data(struct sdhci_host *);
114
115static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
116static void sdhci_finish_command(struct sdhci_host *);
117
118static void sdhci_dumpregs(struct sdhci_host *host)
119{
120 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
121
122 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
123 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
124 readw(host->ioaddr + SDHCI_HOST_VERSION));
125 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
126 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
127 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
128 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
129 readl(host->ioaddr + SDHCI_ARGUMENT),
130 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
131 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
132 readl(host->ioaddr + SDHCI_PRESENT_STATE),
133 readb(host->ioaddr + SDHCI_HOST_CONTROL));
134 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
135 readb(host->ioaddr + SDHCI_POWER_CONTROL),
136 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
137 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
2df3b71b 138 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
d129bceb
PO		 139 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
140 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
141 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
142 readl(host->ioaddr + SDHCI_INT_STATUS));
143 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
144 readl(host->ioaddr + SDHCI_INT_ENABLE),
145 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
146 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
147 readw(host->ioaddr + SDHCI_ACMD12_ERR),
148 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
149 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
150 readl(host->ioaddr + SDHCI_CAPABILITIES),
151 readl(host->ioaddr + SDHCI_MAX_CURRENT));
152
153 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
154}
155
156/*****************************************************************************\
157 * *
158 * Low level functions *
159 * *
160\*****************************************************************************/
161
162static void sdhci_reset(struct sdhci_host *host, u8 mask)
163{
e16514d8
PO		 164 unsigned long timeout;
165
8a4da143
PO		 166 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
167 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
168 SDHCI_CARD_PRESENT))
169 return;
170 }
171
d129bceb
PO		 172 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
173
e16514d8 174 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 175 host->clock = 0;
176
e16514d8
PO		 177 /* Wait max 100 ms */
178 timeout = 100;
179
180 /* hw clears the bit when it's done */
181 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
182 if (timeout == 0) {
acf1da45 183 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 184 mmc_hostname(host->mmc), (int)mask);
185 sdhci_dumpregs(host);
186 return;
187 }
188 timeout--;
189 mdelay(1);
d129bceb
PO		 190 }
191}
192
193static void sdhci_init(struct sdhci_host *host)
194{
195 u32 intmask;
196
197 sdhci_reset(host, SDHCI_RESET_ALL);
198
3192a28f
PO		 199 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
200 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
201 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
202 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
a406f5a3 203 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
3192a28f 204 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
d129bceb
PO		 205
206 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
207 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 208}
209
210static void sdhci_activate_led(struct sdhci_host *host)
211{
212 u8 ctrl;
213
214 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
215 ctrl |= SDHCI_CTRL_LED;
216 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
217}
218
219static void sdhci_deactivate_led(struct sdhci_host *host)
220{
221 u8 ctrl;
222
223 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
224 ctrl &= ~SDHCI_CTRL_LED;
225 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
226}
227
228/*****************************************************************************\
229 * *
230 * Core functions *
231 * *
232\*****************************************************************************/
233
2a22b14e 234static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
d129bceb 235{
2a22b14e 236 return page_address(host->cur_sg->page) + host->cur_sg->offset;
d129bceb
PO		 237}
238
239static inline int sdhci_next_sg(struct sdhci_host* host)
240{
241 /*
242 * Skip to next SG entry.
243 */
244 host->cur_sg++;
245 host->num_sg--;
246
247 /*
248 * Any entries left?
249 */
250 if (host->num_sg > 0) {
251 host->offset = 0;
252 host->remain = host->cur_sg->length;
253 }
254
255 return host->num_sg;
256}
257
a406f5a3 258static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 259{
a406f5a3
PO		 260 int blksize, chunk_remain;
261 u32 data;
d129bceb 262 char *buffer;
a406f5a3 263 int size;
d129bceb 264
a406f5a3 265 DBG("PIO reading\n");
d129bceb 266
a406f5a3
PO		 267 blksize = host->data->blksz;
268 chunk_remain = 0;
269 data = 0;
d129bceb 270
2a22b14e 271 buffer = sdhci_sg_to_buffer(host) + host->offset;
d129bceb 272
a406f5a3
PO		 273 while (blksize) {
274 if (chunk_remain == 0) {
275 data = readl(host->ioaddr + SDHCI_BUFFER);
276 chunk_remain = min(blksize, 4);
277 }
d129bceb 278
14d836e7 279 size = min(host->remain, chunk_remain);
d129bceb 280
a406f5a3
PO		 281 chunk_remain -= size;
282 blksize -= size;
283 host->offset += size;
284 host->remain -= size;
14d836e7 285
a406f5a3
PO		 286 while (size) {
287 *buffer = data & 0xFF;
288 buffer++;
289 data >>= 8;
290 size--;
291 }
d129bceb 292
a406f5a3 293 if (host->remain == 0) {
a406f5a3
PO		 294 if (sdhci_next_sg(host) == 0) {
295 BUG_ON(blksize != 0);
296 return;
297 }
2a22b14e 298 buffer = sdhci_sg_to_buffer(host);
d129bceb 299 }
a406f5a3 300 }
a406f5a3 301}
d129bceb 302
a406f5a3
PO		 303static void sdhci_write_block_pio(struct sdhci_host *host)
304{
305 int blksize, chunk_remain;
306 u32 data;
307 char *buffer;
308 int bytes, size;
d129bceb 309
a406f5a3
PO		 310 DBG("PIO writing\n");
311
312 blksize = host->data->blksz;
313 chunk_remain = 4;
314 data = 0;
d129bceb 315
a406f5a3 316 bytes = 0;
2a22b14e 317 buffer = sdhci_sg_to_buffer(host) + host->offset;
d129bceb 318
a406f5a3 319 while (blksize) {
14d836e7 320 size = min(host->remain, chunk_remain);
a406f5a3
PO		 321
322 chunk_remain -= size;
323 blksize -= size;
d129bceb
PO		 324 host->offset += size;
325 host->remain -= size;
14d836e7 326
a406f5a3
PO		 327 while (size) {
328 data >>= 8;
329 data |= (u32)*buffer << 24;
330 buffer++;
331 size--;
332 }
333
334 if (chunk_remain == 0) {
335 writel(data, host->ioaddr + SDHCI_BUFFER);
336 chunk_remain = min(blksize, 4);
337 }
d129bceb
PO		 338
339 if (host->remain == 0) {
d129bceb 340 if (sdhci_next_sg(host) == 0) {
a406f5a3 341 BUG_ON(blksize != 0);
d129bceb
PO		 342 return;
343 }
2a22b14e 344 buffer = sdhci_sg_to_buffer(host);
d129bceb
PO		 345 }
346 }
a406f5a3
PO		 347}
348
349static void sdhci_transfer_pio(struct sdhci_host *host)
350{
351 u32 mask;
352
353 BUG_ON(!host->data);
354
14d836e7 355 if (host->num_sg == 0)
a406f5a3
PO		 356 return;
357
358 if (host->data->flags & MMC_DATA_READ)
359 mask = SDHCI_DATA_AVAILABLE;
360 else
361 mask = SDHCI_SPACE_AVAILABLE;
362
363 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
364 if (host->data->flags & MMC_DATA_READ)
365 sdhci_read_block_pio(host);
366 else
367 sdhci_write_block_pio(host);
d129bceb 368
14d836e7 369 if (host->num_sg == 0)
a406f5a3 370 break;
a406f5a3 371 }
d129bceb 372
a406f5a3 373 DBG("PIO transfer complete.\n");
d129bceb
PO		 374}
375
376static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
377{
1c8cde92
PO		 378 u8 count;
379 unsigned target_timeout, current_timeout;
d129bceb
PO		 380
381 WARN_ON(host->data);
382
c7fa9963 383 if (data == NULL)
d129bceb 384 return;
d129bceb 385
bab76961
PO		 386 /* Sanity checks */
387 BUG_ON(data->blksz * data->blocks > 524288);
fe4a3c7a 388 BUG_ON(data->blksz > host->mmc->max_blk_size);
1d676e02 389 BUG_ON(data->blocks > 65535);
d129bceb 390
e538fbe8
PO		 391 host->data = data;
392 host->data_early = 0;
393
1c8cde92
PO		 394 /* timeout in us */
395 target_timeout = data->timeout_ns / 1000 +
396 data->timeout_clks / host->clock;
d129bceb 397
1c8cde92
PO		 398 /*
399 * Figure out needed cycles.
400 * We do this in steps in order to fit inside a 32 bit int.
401 * The first step is the minimum timeout, which will have a
402 * minimum resolution of 6 bits:
403 * (1) 2^13*1000 > 2^22,
404 * (2) host->timeout_clk < 2^16
405 * =>
406 * (1) / (2) > 2^6
407 */
408 count = 0;
409 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
410 while (current_timeout < target_timeout) {
411 count++;
412 current_timeout <<= 1;
413 if (count >= 0xF)
414 break;
415 }
416
417 if (count >= 0xF) {
418 printk(KERN_WARNING "%s: Too large timeout requested!\n",
419 mmc_hostname(host->mmc));
420 count = 0xE;
421 }
422
423 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
d129bceb
PO		 424
425 if (host->flags & SDHCI_USE_DMA) {
426 int count;
427
428 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
429 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
430 BUG_ON(count != 1);
431
432 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
433 } else {
d129bceb
PO		 434 host->cur_sg = data->sg;
435 host->num_sg = data->sg_len;
436
437 host->offset = 0;
438 host->remain = host->cur_sg->length;
439 }
c7fa9963 440
bab76961
PO		 441 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
442 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
443 host->ioaddr + SDHCI_BLOCK_SIZE);
c7fa9963
PO		 444 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
445}
446
447static void sdhci_set_transfer_mode(struct sdhci_host *host,
448 struct mmc_data *data)
449{
450 u16 mode;
451
c7fa9963
PO		 452 if (data == NULL)
453 return;
454
e538fbe8
PO		 455 WARN_ON(!host->data);
456
c7fa9963
PO		 457 mode = SDHCI_TRNS_BLK_CNT_EN;
458 if (data->blocks > 1)
459 mode |= SDHCI_TRNS_MULTI;
460 if (data->flags & MMC_DATA_READ)
461 mode |= SDHCI_TRNS_READ;
462 if (host->flags & SDHCI_USE_DMA)
463 mode |= SDHCI_TRNS_DMA;
464
465 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
d129bceb
PO		 466}
467
468static void sdhci_finish_data(struct sdhci_host *host)
469{
470 struct mmc_data *data;
d129bceb
PO		 471 u16 blocks;
472
473 BUG_ON(!host->data);
474
475 data = host->data;
476 host->data = NULL;
477
478 if (host->flags & SDHCI_USE_DMA) {
479 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
480 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
d129bceb
PO		 481 }
482
483 /*
484 * Controller doesn't count down when in single block mode.
485 */
2b061973 486 if (data->blocks == 1)
17b0429d 487 blocks = (data->error == 0) ? 0 : 1;
d129bceb
PO		 488 else
489 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
a3fd4a1b 490 data->bytes_xfered = data->blksz * (data->blocks - blocks);
d129bceb 491
17b0429d 492 if (!data->error && blocks) {
d129bceb 493 printk(KERN_ERR "%s: Controller signalled completion even "
acf1da45
PO		 494 "though there were blocks left.\n",
495 mmc_hostname(host->mmc));
17b0429d 496 data->error = -EIO;
d129bceb
PO		 497 }
498
d129bceb
PO		 499 if (data->stop) {
500 /*
501 * The controller needs a reset of internal state machines
502 * upon error conditions.
503 */
17b0429d 504 if (data->error) {
d129bceb
PO		 505 sdhci_reset(host, SDHCI_RESET_CMD);
506 sdhci_reset(host, SDHCI_RESET_DATA);
507 }
508
509 sdhci_send_command(host, data->stop);
510 } else
511 tasklet_schedule(&host->finish_tasklet);
512}
513
514static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
515{
516 int flags;
fd2208d7 517 u32 mask;
7cb2c76f 518 unsigned long timeout;
d129bceb
PO		 519
520 WARN_ON(host->cmd);
521
d129bceb 522 /* Wait max 10 ms */
7cb2c76f 523 timeout = 10;
fd2208d7
PO		 524
525 mask = SDHCI_CMD_INHIBIT;
526 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
527 mask |= SDHCI_DATA_INHIBIT;
528
529 /* We shouldn't wait for data inihibit for stop commands, even
530 though they might use busy signaling */
531 if (host->mrq->data && (cmd == host->mrq->data->stop))
532 mask &= ~SDHCI_DATA_INHIBIT;
533
534 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 535 if (timeout == 0) {
d129bceb 536 printk(KERN_ERR "%s: Controller never released "
acf1da45 537 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 538 sdhci_dumpregs(host);
17b0429d 539 cmd->error = -EIO;
d129bceb
PO		 540 tasklet_schedule(&host->finish_tasklet);
541 return;
542 }
7cb2c76f
PO		 543 timeout--;
544 mdelay(1);
545 }
d129bceb
PO		 546
547 mod_timer(&host->timer, jiffies + 10 * HZ);
548
549 host->cmd = cmd;
550
551 sdhci_prepare_data(host, cmd->data);
552
553 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
554
c7fa9963
PO		 555 sdhci_set_transfer_mode(host, cmd->data);
556
d129bceb 557 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 558 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb 559 mmc_hostname(host->mmc));
17b0429d 560 cmd->error = -EINVAL;
d129bceb
PO		 561 tasklet_schedule(&host->finish_tasklet);
562 return;
563 }
564
565 if (!(cmd->flags & MMC_RSP_PRESENT))
566 flags = SDHCI_CMD_RESP_NONE;
567 else if (cmd->flags & MMC_RSP_136)
568 flags = SDHCI_CMD_RESP_LONG;
569 else if (cmd->flags & MMC_RSP_BUSY)
570 flags = SDHCI_CMD_RESP_SHORT_BUSY;
571 else
572 flags = SDHCI_CMD_RESP_SHORT;
573
574 if (cmd->flags & MMC_RSP_CRC)
575 flags |= SDHCI_CMD_CRC;
576 if (cmd->flags & MMC_RSP_OPCODE)
577 flags |= SDHCI_CMD_INDEX;
578 if (cmd->data)
579 flags |= SDHCI_CMD_DATA;
580
fb61e289 581 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
d129bceb
PO		 582 host->ioaddr + SDHCI_COMMAND);
583}
584
585static void sdhci_finish_command(struct sdhci_host *host)
586{
587 int i;
588
589 BUG_ON(host->cmd == NULL);
590
591 if (host->cmd->flags & MMC_RSP_PRESENT) {
592 if (host->cmd->flags & MMC_RSP_136) {
593 /* CRC is stripped so we need to do some shifting. */
594 for (i = 0;i < 4;i++) {
595 host->cmd->resp[i] = readl(host->ioaddr +
596 SDHCI_RESPONSE + (3-i)*4) << 8;
597 if (i != 3)
598 host->cmd->resp[i] |=
599 readb(host->ioaddr +
600 SDHCI_RESPONSE + (3-i)*4-1);
601 }
602 } else {
603 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
604 }
605 }
606
17b0429d 607 host->cmd->error = 0;
d129bceb 608
e538fbe8
PO		 609 if (host->data && host->data_early)
610 sdhci_finish_data(host);
611
612 if (!host->cmd->data)
d129bceb
PO		 613 tasklet_schedule(&host->finish_tasklet);
614
615 host->cmd = NULL;
616}
617
618static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
619{
620 int div;
621 u16 clk;
7cb2c76f 622 unsigned long timeout;
d129bceb
PO		 623
624 if (clock == host->clock)
625 return;
626
627 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
628
629 if (clock == 0)
630 goto out;
631
632 for (div = 1;div < 256;div *= 2) {
633 if ((host->max_clk / div) <= clock)
634 break;
635 }
636 div >>= 1;
637
638 clk = div << SDHCI_DIVIDER_SHIFT;
639 clk |= SDHCI_CLOCK_INT_EN;
640 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
641
642 /* Wait max 10 ms */
7cb2c76f
PO		 643 timeout = 10;
644 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
645 & SDHCI_CLOCK_INT_STABLE)) {
646 if (timeout == 0) {
acf1da45
PO		 647 printk(KERN_ERR "%s: Internal clock never "
648 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 649 sdhci_dumpregs(host);
650 return;
651 }
7cb2c76f
PO		 652 timeout--;
653 mdelay(1);
654 }
d129bceb
PO		 655
656 clk |= SDHCI_CLOCK_CARD_EN;
657 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
658
659out:
660 host->clock = clock;
661}
662
146ad66e
PO		 663static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
664{
665 u8 pwr;
666
667 if (host->power == power)
668 return;
669
9e9dc5f2
DS		 670 if (power == (unsigned short)-1) {
671 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
146ad66e 672 goto out;
9e9dc5f2
DS		 673 }
674
675 /*
676 * Spec says that we should clear the power reg before setting
677 * a new value. Some controllers don't seem to like this though.
678 */
679 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
680 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
146ad66e
PO		 681
682 pwr = SDHCI_POWER_ON;
683
4be34c99 684 switch (1 << power) {
55556da0 685 case MMC_VDD_165_195:
146ad66e
PO		 686 pwr |= SDHCI_POWER_180;
687 break;
4be34c99
PL		 688 case MMC_VDD_29_30:
689 case MMC_VDD_30_31:
146ad66e
PO		 690 pwr |= SDHCI_POWER_300;
691 break;
4be34c99
PL		 692 case MMC_VDD_32_33:
693 case MMC_VDD_33_34:
146ad66e
PO		 694 pwr |= SDHCI_POWER_330;
695 break;
696 default:
697 BUG();
698 }
699
700 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
701
702out:
703 host->power = power;
704}
705
d129bceb
PO		 706/*****************************************************************************\
707 * *
708 * MMC callbacks *
709 * *
710\*****************************************************************************/
711
712static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
713{
714 struct sdhci_host *host;
715 unsigned long flags;
716
717 host = mmc_priv(mmc);
718
719 spin_lock_irqsave(&host->lock, flags);
720
721 WARN_ON(host->mrq != NULL);
722
723 sdhci_activate_led(host);
724
725 host->mrq = mrq;
726
727 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
17b0429d 728 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 729 tasklet_schedule(&host->finish_tasklet);
730 } else
731 sdhci_send_command(host, mrq->cmd);
732
5f25a66f 733 mmiowb();
d129bceb
PO		 734 spin_unlock_irqrestore(&host->lock, flags);
735}
736
737static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
738{
739 struct sdhci_host *host;
740 unsigned long flags;
741 u8 ctrl;
742
743 host = mmc_priv(mmc);
744
745 spin_lock_irqsave(&host->lock, flags);
746
d129bceb
PO		 747 /*
748 * Reset the chip on each power off.
749 * Should clear out any weird states.
750 */
751 if (ios->power_mode == MMC_POWER_OFF) {
752 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb 753 sdhci_init(host);
d129bceb
PO		 754 }
755
756 sdhci_set_clock(host, ios->clock);
757
758 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 759 sdhci_set_power(host, -1);
d129bceb 760 else
146ad66e 761 sdhci_set_power(host, ios->vdd);
d129bceb
PO		 762
763 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
cd9277c0 764
d129bceb
PO		 765 if (ios->bus_width == MMC_BUS_WIDTH_4)
766 ctrl |= SDHCI_CTRL_4BITBUS;
767 else
768 ctrl &= ~SDHCI_CTRL_4BITBUS;
cd9277c0
PO		 769
770 if (ios->timing == MMC_TIMING_SD_HS)
771 ctrl |= SDHCI_CTRL_HISPD;
772 else
773 ctrl &= ~SDHCI_CTRL_HISPD;
774
d129bceb
PO		 775 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
776
b8352260
LD		 777 /*
778 * Some (ENE) controllers go apeshit on some ios operation,
779 * signalling timeout and CRC errors even on CMD0. Resetting
780 * it on each ios seems to solve the problem.
781 */
782 if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
783 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
784
5f25a66f 785 mmiowb();
d129bceb
PO		 786 spin_unlock_irqrestore(&host->lock, flags);
787}
788
789static int sdhci_get_ro(struct mmc_host *mmc)
790{
791 struct sdhci_host *host;
792 unsigned long flags;
793 int present;
794
795 host = mmc_priv(mmc);
796
797 spin_lock_irqsave(&host->lock, flags);
798
799 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
800
801 spin_unlock_irqrestore(&host->lock, flags);
802
803 return !(present & SDHCI_WRITE_PROTECT);
804}
805
f75979b7
PO		 806static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
807{
808 struct sdhci_host *host;
809 unsigned long flags;
810 u32 ier;
811
812 host = mmc_priv(mmc);
813
814 spin_lock_irqsave(&host->lock, flags);
815
816 ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
817
818 ier &= ~SDHCI_INT_CARD_INT;
819 if (enable)
820 ier |= SDHCI_INT_CARD_INT;
821
822 writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
823 writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
824
825 mmiowb();
826
827 spin_unlock_irqrestore(&host->lock, flags);
828}
829
ab7aefd0 830static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 831 .request = sdhci_request,
832 .set_ios = sdhci_set_ios,
833 .get_ro = sdhci_get_ro,
f75979b7 834 .enable_sdio_irq = sdhci_enable_sdio_irq,
d129bceb
PO		 835};
836
837/*****************************************************************************\
838 * *
839 * Tasklets *
840 * *
841\*****************************************************************************/
842
843static void sdhci_tasklet_card(unsigned long param)
844{
845 struct sdhci_host *host;
846 unsigned long flags;
847
848 host = (struct sdhci_host*)param;
849
850 spin_lock_irqsave(&host->lock, flags);
851
852 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
853 if (host->mrq) {
854 printk(KERN_ERR "%s: Card removed during transfer!\n",
855 mmc_hostname(host->mmc));
856 printk(KERN_ERR "%s: Resetting controller.\n",
857 mmc_hostname(host->mmc));
858
859 sdhci_reset(host, SDHCI_RESET_CMD);
860 sdhci_reset(host, SDHCI_RESET_DATA);
861
17b0429d 862 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 863 tasklet_schedule(&host->finish_tasklet);
864 }
865 }
866
867 spin_unlock_irqrestore(&host->lock, flags);
868
869 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
870}
871
872static void sdhci_tasklet_finish(unsigned long param)
873{
874 struct sdhci_host *host;
875 unsigned long flags;
876 struct mmc_request *mrq;
877
878 host = (struct sdhci_host*)param;
879
880 spin_lock_irqsave(&host->lock, flags);
881
882 del_timer(&host->timer);
883
884 mrq = host->mrq;
885
d129bceb
PO		 886 /*
887 * The controller needs a reset of internal state machines
888 * upon error conditions.
889 */
17b0429d
PO		 890 if (mrq->cmd->error ||
891 (mrq->data && (mrq->data->error ||
892 (mrq->data->stop && mrq->data->stop->error)))) {
645289dc
PO		 893
894 /* Some controllers need this kick or reset won't work here */
895 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
896 unsigned int clock;
897
898 /* This is to force an update */
899 clock = host->clock;
900 host->clock = 0;
901 sdhci_set_clock(host, clock);
902 }
903
904 /* Spec says we should do both at the same time, but Ricoh
905 controllers do not like that. */
d129bceb
PO		 906 sdhci_reset(host, SDHCI_RESET_CMD);
907 sdhci_reset(host, SDHCI_RESET_DATA);
908 }
909
910 host->mrq = NULL;
911 host->cmd = NULL;
912 host->data = NULL;
913
914 sdhci_deactivate_led(host);
915
5f25a66f 916 mmiowb();
d129bceb
PO		 917 spin_unlock_irqrestore(&host->lock, flags);
918
919 mmc_request_done(host->mmc, mrq);
920}
921
922static void sdhci_timeout_timer(unsigned long data)
923{
924 struct sdhci_host *host;
925 unsigned long flags;
926
927 host = (struct sdhci_host*)data;
928
929 spin_lock_irqsave(&host->lock, flags);
930
931 if (host->mrq) {
acf1da45
PO		 932 printk(KERN_ERR "%s: Timeout waiting for hardware "
933 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 934 sdhci_dumpregs(host);
935
936 if (host->data) {
17b0429d 937 host->data->error = -ETIMEDOUT;
d129bceb
PO		 938 sdhci_finish_data(host);
939 } else {
940 if (host->cmd)
17b0429d 941 host->cmd->error = -ETIMEDOUT;
d129bceb 942 else
17b0429d 943 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 944
945 tasklet_schedule(&host->finish_tasklet);
946 }
947 }
948
5f25a66f 949 mmiowb();
d129bceb
PO		 950 spin_unlock_irqrestore(&host->lock, flags);
951}
952
953/*****************************************************************************\
954 * *
955 * Interrupt handling *
956 * *
957\*****************************************************************************/
958
959static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
960{
961 BUG_ON(intmask == 0);
962
963 if (!host->cmd) {
b67ac3f3
PO		 964 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
965 "though no command operation was in progress.\n",
966 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 967 sdhci_dumpregs(host);
968 return;
969 }
970
43b58b36 971 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 972 host->cmd->error = -ETIMEDOUT;
973 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
974 SDHCI_INT_INDEX))
975 host->cmd->error = -EILSEQ;
43b58b36 976
17b0429d 977 if (host->cmd->error)
d129bceb 978 tasklet_schedule(&host->finish_tasklet);
43b58b36
PO		 979 else if (intmask & SDHCI_INT_RESPONSE)
980 sdhci_finish_command(host);
d129bceb
PO		 981}
982
983static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
984{
985 BUG_ON(intmask == 0);
986
987 if (!host->data) {
988 /*
989 * A data end interrupt is sent together with the response
990 * for the stop command.
991 */
992 if (intmask & SDHCI_INT_DATA_END)
993 return;
994
b67ac3f3
PO		 995 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
996 "though no data operation was in progress.\n",
997 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 998 sdhci_dumpregs(host);
999
1000 return;
1001 }
1002
1003 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d
PO		 1004 host->data->error = -ETIMEDOUT;
1005 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1006 host->data->error = -EILSEQ;
d129bceb 1007
17b0429d 1008 if (host->data->error)
d129bceb
PO		 1009 sdhci_finish_data(host);
1010 else {
a406f5a3 1011 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 1012 sdhci_transfer_pio(host);
1013
6ba736a1
PO		 1014 /*
1015 * We currently don't do anything fancy with DMA
1016 * boundaries, but as we can't disable the feature
1017 * we need to at least restart the transfer.
1018 */
1019 if (intmask & SDHCI_INT_DMA_END)
1020 writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1021 host->ioaddr + SDHCI_DMA_ADDRESS);
1022
e538fbe8
PO		 1023 if (intmask & SDHCI_INT_DATA_END) {
1024 if (host->cmd) {
1025 /*
1026 * Data managed to finish before the
1027 * command completed. Make sure we do
1028 * things in the proper order.
1029 */
1030 host->data_early = 1;
1031 } else {
1032 sdhci_finish_data(host);
1033 }
1034 }
d129bceb
PO		 1035 }
1036}
1037
7d12e780 1038static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 1039{
1040 irqreturn_t result;
1041 struct sdhci_host* host = dev_id;
1042 u32 intmask;
f75979b7 1043 int cardint = 0;
d129bceb
PO		 1044
1045 spin_lock(&host->lock);
1046
1047 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1048
62df67a5 1049 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 1050 result = IRQ_NONE;
1051 goto out;
1052 }
1053
1054 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1055
3192a28f
PO		 1056 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1057 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1058 host->ioaddr + SDHCI_INT_STATUS);
d129bceb 1059 tasklet_schedule(&host->card_tasklet);
3192a28f 1060 }
d129bceb 1061
3192a28f 1062 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1063
3192a28f 1064 if (intmask & SDHCI_INT_CMD_MASK) {
d129bceb
PO		 1065 writel(intmask & SDHCI_INT_CMD_MASK,
1066 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1067 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1068 }
1069
1070 if (intmask & SDHCI_INT_DATA_MASK) {
d129bceb
PO		 1071 writel(intmask & SDHCI_INT_DATA_MASK,
1072 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1073 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1074 }
1075
1076 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1077
964f9ce2
PO		 1078 intmask &= ~SDHCI_INT_ERROR;
1079
d129bceb 1080 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1081 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1082 mmc_hostname(host->mmc));
3192a28f 1083 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
d129bceb
PO		 1084 }
1085
9d26a5d3 1086 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 1087
f75979b7
PO		 1088 if (intmask & SDHCI_INT_CARD_INT)
1089 cardint = 1;
1090
1091 intmask &= ~SDHCI_INT_CARD_INT;
1092
3192a28f 1093 if (intmask) {
acf1da45 1094 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 1095 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1096 sdhci_dumpregs(host);
1097
d129bceb 1098 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1099 }
d129bceb
PO		 1100
1101 result = IRQ_HANDLED;
1102
5f25a66f 1103 mmiowb();
d129bceb
PO		 1104out:
1105 spin_unlock(&host->lock);
1106
f75979b7
PO		 1107 /*
1108 * We have to delay this as it calls back into the driver.
1109 */
1110 if (cardint)
1111 mmc_signal_sdio_irq(host->mmc);
1112
d129bceb
PO		 1113 return result;
1114}
1115
1116/*****************************************************************************\
1117 * *
1118 * Suspend/resume *
1119 * *
1120\*****************************************************************************/
1121
1122#ifdef CONFIG_PM
1123
1124static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1125{
1126 struct sdhci_chip *chip;
1127 int i, ret;
1128
1129 chip = pci_get_drvdata(pdev);
1130 if (!chip)
1131 return 0;
1132
1133 DBG("Suspending...\n");
1134
1135 for (i = 0;i < chip->num_slots;i++) {
1136 if (!chip->hosts[i])
1137 continue;
1138 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1139 if (ret) {
1140 for (i--;i >= 0;i--)
1141 mmc_resume_host(chip->hosts[i]->mmc);
1142 return ret;
1143 }
1144 }
1145
1146 pci_save_state(pdev);
1147 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
a715dfc7
PO		 1148
1149 for (i = 0;i < chip->num_slots;i++) {
1150 if (!chip->hosts[i])
1151 continue;
1152 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1153 }
1154
d129bceb
PO		 1155 pci_disable_device(pdev);
1156 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1157
1158 return 0;
1159}
1160
1161static int sdhci_resume (struct pci_dev *pdev)
1162{
1163 struct sdhci_chip *chip;
1164 int i, ret;
1165
1166 chip = pci_get_drvdata(pdev);
1167 if (!chip)
1168 return 0;
1169
1170 DBG("Resuming...\n");
1171
1172 pci_set_power_state(pdev, PCI_D0);
1173 pci_restore_state(pdev);
df1c4b7b
PO		 1174 ret = pci_enable_device(pdev);
1175 if (ret)
1176 return ret;
d129bceb
PO		 1177
1178 for (i = 0;i < chip->num_slots;i++) {
1179 if (!chip->hosts[i])
1180 continue;
1181 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1182 pci_set_master(pdev);
a715dfc7
PO		 1183 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1184 IRQF_SHARED, chip->hosts[i]->slot_descr,
1185 chip->hosts[i]);
1186 if (ret)
1187 return ret;
d129bceb 1188 sdhci_init(chip->hosts[i]);
5f25a66f 1189 mmiowb();
d129bceb
PO		 1190 ret = mmc_resume_host(chip->hosts[i]->mmc);
1191 if (ret)
1192 return ret;
1193 }
1194
1195 return 0;
1196}
1197
1198#else /* CONFIG_PM */
1199
1200#define sdhci_suspend NULL
1201#define sdhci_resume NULL
1202
1203#endif /* CONFIG_PM */
1204
1205/*****************************************************************************\
1206 * *
1207 * Device probing/removal *
1208 * *
1209\*****************************************************************************/
1210
1211static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1212{
1213 int ret;
4a965505 1214 unsigned int version;
d129bceb
PO		 1215 struct sdhci_chip *chip;
1216 struct mmc_host *mmc;
1217 struct sdhci_host *host;
1218
1219 u8 first_bar;
1220 unsigned int caps;
1221
1222 chip = pci_get_drvdata(pdev);
1223 BUG_ON(!chip);
1224
1225 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1226 if (ret)
1227 return ret;
1228
1229 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1230
1231 if (first_bar > 5) {
1232 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1233 return -ENODEV;
1234 }
1235
1236 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1237 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1238 return -ENODEV;
1239 }
1240
1241 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
a98087cf
PO		 1242 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1243 "You may experience problems.\n");
d129bceb
PO		 1244 }
1245
67435274
PO		 1246 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1247 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1248 return -ENODEV;
1249 }
1250
1251 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1252 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1253 return -ENODEV;
1254 }
1255
d129bceb
PO		 1256 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1257 if (!mmc)
1258 return -ENOMEM;
1259
1260 host = mmc_priv(mmc);
1261 host->mmc = mmc;
1262
8a4da143
PO		 1263 host->chip = chip;
1264 chip->hosts[slot] = host;
1265
d129bceb
PO		 1266 host->bar = first_bar + slot;
1267
1268 host->addr = pci_resource_start(pdev, host->bar);
1269 host->irq = pdev->irq;
1270
1271 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1272
1273 snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1274
1275 ret = pci_request_region(pdev, host->bar, host->slot_descr);
1276 if (ret)
1277 goto free;
1278
1279 host->ioaddr = ioremap_nocache(host->addr,
1280 pci_resource_len(pdev, host->bar));
1281 if (!host->ioaddr) {
1282 ret = -ENOMEM;
1283 goto release;
1284 }
1285
d96649ed
PO		 1286 sdhci_reset(host, SDHCI_RESET_ALL);
1287
4a965505
PO		 1288 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1289 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1290 if (version != 0) {
1291 printk(KERN_ERR "%s: Unknown controller version (%d). "
8b1b2185 1292 "You may experience problems.\n", host->slot_descr,
4a965505 1293 version);
4a965505
PO		 1294 }
1295
d129bceb
PO		 1296 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1297
67435274
PO		 1298 if (debug_nodma)
1299 DBG("DMA forced off\n");
1300 else if (debug_forcedma) {
1301 DBG("DMA forced on\n");
1302 host->flags |= SDHCI_USE_DMA;
98608076
PO		 1303 } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1304 host->flags |= SDHCI_USE_DMA;
67435274
PO		 1305 else if (!(caps & SDHCI_CAN_DO_DMA))
1306 DBG("Controller doesn't have DMA capability\n");
1307 else
d129bceb
PO		 1308 host->flags |= SDHCI_USE_DMA;
1309
7c168e3d
FT		 1310 if ((chip->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1311 (host->flags & SDHCI_USE_DMA)) {
1312 DBG("Disabling DMA as it is marked broken");
1313 host->flags &= ~SDHCI_USE_DMA;
1314 }
1315
56e71efe
FT		 1316 if (((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1317 (host->flags & SDHCI_USE_DMA)) {
1318 printk(KERN_WARNING "%s: Will use DMA "
1319 "mode even though HW doesn't fully "
1320 "claim to support it.\n", host->slot_descr);
1321 }
1322
d129bceb
PO		 1323 if (host->flags & SDHCI_USE_DMA) {
1324 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1325 printk(KERN_WARNING "%s: No suitable DMA available. "
1326 "Falling back to PIO.\n", host->slot_descr);
1327 host->flags &= ~SDHCI_USE_DMA;
1328 }
1329 }
1330
1331 if (host->flags & SDHCI_USE_DMA)
1332 pci_set_master(pdev);
1333 else /* XXX: Hack to get MMC layer to avoid highmem */
1334 pdev->dma_mask = 0;
1335
8ef1a143
PO		 1336 host->max_clk =
1337 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1338 if (host->max_clk == 0) {
1339 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1340 "frequency.\n", host->slot_descr);
1341 ret = -ENODEV;
1342 goto unmap;
1343 }
d129bceb
PO		 1344 host->max_clk *= 1000000;
1345
1c8cde92
PO		 1346 host->timeout_clk =
1347 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1348 if (host->timeout_clk == 0) {
1349 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1350 "frequency.\n", host->slot_descr);
1351 ret = -ENODEV;
1352 goto unmap;
1353 }
1354 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1355 host->timeout_clk *= 1000;
d129bceb
PO		 1356
1357 /*
1358 * Set host parameters.
1359 */
1360 mmc->ops = &sdhci_ops;
1361 mmc->f_min = host->max_clk / 256;
1362 mmc->f_max = host->max_clk;
f75979b7 1363 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_SDIO_IRQ;
d129bceb 1364
cd9277c0
PO		 1365 if (caps & SDHCI_CAN_DO_HISPD)
1366 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1367
146ad66e
PO		 1368 mmc->ocr_avail = 0;
1369 if (caps & SDHCI_CAN_VDD_330)
1370 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
c70840e8 1371 if (caps & SDHCI_CAN_VDD_300)
146ad66e 1372 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
c70840e8 1373 if (caps & SDHCI_CAN_VDD_180)
55556da0 1374 mmc->ocr_avail |= MMC_VDD_165_195;
146ad66e
PO		 1375
1376 if (mmc->ocr_avail == 0) {
1377 printk(KERN_ERR "%s: Hardware doesn't report any "
1378 "support voltages.\n", host->slot_descr);
1379 ret = -ENODEV;
1380 goto unmap;
1381 }
1382
d129bceb
PO		 1383 spin_lock_init(&host->lock);
1384
1385 /*
1386 * Maximum number of segments. Hardware cannot do scatter lists.
1387 */
1388 if (host->flags & SDHCI_USE_DMA)
1389 mmc->max_hw_segs = 1;
1390 else
1391 mmc->max_hw_segs = 16;
1392 mmc->max_phys_segs = 16;
1393
1394 /*
bab76961 1395 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 1396 * size (512KiB).
d129bceb 1397 */
55db890a 1398 mmc->max_req_size = 524288;
d129bceb
PO		 1399
1400 /*
1401 * Maximum segment size. Could be one segment with the maximum number
55db890a 1402 * of bytes.
d129bceb 1403 */
55db890a 1404 mmc->max_seg_size = mmc->max_req_size;
d129bceb 1405
fe4a3c7a
PO		 1406 /*
1407 * Maximum block size. This varies from controller to controller and
1408 * is specified in the capabilities register.
1409 */
1410 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1411 if (mmc->max_blk_size >= 3) {
03f8590d 1412 printk(KERN_WARNING "%s: Invalid maximum block size, assuming 512\n",
fe4a3c7a 1413 host->slot_descr);
03f8590d
DV		 1414 mmc->max_blk_size = 512;
1415 } else
1416 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 1417
55db890a
PO		 1418 /*
1419 * Maximum block count.
1420 */
1421 mmc->max_blk_count = 65535;
1422
d129bceb
PO		 1423 /*
1424 * Init tasklets.
1425 */
1426 tasklet_init(&host->card_tasklet,
1427 sdhci_tasklet_card, (unsigned long)host);
1428 tasklet_init(&host->finish_tasklet,
1429 sdhci_tasklet_finish, (unsigned long)host);
1430
e4cad1b5 1431 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 1432
dace1453 1433 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
d129bceb
PO		 1434 host->slot_descr, host);
1435 if (ret)
8ef1a143 1436 goto untasklet;
d129bceb
PO		 1437
1438 sdhci_init(host);
1439
1440#ifdef CONFIG_MMC_DEBUG
1441 sdhci_dumpregs(host);
1442#endif
1443
5f25a66f
PO		 1444 mmiowb();
1445
d129bceb
PO		 1446 mmc_add_host(mmc);
1447
1448 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1449 host->addr, host->irq,
1450 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1451
1452 return 0;
1453
8ef1a143 1454untasklet:
d129bceb
PO		 1455 tasklet_kill(&host->card_tasklet);
1456 tasklet_kill(&host->finish_tasklet);
8ef1a143 1457unmap:
d129bceb
PO		 1458 iounmap(host->ioaddr);
1459release:
1460 pci_release_region(pdev, host->bar);
1461free:
1462 mmc_free_host(mmc);
1463
1464 return ret;
1465}
1466
1467static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1468{
1469 struct sdhci_chip *chip;
1470 struct mmc_host *mmc;
1471 struct sdhci_host *host;
1472
1473 chip = pci_get_drvdata(pdev);
1474 host = chip->hosts[slot];
1475 mmc = host->mmc;
1476
1477 chip->hosts[slot] = NULL;
1478
1479 mmc_remove_host(mmc);
1480
1481 sdhci_reset(host, SDHCI_RESET_ALL);
1482
1483 free_irq(host->irq, host);
1484
1485 del_timer_sync(&host->timer);
1486
1487 tasklet_kill(&host->card_tasklet);
1488 tasklet_kill(&host->finish_tasklet);
1489
1490 iounmap(host->ioaddr);
1491
1492 pci_release_region(pdev, host->bar);
1493
1494 mmc_free_host(mmc);
1495}
1496
1497static int __devinit sdhci_probe(struct pci_dev *pdev,
1498 const struct pci_device_id *ent)
1499{
1500 int ret, i;
51f82bc0 1501 u8 slots, rev;
d129bceb
PO		 1502 struct sdhci_chip *chip;
1503
1504 BUG_ON(pdev == NULL);
1505 BUG_ON(ent == NULL);
1506
51f82bc0
PO		 1507 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1508
1509 printk(KERN_INFO DRIVER_NAME
1510 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1511 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1512 (int)rev);
d129bceb
PO		 1513
1514 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1515 if (ret)
1516 return ret;
1517
1518 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1519 DBG("found %d slot(s)\n", slots);
1520 if (slots == 0)
1521 return -ENODEV;
1522
1523 ret = pci_enable_device(pdev);
1524 if (ret)
1525 return ret;
1526
1527 chip = kzalloc(sizeof(struct sdhci_chip) +
1528 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1529 if (!chip) {
1530 ret = -ENOMEM;
1531 goto err;
1532 }
1533
1534 chip->pdev = pdev;
df673b22
PO		 1535 chip->quirks = ent->driver_data;
1536
1537 if (debug_quirks)
1538 chip->quirks = debug_quirks;
d129bceb
PO		 1539
1540 chip->num_slots = slots;
1541 pci_set_drvdata(pdev, chip);
1542
1543 for (i = 0;i < slots;i++) {
1544 ret = sdhci_probe_slot(pdev, i);
1545 if (ret) {
1546 for (i--;i >= 0;i--)
1547 sdhci_remove_slot(pdev, i);
1548 goto free;
1549 }
1550 }
1551
1552 return 0;
1553
1554free:
1555 pci_set_drvdata(pdev, NULL);
1556 kfree(chip);
1557
1558err:
1559 pci_disable_device(pdev);
1560 return ret;
1561}
1562
1563static void __devexit sdhci_remove(struct pci_dev *pdev)
1564{
1565 int i;
1566 struct sdhci_chip *chip;
1567
1568 chip = pci_get_drvdata(pdev);
1569
1570 if (chip) {
1571 for (i = 0;i < chip->num_slots;i++)
1572 sdhci_remove_slot(pdev, i);
1573
1574 pci_set_drvdata(pdev, NULL);
1575
1576 kfree(chip);
1577 }
1578
1579 pci_disable_device(pdev);
1580}
1581
1582static struct pci_driver sdhci_driver = {
1583 .name = DRIVER_NAME,
1584 .id_table = pci_ids,
1585 .probe = sdhci_probe,
1586 .remove = __devexit_p(sdhci_remove),
1587 .suspend = sdhci_suspend,
1588 .resume = sdhci_resume,
1589};
1590
1591/*****************************************************************************\
1592 * *
1593 * Driver init/exit *
1594 * *
1595\*****************************************************************************/
1596
1597static int __init sdhci_drv_init(void)
1598{
1599 printk(KERN_INFO DRIVER_NAME
52fbf9c9 1600 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 1601 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1602
1603 return pci_register_driver(&sdhci_driver);
1604}
1605
1606static void __exit sdhci_drv_exit(void)
1607{
1608 DBG("Exiting\n");
1609
1610 pci_unregister_driver(&sdhci_driver);
1611}
1612
1613module_init(sdhci_drv_init);
1614module_exit(sdhci_drv_exit);
1615
67435274
PO		 1616module_param(debug_nodma, uint, 0444);
1617module_param(debug_forcedma, uint, 0444);
df673b22 1618module_param(debug_quirks, uint, 0444);
67435274 1619
d129bceb
PO		 1620MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1621MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
d129bceb 1622MODULE_LICENSE("GPL");
67435274
PO		 1623
1624MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1625MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
df673b22 1626MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
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