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mmc: sdhci: clean up host cookie handling
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
f9134319
PO		 41#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43#define SDHCI_USE_LEDS_CLASS
44#endif
45
b513ea25
AN		 46#define MAX_TUNING_LOOP 40
47
df673b22 48static unsigned int debug_quirks = 0;
66fd8ad5 49static unsigned int debug_quirks2;
67435274 50
d129bceb
PO		 51static void sdhci_finish_data(struct sdhci_host *);
52
d129bceb 53static void sdhci_finish_command(struct sdhci_host *);
069c9f14 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
04e079cf 56static int sdhci_do_get_cd(struct sdhci_host *host);
d129bceb 57
162d6f98 58#ifdef CONFIG_PM
66fd8ad5
AH		 59static int sdhci_runtime_pm_get(struct sdhci_host *host);
60static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 61static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
62static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 63#else
64static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
65{
66 return 0;
67}
68static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
69{
70 return 0;
71}
f0710a55
AH		 72static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
73{
74}
75static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
76{
77}
66fd8ad5
AH		 78#endif
79
d129bceb
PO		 80static void sdhci_dumpregs(struct sdhci_host *host)
81{
a3c76eb9 82 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 83 mmc_hostname(host->mmc));
d129bceb 84
a3c76eb9 85 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 86 sdhci_readl(host, SDHCI_DMA_ADDRESS),
87 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 88 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 89 sdhci_readw(host, SDHCI_BLOCK_SIZE),
90 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 91 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 92 sdhci_readl(host, SDHCI_ARGUMENT),
93 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 94 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 95 sdhci_readl(host, SDHCI_PRESENT_STATE),
96 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 97 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 98 sdhci_readb(host, SDHCI_POWER_CONTROL),
99 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 100 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 101 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
102 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 103 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 104 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
105 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 106 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 107 sdhci_readl(host, SDHCI_INT_ENABLE),
108 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 109 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 110 sdhci_readw(host, SDHCI_ACMD12_ERR),
111 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 112 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 113 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 114 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 115 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 116 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 117 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 118 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 119 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 120
e57a5f61
AH		 121 if (host->flags & SDHCI_USE_ADMA) {
122 if (host->flags & SDHCI_USE_64_BIT_DMA)
123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
124 readl(host->ioaddr + SDHCI_ADMA_ERROR),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
126 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
127 else
128 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
129 readl(host->ioaddr + SDHCI_ADMA_ERROR),
130 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
131 }
be3f4ae0 132
a3c76eb9 133 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 134}
135
136/*****************************************************************************\
137 * *
138 * Low level functions *
139 * *
140\*****************************************************************************/
141
7260cf5e
AV		 142static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
143{
5b4f1f6c 144 u32 present;
7260cf5e 145
c79396c1 146 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 147 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 148 return;
149
5b4f1f6c
RK		 150 if (enable) {
151 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
152 SDHCI_CARD_PRESENT;
d25928d1 153
5b4f1f6c
RK		 154 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
155 SDHCI_INT_CARD_INSERT;
156 } else {
157 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
158 }
b537f94c
RK		 159
160 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
161 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 162}
163
164static void sdhci_enable_card_detection(struct sdhci_host *host)
165{
166 sdhci_set_card_detection(host, true);
167}
168
169static void sdhci_disable_card_detection(struct sdhci_host *host)
170{
171 sdhci_set_card_detection(host, false);
172}
173
03231f9b 174void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 175{
e16514d8 176 unsigned long timeout;
393c1a34 177
4e4141a5 178 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 179
f0710a55 180 if (mask & SDHCI_RESET_ALL) {
d129bceb 181 host->clock = 0;
f0710a55
AH		 182 /* Reset-all turns off SD Bus Power */
183 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
184 sdhci_runtime_pm_bus_off(host);
185 }
d129bceb 186
e16514d8
PO		 187 /* Wait max 100 ms */
188 timeout = 100;
189
190 /* hw clears the bit when it's done */
4e4141a5 191 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 192 if (timeout == 0) {
a3c76eb9 193 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 194 mmc_hostname(host->mmc), (int)mask);
195 sdhci_dumpregs(host);
196 return;
197 }
198 timeout--;
199 mdelay(1);
d129bceb 200 }
03231f9b
RK		 201}
202EXPORT_SYMBOL_GPL(sdhci_reset);
203
204static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
205{
206 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
135b0a28 207 if (!sdhci_do_get_cd(host))
03231f9b
RK		 208 return;
209 }
063a9dbb 210
03231f9b 211 host->ops->reset(host, mask);
393c1a34 212
da91a8f9
RK		 213 if (mask & SDHCI_RESET_ALL) {
214 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
215 if (host->ops->enable_dma)
216 host->ops->enable_dma(host);
217 }
218
219 /* Resetting the controller clears many */
220 host->preset_enabled = false;
3abc1e80 221 }
d129bceb
PO		 222}
223
2f4cbb3d
NP		 224static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
225
226static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 227{
2f4cbb3d 228 if (soft)
03231f9b 229 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 230 else
03231f9b 231 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 232
b537f94c
RK		 233 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
235 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
236 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
237 SDHCI_INT_RESPONSE;
238
239 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
240 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 241
242 if (soft) {
243 /* force clock reconfiguration */
244 host->clock = 0;
245 sdhci_set_ios(host->mmc, &host->mmc->ios);
246 }
7260cf5e 247}
d129bceb 248
7260cf5e
AV		 249static void sdhci_reinit(struct sdhci_host *host)
250{
2f4cbb3d 251 sdhci_init(host, 0);
7260cf5e 252 sdhci_enable_card_detection(host);
d129bceb
PO		 253}
254
255static void sdhci_activate_led(struct sdhci_host *host)
256{
257 u8 ctrl;
258
4e4141a5 259 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 260 ctrl |= SDHCI_CTRL_LED;
4e4141a5 261 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 262}
263
264static void sdhci_deactivate_led(struct sdhci_host *host)
265{
266 u8 ctrl;
267
4e4141a5 268 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 269 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 270 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 271}
272
f9134319 273#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 274static void sdhci_led_control(struct led_classdev *led,
275 enum led_brightness brightness)
276{
277 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
278 unsigned long flags;
279
280 spin_lock_irqsave(&host->lock, flags);
281
66fd8ad5
AH		 282 if (host->runtime_suspended)
283 goto out;
284
2f730fec
PO		 285 if (brightness == LED_OFF)
286 sdhci_deactivate_led(host);
287 else
288 sdhci_activate_led(host);
66fd8ad5 289out:
2f730fec
PO		 290 spin_unlock_irqrestore(&host->lock, flags);
291}
292#endif
293
d129bceb
PO		 294/*****************************************************************************\
295 * *
296 * Core functions *
297 * *
298\*****************************************************************************/
299
a406f5a3 300static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 301{
7659150c
PO		 302 unsigned long flags;
303 size_t blksize, len, chunk;
7244b85b 304 u32 uninitialized_var(scratch);
7659150c 305 u8 *buf;
d129bceb 306
a406f5a3 307 DBG("PIO reading\n");
d129bceb 308
a406f5a3 309 blksize = host->data->blksz;
7659150c 310 chunk = 0;
d129bceb 311
7659150c 312 local_irq_save(flags);
d129bceb 313
a406f5a3 314 while (blksize) {
bf3a35ac 315 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 316
7659150c 317 len = min(host->sg_miter.length, blksize);
d129bceb 318
7659150c
PO		 319 blksize -= len;
320 host->sg_miter.consumed = len;
14d836e7 321
7659150c 322 buf = host->sg_miter.addr;
d129bceb 323
7659150c
PO		 324 while (len) {
325 if (chunk == 0) {
4e4141a5 326 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 327 chunk = 4;
a406f5a3 328 }
7659150c
PO		 329
330 *buf = scratch & 0xFF;
331
332 buf++;
333 scratch >>= 8;
334 chunk--;
335 len--;
d129bceb 336 }
a406f5a3 337 }
7659150c
PO		 338
339 sg_miter_stop(&host->sg_miter);
340
341 local_irq_restore(flags);
a406f5a3 342}
d129bceb 343
a406f5a3
PO		 344static void sdhci_write_block_pio(struct sdhci_host *host)
345{
7659150c
PO		 346 unsigned long flags;
347 size_t blksize, len, chunk;
348 u32 scratch;
349 u8 *buf;
d129bceb 350
a406f5a3
PO		 351 DBG("PIO writing\n");
352
353 blksize = host->data->blksz;
7659150c
PO		 354 chunk = 0;
355 scratch = 0;
d129bceb 356
7659150c 357 local_irq_save(flags);
d129bceb 358
a406f5a3 359 while (blksize) {
bf3a35ac 360 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 361
7659150c
PO		 362 len = min(host->sg_miter.length, blksize);
363
364 blksize -= len;
365 host->sg_miter.consumed = len;
366
367 buf = host->sg_miter.addr;
d129bceb 368
7659150c
PO		 369 while (len) {
370 scratch |= (u32)*buf << (chunk * 8);
371
372 buf++;
373 chunk++;
374 len--;
375
376 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 377 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 378 chunk = 0;
379 scratch = 0;
d129bceb 380 }
d129bceb
PO		 381 }
382 }
7659150c
PO		 383
384 sg_miter_stop(&host->sg_miter);
385
386 local_irq_restore(flags);
a406f5a3
PO		 387}
388
389static void sdhci_transfer_pio(struct sdhci_host *host)
390{
391 u32 mask;
392
393 BUG_ON(!host->data);
394
7659150c 395 if (host->blocks == 0)
a406f5a3
PO		 396 return;
397
398 if (host->data->flags & MMC_DATA_READ)
399 mask = SDHCI_DATA_AVAILABLE;
400 else
401 mask = SDHCI_SPACE_AVAILABLE;
402
4a3cba32
PO		 403 /*
404 * Some controllers (JMicron JMB38x) mess up the buffer bits
405 * for transfers < 4 bytes. As long as it is just one block,
406 * we can ignore the bits.
407 */
408 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
409 (host->data->blocks == 1))
410 mask = ~0;
411
4e4141a5 412 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 413 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
414 udelay(100);
415
a406f5a3
PO		 416 if (host->data->flags & MMC_DATA_READ)
417 sdhci_read_block_pio(host);
418 else
419 sdhci_write_block_pio(host);
d129bceb 420
7659150c
PO		 421 host->blocks--;
422 if (host->blocks == 0)
a406f5a3 423 break;
a406f5a3 424 }
d129bceb 425
a406f5a3 426 DBG("PIO transfer complete.\n");
d129bceb
PO		 427}
428
48857d9b 429static int sdhci_pre_dma_transfer(struct sdhci_host *host,
c0999b72 430 struct mmc_data *data, int cookie)
48857d9b
RK		 431{
432 int sg_count;
433
94538e51
RK		 434 /*
435 * If the data buffers are already mapped, return the previous
436 * dma_map_sg() result.
437 */
438 if (data->host_cookie == COOKIE_PRE_MAPPED)
48857d9b 439 return data->sg_count;
48857d9b
RK		 440
441 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
442 data->flags & MMC_DATA_WRITE ?
443 DMA_TO_DEVICE : DMA_FROM_DEVICE);
444
445 if (sg_count == 0)
446 return -ENOSPC;
447
448 data->sg_count = sg_count;
c0999b72 449 data->host_cookie = cookie;
48857d9b
RK		 450
451 return sg_count;
452}
453
2134a922
PO		 454static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
455{
456 local_irq_save(*flags);
482fce99 457 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 458}
459
460static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
461{
482fce99 462 kunmap_atomic(buffer);
2134a922
PO		 463 local_irq_restore(*flags);
464}
465
e57a5f61
AH		 466static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
467 dma_addr_t addr, int len, unsigned cmd)
118cd17d 468{
e57a5f61 469 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 470
e57a5f61 471 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 472 dma_desc->cmd = cpu_to_le16(cmd);
473 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 474 dma_desc->addr_lo = cpu_to_le32((u32)addr);
475
476 if (host->flags & SDHCI_USE_64_BIT_DMA)
477 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 478}
479
b5ffa674
AH		 480static void sdhci_adma_mark_end(void *desc)
481{
e57a5f61 482 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 483
e57a5f61 484 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 485 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 486}
487
60c64762
RK		 488static void sdhci_adma_table_pre(struct sdhci_host *host,
489 struct mmc_data *data, int sg_count)
2134a922 490{
2134a922 491 struct scatterlist *sg;
2134a922 492 unsigned long flags;
acc3ad13
RK		 493 dma_addr_t addr, align_addr;
494 void *desc, *align;
495 char *buffer;
496 int len, offset, i;
2134a922
PO		 497
498 /*
499 * The spec does not specify endianness of descriptor table.
500 * We currently guess that it is LE.
501 */
502
60c64762 503 host->sg_count = sg_count;
2134a922 504
4efaa6fb 505 desc = host->adma_table;
2134a922
PO		 506 align = host->align_buffer;
507
508 align_addr = host->align_addr;
509
510 for_each_sg(data->sg, sg, host->sg_count, i) {
511 addr = sg_dma_address(sg);
512 len = sg_dma_len(sg);
513
514 /*
acc3ad13
RK		 515 * The SDHCI specification states that ADMA addresses must
516 * be 32-bit aligned. If they aren't, then we use a bounce
517 * buffer for the (up to three) bytes that screw up the
2134a922
PO		 518 * alignment.
519 */
04a5ae6f
AH		 520 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
521 SDHCI_ADMA2_MASK;
2134a922
PO		 522 if (offset) {
523 if (data->flags & MMC_DATA_WRITE) {
524 buffer = sdhci_kmap_atomic(sg, &flags);
525 memcpy(align, buffer, offset);
526 sdhci_kunmap_atomic(buffer, &flags);
527 }
528
118cd17d 529 /* tran, valid */
e57a5f61 530 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 531 ADMA2_TRAN_VALID);
2134a922
PO		 532
533 BUG_ON(offset > 65536);
534
04a5ae6f
AH		 535 align += SDHCI_ADMA2_ALIGN;
536 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 537
76fe379a 538 desc += host->desc_sz;
2134a922
PO		 539
540 addr += offset;
541 len -= offset;
542 }
543
2134a922
PO		 544 BUG_ON(len > 65536);
545
347ea32d
AH		 546 if (len) {
547 /* tran, valid */
548 sdhci_adma_write_desc(host, desc, addr, len,
549 ADMA2_TRAN_VALID);
550 desc += host->desc_sz;
551 }
2134a922
PO		 552
553 /*
554 * If this triggers then we have a calculation bug
555 * somewhere. :/
556 */
76fe379a 557 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 558 }
559
70764a90 560 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
acc3ad13 561 /* Mark the last descriptor as the terminating descriptor */
4efaa6fb 562 if (desc != host->adma_table) {
76fe379a 563 desc -= host->desc_sz;
b5ffa674 564 sdhci_adma_mark_end(desc);
70764a90
TA		 565 }
566 } else {
acc3ad13 567 /* Add a terminating entry - nop, end, valid */
e57a5f61 568 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 569 }
2134a922
PO		 570}
571
572static void sdhci_adma_table_post(struct sdhci_host *host,
573 struct mmc_data *data)
574{
2134a922
PO		 575 struct scatterlist *sg;
576 int i, size;
1c3d5f6d 577 void *align;
2134a922
PO		 578 char *buffer;
579 unsigned long flags;
580
47fa9613
RK		 581 if (data->flags & MMC_DATA_READ) {
582 bool has_unaligned = false;
de0b65a7 583
47fa9613
RK		 584 /* Do a quick scan of the SG list for any unaligned mappings */
585 for_each_sg(data->sg, sg, host->sg_count, i)
586 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
587 has_unaligned = true;
588 break;
589 }
2134a922 590
47fa9613
RK		 591 if (has_unaligned) {
592 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
f55c98f7 593 data->sg_len, DMA_FROM_DEVICE);
2134a922 594
47fa9613 595 align = host->align_buffer;
2134a922 596
47fa9613
RK		 597 for_each_sg(data->sg, sg, host->sg_count, i) {
598 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
599 size = SDHCI_ADMA2_ALIGN -
600 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
601
602 buffer = sdhci_kmap_atomic(sg, &flags);
603 memcpy(buffer, align, size);
604 sdhci_kunmap_atomic(buffer, &flags);
2134a922 605
47fa9613
RK		 606 align += SDHCI_ADMA2_ALIGN;
607 }
2134a922
PO		 608 }
609 }
610 }
2134a922
PO		 611}
612
a3c7778f 613static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 614{
1c8cde92 615 u8 count;
a3c7778f 616 struct mmc_data *data = cmd->data;
1c8cde92 617 unsigned target_timeout, current_timeout;
d129bceb 618
ee53ab5d
PO		 619 /*
620 * If the host controller provides us with an incorrect timeout
621 * value, just skip the check and use 0xE. The hardware may take
622 * longer to time out, but that's much better than having a too-short
623 * timeout value.
624 */
11a2f1b7 625 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 626 return 0xE;
e538fbe8 627
a3c7778f 628 /* Unspecified timeout, assume max */
1d4d7744 629 if (!data && !cmd->busy_timeout)
a3c7778f 630 return 0xE;
d129bceb 631
a3c7778f
AW		 632 /* timeout in us */
633 if (!data)
1d4d7744 634 target_timeout = cmd->busy_timeout * 1000;
78a2ca27 635 else {
fafcfda9 636 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
7f05538a
RK		 637 if (host->clock && data->timeout_clks) {
638 unsigned long long val;
639
640 /*
641 * data->timeout_clks is in units of clock cycles.
642 * host->clock is in Hz. target_timeout is in us.
643 * Hence, us = 1000000 * cycles / Hz. Round up.
644 */
645 val = 1000000 * data->timeout_clks;
646 if (do_div(val, host->clock))
647 target_timeout++;
648 target_timeout += val;
649 }
78a2ca27 650 }
81b39802 651
1c8cde92
PO		 652 /*
653 * Figure out needed cycles.
654 * We do this in steps in order to fit inside a 32 bit int.
655 * The first step is the minimum timeout, which will have a
656 * minimum resolution of 6 bits:
657 * (1) 2^13*1000 > 2^22,
658 * (2) host->timeout_clk < 2^16
659 * =>
660 * (1) / (2) > 2^6
661 */
662 count = 0;
663 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
664 while (current_timeout < target_timeout) {
665 count++;
666 current_timeout <<= 1;
667 if (count >= 0xF)
668 break;
669 }
670
671 if (count >= 0xF) {
09eeff52
CB		 672 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
673 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 674 count = 0xE;
675 }
676
ee53ab5d
PO		 677 return count;
678}
679
6aa943ab
AV		 680static void sdhci_set_transfer_irqs(struct sdhci_host *host)
681{
682 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
683 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
684
685 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 686 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 687 else
b537f94c
RK		 688 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
689
690 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
691 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 692}
693
b45e668a 694static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 695{
696 u8 count;
b45e668a
AD		 697
698 if (host->ops->set_timeout) {
699 host->ops->set_timeout(host, cmd);
700 } else {
701 count = sdhci_calc_timeout(host, cmd);
702 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
703 }
704}
705
706static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
707{
2134a922 708 u8 ctrl;
a3c7778f 709 struct mmc_data *data = cmd->data;
ee53ab5d
PO		 710
711 WARN_ON(host->data);
712
b45e668a
AD		 713 if (data || (cmd->flags & MMC_RSP_BUSY))
714 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 715
716 if (!data)
ee53ab5d
PO		 717 return;
718
719 /* Sanity checks */
720 BUG_ON(data->blksz * data->blocks > 524288);
721 BUG_ON(data->blksz > host->mmc->max_blk_size);
722 BUG_ON(data->blocks > 65535);
723
724 host->data = data;
725 host->data_early = 0;
f6a03cbf 726 host->data->bytes_xfered = 0;
ee53ab5d 727
a13abc7b 728 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 729 host->flags |= SDHCI_REQ_USE_DMA;
730
2134a922
PO		 731 /*
732 * FIXME: This doesn't account for merging when mapping the
733 * scatterlist.
734 */
735 if (host->flags & SDHCI_REQ_USE_DMA) {
736 int broken, i;
737 struct scatterlist *sg;
738
739 broken = 0;
740 if (host->flags & SDHCI_USE_ADMA) {
741 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
742 broken = 1;
743 } else {
744 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
745 broken = 1;
746 }
747
748 if (unlikely(broken)) {
749 for_each_sg(data->sg, sg, data->sg_len, i) {
750 if (sg->length & 0x3) {
2e4456f0 751 DBG("Reverting to PIO because of transfer size (%d)\n",
2134a922
PO		 752 sg->length);
753 host->flags &= ~SDHCI_REQ_USE_DMA;
754 break;
755 }
756 }
757 }
c9fddbc4
PO		 758 }
759
760 /*
761 * The assumption here being that alignment is the same after
762 * translation to device address space.
763 */
2134a922
PO		 764 if (host->flags & SDHCI_REQ_USE_DMA) {
765 int broken, i;
766 struct scatterlist *sg;
767
768 broken = 0;
769 if (host->flags & SDHCI_USE_ADMA) {
770 /*
771 * As we use 3 byte chunks to work around
772 * alignment problems, we need to check this
773 * quirk.
774 */
775 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
776 broken = 1;
777 } else {
778 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
779 broken = 1;
780 }
781
782 if (unlikely(broken)) {
783 for_each_sg(data->sg, sg, data->sg_len, i) {
784 if (sg->offset & 0x3) {
2e4456f0 785 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 786 host->flags &= ~SDHCI_REQ_USE_DMA;
787 break;
788 }
789 }
790 }
791 }
792
8f1934ce 793 if (host->flags & SDHCI_REQ_USE_DMA) {
c0999b72 794 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
60c64762
RK		 795
796 if (sg_cnt <= 0) {
797 /*
798 * This only happens when someone fed
799 * us an invalid request.
800 */
801 WARN_ON(1);
802 host->flags &= ~SDHCI_REQ_USE_DMA;
803 } else if (host->flags & SDHCI_USE_ADMA) {
804 sdhci_adma_table_pre(host, data, sg_cnt);
805
806 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
807 if (host->flags & SDHCI_USE_64_BIT_DMA)
808 sdhci_writel(host,
809 (u64)host->adma_addr >> 32,
810 SDHCI_ADMA_ADDRESS_HI);
8f1934ce 811 } else {
60c64762
RK		 812 WARN_ON(sg_cnt != 1);
813 sdhci_writel(host, sg_dma_address(data->sg),
814 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 815 }
816 }
817
2134a922
PO		 818 /*
819 * Always adjust the DMA selection as some controllers
820 * (e.g. JMicron) can't do PIO properly when the selection
821 * is ADMA.
822 */
823 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 824 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 825 ctrl &= ~SDHCI_CTRL_DMA_MASK;
826 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 827 (host->flags & SDHCI_USE_ADMA)) {
828 if (host->flags & SDHCI_USE_64_BIT_DMA)
829 ctrl |= SDHCI_CTRL_ADMA64;
830 else
831 ctrl |= SDHCI_CTRL_ADMA32;
832 } else {
2134a922 833 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 834 }
4e4141a5 835 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 836 }
837
8f1934ce 838 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 839 int flags;
840
841 flags = SG_MITER_ATOMIC;
842 if (host->data->flags & MMC_DATA_READ)
843 flags |= SG_MITER_TO_SG;
844 else
845 flags |= SG_MITER_FROM_SG;
846 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 847 host->blocks = data->blocks;
d129bceb 848 }
c7fa9963 849
6aa943ab
AV		 850 sdhci_set_transfer_irqs(host);
851
f6a03cbf
MV		 852 /* Set the DMA boundary value and block size */
853 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
854 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 855 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 856}
857
858static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 859 struct mmc_command *cmd)
c7fa9963 860{
d3fc5d71 861 u16 mode = 0;
e89d456f 862 struct mmc_data *data = cmd->data;
c7fa9963 863
2b558c13 864 if (data == NULL) {
9b8ffea6
VW		 865 if (host->quirks2 &
866 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
867 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
868 } else {
2b558c13 869 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 870 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
871 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 872 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 873 }
c7fa9963 874 return;
2b558c13 875 }
c7fa9963 876
e538fbe8
PO		 877 WARN_ON(!host->data);
878
d3fc5d71
VY		 879 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
880 mode = SDHCI_TRNS_BLK_CNT_EN;
881
e89d456f 882 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 883 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 884 /*
885 * If we are sending CMD23, CMD12 never gets sent
886 * on successful completion (so no Auto-CMD12).
887 */
85cc1c33
CD		 888 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
889 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 890 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 891 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
892 mode |= SDHCI_TRNS_AUTO_CMD23;
893 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
894 }
c4512f79 895 }
8edf6371 896
c7fa9963
PO		 897 if (data->flags & MMC_DATA_READ)
898 mode |= SDHCI_TRNS_READ;
c9fddbc4 899 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 900 mode |= SDHCI_TRNS_DMA;
901
4e4141a5 902 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 903}
904
905static void sdhci_finish_data(struct sdhci_host *host)
906{
907 struct mmc_data *data;
d129bceb
PO		 908
909 BUG_ON(!host->data);
910
911 data = host->data;
912 host->data = NULL;
913
c9fddbc4 914 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 915 if (host->flags & SDHCI_USE_ADMA)
916 sdhci_adma_table_post(host, data);
f55c98f7
RK		 917
918 if (data->host_cookie == COOKIE_MAPPED) {
919 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
920 (data->flags & MMC_DATA_READ) ?
921 DMA_FROM_DEVICE : DMA_TO_DEVICE);
922 data->host_cookie = COOKIE_UNMAPPED;
2134a922 923 }
d129bceb
PO		 924 }
925
926 /*
c9b74c5b
PO		 927 * The specification states that the block count register must
928 * be updated, but it does not specify at what point in the
929 * data flow. That makes the register entirely useless to read
930 * back so we have to assume that nothing made it to the card
931 * in the event of an error.
d129bceb 932 */
c9b74c5b
PO		 933 if (data->error)
934 data->bytes_xfered = 0;
d129bceb 935 else
c9b74c5b 936 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 937
e89d456f
AW		 938 /*
939 * Need to send CMD12 if -
940 * a) open-ended multiblock transfer (no CMD23)
941 * b) error in multiblock transfer
942 */
943 if (data->stop &&
944 (data->error ||
945 !host->mrq->sbc)) {
946
d129bceb
PO		 947 /*
948 * The controller needs a reset of internal state machines
949 * upon error conditions.
950 */
17b0429d 951 if (data->error) {
03231f9b
RK		 952 sdhci_do_reset(host, SDHCI_RESET_CMD);
953 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 954 }
955
956 sdhci_send_command(host, data->stop);
957 } else
958 tasklet_schedule(&host->finish_tasklet);
959}
960
c0e55129 961void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 962{
963 int flags;
fd2208d7 964 u32 mask;
7cb2c76f 965 unsigned long timeout;
d129bceb
PO		 966
967 WARN_ON(host->cmd);
968
96776200
RK		 969 /* Initially, a command has no error */
970 cmd->error = 0;
971
d129bceb 972 /* Wait max 10 ms */
7cb2c76f 973 timeout = 10;
fd2208d7
PO		 974
975 mask = SDHCI_CMD_INHIBIT;
976 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
977 mask |= SDHCI_DATA_INHIBIT;
978
979 /* We shouldn't wait for data inihibit for stop commands, even
980 though they might use busy signaling */
981 if (host->mrq->data && (cmd == host->mrq->data->stop))
982 mask &= ~SDHCI_DATA_INHIBIT;
983
4e4141a5 984 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 985 if (timeout == 0) {
2e4456f0
MV		 986 pr_err("%s: Controller never released inhibit bit(s).\n",
987 mmc_hostname(host->mmc));
d129bceb 988 sdhci_dumpregs(host);
17b0429d 989 cmd->error = -EIO;
d129bceb
PO		 990 tasklet_schedule(&host->finish_tasklet);
991 return;
992 }
7cb2c76f
PO		 993 timeout--;
994 mdelay(1);
995 }
d129bceb 996
3e1a6892 997 timeout = jiffies;
1d4d7744
UH		 998 if (!cmd->data && cmd->busy_timeout > 9000)
999 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1000 else
1001 timeout += 10 * HZ;
1002 mod_timer(&host->timer, timeout);
d129bceb
PO		 1003
1004 host->cmd = cmd;
e99783a4 1005 host->busy_handle = 0;
d129bceb 1006
a3c7778f 1007 sdhci_prepare_data(host, cmd);
d129bceb 1008
4e4141a5 1009 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1010
e89d456f 1011 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1012
d129bceb 1013 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1014 pr_err("%s: Unsupported response type!\n",
d129bceb 1015 mmc_hostname(host->mmc));
17b0429d 1016 cmd->error = -EINVAL;
d129bceb
PO		 1017 tasklet_schedule(&host->finish_tasklet);
1018 return;
1019 }
1020
1021 if (!(cmd->flags & MMC_RSP_PRESENT))
1022 flags = SDHCI_CMD_RESP_NONE;
1023 else if (cmd->flags & MMC_RSP_136)
1024 flags = SDHCI_CMD_RESP_LONG;
1025 else if (cmd->flags & MMC_RSP_BUSY)
1026 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1027 else
1028 flags = SDHCI_CMD_RESP_SHORT;
1029
1030 if (cmd->flags & MMC_RSP_CRC)
1031 flags |= SDHCI_CMD_CRC;
1032 if (cmd->flags & MMC_RSP_OPCODE)
1033 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1034
1035 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1036 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1037 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1038 flags |= SDHCI_CMD_DATA;
1039
4e4141a5 1040 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1041}
c0e55129 1042EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1043
1044static void sdhci_finish_command(struct sdhci_host *host)
1045{
1046 int i;
1047
1048 BUG_ON(host->cmd == NULL);
1049
1050 if (host->cmd->flags & MMC_RSP_PRESENT) {
1051 if (host->cmd->flags & MMC_RSP_136) {
1052 /* CRC is stripped so we need to do some shifting. */
1053 for (i = 0;i < 4;i++) {
4e4141a5 1054 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1055 SDHCI_RESPONSE + (3-i)*4) << 8;
1056 if (i != 3)
1057 host->cmd->resp[i] |=
4e4141a5 1058 sdhci_readb(host,
d129bceb
PO		 1059 SDHCI_RESPONSE + (3-i)*4-1);
1060 }
1061 } else {
4e4141a5 1062 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1063 }
1064 }
1065
e89d456f
AW		 1066 /* Finished CMD23, now send actual command. */
1067 if (host->cmd == host->mrq->sbc) {
1068 host->cmd = NULL;
1069 sdhci_send_command(host, host->mrq->cmd);
1070 } else {
e538fbe8 1071
e89d456f
AW		 1072 /* Processed actual command. */
1073 if (host->data && host->data_early)
1074 sdhci_finish_data(host);
d129bceb 1075
e89d456f
AW		 1076 if (!host->cmd->data)
1077 tasklet_schedule(&host->finish_tasklet);
1078
1079 host->cmd = NULL;
1080 }
d129bceb
PO		 1081}
1082
52983382
KL		 1083static u16 sdhci_get_preset_value(struct sdhci_host *host)
1084{
d975f121 1085 u16 preset = 0;
52983382 1086
d975f121
RK		 1087 switch (host->timing) {
1088 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1089 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1090 break;
d975f121 1091 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1092 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1093 break;
d975f121 1094 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1095 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1096 break;
d975f121
RK		 1097 case MMC_TIMING_UHS_SDR104:
1098 case MMC_TIMING_MMC_HS200:
52983382
KL		 1099 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1100 break;
d975f121 1101 case MMC_TIMING_UHS_DDR50:
0dafa60e 1102 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1103 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1104 break;
e9fb05d5
AH		 1105 case MMC_TIMING_MMC_HS400:
1106 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1107 break;
52983382
KL		 1108 default:
1109 pr_warn("%s: Invalid UHS-I mode selected\n",
1110 mmc_hostname(host->mmc));
1111 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1112 break;
1113 }
1114 return preset;
1115}
1116
1771059c 1117void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1118{
c3ed3877 1119 int div = 0; /* Initialized for compiler warning */
df16219f 1120 int real_div = div, clk_mul = 1;
c3ed3877 1121 u16 clk = 0;
7cb2c76f 1122 unsigned long timeout;
5497159c 1123 bool switch_base_clk = false;
d129bceb 1124
1650d0c7
RK		 1125 host->mmc->actual_clock = 0;
1126
4e4141a5 1127 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
af951761 1128 if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1129 mdelay(1);
d129bceb
PO		 1130
1131 if (clock == 0)
373073ef 1132 return;
d129bceb 1133
85105c53 1134 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1135 if (host->preset_enabled) {
52983382
KL		 1136 u16 pre_val;
1137
1138 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1139 pre_val = sdhci_get_preset_value(host);
1140 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1141 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1142 if (host->clk_mul &&
1143 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1144 clk = SDHCI_PROG_CLOCK_MODE;
1145 real_div = div + 1;
1146 clk_mul = host->clk_mul;
1147 } else {
1148 real_div = max_t(int, 1, div << 1);
1149 }
1150 goto clock_set;
1151 }
1152
c3ed3877
AN		 1153 /*
1154 * Check if the Host Controller supports Programmable Clock
1155 * Mode.
1156 */
1157 if (host->clk_mul) {
52983382
KL		 1158 for (div = 1; div <= 1024; div++) {
1159 if ((host->max_clk * host->clk_mul / div)
1160 <= clock)
1161 break;
1162 }
5497159c 1163 if ((host->max_clk * host->clk_mul / div) <= clock) {
1164 /*
1165 * Set Programmable Clock Mode in the Clock
1166 * Control register.
1167 */
1168 clk = SDHCI_PROG_CLOCK_MODE;
1169 real_div = div;
1170 clk_mul = host->clk_mul;
1171 div--;
1172 } else {
1173 /*
1174 * Divisor can be too small to reach clock
1175 * speed requirement. Then use the base clock.
1176 */
1177 switch_base_clk = true;
1178 }
1179 }
1180
1181 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1182 /* Version 3.00 divisors must be a multiple of 2. */
1183 if (host->max_clk <= clock)
1184 div = 1;
1185 else {
1186 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1187 div += 2) {
1188 if ((host->max_clk / div) <= clock)
1189 break;
1190 }
85105c53 1191 }
df16219f 1192 real_div = div;
c3ed3877 1193 div >>= 1;
d1955c3a
SG		 1194 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1195 && !div && host->max_clk <= 25000000)
1196 div = 1;
85105c53
ZG		 1197 }
1198 } else {
1199 /* Version 2.00 divisors must be a power of 2. */
0397526d 1200 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1201 if ((host->max_clk / div) <= clock)
1202 break;
1203 }
df16219f 1204 real_div = div;
c3ed3877 1205 div >>= 1;
d129bceb 1206 }
d129bceb 1207
52983382 1208clock_set:
03d6f5ff 1209 if (real_div)
df16219f 1210 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1211 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1212 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1213 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1214 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1215 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1216
27f6cb16
CB		 1217 /* Wait max 20 ms */
1218 timeout = 20;
4e4141a5 1219 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1220 & SDHCI_CLOCK_INT_STABLE)) {
1221 if (timeout == 0) {
2e4456f0
MV		 1222 pr_err("%s: Internal clock never stabilised.\n",
1223 mmc_hostname(host->mmc));
d129bceb
PO		 1224 sdhci_dumpregs(host);
1225 return;
1226 }
7cb2c76f
PO		 1227 timeout--;
1228 mdelay(1);
1229 }
d129bceb
PO		 1230
1231 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1232 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1233}
1771059c 1234EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1235
24fbb3ca
RK		 1236static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1237 unsigned short vdd)
146ad66e 1238{
3a48edc4 1239 struct mmc_host *mmc = host->mmc;
8364248a 1240 u8 pwr = 0;
146ad66e 1241
24fbb3ca
RK		 1242 if (mode != MMC_POWER_OFF) {
1243 switch (1 << vdd) {
ae628903
PO		 1244 case MMC_VDD_165_195:
1245 pwr = SDHCI_POWER_180;
1246 break;
1247 case MMC_VDD_29_30:
1248 case MMC_VDD_30_31:
1249 pwr = SDHCI_POWER_300;
1250 break;
1251 case MMC_VDD_32_33:
1252 case MMC_VDD_33_34:
1253 pwr = SDHCI_POWER_330;
1254 break;
1255 default:
9d5de93f
AH		 1256 WARN(1, "%s: Invalid vdd %#x\n",
1257 mmc_hostname(host->mmc), vdd);
1258 break;
ae628903
PO		 1259 }
1260 }
1261
1262 if (host->pwr == pwr)
e921a8b6 1263 return;
146ad66e 1264
ae628903
PO		 1265 host->pwr = pwr;
1266
1267 if (pwr == 0) {
4e4141a5 1268 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1269 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1270 sdhci_runtime_pm_bus_off(host);
24fbb3ca 1271 vdd = 0;
e921a8b6
RK		 1272 } else {
1273 /*
1274 * Spec says that we should clear the power reg before setting
1275 * a new value. Some controllers don't seem to like this though.
1276 */
1277 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1278 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1279
e921a8b6
RK		 1280 /*
1281 * At least the Marvell CaFe chip gets confused if we set the
1282 * voltage and set turn on power at the same time, so set the
1283 * voltage first.
1284 */
1285 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1286 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1287
e921a8b6 1288 pwr |= SDHCI_POWER_ON;
146ad66e 1289
e921a8b6 1290 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1291
e921a8b6
RK		 1292 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1293 sdhci_runtime_pm_bus_on(host);
f0710a55 1294
e921a8b6
RK		 1295 /*
1296 * Some controllers need an extra 10ms delay of 10ms before
1297 * they can apply clock after applying power
1298 */
1299 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1300 mdelay(10);
1301 }
918f4cbd
JZ		 1302
1303 if (!IS_ERR(mmc->supply.vmmc)) {
1304 spin_unlock_irq(&host->lock);
1305 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1306 spin_lock_irq(&host->lock);
1307 }
146ad66e
PO		 1308}
1309
d129bceb
PO		 1310/*****************************************************************************\
1311 * *
1312 * MMC callbacks *
1313 * *
1314\*****************************************************************************/
1315
1316static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1317{
1318 struct sdhci_host *host;
505a8680 1319 int present;
d129bceb
PO		 1320 unsigned long flags;
1321
1322 host = mmc_priv(mmc);
1323
66fd8ad5
AH		 1324 sdhci_runtime_pm_get(host);
1325
04e079cf 1326 /* Firstly check card presence */
8d28b7a7 1327 present = mmc->ops->get_cd(mmc);
2836766a 1328
d129bceb
PO		 1329 spin_lock_irqsave(&host->lock, flags);
1330
1331 WARN_ON(host->mrq != NULL);
1332
f9134319 1333#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1334 sdhci_activate_led(host);
2f730fec 1335#endif
e89d456f
AW		 1336
1337 /*
1338 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1339 * requests if Auto-CMD12 is enabled.
1340 */
1341 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1342 if (mrq->stop) {
1343 mrq->data->stop = NULL;
1344 mrq->stop = NULL;
1345 }
1346 }
d129bceb
PO		 1347
1348 host->mrq = mrq;
1349
68d1fb7e 1350 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1351 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1352 tasklet_schedule(&host->finish_tasklet);
cf2b5eea 1353 } else {
8edf6371 1354 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1355 sdhci_send_command(host, mrq->sbc);
1356 else
1357 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1358 }
d129bceb 1359
5f25a66f 1360 mmiowb();
d129bceb
PO		 1361 spin_unlock_irqrestore(&host->lock, flags);
1362}
1363
2317f56c
RK		 1364void sdhci_set_bus_width(struct sdhci_host *host, int width)
1365{
1366 u8 ctrl;
1367
1368 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1369 if (width == MMC_BUS_WIDTH_8) {
1370 ctrl &= ~SDHCI_CTRL_4BITBUS;
1371 if (host->version >= SDHCI_SPEC_300)
1372 ctrl |= SDHCI_CTRL_8BITBUS;
1373 } else {
1374 if (host->version >= SDHCI_SPEC_300)
1375 ctrl &= ~SDHCI_CTRL_8BITBUS;
1376 if (width == MMC_BUS_WIDTH_4)
1377 ctrl |= SDHCI_CTRL_4BITBUS;
1378 else
1379 ctrl &= ~SDHCI_CTRL_4BITBUS;
1380 }
1381 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1382}
1383EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1384
96d7b78c
RK		 1385void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1386{
1387 u16 ctrl_2;
1388
1389 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1390 /* Select Bus Speed Mode for host */
1391 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1392 if ((timing == MMC_TIMING_MMC_HS200) ||
1393 (timing == MMC_TIMING_UHS_SDR104))
1394 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1395 else if (timing == MMC_TIMING_UHS_SDR12)
1396 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1397 else if (timing == MMC_TIMING_UHS_SDR25)
1398 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1399 else if (timing == MMC_TIMING_UHS_SDR50)
1400 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1401 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1402 (timing == MMC_TIMING_MMC_DDR52))
1403 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1404 else if (timing == MMC_TIMING_MMC_HS400)
1405 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1406 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1407}
1408EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1409
66fd8ad5 1410static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1411{
d129bceb
PO		 1412 unsigned long flags;
1413 u8 ctrl;
3a48edc4 1414 struct mmc_host *mmc = host->mmc;
d129bceb 1415
d129bceb
PO		 1416 spin_lock_irqsave(&host->lock, flags);
1417
ceb6143b
AH		 1418 if (host->flags & SDHCI_DEVICE_DEAD) {
1419 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1420 if (!IS_ERR(mmc->supply.vmmc) &&
1421 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1422 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1423 return;
1424 }
1e72859e 1425
d129bceb
PO		 1426 /*
1427 * Reset the chip on each power off.
1428 * Should clear out any weird states.
1429 */
1430 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1431 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1432 sdhci_reinit(host);
d129bceb
PO		 1433 }
1434
52983382 1435 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1436 (ios->power_mode == MMC_POWER_UP) &&
1437 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1438 sdhci_enable_preset_value(host, false);
1439
373073ef 1440 if (!ios->clock || ios->clock != host->clock) {
1771059c 1441 host->ops->set_clock(host, ios->clock);
373073ef 1442 host->clock = ios->clock;
03d6f5ff
AD		 1443
1444 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1445 host->clock) {
1446 host->timeout_clk = host->mmc->actual_clock ?
1447 host->mmc->actual_clock / 1000 :
1448 host->clock / 1000;
1449 host->mmc->max_busy_timeout =
1450 host->ops->get_max_timeout_count ?
1451 host->ops->get_max_timeout_count(host) :
1452 1 << 27;
1453 host->mmc->max_busy_timeout /= host->timeout_clk;
1454 }
373073ef 1455 }
d129bceb 1456
24fbb3ca 1457 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1458
643a81ff
PR		 1459 if (host->ops->platform_send_init_74_clocks)
1460 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1461
2317f56c 1462 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1463
15ec4461 1464 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1465
3ab9c8da
PR		 1466 if ((ios->timing == MMC_TIMING_SD_HS ||
1467 ios->timing == MMC_TIMING_MMC_HS)
1468 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1469 ctrl |= SDHCI_CTRL_HISPD;
1470 else
1471 ctrl &= ~SDHCI_CTRL_HISPD;
1472
d6d50a15 1473 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1474 u16 clk, ctrl_2;
49c468fc
AN		 1475
1476 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1477 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1478 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1479 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1480 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1481 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1482 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1483 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1484 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1485
da91a8f9 1486 if (!host->preset_enabled) {
758535c4 1487 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1488 /*
1489 * We only need to set Driver Strength if the
1490 * preset value enable is not set.
1491 */
da91a8f9 1492 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1493 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1494 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1495 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1496 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1497 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1498 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1499 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1500 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1501 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1502 else {
2e4456f0
MV		 1503 pr_warn("%s: invalid driver type, default to driver type B\n",
1504 mmc_hostname(mmc));
43e943a0
PG		 1505 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1506 }
d6d50a15
AN		 1507
1508 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1509 } else {
1510 /*
1511 * According to SDHC Spec v3.00, if the Preset Value
1512 * Enable in the Host Control 2 register is set, we
1513 * need to reset SD Clock Enable before changing High
1514 * Speed Enable to avoid generating clock gliches.
1515 */
758535c4
AN		 1516
1517 /* Reset SD Clock Enable */
1518 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1519 clk &= ~SDHCI_CLOCK_CARD_EN;
1520 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1521
1522 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1523
1524 /* Re-enable SD Clock */
1771059c 1525 host->ops->set_clock(host, host->clock);
d6d50a15 1526 }
49c468fc 1527
49c468fc
AN		 1528 /* Reset SD Clock Enable */
1529 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1530 clk &= ~SDHCI_CLOCK_CARD_EN;
1531 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1532
96d7b78c 1533 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1534 host->timing = ios->timing;
49c468fc 1535
52983382
KL		 1536 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1537 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1538 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1539 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1540 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 1541 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1542 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 1543 u16 preset;
1544
1545 sdhci_enable_preset_value(host, true);
1546 preset = sdhci_get_preset_value(host);
1547 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1548 >> SDHCI_PRESET_DRV_SHIFT;
1549 }
1550
49c468fc 1551 /* Re-enable SD Clock */
1771059c 1552 host->ops->set_clock(host, host->clock);
758535c4
AN		 1553 } else
1554 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1555
b8352260
LD		 1556 /*
1557 * Some (ENE) controllers go apeshit on some ios operation,
1558 * signalling timeout and CRC errors even on CMD0. Resetting
1559 * it on each ios seems to solve the problem.
1560 */
c63705e1 1561 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1562 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1563
5f25a66f 1564 mmiowb();
d129bceb
PO		 1565 spin_unlock_irqrestore(&host->lock, flags);
1566}
1567
66fd8ad5
AH		 1568static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1569{
1570 struct sdhci_host *host = mmc_priv(mmc);
1571
1572 sdhci_runtime_pm_get(host);
1573 sdhci_do_set_ios(host, ios);
1574 sdhci_runtime_pm_put(host);
1575}
1576
94144a46
KL		 1577static int sdhci_do_get_cd(struct sdhci_host *host)
1578{
1579 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1580
1581 if (host->flags & SDHCI_DEVICE_DEAD)
1582 return 0;
1583
88af5655
II		 1584 /* If nonremovable, assume that the card is always present. */
1585 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
94144a46
KL		 1586 return 1;
1587
88af5655
II		 1588 /*
1589 * Try slot gpio detect, if defined it take precedence
1590 * over build in controller functionality
1591 */
94144a46
KL		 1592 if (!IS_ERR_VALUE(gpio_cd))
1593 return !!gpio_cd;
1594
88af5655
II		 1595 /* If polling, assume that the card is always present. */
1596 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1597 return 1;
1598
94144a46
KL		 1599 /* Host native card detect */
1600 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1601}
1602
1603static int sdhci_get_cd(struct mmc_host *mmc)
1604{
1605 struct sdhci_host *host = mmc_priv(mmc);
1606 int ret;
1607
1608 sdhci_runtime_pm_get(host);
1609 ret = sdhci_do_get_cd(host);
1610 sdhci_runtime_pm_put(host);
1611 return ret;
1612}
1613
66fd8ad5 1614static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1615{
d129bceb 1616 unsigned long flags;
2dfb579c 1617 int is_readonly;
d129bceb 1618
d129bceb
PO		 1619 spin_lock_irqsave(&host->lock, flags);
1620
1e72859e 1621 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1622 is_readonly = 0;
1623 else if (host->ops->get_ro)
1624 is_readonly = host->ops->get_ro(host);
1e72859e 1625 else
2dfb579c
WS		 1626 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1627 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1628
1629 spin_unlock_irqrestore(&host->lock, flags);
1630
2dfb579c
WS		 1631 /* This quirk needs to be replaced by a callback-function later */
1632 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1633 !is_readonly : is_readonly;
d129bceb
PO		 1634}
1635
82b0e23a
TI		 1636#define SAMPLE_COUNT 5
1637
66fd8ad5 1638static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1639{
82b0e23a
TI		 1640 int i, ro_count;
1641
82b0e23a 1642 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1643 return sdhci_check_ro(host);
82b0e23a
TI		 1644
1645 ro_count = 0;
1646 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1647 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1648 if (++ro_count > SAMPLE_COUNT / 2)
1649 return 1;
1650 }
1651 msleep(30);
1652 }
1653 return 0;
1654}
1655
20758b66
AH		 1656static void sdhci_hw_reset(struct mmc_host *mmc)
1657{
1658 struct sdhci_host *host = mmc_priv(mmc);
1659
1660 if (host->ops && host->ops->hw_reset)
1661 host->ops->hw_reset(host);
1662}
1663
66fd8ad5 1664static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1665{
66fd8ad5
AH		 1666 struct sdhci_host *host = mmc_priv(mmc);
1667 int ret;
f75979b7 1668
66fd8ad5
AH		 1669 sdhci_runtime_pm_get(host);
1670 ret = sdhci_do_get_ro(host);
1671 sdhci_runtime_pm_put(host);
1672 return ret;
1673}
f75979b7 1674
66fd8ad5
AH		 1675static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1676{
be138554 1677 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1678 if (enable)
b537f94c 1679 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1680 else
b537f94c
RK		 1681 host->ier &= ~SDHCI_INT_CARD_INT;
1682
1683 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1684 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1685 mmiowb();
1686 }
66fd8ad5
AH		 1687}
1688
1689static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1690{
1691 struct sdhci_host *host = mmc_priv(mmc);
1692 unsigned long flags;
f75979b7 1693
ef104333
RK		 1694 sdhci_runtime_pm_get(host);
1695
66fd8ad5 1696 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1697 if (enable)
1698 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1699 else
1700 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1701
66fd8ad5 1702 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1703 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1704
1705 sdhci_runtime_pm_put(host);
f75979b7
PO		 1706}
1707
20b92a30 1708static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1709 struct mmc_ios *ios)
f2119df6 1710{
3a48edc4 1711 struct mmc_host *mmc = host->mmc;
20b92a30 1712 u16 ctrl;
6231f3de 1713 int ret;
f2119df6 1714
20b92a30
KL		 1715 /*
1716 * Signal Voltage Switching is only applicable for Host Controllers
1717 * v3.00 and above.
1718 */
1719 if (host->version < SDHCI_SPEC_300)
1720 return 0;
6231f3de 1721
f2119df6 1722 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1723
21f5998f 1724 switch (ios->signal_voltage) {
20b92a30
KL		 1725 case MMC_SIGNAL_VOLTAGE_330:
1726 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1727 ctrl &= ~SDHCI_CTRL_VDD_180;
1728 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1729
3a48edc4
TK		 1730 if (!IS_ERR(mmc->supply.vqmmc)) {
1731 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1732 3600000);
20b92a30 1733 if (ret) {
6606110d
JP		 1734 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1735 mmc_hostname(mmc));
20b92a30
KL		 1736 return -EIO;
1737 }
1738 }
1739 /* Wait for 5ms */
1740 usleep_range(5000, 5500);
f2119df6 1741
20b92a30
KL		 1742 /* 3.3V regulator output should be stable within 5 ms */
1743 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1744 if (!(ctrl & SDHCI_CTRL_VDD_180))
1745 return 0;
6231f3de 1746
6606110d
JP		 1747 pr_warn("%s: 3.3V regulator output did not became stable\n",
1748 mmc_hostname(mmc));
20b92a30
KL		 1749
1750 return -EAGAIN;
1751 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1752 if (!IS_ERR(mmc->supply.vqmmc)) {
1753 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1754 1700000, 1950000);
1755 if (ret) {
6606110d
JP		 1756 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1757 mmc_hostname(mmc));
20b92a30
KL		 1758 return -EIO;
1759 }
1760 }
6231f3de 1761
6231f3de
PR		 1762 /*
1763 * Enable 1.8V Signal Enable in the Host Control2
1764 * register
1765 */
20b92a30
KL		 1766 ctrl |= SDHCI_CTRL_VDD_180;
1767 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1768
9d967a61
VY		 1769 /* Some controller need to do more when switching */
1770 if (host->ops->voltage_switch)
1771 host->ops->voltage_switch(host);
1772
20b92a30
KL		 1773 /* 1.8V regulator output should be stable within 5 ms */
1774 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1775 if (ctrl & SDHCI_CTRL_VDD_180)
1776 return 0;
f2119df6 1777
6606110d
JP		 1778 pr_warn("%s: 1.8V regulator output did not became stable\n",
1779 mmc_hostname(mmc));
f2119df6 1780
20b92a30
KL		 1781 return -EAGAIN;
1782 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1783 if (!IS_ERR(mmc->supply.vqmmc)) {
1784 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1785 1300000);
20b92a30 1786 if (ret) {
6606110d
JP		 1787 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1788 mmc_hostname(mmc));
20b92a30 1789 return -EIO;
f2119df6
AN		 1790 }
1791 }
6231f3de 1792 return 0;
20b92a30 1793 default:
f2119df6
AN		 1794 /* No signal voltage switch required */
1795 return 0;
20b92a30 1796 }
f2119df6
AN		 1797}
1798
66fd8ad5 1799static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1800 struct mmc_ios *ios)
66fd8ad5
AH		 1801{
1802 struct sdhci_host *host = mmc_priv(mmc);
1803 int err;
1804
1805 if (host->version < SDHCI_SPEC_300)
1806 return 0;
1807 sdhci_runtime_pm_get(host);
21f5998f 1808 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1809 sdhci_runtime_pm_put(host);
1810 return err;
1811}
1812
20b92a30
KL		 1813static int sdhci_card_busy(struct mmc_host *mmc)
1814{
1815 struct sdhci_host *host = mmc_priv(mmc);
1816 u32 present_state;
1817
1818 sdhci_runtime_pm_get(host);
1819 /* Check whether DAT[3:0] is 0000 */
1820 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1821 sdhci_runtime_pm_put(host);
1822
1823 return !(present_state & SDHCI_DATA_LVL_MASK);
1824}
1825
b5540ce1
AH		 1826static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1827{
1828 struct sdhci_host *host = mmc_priv(mmc);
1829 unsigned long flags;
1830
1831 spin_lock_irqsave(&host->lock, flags);
1832 host->flags |= SDHCI_HS400_TUNING;
1833 spin_unlock_irqrestore(&host->lock, flags);
1834
1835 return 0;
1836}
1837
069c9f14 1838static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1839{
4b6f37d3 1840 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1841 u16 ctrl;
b513ea25 1842 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1843 int err = 0;
2b35bd83 1844 unsigned long flags;
38e40bf5 1845 unsigned int tuning_count = 0;
b5540ce1 1846 bool hs400_tuning;
b513ea25 1847
66fd8ad5 1848 sdhci_runtime_pm_get(host);
2b35bd83 1849 spin_lock_irqsave(&host->lock, flags);
b513ea25 1850
b5540ce1
AH		 1851 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1852 host->flags &= ~SDHCI_HS400_TUNING;
1853
38e40bf5
AH		 1854 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1855 tuning_count = host->tuning_count;
1856
b513ea25 1857 /*
9faac7b9
WY		 1858 * The Host Controller needs tuning in case of SDR104 and DDR50
1859 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1860 * the Capabilities register.
069c9f14
G		 1861 * If the Host Controller supports the HS200 mode then the
1862 * tuning function has to be executed.
b513ea25 1863 */
4b6f37d3 1864 switch (host->timing) {
b5540ce1 1865 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1866 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1867 err = -EINVAL;
1868 goto out_unlock;
1869
4b6f37d3 1870 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1871 /*
1872 * Periodic re-tuning for HS400 is not expected to be needed, so
1873 * disable it here.
1874 */
1875 if (hs400_tuning)
1876 tuning_count = 0;
1877 break;
1878
4b6f37d3 1879 case MMC_TIMING_UHS_SDR104:
9faac7b9 1880 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 1881 break;
1882
1883 case MMC_TIMING_UHS_SDR50:
1884 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1885 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1886 break;
1887 /* FALLTHROUGH */
1888
1889 default:
d519c863 1890 goto out_unlock;
b513ea25
AN		 1891 }
1892
45251812 1893 if (host->ops->platform_execute_tuning) {
2b35bd83 1894 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1895 err = host->ops->platform_execute_tuning(host, opcode);
1896 sdhci_runtime_pm_put(host);
1897 return err;
1898 }
1899
4b6f37d3
RK		 1900 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1901 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 1902 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1903 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 1904 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1905
1906 /*
1907 * As per the Host Controller spec v3.00, tuning command
1908 * generates Buffer Read Ready interrupt, so enable that.
1909 *
1910 * Note: The spec clearly says that when tuning sequence
1911 * is being performed, the controller does not generate
1912 * interrupts other than Buffer Read Ready interrupt. But
1913 * to make sure we don't hit a controller bug, we _only_
1914 * enable Buffer Read Ready interrupt here.
1915 */
b537f94c
RK		 1916 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1917 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1918
1919 /*
1920 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1921 * of loops reaches 40 times or a timeout of 150ms occurs.
1922 */
b513ea25
AN		 1923 do {
1924 struct mmc_command cmd = {0};
66fd8ad5 1925 struct mmc_request mrq = {NULL};
b513ea25 1926
069c9f14 1927 cmd.opcode = opcode;
b513ea25
AN		 1928 cmd.arg = 0;
1929 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1930 cmd.retries = 0;
1931 cmd.data = NULL;
1932 cmd.error = 0;
1933
7ce45e95
AC		 1934 if (tuning_loop_counter-- == 0)
1935 break;
1936
b513ea25
AN		 1937 mrq.cmd = &cmd;
1938 host->mrq = &mrq;
1939
1940 /*
1941 * In response to CMD19, the card sends 64 bytes of tuning
1942 * block to the Host Controller. So we set the block size
1943 * to 64 here.
1944 */
069c9f14
G		 1945 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1946 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1947 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1948 SDHCI_BLOCK_SIZE);
1949 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1950 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1951 SDHCI_BLOCK_SIZE);
1952 } else {
1953 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1954 SDHCI_BLOCK_SIZE);
1955 }
b513ea25
AN		 1956
1957 /*
1958 * The tuning block is sent by the card to the host controller.
1959 * So we set the TRNS_READ bit in the Transfer Mode register.
1960 * This also takes care of setting DMA Enable and Multi Block
1961 * Select in the same register to 0.
1962 */
1963 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1964
1965 sdhci_send_command(host, &cmd);
1966
1967 host->cmd = NULL;
1968 host->mrq = NULL;
1969
2b35bd83 1970 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1971 /* Wait for Buffer Read Ready interrupt */
1972 wait_event_interruptible_timeout(host->buf_ready_int,
1973 (host->tuning_done == 1),
1974 msecs_to_jiffies(50));
2b35bd83 1975 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1976
1977 if (!host->tuning_done) {
2e4456f0 1978 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
b513ea25
AN		 1979 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1980 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1981 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1982 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1983
1984 err = -EIO;
1985 goto out;
1986 }
1987
1988 host->tuning_done = 0;
1989
1990 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 1991
1992 /* eMMC spec does not require a delay between tuning cycles */
1993 if (opcode == MMC_SEND_TUNING_BLOCK)
1994 mdelay(1);
b513ea25
AN		 1995 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1996
1997 /*
1998 * The Host Driver has exhausted the maximum number of loops allowed,
1999 * so use fixed sampling frequency.
2000 */
7ce45e95 2001 if (tuning_loop_counter < 0) {
b513ea25
AN		 2002 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2003 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2004 }
2005 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2e4456f0 2006 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
114f2bf6 2007 err = -EIO;
b513ea25
AN		 2008 }
2009
2010out:
38e40bf5 2011 if (tuning_count) {
66c39dfc
AH		 2012 /*
2013 * In case tuning fails, host controllers which support
2014 * re-tuning can try tuning again at a later time, when the
2015 * re-tuning timer expires. So for these controllers, we
2016 * return 0. Since there might be other controllers who do not
2017 * have this capability, we return error for them.
2018 */
2019 err = 0;
cf2b5eea
AN		 2020 }
2021
66c39dfc 2022 host->mmc->retune_period = err ? 0 : tuning_count;
cf2b5eea 2023
b537f94c
RK		 2024 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2025 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2026out_unlock:
2b35bd83 2027 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2028 sdhci_runtime_pm_put(host);
b513ea25
AN		 2029
2030 return err;
2031}
2032
cb849648
AH		 2033static int sdhci_select_drive_strength(struct mmc_card *card,
2034 unsigned int max_dtr, int host_drv,
2035 int card_drv, int *drv_type)
2036{
2037 struct sdhci_host *host = mmc_priv(card->host);
2038
2039 if (!host->ops->select_drive_strength)
2040 return 0;
2041
2042 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2043 card_drv, drv_type);
2044}
52983382
KL		 2045
2046static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2047{
4d55c5a1
AN		 2048 /* Host Controller v3.00 defines preset value registers */
2049 if (host->version < SDHCI_SPEC_300)
2050 return;
2051
4d55c5a1
AN		 2052 /*
2053 * We only enable or disable Preset Value if they are not already
2054 * enabled or disabled respectively. Otherwise, we bail out.
2055 */
da91a8f9
RK		 2056 if (host->preset_enabled != enable) {
2057 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2058
2059 if (enable)
2060 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2061 else
2062 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2063
4d55c5a1 2064 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2065
2066 if (enable)
2067 host->flags |= SDHCI_PV_ENABLED;
2068 else
2069 host->flags &= ~SDHCI_PV_ENABLED;
2070
2071 host->preset_enabled = enable;
4d55c5a1 2072 }
66fd8ad5
AH		 2073}
2074
348487cb
HC		 2075static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2076 int err)
2077{
2078 struct sdhci_host *host = mmc_priv(mmc);
2079 struct mmc_data *data = mrq->data;
2080
f48f039c 2081 if (data->host_cookie != COOKIE_UNMAPPED)
771a3dc2
RK		 2082 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2083 data->flags & MMC_DATA_WRITE ?
2084 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2085
2086 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2087}
2088
348487cb
HC		 2089static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2090 bool is_first_req)
2091{
2092 struct sdhci_host *host = mmc_priv(mmc);
2093
d31911b9 2094 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2095
2096 if (host->flags & SDHCI_REQ_USE_DMA)
94538e51 2097 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
348487cb
HC		 2098}
2099
71e69211 2100static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2101{
71e69211 2102 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2103 unsigned long flags;
2836766a 2104 int present;
d129bceb 2105
722e1280
CD		 2106 /* First check if client has provided their own card event */
2107 if (host->ops->card_event)
2108 host->ops->card_event(host);
2109
2836766a
KK		 2110 present = sdhci_do_get_cd(host);
2111
d129bceb
PO		 2112 spin_lock_irqsave(&host->lock, flags);
2113
66fd8ad5 2114 /* Check host->mrq first in case we are runtime suspended */
2836766a 2115 if (host->mrq && !present) {
a3c76eb9 2116 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2117 mmc_hostname(host->mmc));
a3c76eb9 2118 pr_err("%s: Resetting controller.\n",
66fd8ad5 2119 mmc_hostname(host->mmc));
d129bceb 2120
03231f9b
RK		 2121 sdhci_do_reset(host, SDHCI_RESET_CMD);
2122 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2123
66fd8ad5
AH		 2124 host->mrq->cmd->error = -ENOMEDIUM;
2125 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2126 }
2127
2128 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2129}
2130
2131static const struct mmc_host_ops sdhci_ops = {
2132 .request = sdhci_request,
348487cb
HC		 2133 .post_req = sdhci_post_req,
2134 .pre_req = sdhci_pre_req,
71e69211 2135 .set_ios = sdhci_set_ios,
94144a46 2136 .get_cd = sdhci_get_cd,
71e69211
GL		 2137 .get_ro = sdhci_get_ro,
2138 .hw_reset = sdhci_hw_reset,
2139 .enable_sdio_irq = sdhci_enable_sdio_irq,
2140 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2141 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2142 .execute_tuning = sdhci_execute_tuning,
cb849648 2143 .select_drive_strength = sdhci_select_drive_strength,
71e69211 2144 .card_event = sdhci_card_event,
20b92a30 2145 .card_busy = sdhci_card_busy,
71e69211
GL		 2146};
2147
2148/*****************************************************************************\
2149 * *
2150 * Tasklets *
2151 * *
2152\*****************************************************************************/
2153
d129bceb
PO		 2154static void sdhci_tasklet_finish(unsigned long param)
2155{
2156 struct sdhci_host *host;
2157 unsigned long flags;
2158 struct mmc_request *mrq;
2159
2160 host = (struct sdhci_host*)param;
2161
66fd8ad5
AH		 2162 spin_lock_irqsave(&host->lock, flags);
2163
0c9c99a7
CB		 2164 /*
2165 * If this tasklet gets rescheduled while running, it will
2166 * be run again afterwards but without any active request.
2167 */
66fd8ad5
AH		 2168 if (!host->mrq) {
2169 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2170 return;
66fd8ad5 2171 }
d129bceb
PO		 2172
2173 del_timer(&host->timer);
2174
2175 mrq = host->mrq;
2176
054cedff
RK		 2177 /*
2178 * Always unmap the data buffers if they were mapped by
2179 * sdhci_prepare_data() whenever we finish with a request.
2180 * This avoids leaking DMA mappings on error.
2181 */
2182 if (host->flags & SDHCI_REQ_USE_DMA) {
2183 struct mmc_data *data = mrq->data;
2184
2185 if (data && data->host_cookie == COOKIE_MAPPED) {
2186 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2187 (data->flags & MMC_DATA_READ) ?
2188 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2189 data->host_cookie = COOKIE_UNMAPPED;
2190 }
2191 }
2192
d129bceb
PO		 2193 /*
2194 * The controller needs a reset of internal state machines
2195 * upon error conditions.
2196 */
1e72859e 2197 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2198 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2199 (mrq->sbc && mrq->sbc->error) ||
2200 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2201 (mrq->data->stop && mrq->data->stop->error))) ||
2202 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2203
2204 /* Some controllers need this kick or reset won't work here */
8213af3b 2205 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2206 /* This is to force an update */
1771059c 2207 host->ops->set_clock(host, host->clock);
645289dc
PO		 2208
2209 /* Spec says we should do both at the same time, but Ricoh
2210 controllers do not like that. */
03231f9b
RK		 2211 sdhci_do_reset(host, SDHCI_RESET_CMD);
2212 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2213 }
2214
2215 host->mrq = NULL;
2216 host->cmd = NULL;
2217 host->data = NULL;
2218
f9134319 2219#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2220 sdhci_deactivate_led(host);
2f730fec 2221#endif
d129bceb 2222
5f25a66f 2223 mmiowb();
d129bceb
PO		 2224 spin_unlock_irqrestore(&host->lock, flags);
2225
2226 mmc_request_done(host->mmc, mrq);
66fd8ad5 2227 sdhci_runtime_pm_put(host);
d129bceb
PO		 2228}
2229
2230static void sdhci_timeout_timer(unsigned long data)
2231{
2232 struct sdhci_host *host;
2233 unsigned long flags;
2234
2235 host = (struct sdhci_host*)data;
2236
2237 spin_lock_irqsave(&host->lock, flags);
2238
2239 if (host->mrq) {
2e4456f0
MV		 2240 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2241 mmc_hostname(host->mmc));
d129bceb
PO		 2242 sdhci_dumpregs(host);
2243
2244 if (host->data) {
17b0429d 2245 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2246 sdhci_finish_data(host);
2247 } else {
2248 if (host->cmd)
17b0429d 2249 host->cmd->error = -ETIMEDOUT;
d129bceb 2250 else
17b0429d 2251 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2252
2253 tasklet_schedule(&host->finish_tasklet);
2254 }
2255 }
2256
5f25a66f 2257 mmiowb();
d129bceb
PO		 2258 spin_unlock_irqrestore(&host->lock, flags);
2259}
2260
2261/*****************************************************************************\
2262 * *
2263 * Interrupt handling *
2264 * *
2265\*****************************************************************************/
2266
61541397 2267static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb
PO		 2268{
2269 BUG_ON(intmask == 0);
2270
2271 if (!host->cmd) {
2e4456f0
MV		 2272 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2273 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2274 sdhci_dumpregs(host);
2275 return;
2276 }
2277
ec014cba
RK		 2278 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2279 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2280 if (intmask & SDHCI_INT_TIMEOUT)
2281 host->cmd->error = -ETIMEDOUT;
2282 else
2283 host->cmd->error = -EILSEQ;
43b58b36 2284
71fcbda0
RK		 2285 /*
2286 * If this command initiates a data phase and a response
2287 * CRC error is signalled, the card can start transferring
2288 * data - the card may have received the command without
2289 * error. We must not terminate the mmc_request early.
2290 *
2291 * If the card did not receive the command or returned an
2292 * error which prevented it sending data, the data phase
2293 * will time out.
2294 */
2295 if (host->cmd->data &&
2296 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2297 SDHCI_INT_CRC) {
2298 host->cmd = NULL;
2299 return;
2300 }
2301
d129bceb 2302 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2303 return;
2304 }
2305
2306 /*
2307 * The host can send and interrupt when the busy state has
2308 * ended, allowing us to wait without wasting CPU cycles.
2309 * Unfortunately this is overloaded on the "data complete"
2310 * interrupt, so we need to take some care when handling
2311 * it.
2312 *
2313 * Note: The 1.0 specification is a bit ambiguous about this
2314 * feature so there might be some problems with older
2315 * controllers.
2316 */
2317 if (host->cmd->flags & MMC_RSP_BUSY) {
2318 if (host->cmd->data)
2e4456f0 2319 DBG("Cannot wait for busy signal when also doing a data transfer");
e99783a4
CM		 2320 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2321 && !host->busy_handle) {
2322 /* Mark that command complete before busy is ended */
2323 host->busy_handle = 1;
e809517f 2324 return;
e99783a4 2325 }
f945405c
BD		 2326
2327 /* The controller does not support the end-of-busy IRQ,
2328 * fall through and take the SDHCI_INT_RESPONSE */
61541397
AH		 2329 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2330 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2331 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2332 }
2333
2334 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2335 sdhci_finish_command(host);
d129bceb
PO		 2336}
2337
0957c333 2338#ifdef CONFIG_MMC_DEBUG
08621b18 2339static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2340{
2341 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2342 void *desc = host->adma_table;
6882a8c0
BD		 2343
2344 sdhci_dumpregs(host);
2345
2346 while (true) {
e57a5f61
AH		 2347 struct sdhci_adma2_64_desc *dma_desc = desc;
2348
2349 if (host->flags & SDHCI_USE_64_BIT_DMA)
2350 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2351 name, desc, le32_to_cpu(dma_desc->addr_hi),
2352 le32_to_cpu(dma_desc->addr_lo),
2353 le16_to_cpu(dma_desc->len),
2354 le16_to_cpu(dma_desc->cmd));
2355 else
2356 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2357 name, desc, le32_to_cpu(dma_desc->addr_lo),
2358 le16_to_cpu(dma_desc->len),
2359 le16_to_cpu(dma_desc->cmd));
6882a8c0 2360
76fe379a 2361 desc += host->desc_sz;
6882a8c0 2362
0545230f 2363 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2364 break;
2365 }
2366}
2367#else
08621b18 2368static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2369#endif
2370
d129bceb
PO		 2371static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2372{
069c9f14 2373 u32 command;
d129bceb
PO		 2374 BUG_ON(intmask == 0);
2375
b513ea25
AN		 2376 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2377 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2378 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2379 if (command == MMC_SEND_TUNING_BLOCK ||
2380 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2381 host->tuning_done = 1;
2382 wake_up(&host->buf_ready_int);
2383 return;
2384 }
2385 }
2386
d129bceb
PO		 2387 if (!host->data) {
2388 /*
e809517f
PO		 2389 * The "data complete" interrupt is also used to
2390 * indicate that a busy state has ended. See comment
2391 * above in sdhci_cmd_irq().
d129bceb 2392 */
e809517f 2393 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2394 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2395 host->cmd->error = -ETIMEDOUT;
2396 tasklet_schedule(&host->finish_tasklet);
2397 return;
2398 }
e809517f 2399 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2400 /*
2401 * Some cards handle busy-end interrupt
2402 * before the command completed, so make
2403 * sure we do things in the proper order.
2404 */
2405 if (host->busy_handle)
2406 sdhci_finish_command(host);
2407 else
2408 host->busy_handle = 1;
e809517f
PO		 2409 return;
2410 }
2411 }
d129bceb 2412
2e4456f0
MV		 2413 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2414 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2415 sdhci_dumpregs(host);
2416
2417 return;
2418 }
2419
2420 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2421 host->data->error = -ETIMEDOUT;
22113efd
AL		 2422 else if (intmask & SDHCI_INT_DATA_END_BIT)
2423 host->data->error = -EILSEQ;
2424 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2425 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2426 != MMC_BUS_TEST_R)
17b0429d 2427 host->data->error = -EILSEQ;
6882a8c0 2428 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2429 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2430 sdhci_adma_show_error(host);
2134a922 2431 host->data->error = -EIO;
a4071fbb
HZ		 2432 if (host->ops->adma_workaround)
2433 host->ops->adma_workaround(host, intmask);
6882a8c0 2434 }
d129bceb 2435
17b0429d 2436 if (host->data->error)
d129bceb
PO		 2437 sdhci_finish_data(host);
2438 else {
a406f5a3 2439 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2440 sdhci_transfer_pio(host);
2441
6ba736a1
PO		 2442 /*
2443 * We currently don't do anything fancy with DMA
2444 * boundaries, but as we can't disable the feature
2445 * we need to at least restart the transfer.
f6a03cbf
MV		 2446 *
2447 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2448 * should return a valid address to continue from, but as
2449 * some controllers are faulty, don't trust them.
6ba736a1 2450 */
f6a03cbf
MV		 2451 if (intmask & SDHCI_INT_DMA_END) {
2452 u32 dmastart, dmanow;
2453 dmastart = sg_dma_address(host->data->sg);
2454 dmanow = dmastart + host->data->bytes_xfered;
2455 /*
2456 * Force update to the next DMA block boundary.
2457 */
2458 dmanow = (dmanow &
2459 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2460 SDHCI_DEFAULT_BOUNDARY_SIZE;
2461 host->data->bytes_xfered = dmanow - dmastart;
2462 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2463 " next 0x%08x\n",
2464 mmc_hostname(host->mmc), dmastart,
2465 host->data->bytes_xfered, dmanow);
2466 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2467 }
6ba736a1 2468
e538fbe8
PO		 2469 if (intmask & SDHCI_INT_DATA_END) {
2470 if (host->cmd) {
2471 /*
2472 * Data managed to finish before the
2473 * command completed. Make sure we do
2474 * things in the proper order.
2475 */
2476 host->data_early = 1;
2477 } else {
2478 sdhci_finish_data(host);
2479 }
2480 }
d129bceb
PO		 2481 }
2482}
2483
7d12e780 2484static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2485{
781e989c 2486 irqreturn_t result = IRQ_NONE;
66fd8ad5 2487 struct sdhci_host *host = dev_id;
41005003 2488 u32 intmask, mask, unexpected = 0;
781e989c 2489 int max_loops = 16;
d129bceb
PO		 2490
2491 spin_lock(&host->lock);
2492
be138554 2493 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2494 spin_unlock(&host->lock);
655bca76 2495 return IRQ_NONE;
66fd8ad5
AH		 2496 }
2497
4e4141a5 2498 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2499 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2500 result = IRQ_NONE;
2501 goto out;
2502 }
2503
41005003
RK		 2504 do {
2505 /* Clear selected interrupts. */
2506 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2507 SDHCI_INT_BUS_POWER);
2508 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2509
41005003
RK		 2510 DBG("*** %s got interrupt: 0x%08x\n",
2511 mmc_hostname(host->mmc), intmask);
d129bceb 2512
41005003
RK		 2513 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2514 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2515 SDHCI_CARD_PRESENT;
d129bceb 2516
41005003
RK		 2517 /*
2518 * There is a observation on i.mx esdhc. INSERT
2519 * bit will be immediately set again when it gets
2520 * cleared, if a card is inserted. We have to mask
2521 * the irq to prevent interrupt storm which will
2522 * freeze the system. And the REMOVE gets the
2523 * same situation.
2524 *
2525 * More testing are needed here to ensure it works
2526 * for other platforms though.
2527 */
b537f94c
RK		 2528 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2529 SDHCI_INT_CARD_REMOVE);
2530 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2531 SDHCI_INT_CARD_INSERT;
2532 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2533 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2534
2535 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2536 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2537
2538 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2539 SDHCI_INT_CARD_REMOVE);
2540 result = IRQ_WAKE_THREAD;
41005003 2541 }
d129bceb 2542
41005003 2543 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2544 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2545 &intmask);
964f9ce2 2546
41005003
RK		 2547 if (intmask & SDHCI_INT_DATA_MASK)
2548 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2549
41005003
RK		 2550 if (intmask & SDHCI_INT_BUS_POWER)
2551 pr_err("%s: Card is consuming too much power!\n",
2552 mmc_hostname(host->mmc));
3192a28f 2553
781e989c
RK		 2554 if (intmask & SDHCI_INT_CARD_INT) {
2555 sdhci_enable_sdio_irq_nolock(host, false);
2556 host->thread_isr |= SDHCI_INT_CARD_INT;
2557 result = IRQ_WAKE_THREAD;
2558 }
f75979b7 2559
41005003
RK		 2560 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2561 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2562 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2563 SDHCI_INT_CARD_INT);
f75979b7 2564
41005003
RK		 2565 if (intmask) {
2566 unexpected |= intmask;
2567 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2568 }
d129bceb 2569
781e989c
RK		 2570 if (result == IRQ_NONE)
2571 result = IRQ_HANDLED;
d129bceb 2572
41005003 2573 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2574 } while (intmask && --max_loops);
d129bceb
PO		 2575out:
2576 spin_unlock(&host->lock);
2577
6379b237
AS		 2578 if (unexpected) {
2579 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2580 mmc_hostname(host->mmc), unexpected);
2581 sdhci_dumpregs(host);
2582 }
f75979b7 2583
d129bceb
PO		 2584 return result;
2585}
2586
781e989c
RK		 2587static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2588{
2589 struct sdhci_host *host = dev_id;
2590 unsigned long flags;
2591 u32 isr;
2592
2593 spin_lock_irqsave(&host->lock, flags);
2594 isr = host->thread_isr;
2595 host->thread_isr = 0;
2596 spin_unlock_irqrestore(&host->lock, flags);
2597
3560db8e
RK		 2598 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2599 sdhci_card_event(host->mmc);
2600 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2601 }
2602
781e989c
RK		 2603 if (isr & SDHCI_INT_CARD_INT) {
2604 sdio_run_irqs(host->mmc);
2605
2606 spin_lock_irqsave(&host->lock, flags);
2607 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2608 sdhci_enable_sdio_irq_nolock(host, true);
2609 spin_unlock_irqrestore(&host->lock, flags);
2610 }
2611
2612 return isr ? IRQ_HANDLED : IRQ_NONE;
2613}
2614
d129bceb
PO		 2615/*****************************************************************************\
2616 * *
2617 * Suspend/resume *
2618 * *
2619\*****************************************************************************/
2620
2621#ifdef CONFIG_PM
ad080d79
KL		 2622void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2623{
2624 u8 val;
2625 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2626 | SDHCI_WAKE_ON_INT;
2627
2628 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2629 val |= mask ;
2630 /* Avoid fake wake up */
2631 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2632 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2633 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2634}
2635EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2636
0b10f478 2637static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2638{
2639 u8 val;
2640 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2641 | SDHCI_WAKE_ON_INT;
2642
2643 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2644 val &= ~mask;
2645 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2646}
d129bceb 2647
29495aa0 2648int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2649{
7260cf5e
AV		 2650 sdhci_disable_card_detection(host);
2651
66c39dfc
AH		 2652 mmc_retune_timer_stop(host->mmc);
2653 mmc_retune_needed(host->mmc);
cf2b5eea 2654
ad080d79 2655 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2656 host->ier = 0;
2657 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2658 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2659 free_irq(host->irq, host);
2660 } else {
2661 sdhci_enable_irq_wakeups(host);
2662 enable_irq_wake(host->irq);
2663 }
4ee14ec6 2664 return 0;
d129bceb
PO		 2665}
2666
b8c86fc5 2667EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2668
b8c86fc5
PO		 2669int sdhci_resume_host(struct sdhci_host *host)
2670{
4ee14ec6 2671 int ret = 0;
d129bceb 2672
a13abc7b 2673 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2674 if (host->ops->enable_dma)
2675 host->ops->enable_dma(host);
2676 }
d129bceb 2677
6308d290
AH		 2678 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2679 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2680 /* Card keeps power but host controller does not */
2681 sdhci_init(host, 0);
2682 host->pwr = 0;
2683 host->clock = 0;
2684 sdhci_do_set_ios(host, &host->mmc->ios);
2685 } else {
2686 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2687 mmiowb();
2688 }
b8c86fc5 2689
14a7b416
HC		 2690 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2691 ret = request_threaded_irq(host->irq, sdhci_irq,
2692 sdhci_thread_irq, IRQF_SHARED,
2693 mmc_hostname(host->mmc), host);
2694 if (ret)
2695 return ret;
2696 } else {
2697 sdhci_disable_irq_wakeups(host);
2698 disable_irq_wake(host->irq);
2699 }
2700
7260cf5e
AV		 2701 sdhci_enable_card_detection(host);
2702
2f4cbb3d 2703 return ret;
d129bceb
PO		 2704}
2705
b8c86fc5 2706EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5
AH		 2707
2708static int sdhci_runtime_pm_get(struct sdhci_host *host)
2709{
2710 return pm_runtime_get_sync(host->mmc->parent);
2711}
2712
2713static int sdhci_runtime_pm_put(struct sdhci_host *host)
2714{
2715 pm_runtime_mark_last_busy(host->mmc->parent);
2716 return pm_runtime_put_autosuspend(host->mmc->parent);
2717}
2718
f0710a55
AH		 2719static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2720{
5c671c41 2721 if (host->bus_on)
f0710a55
AH		 2722 return;
2723 host->bus_on = true;
2724 pm_runtime_get_noresume(host->mmc->parent);
2725}
2726
2727static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2728{
5c671c41 2729 if (!host->bus_on)
f0710a55
AH		 2730 return;
2731 host->bus_on = false;
2732 pm_runtime_put_noidle(host->mmc->parent);
2733}
2734
66fd8ad5
AH		 2735int sdhci_runtime_suspend_host(struct sdhci_host *host)
2736{
2737 unsigned long flags;
66fd8ad5 2738
66c39dfc
AH		 2739 mmc_retune_timer_stop(host->mmc);
2740 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2741
2742 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2743 host->ier &= SDHCI_INT_CARD_INT;
2744 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2745 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2746 spin_unlock_irqrestore(&host->lock, flags);
2747
781e989c 2748 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2749
2750 spin_lock_irqsave(&host->lock, flags);
2751 host->runtime_suspended = true;
2752 spin_unlock_irqrestore(&host->lock, flags);
2753
8a125bad 2754 return 0;
66fd8ad5
AH		 2755}
2756EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2757
2758int sdhci_runtime_resume_host(struct sdhci_host *host)
2759{
2760 unsigned long flags;
8a125bad 2761 int host_flags = host->flags;
66fd8ad5
AH		 2762
2763 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2764 if (host->ops->enable_dma)
2765 host->ops->enable_dma(host);
2766 }
2767
2768 sdhci_init(host, 0);
2769
2770 /* Force clock and power re-program */
2771 host->pwr = 0;
2772 host->clock = 0;
3396e736 2773 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
66fd8ad5
AH		 2774 sdhci_do_set_ios(host, &host->mmc->ios);
2775
52983382
KL		 2776 if ((host_flags & SDHCI_PV_ENABLED) &&
2777 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2778 spin_lock_irqsave(&host->lock, flags);
2779 sdhci_enable_preset_value(host, true);
2780 spin_unlock_irqrestore(&host->lock, flags);
2781 }
66fd8ad5 2782
66fd8ad5
AH		 2783 spin_lock_irqsave(&host->lock, flags);
2784
2785 host->runtime_suspended = false;
2786
2787 /* Enable SDIO IRQ */
ef104333 2788 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2789 sdhci_enable_sdio_irq_nolock(host, true);
2790
2791 /* Enable Card Detection */
2792 sdhci_enable_card_detection(host);
2793
2794 spin_unlock_irqrestore(&host->lock, flags);
2795
8a125bad 2796 return 0;
66fd8ad5
AH		 2797}
2798EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2799
162d6f98 2800#endif /* CONFIG_PM */
66fd8ad5 2801
d129bceb
PO		 2802/*****************************************************************************\
2803 * *
b8c86fc5 2804 * Device allocation/registration *
d129bceb
PO		 2805 * *
2806\*****************************************************************************/
2807
b8c86fc5
PO		 2808struct sdhci_host *sdhci_alloc_host(struct device *dev,
2809 size_t priv_size)
d129bceb 2810{
d129bceb
PO		 2811 struct mmc_host *mmc;
2812 struct sdhci_host *host;
2813
b8c86fc5 2814 WARN_ON(dev == NULL);
d129bceb 2815
b8c86fc5 2816 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2817 if (!mmc)
b8c86fc5 2818 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2819
2820 host = mmc_priv(mmc);
2821 host->mmc = mmc;
bf60e592
AH		 2822 host->mmc_host_ops = sdhci_ops;
2823 mmc->ops = &host->mmc_host_ops;
d129bceb 2824
b8c86fc5
PO		 2825 return host;
2826}
8a4da143 2827
b8c86fc5 2828EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2829
b8c86fc5
PO		 2830int sdhci_add_host(struct sdhci_host *host)
2831{
2832 struct mmc_host *mmc;
bd6a8c30 2833 u32 caps[2] = {0, 0};
f2119df6
AN		 2834 u32 max_current_caps;
2835 unsigned int ocr_avail;
f5fa92e5 2836 unsigned int override_timeout_clk;
59241757 2837 u32 max_clk;
b8c86fc5 2838 int ret;
d129bceb 2839
b8c86fc5
PO		 2840 WARN_ON(host == NULL);
2841 if (host == NULL)
2842 return -EINVAL;
d129bceb 2843
b8c86fc5 2844 mmc = host->mmc;
d129bceb 2845
b8c86fc5
PO		 2846 if (debug_quirks)
2847 host->quirks = debug_quirks;
66fd8ad5
AH		 2848 if (debug_quirks2)
2849 host->quirks2 = debug_quirks2;
d129bceb 2850
f5fa92e5
AH		 2851 override_timeout_clk = host->timeout_clk;
2852
03231f9b 2853 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2854
4e4141a5 2855 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2856 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2857 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2858 if (host->version > SDHCI_SPEC_300) {
2e4456f0
MV		 2859 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2860 mmc_hostname(mmc), host->version);
4a965505
PO		 2861 }
2862
f2119df6 2863 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2864 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2865
bd6a8c30
PR		 2866 if (host->version >= SDHCI_SPEC_300)
2867 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2868 host->caps1 :
2869 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2870
b8c86fc5 2871 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2872 host->flags |= SDHCI_USE_SDMA;
f2119df6 2873 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2874 DBG("Controller doesn't have SDMA capability\n");
67435274 2875 else
a13abc7b 2876 host->flags |= SDHCI_USE_SDMA;
d129bceb 2877
b8c86fc5 2878 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2879 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2880 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2881 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2882 }
2883
f2119df6
AN		 2884 if ((host->version >= SDHCI_SPEC_200) &&
2885 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2886 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2887
2888 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2889 (host->flags & SDHCI_USE_ADMA)) {
2890 DBG("Disabling ADMA as it is marked broken\n");
2891 host->flags &= ~SDHCI_USE_ADMA;
2892 }
2893
e57a5f61
AH		 2894 /*
2895 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2896 * and *must* do 64-bit DMA. A driver has the opportunity to change
2897 * that during the first call to ->enable_dma(). Similarly
2898 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2899 * implement.
2900 */
5eaa7476 2901 if (caps[0] & SDHCI_CAN_64BIT)
e57a5f61
AH		 2902 host->flags |= SDHCI_USE_64_BIT_DMA;
2903
a13abc7b 2904 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2905 if (host->ops->enable_dma) {
2906 if (host->ops->enable_dma(host)) {
6606110d 2907 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
b8c86fc5 2908 mmc_hostname(mmc));
a13abc7b
RR		 2909 host->flags &=
2910 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2911 }
d129bceb
PO		 2912 }
2913 }
2914
e57a5f61
AH		 2915 /* SDMA does not support 64-bit DMA */
2916 if (host->flags & SDHCI_USE_64_BIT_DMA)
2917 host->flags &= ~SDHCI_USE_SDMA;
2918
2134a922 2919 if (host->flags & SDHCI_USE_ADMA) {
e66e61cb
RK		 2920 dma_addr_t dma;
2921 void *buf;
2922
2134a922 2923 /*
76fe379a
AH		 2924 * The DMA descriptor table size is calculated as the maximum
2925 * number of segments times 2, to allow for an alignment
2926 * descriptor for each segment, plus 1 for a nop end descriptor,
2927 * all multipled by the descriptor size.
2134a922 2928 */
e57a5f61
AH		 2929 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2930 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2931 SDHCI_ADMA2_64_DESC_SZ;
e57a5f61 2932 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
e57a5f61
AH		 2933 } else {
2934 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2935 SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2936 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2937 }
e66e61cb 2938
04a5ae6f 2939 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
e66e61cb
RK		 2940 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
2941 host->adma_table_sz, &dma, GFP_KERNEL);
2942 if (!buf) {
6606110d 2943 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 2944 mmc_hostname(mmc));
2945 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 2946 } else if ((dma + host->align_buffer_sz) &
2947 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 2948 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2949 mmc_hostname(mmc));
d1e49f77 2950 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 2951 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
2952 host->adma_table_sz, buf, dma);
2953 } else {
2954 host->align_buffer = buf;
2955 host->align_addr = dma;
edd63fcc 2956
e66e61cb
RK		 2957 host->adma_table = buf + host->align_buffer_sz;
2958 host->adma_addr = dma + host->align_buffer_sz;
2959 }
2134a922
PO		 2960 }
2961
7659150c
PO		 2962 /*
2963 * If we use DMA, then it's up to the caller to set the DMA
2964 * mask, but PIO does not need the hw shim so we set a new
2965 * mask here in that case.
2966 */
a13abc7b 2967 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 2968 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 2969 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 2970 }
d129bceb 2971
c4687d5f 2972 if (host->version >= SDHCI_SPEC_300)
f2119df6 2973 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2974 >> SDHCI_CLOCK_BASE_SHIFT;
2975 else
f2119df6 2976 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2977 >> SDHCI_CLOCK_BASE_SHIFT;
2978
4240ff0a 2979 host->max_clk *= 1000000;
f27f47ef
AV		 2980 if (host->max_clk == 0 || host->quirks &
2981 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2982 if (!host->ops->get_max_clock) {
2e4456f0
MV		 2983 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
2984 mmc_hostname(mmc));
4240ff0a
BD		 2985 return -ENODEV;
2986 }
2987 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2988 }
d129bceb 2989
c3ed3877
AN		 2990 /*
2991 * In case of Host Controller v3.00, find out whether clock
2992 * multiplier is supported.
2993 */
2994 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2995 SDHCI_CLOCK_MUL_SHIFT;
2996
2997 /*
2998 * In case the value in Clock Multiplier is 0, then programmable
2999 * clock mode is not supported, otherwise the actual clock
3000 * multiplier is one more than the value of Clock Multiplier
3001 * in the Capabilities Register.
3002 */
3003 if (host->clk_mul)
3004 host->clk_mul += 1;
3005
d129bceb
PO		 3006 /*
3007 * Set host parameters.
3008 */
59241757
DA		 3009 max_clk = host->max_clk;
3010
ce5f036b 3011 if (host->ops->get_min_clock)
a9e58f25 3012 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3013 else if (host->version >= SDHCI_SPEC_300) {
3014 if (host->clk_mul) {
3015 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3016 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3017 } else
3018 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3019 } else
0397526d 3020 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3021
59241757
DA		 3022 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3023 mmc->f_max = max_clk;
3024
28aab053
AD		 3025 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3026 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3027 SDHCI_TIMEOUT_CLK_SHIFT;
3028 if (host->timeout_clk == 0) {
3029 if (host->ops->get_timeout_clock) {
3030 host->timeout_clk =
3031 host->ops->get_timeout_clock(host);
3032 } else {
3033 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3034 mmc_hostname(mmc));
3035 return -ENODEV;
3036 }
272308ca 3037 }
272308ca 3038
28aab053
AD		 3039 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3040 host->timeout_clk *= 1000;
272308ca 3041
28aab053 3042 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3043 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3044 mmc->max_busy_timeout /= host->timeout_clk;
3045 }
58d1246d 3046
f5fa92e5
AH		 3047 if (override_timeout_clk)
3048 host->timeout_clk = override_timeout_clk;
3049
e89d456f 3050 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3051 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3052
3053 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3054 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3055
8edf6371 3056 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3057 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3058 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3059 !(host->flags & SDHCI_USE_SDMA)) &&
3060 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3061 host->flags |= SDHCI_AUTO_CMD23;
3062 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3063 } else {
3064 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3065 }
3066
15ec4461
PR		 3067 /*
3068 * A controller may support 8-bit width, but the board itself
3069 * might not have the pins brought out. Boards that support
3070 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3071 * their platform code before calling sdhci_add_host(), and we
3072 * won't assume 8-bit width for hosts without that CAP.
3073 */
5fe23c7f 3074 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3075 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3076
63ef5d8c
JH		 3077 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3078 mmc->caps &= ~MMC_CAP_CMD23;
3079
f2119df6 3080 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 3081 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3082
176d1ed4 3083 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
c31d22eb
II		 3084 !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3085 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
68d1fb7e
AV		 3086 mmc->caps |= MMC_CAP_NEEDS_POLL;
3087
3a48edc4
TK		 3088 /* If there are external regulators, get them */
3089 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3090 return -EPROBE_DEFER;
3091
6231f3de 3092 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3093 if (!IS_ERR(mmc->supply.vqmmc)) {
3094 ret = regulator_enable(mmc->supply.vqmmc);
3095 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3096 1950000))
8363c374
KL		 3097 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3098 SDHCI_SUPPORT_SDR50 |
3099 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3100 if (ret) {
3101 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3102 mmc_hostname(mmc), ret);
4bb74313 3103 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3104 }
8363c374 3105 }
6231f3de 3106
6a66180a
DD		 3107 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3108 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3109 SDHCI_SUPPORT_DDR50);
3110
4188bba0
AC		 3111 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3112 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3113 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3114 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3115
3116 /* SDR104 supports also implies SDR50 support */
156e14b1 3117 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3118 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3119 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3120 * field can be promoted to support HS200.
3121 */
549c0b18 3122 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3123 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3124 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3125 mmc->caps |= MMC_CAP_UHS_SDR50;
3126
e9fb05d5
AH		 3127 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3128 (caps[1] & SDHCI_SUPPORT_HS400))
3129 mmc->caps2 |= MMC_CAP2_HS400;
3130
549c0b18
AH		 3131 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3132 (IS_ERR(mmc->supply.vqmmc) ||
3133 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3134 1300000)))
3135 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3136
9107ebbf
MC		 3137 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3138 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3139 mmc->caps |= MMC_CAP_UHS_DDR50;
3140
069c9f14 3141 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3142 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3143 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3144
156e14b1 3145 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3146 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3147 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3148
d6d50a15
AN		 3149 /* Driver Type(s) (A, C, D) supported by the host */
3150 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3151 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3152 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3153 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3154 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3155 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3156
cf2b5eea
AN		 3157 /* Initial value for re-tuning timer count */
3158 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3159 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3160
3161 /*
3162 * In case Re-tuning Timer is not disabled, the actual value of
3163 * re-tuning timer will be 2 ^ (n - 1).
3164 */
3165 if (host->tuning_count)
3166 host->tuning_count = 1 << (host->tuning_count - 1);
3167
3168 /* Re-tuning mode supported by the Host Controller */
3169 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3170 SDHCI_RETUNING_MODE_SHIFT;
3171
8f230f45 3172 ocr_avail = 0;
bad37e1a 3173
f2119df6
AN		 3174 /*
3175 * According to SD Host Controller spec v3.00, if the Host System
3176 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3177 * the value is meaningful only if Voltage Support in the Capabilities
3178 * register is set. The actual current value is 4 times the register
3179 * value.
3180 */
3181 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3182 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3183 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3184 if (curr > 0) {
3185
3186 /* convert to SDHCI_MAX_CURRENT format */
3187 curr = curr/1000; /* convert to mA */
3188 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3189
3190 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3191 max_current_caps =
3192 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3193 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3194 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3195 }
3196 }
f2119df6
AN		 3197
3198 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3199 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3200
55c4665e 3201 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3202 SDHCI_MAX_CURRENT_330_MASK) >>
3203 SDHCI_MAX_CURRENT_330_SHIFT) *
3204 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3205 }
3206 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3207 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3208
55c4665e 3209 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3210 SDHCI_MAX_CURRENT_300_MASK) >>
3211 SDHCI_MAX_CURRENT_300_SHIFT) *
3212 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3213 }
3214 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3215 ocr_avail |= MMC_VDD_165_195;
3216
55c4665e 3217 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3218 SDHCI_MAX_CURRENT_180_MASK) >>
3219 SDHCI_MAX_CURRENT_180_SHIFT) *
3220 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3221 }
3222
5fd26c7e
UH		 3223 /* If OCR set by host, use it instead. */
3224 if (host->ocr_mask)
3225 ocr_avail = host->ocr_mask;
3226
3227 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3228 if (mmc->ocr_avail)
52221610 3229 ocr_avail = mmc->ocr_avail;
3a48edc4 3230
8f230f45
TI		 3231 mmc->ocr_avail = ocr_avail;
3232 mmc->ocr_avail_sdio = ocr_avail;
3233 if (host->ocr_avail_sdio)
3234 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3235 mmc->ocr_avail_sd = ocr_avail;
3236 if (host->ocr_avail_sd)
3237 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3238 else /* normal SD controllers don't support 1.8V */
3239 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3240 mmc->ocr_avail_mmc = ocr_avail;
3241 if (host->ocr_avail_mmc)
3242 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3243
3244 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 3245 pr_err("%s: Hardware doesn't report any support voltages.\n",
3246 mmc_hostname(mmc));
b8c86fc5 3247 return -ENODEV;
146ad66e
PO		 3248 }
3249
d129bceb
PO		 3250 spin_lock_init(&host->lock);
3251
3252 /*
2134a922
PO		 3253 * Maximum number of segments. Depends on if the hardware
3254 * can do scatter/gather or not.
d129bceb 3255 */
2134a922 3256 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3257 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3258 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3259 mmc->max_segs = 1;
2134a922 3260 else /* PIO */
4fb213f8 3261 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3262
3263 /*
ac00531d
AH		 3264 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3265 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3266 * is less anyway.
d129bceb 3267 */
55db890a 3268 mmc->max_req_size = 524288;
d129bceb
PO		 3269
3270 /*
3271 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3272 * of bytes. When doing hardware scatter/gather, each entry cannot
3273 * be larger than 64 KiB though.
d129bceb 3274 */
30652aa3
OJ		 3275 if (host->flags & SDHCI_USE_ADMA) {
3276 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3277 mmc->max_seg_size = 65535;
3278 else
3279 mmc->max_seg_size = 65536;
3280 } else {
2134a922 3281 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3282 }
d129bceb 3283
fe4a3c7a
PO		 3284 /*
3285 * Maximum block size. This varies from controller to controller and
3286 * is specified in the capabilities register.
3287 */
0633f654
AV		 3288 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3289 mmc->max_blk_size = 2;
3290 } else {
f2119df6 3291 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3292 SDHCI_MAX_BLOCK_SHIFT;
3293 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3294 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3295 mmc_hostname(mmc));
0633f654
AV		 3296 mmc->max_blk_size = 0;
3297 }
3298 }
3299
3300 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3301
55db890a
PO		 3302 /*
3303 * Maximum block count.
3304 */
1388eefd 3305 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3306
d129bceb
PO		 3307 /*
3308 * Init tasklets.
3309 */
d129bceb
PO		 3310 tasklet_init(&host->finish_tasklet,
3311 sdhci_tasklet_finish, (unsigned long)host);
3312
e4cad1b5 3313 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3314
250fb7b4 3315 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3316
2af502ca
SG		 3317 sdhci_init(host, 0);
3318
781e989c
RK		 3319 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3320 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3321 if (ret) {
3322 pr_err("%s: Failed to request IRQ %d: %d\n",
3323 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3324 goto untasklet;
0fc81ee3 3325 }
d129bceb 3326
d129bceb
PO		 3327#ifdef CONFIG_MMC_DEBUG
3328 sdhci_dumpregs(host);
3329#endif
3330
f9134319 3331#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3332 snprintf(host->led_name, sizeof(host->led_name),
3333 "%s::", mmc_hostname(mmc));
3334 host->led.name = host->led_name;
2f730fec
PO		 3335 host->led.brightness = LED_OFF;
3336 host->led.default_trigger = mmc_hostname(mmc);
3337 host->led.brightness_set = sdhci_led_control;
3338
b8c86fc5 3339 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3340 if (ret) {
3341 pr_err("%s: Failed to register LED device: %d\n",
3342 mmc_hostname(mmc), ret);
2f730fec 3343 goto reset;
0fc81ee3 3344 }
2f730fec
PO		 3345#endif
3346
5f25a66f
PO		 3347 mmiowb();
3348
d129bceb
PO		 3349 mmc_add_host(mmc);
3350
a3c76eb9 3351 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3352 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3353 (host->flags & SDHCI_USE_ADMA) ?
3354 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3355 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3356
7260cf5e
AV		 3357 sdhci_enable_card_detection(host);
3358
d129bceb
PO		 3359 return 0;
3360
f9134319 3361#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3362reset:
03231f9b 3363 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3364 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3365 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3366 free_irq(host->irq, host);
3367#endif
8ef1a143 3368untasklet:
d129bceb 3369 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3370
3371 return ret;
3372}
3373
b8c86fc5 3374EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3375
1e72859e 3376void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3377{
3a48edc4 3378 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3379 unsigned long flags;
3380
3381 if (dead) {
3382 spin_lock_irqsave(&host->lock, flags);
3383
3384 host->flags |= SDHCI_DEVICE_DEAD;
3385
3386 if (host->mrq) {
a3c76eb9 3387 pr_err("%s: Controller removed during "
4e743f1f 3388 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3389
3390 host->mrq->cmd->error = -ENOMEDIUM;
3391 tasklet_schedule(&host->finish_tasklet);
3392 }
3393
3394 spin_unlock_irqrestore(&host->lock, flags);
3395 }
3396
7260cf5e
AV		 3397 sdhci_disable_card_detection(host);
3398
4e743f1f 3399 mmc_remove_host(mmc);
d129bceb 3400
f9134319 3401#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3402 led_classdev_unregister(&host->led);
3403#endif
3404
1e72859e 3405 if (!dead)
03231f9b 3406 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3407
b537f94c
RK		 3408 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3409 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3410 free_irq(host->irq, host);
3411
3412 del_timer_sync(&host->timer);
3413
d129bceb 3414 tasklet_kill(&host->finish_tasklet);
2134a922 3415
3a48edc4
TK		 3416 if (!IS_ERR(mmc->supply.vqmmc))
3417 regulator_disable(mmc->supply.vqmmc);
6231f3de 3418
edd63fcc 3419 if (host->align_buffer)
e66e61cb
RK		 3420 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3421 host->adma_table_sz, host->align_buffer,
3422 host->align_addr);
2134a922 3423
4efaa6fb 3424 host->adma_table = NULL;
2134a922 3425 host->align_buffer = NULL;
d129bceb
PO		 3426}
3427
b8c86fc5 3428EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3429
b8c86fc5 3430void sdhci_free_host(struct sdhci_host *host)
d129bceb 3431{
b8c86fc5 3432 mmc_free_host(host->mmc);
d129bceb
PO		 3433}
3434
b8c86fc5 3435EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3436
3437/*****************************************************************************\
3438 * *
3439 * Driver init/exit *
3440 * *
3441\*****************************************************************************/
3442
3443static int __init sdhci_drv_init(void)
3444{
a3c76eb9 3445 pr_info(DRIVER_NAME
52fbf9c9 3446 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3447 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3448
b8c86fc5 3449 return 0;
d129bceb
PO		 3450}
3451
3452static void __exit sdhci_drv_exit(void)
3453{
d129bceb
PO		 3454}
3455
3456module_init(sdhci_drv_init);
3457module_exit(sdhci_drv_exit);
3458
df673b22 3459module_param(debug_quirks, uint, 0444);
66fd8ad5 3460module_param(debug_quirks2, uint, 0444);
67435274 3461
32710e8f 3462MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3463MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3464MODULE_LICENSE("GPL");
67435274 3465
df673b22 3466MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3467MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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