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mmc: core: HS200 mode support for eMMC 4.5
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
d129bceb 30
d129bceb
PO		 31#include "sdhci.h"
32
33#define DRIVER_NAME "sdhci"
d129bceb 34
d129bceb 35#define DBG(f, x...) \
c6563178 36 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 37
f9134319
PO		 38#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
39 defined(CONFIG_MMC_SDHCI_MODULE))
40#define SDHCI_USE_LEDS_CLASS
41#endif
42
b513ea25
AN		 43#define MAX_TUNING_LOOP 40
44
df673b22 45static unsigned int debug_quirks = 0;
66fd8ad5 46static unsigned int debug_quirks2;
67435274 47
d129bceb
PO		 48static void sdhci_finish_data(struct sdhci_host *);
49
50static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
51static void sdhci_finish_command(struct sdhci_host *);
cf2b5eea
AN		 52static int sdhci_execute_tuning(struct mmc_host *mmc);
53static void sdhci_tuning_timer(unsigned long data);
d129bceb 54
66fd8ad5
AH		 55#ifdef CONFIG_PM_RUNTIME
56static int sdhci_runtime_pm_get(struct sdhci_host *host);
57static int sdhci_runtime_pm_put(struct sdhci_host *host);
58#else
59static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
60{
61 return 0;
62}
63static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
64{
65 return 0;
66}
67#endif
68
d129bceb
PO		 69static void sdhci_dumpregs(struct sdhci_host *host)
70{
a3c76eb9 71 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 72 mmc_hostname(host->mmc));
d129bceb 73
a3c76eb9 74 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 75 sdhci_readl(host, SDHCI_DMA_ADDRESS),
76 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 77 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 78 sdhci_readw(host, SDHCI_BLOCK_SIZE),
79 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 80 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 81 sdhci_readl(host, SDHCI_ARGUMENT),
82 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 83 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 84 sdhci_readl(host, SDHCI_PRESENT_STATE),
85 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 86 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 87 sdhci_readb(host, SDHCI_POWER_CONTROL),
88 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 89 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 90 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
91 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 92 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 93 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
94 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 95 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 96 sdhci_readl(host, SDHCI_INT_ENABLE),
97 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 98 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 99 sdhci_readw(host, SDHCI_ACMD12_ERR),
100 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 101 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 102 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 103 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 104 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 105 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 106 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 107 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 108 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 109
be3f4ae0 110 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 111 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 112 readl(host->ioaddr + SDHCI_ADMA_ERROR),
113 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
114
a3c76eb9 115 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 116}
117
118/*****************************************************************************\
119 * *
120 * Low level functions *
121 * *
122\*****************************************************************************/
123
7260cf5e
AV		 124static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
125{
126 u32 ier;
127
128 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
129 ier &= ~clear;
130 ier |= set;
131 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
132 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
133}
134
135static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
136{
137 sdhci_clear_set_irqs(host, 0, irqs);
138}
139
140static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
141{
142 sdhci_clear_set_irqs(host, irqs, 0);
143}
144
145static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
146{
d25928d1 147 u32 present, irqs;
7260cf5e 148
c79396c1 149 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
c79396c1 150 !mmc_card_is_removable(host->mmc))
66fd8ad5
AH		 151 return;
152
d25928d1
SG		 153 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
154 SDHCI_CARD_PRESENT;
155 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
156
7260cf5e
AV		 157 if (enable)
158 sdhci_unmask_irqs(host, irqs);
159 else
160 sdhci_mask_irqs(host, irqs);
161}
162
163static void sdhci_enable_card_detection(struct sdhci_host *host)
164{
165 sdhci_set_card_detection(host, true);
166}
167
168static void sdhci_disable_card_detection(struct sdhci_host *host)
169{
170 sdhci_set_card_detection(host, false);
171}
172
d129bceb
PO		 173static void sdhci_reset(struct sdhci_host *host, u8 mask)
174{
e16514d8 175 unsigned long timeout;
063a9dbb 176 u32 uninitialized_var(ier);
e16514d8 177
b8c86fc5 178 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 179 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 180 SDHCI_CARD_PRESENT))
181 return;
182 }
183
063a9dbb
AV		 184 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
185 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
186
393c1a34
PR		 187 if (host->ops->platform_reset_enter)
188 host->ops->platform_reset_enter(host, mask);
189
4e4141a5 190 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 191
e16514d8 192 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 193 host->clock = 0;
194
e16514d8
PO		 195 /* Wait max 100 ms */
196 timeout = 100;
197
198 /* hw clears the bit when it's done */
4e4141a5 199 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 200 if (timeout == 0) {
a3c76eb9 201 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 202 mmc_hostname(host->mmc), (int)mask);
203 sdhci_dumpregs(host);
204 return;
205 }
206 timeout--;
207 mdelay(1);
d129bceb 208 }
063a9dbb 209
393c1a34
PR		 210 if (host->ops->platform_reset_exit)
211 host->ops->platform_reset_exit(host, mask);
212
063a9dbb
AV		 213 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
214 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
d129bceb
PO		 215}
216
2f4cbb3d
NP		 217static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
218
219static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 220{
2f4cbb3d
NP		 221 if (soft)
222 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
223 else
224 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 225
7260cf5e
AV		 226 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
227 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 228 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
229 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 230 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 231
232 if (soft) {
233 /* force clock reconfiguration */
234 host->clock = 0;
235 sdhci_set_ios(host->mmc, &host->mmc->ios);
236 }
7260cf5e 237}
d129bceb 238
7260cf5e
AV		 239static void sdhci_reinit(struct sdhci_host *host)
240{
2f4cbb3d 241 sdhci_init(host, 0);
7260cf5e 242 sdhci_enable_card_detection(host);
d129bceb
PO		 243}
244
245static void sdhci_activate_led(struct sdhci_host *host)
246{
247 u8 ctrl;
248
4e4141a5 249 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 250 ctrl |= SDHCI_CTRL_LED;
4e4141a5 251 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 252}
253
254static void sdhci_deactivate_led(struct sdhci_host *host)
255{
256 u8 ctrl;
257
4e4141a5 258 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 259 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 260 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 261}
262
f9134319 263#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 264static void sdhci_led_control(struct led_classdev *led,
265 enum led_brightness brightness)
266{
267 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
268 unsigned long flags;
269
270 spin_lock_irqsave(&host->lock, flags);
271
66fd8ad5
AH		 272 if (host->runtime_suspended)
273 goto out;
274
2f730fec
PO		 275 if (brightness == LED_OFF)
276 sdhci_deactivate_led(host);
277 else
278 sdhci_activate_led(host);
66fd8ad5 279out:
2f730fec
PO		 280 spin_unlock_irqrestore(&host->lock, flags);
281}
282#endif
283
d129bceb
PO		 284/*****************************************************************************\
285 * *
286 * Core functions *
287 * *
288\*****************************************************************************/
289
a406f5a3 290static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 291{
7659150c
PO		 292 unsigned long flags;
293 size_t blksize, len, chunk;
7244b85b 294 u32 uninitialized_var(scratch);
7659150c 295 u8 *buf;
d129bceb 296
a406f5a3 297 DBG("PIO reading\n");
d129bceb 298
a406f5a3 299 blksize = host->data->blksz;
7659150c 300 chunk = 0;
d129bceb 301
7659150c 302 local_irq_save(flags);
d129bceb 303
a406f5a3 304 while (blksize) {
7659150c
PO		 305 if (!sg_miter_next(&host->sg_miter))
306 BUG();
d129bceb 307
7659150c 308 len = min(host->sg_miter.length, blksize);
d129bceb 309
7659150c
PO		 310 blksize -= len;
311 host->sg_miter.consumed = len;
14d836e7 312
7659150c 313 buf = host->sg_miter.addr;
d129bceb 314
7659150c
PO		 315 while (len) {
316 if (chunk == 0) {
4e4141a5 317 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 318 chunk = 4;
a406f5a3 319 }
7659150c
PO		 320
321 *buf = scratch & 0xFF;
322
323 buf++;
324 scratch >>= 8;
325 chunk--;
326 len--;
d129bceb 327 }
a406f5a3 328 }
7659150c
PO		 329
330 sg_miter_stop(&host->sg_miter);
331
332 local_irq_restore(flags);
a406f5a3 333}
d129bceb 334
a406f5a3
PO		 335static void sdhci_write_block_pio(struct sdhci_host *host)
336{
7659150c
PO		 337 unsigned long flags;
338 size_t blksize, len, chunk;
339 u32 scratch;
340 u8 *buf;
d129bceb 341
a406f5a3
PO		 342 DBG("PIO writing\n");
343
344 blksize = host->data->blksz;
7659150c
PO		 345 chunk = 0;
346 scratch = 0;
d129bceb 347
7659150c 348 local_irq_save(flags);
d129bceb 349
a406f5a3 350 while (blksize) {
7659150c
PO		 351 if (!sg_miter_next(&host->sg_miter))
352 BUG();
a406f5a3 353
7659150c
PO		 354 len = min(host->sg_miter.length, blksize);
355
356 blksize -= len;
357 host->sg_miter.consumed = len;
358
359 buf = host->sg_miter.addr;
d129bceb 360
7659150c
PO		 361 while (len) {
362 scratch |= (u32)*buf << (chunk * 8);
363
364 buf++;
365 chunk++;
366 len--;
367
368 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 369 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 370 chunk = 0;
371 scratch = 0;
d129bceb 372 }
d129bceb
PO		 373 }
374 }
7659150c
PO		 375
376 sg_miter_stop(&host->sg_miter);
377
378 local_irq_restore(flags);
a406f5a3
PO		 379}
380
381static void sdhci_transfer_pio(struct sdhci_host *host)
382{
383 u32 mask;
384
385 BUG_ON(!host->data);
386
7659150c 387 if (host->blocks == 0)
a406f5a3
PO		 388 return;
389
390 if (host->data->flags & MMC_DATA_READ)
391 mask = SDHCI_DATA_AVAILABLE;
392 else
393 mask = SDHCI_SPACE_AVAILABLE;
394
4a3cba32
PO		 395 /*
396 * Some controllers (JMicron JMB38x) mess up the buffer bits
397 * for transfers < 4 bytes. As long as it is just one block,
398 * we can ignore the bits.
399 */
400 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
401 (host->data->blocks == 1))
402 mask = ~0;
403
4e4141a5 404 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 405 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
406 udelay(100);
407
a406f5a3
PO		 408 if (host->data->flags & MMC_DATA_READ)
409 sdhci_read_block_pio(host);
410 else
411 sdhci_write_block_pio(host);
d129bceb 412
7659150c
PO		 413 host->blocks--;
414 if (host->blocks == 0)
a406f5a3 415 break;
a406f5a3 416 }
d129bceb 417
a406f5a3 418 DBG("PIO transfer complete.\n");
d129bceb
PO		 419}
420
2134a922
PO		 421static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
422{
423 local_irq_save(*flags);
482fce99 424 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 425}
426
427static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
428{
482fce99 429 kunmap_atomic(buffer);
2134a922
PO		 430 local_irq_restore(*flags);
431}
432
118cd17d
BD		 433static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
434{
9e506f35
BD		 435 __le32 *dataddr = (__le32 __force *)(desc + 4);
436 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 437
9e506f35
BD		 438 /* SDHCI specification says ADMA descriptors should be 4 byte
439 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 440
9e506f35
BD		 441 cmdlen[0] = cpu_to_le16(cmd);
442 cmdlen[1] = cpu_to_le16(len);
443
444 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 445}
446
8f1934ce 447static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 448 struct mmc_data *data)
449{
450 int direction;
451
452 u8 *desc;
453 u8 *align;
454 dma_addr_t addr;
455 dma_addr_t align_addr;
456 int len, offset;
457
458 struct scatterlist *sg;
459 int i;
460 char *buffer;
461 unsigned long flags;
462
463 /*
464 * The spec does not specify endianness of descriptor table.
465 * We currently guess that it is LE.
466 */
467
468 if (data->flags & MMC_DATA_READ)
469 direction = DMA_FROM_DEVICE;
470 else
471 direction = DMA_TO_DEVICE;
472
473 /*
474 * The ADMA descriptor table is mapped further down as we
475 * need to fill it with data first.
476 */
477
478 host->align_addr = dma_map_single(mmc_dev(host->mmc),
479 host->align_buffer, 128 * 4, direction);
8d8bb39b 480 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 481 goto fail;
2134a922
PO		 482 BUG_ON(host->align_addr & 0x3);
483
484 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
485 data->sg, data->sg_len, direction);
8f1934ce
PO		 486 if (host->sg_count == 0)
487 goto unmap_align;
2134a922
PO		 488
489 desc = host->adma_desc;
490 align = host->align_buffer;
491
492 align_addr = host->align_addr;
493
494 for_each_sg(data->sg, sg, host->sg_count, i) {
495 addr = sg_dma_address(sg);
496 len = sg_dma_len(sg);
497
498 /*
499 * The SDHCI specification states that ADMA
500 * addresses must be 32-bit aligned. If they
501 * aren't, then we use a bounce buffer for
502 * the (up to three) bytes that screw up the
503 * alignment.
504 */
505 offset = (4 - (addr & 0x3)) & 0x3;
506 if (offset) {
507 if (data->flags & MMC_DATA_WRITE) {
508 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 509 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 510 memcpy(align, buffer, offset);
511 sdhci_kunmap_atomic(buffer, &flags);
512 }
513
118cd17d
BD		 514 /* tran, valid */
515 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 516
517 BUG_ON(offset > 65536);
518
2134a922
PO		 519 align += 4;
520 align_addr += 4;
521
522 desc += 8;
523
524 addr += offset;
525 len -= offset;
526 }
527
2134a922
PO		 528 BUG_ON(len > 65536);
529
118cd17d
BD		 530 /* tran, valid */
531 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 532 desc += 8;
533
534 /*
535 * If this triggers then we have a calculation bug
536 * somewhere. :/
537 */
538 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
539 }
540
70764a90
TA		 541 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
542 /*
543 * Mark the last descriptor as the terminating descriptor
544 */
545 if (desc != host->adma_desc) {
546 desc -= 8;
547 desc[0] |= 0x2; /* end */
548 }
549 } else {
550 /*
551 * Add a terminating entry.
552 */
2134a922 553
70764a90
TA		 554 /* nop, end, valid */
555 sdhci_set_adma_desc(desc, 0, 0, 0x3);
556 }
2134a922
PO		 557
558 /*
559 * Resync align buffer as we might have changed it.
560 */
561 if (data->flags & MMC_DATA_WRITE) {
562 dma_sync_single_for_device(mmc_dev(host->mmc),
563 host->align_addr, 128 * 4, direction);
564 }
565
566 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
567 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 568 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 569 goto unmap_entries;
2134a922 570 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 571
572 return 0;
573
574unmap_entries:
575 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
576 data->sg_len, direction);
577unmap_align:
578 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
579 128 * 4, direction);
580fail:
581 return -EINVAL;
2134a922
PO		 582}
583
584static void sdhci_adma_table_post(struct sdhci_host *host,
585 struct mmc_data *data)
586{
587 int direction;
588
589 struct scatterlist *sg;
590 int i, size;
591 u8 *align;
592 char *buffer;
593 unsigned long flags;
594
595 if (data->flags & MMC_DATA_READ)
596 direction = DMA_FROM_DEVICE;
597 else
598 direction = DMA_TO_DEVICE;
599
600 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
601 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
602
603 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
604 128 * 4, direction);
605
606 if (data->flags & MMC_DATA_READ) {
607 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
608 data->sg_len, direction);
609
610 align = host->align_buffer;
611
612 for_each_sg(data->sg, sg, host->sg_count, i) {
613 if (sg_dma_address(sg) & 0x3) {
614 size = 4 - (sg_dma_address(sg) & 0x3);
615
616 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 617 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 618 memcpy(buffer, align, size);
619 sdhci_kunmap_atomic(buffer, &flags);
620
621 align += 4;
622 }
623 }
624 }
625
626 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
627 data->sg_len, direction);
628}
629
a3c7778f 630static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 631{
1c8cde92 632 u8 count;
a3c7778f 633 struct mmc_data *data = cmd->data;
1c8cde92 634 unsigned target_timeout, current_timeout;
d129bceb 635
ee53ab5d
PO		 636 /*
637 * If the host controller provides us with an incorrect timeout
638 * value, just skip the check and use 0xE. The hardware may take
639 * longer to time out, but that's much better than having a too-short
640 * timeout value.
641 */
11a2f1b7 642 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 643 return 0xE;
e538fbe8 644
a3c7778f
AW		 645 /* Unspecified timeout, assume max */
646 if (!data && !cmd->cmd_timeout_ms)
647 return 0xE;
d129bceb 648
a3c7778f
AW		 649 /* timeout in us */
650 if (!data)
651 target_timeout = cmd->cmd_timeout_ms * 1000;
78a2ca27
AS		 652 else {
653 target_timeout = data->timeout_ns / 1000;
654 if (host->clock)
655 target_timeout += data->timeout_clks / host->clock;
656 }
81b39802 657
1c8cde92
PO		 658 /*
659 * Figure out needed cycles.
660 * We do this in steps in order to fit inside a 32 bit int.
661 * The first step is the minimum timeout, which will have a
662 * minimum resolution of 6 bits:
663 * (1) 2^13*1000 > 2^22,
664 * (2) host->timeout_clk < 2^16
665 * =>
666 * (1) / (2) > 2^6
667 */
668 count = 0;
669 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
670 while (current_timeout < target_timeout) {
671 count++;
672 current_timeout <<= 1;
673 if (count >= 0xF)
674 break;
675 }
676
677 if (count >= 0xF) {
a3c76eb9 678 pr_warning("%s: Too large timeout requested for CMD%d!\n",
a3c7778f 679 mmc_hostname(host->mmc), cmd->opcode);
1c8cde92
PO		 680 count = 0xE;
681 }
682
ee53ab5d
PO		 683 return count;
684}
685
6aa943ab
AV		 686static void sdhci_set_transfer_irqs(struct sdhci_host *host)
687{
688 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
689 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
690
691 if (host->flags & SDHCI_REQ_USE_DMA)
692 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
693 else
694 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
695}
696
a3c7778f 697static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 698{
699 u8 count;
2134a922 700 u8 ctrl;
a3c7778f 701 struct mmc_data *data = cmd->data;
8f1934ce 702 int ret;
ee53ab5d
PO		 703
704 WARN_ON(host->data);
705
a3c7778f
AW		 706 if (data || (cmd->flags & MMC_RSP_BUSY)) {
707 count = sdhci_calc_timeout(host, cmd);
708 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
709 }
710
711 if (!data)
ee53ab5d
PO		 712 return;
713
714 /* Sanity checks */
715 BUG_ON(data->blksz * data->blocks > 524288);
716 BUG_ON(data->blksz > host->mmc->max_blk_size);
717 BUG_ON(data->blocks > 65535);
718
719 host->data = data;
720 host->data_early = 0;
f6a03cbf 721 host->data->bytes_xfered = 0;
ee53ab5d 722
a13abc7b 723 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 724 host->flags |= SDHCI_REQ_USE_DMA;
725
2134a922
PO		 726 /*
727 * FIXME: This doesn't account for merging when mapping the
728 * scatterlist.
729 */
730 if (host->flags & SDHCI_REQ_USE_DMA) {
731 int broken, i;
732 struct scatterlist *sg;
733
734 broken = 0;
735 if (host->flags & SDHCI_USE_ADMA) {
736 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
737 broken = 1;
738 } else {
739 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
740 broken = 1;
741 }
742
743 if (unlikely(broken)) {
744 for_each_sg(data->sg, sg, data->sg_len, i) {
745 if (sg->length & 0x3) {
746 DBG("Reverting to PIO because of "
747 "transfer size (%d)\n",
748 sg->length);
749 host->flags &= ~SDHCI_REQ_USE_DMA;
750 break;
751 }
752 }
753 }
c9fddbc4
PO		 754 }
755
756 /*
757 * The assumption here being that alignment is the same after
758 * translation to device address space.
759 */
2134a922
PO		 760 if (host->flags & SDHCI_REQ_USE_DMA) {
761 int broken, i;
762 struct scatterlist *sg;
763
764 broken = 0;
765 if (host->flags & SDHCI_USE_ADMA) {
766 /*
767 * As we use 3 byte chunks to work around
768 * alignment problems, we need to check this
769 * quirk.
770 */
771 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
772 broken = 1;
773 } else {
774 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
775 broken = 1;
776 }
777
778 if (unlikely(broken)) {
779 for_each_sg(data->sg, sg, data->sg_len, i) {
780 if (sg->offset & 0x3) {
781 DBG("Reverting to PIO because of "
782 "bad alignment\n");
783 host->flags &= ~SDHCI_REQ_USE_DMA;
784 break;
785 }
786 }
787 }
788 }
789
8f1934ce
PO		 790 if (host->flags & SDHCI_REQ_USE_DMA) {
791 if (host->flags & SDHCI_USE_ADMA) {
792 ret = sdhci_adma_table_pre(host, data);
793 if (ret) {
794 /*
795 * This only happens when someone fed
796 * us an invalid request.
797 */
798 WARN_ON(1);
ebd6d357 799 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 800 } else {
4e4141a5
AV		 801 sdhci_writel(host, host->adma_addr,
802 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 803 }
804 } else {
c8b3e02e 805 int sg_cnt;
8f1934ce 806
c8b3e02e 807 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 808 data->sg, data->sg_len,
809 (data->flags & MMC_DATA_READ) ?
810 DMA_FROM_DEVICE :
811 DMA_TO_DEVICE);
c8b3e02e 812 if (sg_cnt == 0) {
8f1934ce
PO		 813 /*
814 * This only happens when someone fed
815 * us an invalid request.
816 */
817 WARN_ON(1);
ebd6d357 818 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 819 } else {
719a61b4 820 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 821 sdhci_writel(host, sg_dma_address(data->sg),
822 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 823 }
824 }
825 }
826
2134a922
PO		 827 /*
828 * Always adjust the DMA selection as some controllers
829 * (e.g. JMicron) can't do PIO properly when the selection
830 * is ADMA.
831 */
832 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 833 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 834 ctrl &= ~SDHCI_CTRL_DMA_MASK;
835 if ((host->flags & SDHCI_REQ_USE_DMA) &&
836 (host->flags & SDHCI_USE_ADMA))
837 ctrl |= SDHCI_CTRL_ADMA32;
838 else
839 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 840 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 841 }
842
8f1934ce 843 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 844 int flags;
845
846 flags = SG_MITER_ATOMIC;
847 if (host->data->flags & MMC_DATA_READ)
848 flags |= SG_MITER_TO_SG;
849 else
850 flags |= SG_MITER_FROM_SG;
851 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 852 host->blocks = data->blocks;
d129bceb 853 }
c7fa9963 854
6aa943ab
AV		 855 sdhci_set_transfer_irqs(host);
856
f6a03cbf
MV		 857 /* Set the DMA boundary value and block size */
858 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
859 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 860 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 861}
862
863static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 864 struct mmc_command *cmd)
c7fa9963
PO		 865{
866 u16 mode;
e89d456f 867 struct mmc_data *data = cmd->data;
c7fa9963 868
c7fa9963
PO		 869 if (data == NULL)
870 return;
871
e538fbe8
PO		 872 WARN_ON(!host->data);
873
c7fa9963 874 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 875 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
876 mode |= SDHCI_TRNS_MULTI;
877 /*
878 * If we are sending CMD23, CMD12 never gets sent
879 * on successful completion (so no Auto-CMD12).
880 */
881 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
882 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 883 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
884 mode |= SDHCI_TRNS_AUTO_CMD23;
885 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
886 }
c4512f79 887 }
8edf6371 888
c7fa9963
PO		 889 if (data->flags & MMC_DATA_READ)
890 mode |= SDHCI_TRNS_READ;
c9fddbc4 891 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 892 mode |= SDHCI_TRNS_DMA;
893
4e4141a5 894 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 895}
896
897static void sdhci_finish_data(struct sdhci_host *host)
898{
899 struct mmc_data *data;
d129bceb
PO		 900
901 BUG_ON(!host->data);
902
903 data = host->data;
904 host->data = NULL;
905
c9fddbc4 906 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 907 if (host->flags & SDHCI_USE_ADMA)
908 sdhci_adma_table_post(host, data);
909 else {
910 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
911 data->sg_len, (data->flags & MMC_DATA_READ) ?
912 DMA_FROM_DEVICE : DMA_TO_DEVICE);
913 }
d129bceb
PO		 914 }
915
916 /*
c9b74c5b
PO		 917 * The specification states that the block count register must
918 * be updated, but it does not specify at what point in the
919 * data flow. That makes the register entirely useless to read
920 * back so we have to assume that nothing made it to the card
921 * in the event of an error.
d129bceb 922 */
c9b74c5b
PO		 923 if (data->error)
924 data->bytes_xfered = 0;
d129bceb 925 else
c9b74c5b 926 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 927
e89d456f
AW		 928 /*
929 * Need to send CMD12 if -
930 * a) open-ended multiblock transfer (no CMD23)
931 * b) error in multiblock transfer
932 */
933 if (data->stop &&
934 (data->error ||
935 !host->mrq->sbc)) {
936
d129bceb
PO		 937 /*
938 * The controller needs a reset of internal state machines
939 * upon error conditions.
940 */
17b0429d 941 if (data->error) {
d129bceb
PO		 942 sdhci_reset(host, SDHCI_RESET_CMD);
943 sdhci_reset(host, SDHCI_RESET_DATA);
944 }
945
946 sdhci_send_command(host, data->stop);
947 } else
948 tasklet_schedule(&host->finish_tasklet);
949}
950
951static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
952{
953 int flags;
fd2208d7 954 u32 mask;
7cb2c76f 955 unsigned long timeout;
d129bceb
PO		 956
957 WARN_ON(host->cmd);
958
d129bceb 959 /* Wait max 10 ms */
7cb2c76f 960 timeout = 10;
fd2208d7
PO		 961
962 mask = SDHCI_CMD_INHIBIT;
963 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
964 mask |= SDHCI_DATA_INHIBIT;
965
966 /* We shouldn't wait for data inihibit for stop commands, even
967 though they might use busy signaling */
968 if (host->mrq->data && (cmd == host->mrq->data->stop))
969 mask &= ~SDHCI_DATA_INHIBIT;
970
4e4141a5 971 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 972 if (timeout == 0) {
a3c76eb9 973 pr_err("%s: Controller never released "
acf1da45 974 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 975 sdhci_dumpregs(host);
17b0429d 976 cmd->error = -EIO;
d129bceb
PO		 977 tasklet_schedule(&host->finish_tasklet);
978 return;
979 }
7cb2c76f
PO		 980 timeout--;
981 mdelay(1);
982 }
d129bceb
PO		 983
984 mod_timer(&host->timer, jiffies + 10 * HZ);
985
986 host->cmd = cmd;
987
a3c7778f 988 sdhci_prepare_data(host, cmd);
d129bceb 989
4e4141a5 990 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 991
e89d456f 992 sdhci_set_transfer_mode(host, cmd);
c7fa9963 993
d129bceb 994 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 995 pr_err("%s: Unsupported response type!\n",
d129bceb 996 mmc_hostname(host->mmc));
17b0429d 997 cmd->error = -EINVAL;
d129bceb
PO		 998 tasklet_schedule(&host->finish_tasklet);
999 return;
1000 }
1001
1002 if (!(cmd->flags & MMC_RSP_PRESENT))
1003 flags = SDHCI_CMD_RESP_NONE;
1004 else if (cmd->flags & MMC_RSP_136)
1005 flags = SDHCI_CMD_RESP_LONG;
1006 else if (cmd->flags & MMC_RSP_BUSY)
1007 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1008 else
1009 flags = SDHCI_CMD_RESP_SHORT;
1010
1011 if (cmd->flags & MMC_RSP_CRC)
1012 flags |= SDHCI_CMD_CRC;
1013 if (cmd->flags & MMC_RSP_OPCODE)
1014 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1015
1016 /* CMD19 is special in that the Data Present Select should be set */
1017 if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
d129bceb
PO		 1018 flags |= SDHCI_CMD_DATA;
1019
4e4141a5 1020 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 1021}
1022
1023static void sdhci_finish_command(struct sdhci_host *host)
1024{
1025 int i;
1026
1027 BUG_ON(host->cmd == NULL);
1028
1029 if (host->cmd->flags & MMC_RSP_PRESENT) {
1030 if (host->cmd->flags & MMC_RSP_136) {
1031 /* CRC is stripped so we need to do some shifting. */
1032 for (i = 0;i < 4;i++) {
4e4141a5 1033 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1034 SDHCI_RESPONSE + (3-i)*4) << 8;
1035 if (i != 3)
1036 host->cmd->resp[i] |=
4e4141a5 1037 sdhci_readb(host,
d129bceb
PO		 1038 SDHCI_RESPONSE + (3-i)*4-1);
1039 }
1040 } else {
4e4141a5 1041 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1042 }
1043 }
1044
17b0429d 1045 host->cmd->error = 0;
d129bceb 1046
e89d456f
AW		 1047 /* Finished CMD23, now send actual command. */
1048 if (host->cmd == host->mrq->sbc) {
1049 host->cmd = NULL;
1050 sdhci_send_command(host, host->mrq->cmd);
1051 } else {
e538fbe8 1052
e89d456f
AW		 1053 /* Processed actual command. */
1054 if (host->data && host->data_early)
1055 sdhci_finish_data(host);
d129bceb 1056
e89d456f
AW		 1057 if (!host->cmd->data)
1058 tasklet_schedule(&host->finish_tasklet);
1059
1060 host->cmd = NULL;
1061 }
d129bceb
PO		 1062}
1063
1064static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1065{
c3ed3877 1066 int div = 0; /* Initialized for compiler warning */
df16219f 1067 int real_div = div, clk_mul = 1;
c3ed3877 1068 u16 clk = 0;
7cb2c76f 1069 unsigned long timeout;
d129bceb 1070
30832ab5 1071 if (clock && clock == host->clock)
d129bceb
PO		 1072 return;
1073
df16219f
GC		 1074 host->mmc->actual_clock = 0;
1075
8114634c
AV		 1076 if (host->ops->set_clock) {
1077 host->ops->set_clock(host, clock);
1078 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1079 return;
1080 }
1081
4e4141a5 1082 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1083
1084 if (clock == 0)
1085 goto out;
1086
85105c53 1087 if (host->version >= SDHCI_SPEC_300) {
c3ed3877
AN		 1088 /*
1089 * Check if the Host Controller supports Programmable Clock
1090 * Mode.
1091 */
1092 if (host->clk_mul) {
1093 u16 ctrl;
1094
1095 /*
1096 * We need to figure out whether the Host Driver needs
1097 * to select Programmable Clock Mode, or the value can
1098 * be set automatically by the Host Controller based on
1099 * the Preset Value registers.
1100 */
1101 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1102 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1103 for (div = 1; div <= 1024; div++) {
1104 if (((host->max_clk * host->clk_mul) /
1105 div) <= clock)
1106 break;
1107 }
1108 /*
1109 * Set Programmable Clock Mode in the Clock
1110 * Control register.
1111 */
1112 clk = SDHCI_PROG_CLOCK_MODE;
df16219f
GC		 1113 real_div = div;
1114 clk_mul = host->clk_mul;
c3ed3877
AN		 1115 div--;
1116 }
1117 } else {
1118 /* Version 3.00 divisors must be a multiple of 2. */
1119 if (host->max_clk <= clock)
1120 div = 1;
1121 else {
1122 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1123 div += 2) {
1124 if ((host->max_clk / div) <= clock)
1125 break;
1126 }
85105c53 1127 }
df16219f 1128 real_div = div;
c3ed3877 1129 div >>= 1;
85105c53
ZG		 1130 }
1131 } else {
1132 /* Version 2.00 divisors must be a power of 2. */
0397526d 1133 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1134 if ((host->max_clk / div) <= clock)
1135 break;
1136 }
df16219f 1137 real_div = div;
c3ed3877 1138 div >>= 1;
d129bceb 1139 }
d129bceb 1140
df16219f
GC		 1141 if (real_div)
1142 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1143
c3ed3877 1144 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1145 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1146 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1147 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1148 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1149
27f6cb16
CB		 1150 /* Wait max 20 ms */
1151 timeout = 20;
4e4141a5 1152 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1153 & SDHCI_CLOCK_INT_STABLE)) {
1154 if (timeout == 0) {
a3c76eb9 1155 pr_err("%s: Internal clock never "
acf1da45 1156 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1157 sdhci_dumpregs(host);
1158 return;
1159 }
7cb2c76f
PO		 1160 timeout--;
1161 mdelay(1);
1162 }
d129bceb
PO		 1163
1164 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1165 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1166
1167out:
1168 host->clock = clock;
1169}
1170
ceb6143b 1171static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
146ad66e 1172{
8364248a 1173 u8 pwr = 0;
146ad66e 1174
8364248a 1175 if (power != (unsigned short)-1) {
ae628903
PO		 1176 switch (1 << power) {
1177 case MMC_VDD_165_195:
1178 pwr = SDHCI_POWER_180;
1179 break;
1180 case MMC_VDD_29_30:
1181 case MMC_VDD_30_31:
1182 pwr = SDHCI_POWER_300;
1183 break;
1184 case MMC_VDD_32_33:
1185 case MMC_VDD_33_34:
1186 pwr = SDHCI_POWER_330;
1187 break;
1188 default:
1189 BUG();
1190 }
1191 }
1192
1193 if (host->pwr == pwr)
ceb6143b 1194 return -1;
146ad66e 1195
ae628903
PO		 1196 host->pwr = pwr;
1197
1198 if (pwr == 0) {
4e4141a5 1199 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ceb6143b 1200 return 0;
9e9dc5f2
DS		 1201 }
1202
1203 /*
1204 * Spec says that we should clear the power reg before setting
1205 * a new value. Some controllers don't seem to like this though.
1206 */
b8c86fc5 1207 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1208 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1209
e08c1694 1210 /*
c71f6512 1211 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1212 * and set turn on power at the same time, so set the voltage first.
1213 */
11a2f1b7 1214 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1215 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1216
ae628903 1217 pwr |= SDHCI_POWER_ON;
146ad66e 1218
ae628903 1219 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1220
1221 /*
1222 * Some controllers need an extra 10ms delay of 10ms before they
1223 * can apply clock after applying power
1224 */
11a2f1b7 1225 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1226 mdelay(10);
ceb6143b
AH		 1227
1228 return power;
146ad66e
PO		 1229}
1230
d129bceb
PO		 1231/*****************************************************************************\
1232 * *
1233 * MMC callbacks *
1234 * *
1235\*****************************************************************************/
1236
1237static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1238{
1239 struct sdhci_host *host;
68d1fb7e 1240 bool present;
d129bceb
PO		 1241 unsigned long flags;
1242
1243 host = mmc_priv(mmc);
1244
66fd8ad5
AH		 1245 sdhci_runtime_pm_get(host);
1246
d129bceb
PO		 1247 spin_lock_irqsave(&host->lock, flags);
1248
1249 WARN_ON(host->mrq != NULL);
1250
f9134319 1251#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1252 sdhci_activate_led(host);
2f730fec 1253#endif
e89d456f
AW		 1254
1255 /*
1256 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1257 * requests if Auto-CMD12 is enabled.
1258 */
1259 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1260 if (mrq->stop) {
1261 mrq->data->stop = NULL;
1262 mrq->stop = NULL;
1263 }
1264 }
d129bceb
PO		 1265
1266 host->mrq = mrq;
1267
68d1fb7e
AV		 1268 /* If polling, assume that the card is always present. */
1269 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1270 present = true;
1271 else
1272 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1273 SDHCI_CARD_PRESENT;
1274
1275 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1276 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1277 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1278 } else {
1279 u32 present_state;
1280
1281 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1282 /*
1283 * Check if the re-tuning timer has already expired and there
1284 * is no on-going data transfer. If so, we need to execute
1285 * tuning procedure before sending command.
1286 */
1287 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1288 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1289 spin_unlock_irqrestore(&host->lock, flags);
1290 sdhci_execute_tuning(mmc);
1291 spin_lock_irqsave(&host->lock, flags);
1292
1293 /* Restore original mmc_request structure */
1294 host->mrq = mrq;
1295 }
1296
8edf6371 1297 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1298 sdhci_send_command(host, mrq->sbc);
1299 else
1300 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1301 }
d129bceb 1302
5f25a66f 1303 mmiowb();
d129bceb
PO		 1304 spin_unlock_irqrestore(&host->lock, flags);
1305}
1306
66fd8ad5 1307static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1308{
d129bceb 1309 unsigned long flags;
ceb6143b 1310 int vdd_bit = -1;
d129bceb
PO		 1311 u8 ctrl;
1312
d129bceb
PO		 1313 spin_lock_irqsave(&host->lock, flags);
1314
ceb6143b
AH		 1315 if (host->flags & SDHCI_DEVICE_DEAD) {
1316 spin_unlock_irqrestore(&host->lock, flags);
1317 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1318 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1319 return;
1320 }
1e72859e 1321
d129bceb
PO		 1322 /*
1323 * Reset the chip on each power off.
1324 * Should clear out any weird states.
1325 */
1326 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1327 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1328 sdhci_reinit(host);
d129bceb
PO		 1329 }
1330
1331 sdhci_set_clock(host, ios->clock);
1332
1333 if (ios->power_mode == MMC_POWER_OFF)
ceb6143b 1334 vdd_bit = sdhci_set_power(host, -1);
d129bceb 1335 else
ceb6143b
AH		 1336 vdd_bit = sdhci_set_power(host, ios->vdd);
1337
1338 if (host->vmmc && vdd_bit != -1) {
1339 spin_unlock_irqrestore(&host->lock, flags);
1340 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1341 spin_lock_irqsave(&host->lock, flags);
1342 }
d129bceb 1343
643a81ff
PR		 1344 if (host->ops->platform_send_init_74_clocks)
1345 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1346
15ec4461
PR		 1347 /*
1348 * If your platform has 8-bit width support but is not a v3 controller,
1349 * or if it requires special setup code, you should implement that in
1350 * platform_8bit_width().
1351 */
1352 if (host->ops->platform_8bit_width)
1353 host->ops->platform_8bit_width(host, ios->bus_width);
1354 else {
1355 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1356 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1357 ctrl &= ~SDHCI_CTRL_4BITBUS;
1358 if (host->version >= SDHCI_SPEC_300)
1359 ctrl |= SDHCI_CTRL_8BITBUS;
1360 } else {
1361 if (host->version >= SDHCI_SPEC_300)
1362 ctrl &= ~SDHCI_CTRL_8BITBUS;
1363 if (ios->bus_width == MMC_BUS_WIDTH_4)
1364 ctrl |= SDHCI_CTRL_4BITBUS;
1365 else
1366 ctrl &= ~SDHCI_CTRL_4BITBUS;
1367 }
1368 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1369 }
ae6d6c92 1370
15ec4461 1371 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1372
3ab9c8da
PR		 1373 if ((ios->timing == MMC_TIMING_SD_HS ||
1374 ios->timing == MMC_TIMING_MMC_HS)
1375 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1376 ctrl |= SDHCI_CTRL_HISPD;
1377 else
1378 ctrl &= ~SDHCI_CTRL_HISPD;
1379
d6d50a15 1380 if (host->version >= SDHCI_SPEC_300) {
49c468fc
AN		 1381 u16 clk, ctrl_2;
1382 unsigned int clock;
1383
1384 /* In case of UHS-I modes, set High Speed Enable */
1385 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1386 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1387 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1388 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1389 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1390
1391 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1392 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1393 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1394 /*
1395 * We only need to set Driver Strength if the
1396 * preset value enable is not set.
1397 */
1398 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1399 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1400 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1401 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1402 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1403
1404 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1405 } else {
1406 /*
1407 * According to SDHC Spec v3.00, if the Preset Value
1408 * Enable in the Host Control 2 register is set, we
1409 * need to reset SD Clock Enable before changing High
1410 * Speed Enable to avoid generating clock gliches.
1411 */
758535c4
AN		 1412
1413 /* Reset SD Clock Enable */
1414 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1415 clk &= ~SDHCI_CLOCK_CARD_EN;
1416 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1417
1418 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1419
1420 /* Re-enable SD Clock */
1421 clock = host->clock;
1422 host->clock = 0;
1423 sdhci_set_clock(host, clock);
d6d50a15 1424 }
49c468fc 1425
49c468fc
AN		 1426
1427 /* Reset SD Clock Enable */
1428 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1429 clk &= ~SDHCI_CLOCK_CARD_EN;
1430 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1431
6322cdd0
PR		 1432 if (host->ops->set_uhs_signaling)
1433 host->ops->set_uhs_signaling(host, ios->timing);
1434 else {
1435 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1436 /* Select Bus Speed Mode for host */
1437 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1438 if (ios->timing == MMC_TIMING_UHS_SDR12)
1439 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1440 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1441 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1442 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1443 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1444 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1445 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1446 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1447 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1448 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1449 }
49c468fc
AN		 1450
1451 /* Re-enable SD Clock */
1452 clock = host->clock;
1453 host->clock = 0;
1454 sdhci_set_clock(host, clock);
758535c4
AN		 1455 } else
1456 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1457
b8352260
LD		 1458 /*
1459 * Some (ENE) controllers go apeshit on some ios operation,
1460 * signalling timeout and CRC errors even on CMD0. Resetting
1461 * it on each ios seems to solve the problem.
1462 */
b8c86fc5 1463 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1464 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1465
5f25a66f 1466 mmiowb();
d129bceb
PO		 1467 spin_unlock_irqrestore(&host->lock, flags);
1468}
1469
66fd8ad5
AH		 1470static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1471{
1472 struct sdhci_host *host = mmc_priv(mmc);
1473
1474 sdhci_runtime_pm_get(host);
1475 sdhci_do_set_ios(host, ios);
1476 sdhci_runtime_pm_put(host);
1477}
1478
1479static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1480{
d129bceb 1481 unsigned long flags;
2dfb579c 1482 int is_readonly;
d129bceb 1483
d129bceb
PO		 1484 spin_lock_irqsave(&host->lock, flags);
1485
1e72859e 1486 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1487 is_readonly = 0;
1488 else if (host->ops->get_ro)
1489 is_readonly = host->ops->get_ro(host);
1e72859e 1490 else
2dfb579c
WS		 1491 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1492 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1493
1494 spin_unlock_irqrestore(&host->lock, flags);
1495
2dfb579c
WS		 1496 /* This quirk needs to be replaced by a callback-function later */
1497 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1498 !is_readonly : is_readonly;
d129bceb
PO		 1499}
1500
82b0e23a
TI		 1501#define SAMPLE_COUNT 5
1502
66fd8ad5 1503static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1504{
82b0e23a
TI		 1505 int i, ro_count;
1506
82b0e23a 1507 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1508 return sdhci_check_ro(host);
82b0e23a
TI		 1509
1510 ro_count = 0;
1511 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1512 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1513 if (++ro_count > SAMPLE_COUNT / 2)
1514 return 1;
1515 }
1516 msleep(30);
1517 }
1518 return 0;
1519}
1520
20758b66
AH		 1521static void sdhci_hw_reset(struct mmc_host *mmc)
1522{
1523 struct sdhci_host *host = mmc_priv(mmc);
1524
1525 if (host->ops && host->ops->hw_reset)
1526 host->ops->hw_reset(host);
1527}
1528
66fd8ad5 1529static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1530{
66fd8ad5
AH		 1531 struct sdhci_host *host = mmc_priv(mmc);
1532 int ret;
f75979b7 1533
66fd8ad5
AH		 1534 sdhci_runtime_pm_get(host);
1535 ret = sdhci_do_get_ro(host);
1536 sdhci_runtime_pm_put(host);
1537 return ret;
1538}
f75979b7 1539
66fd8ad5
AH		 1540static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1541{
1e72859e
PO		 1542 if (host->flags & SDHCI_DEVICE_DEAD)
1543 goto out;
1544
66fd8ad5
AH		 1545 if (enable)
1546 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1547 else
1548 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1549
1550 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1551 if (host->runtime_suspended)
1552 goto out;
1553
f75979b7 1554 if (enable)
7260cf5e
AV		 1555 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1556 else
1557 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1558out:
f75979b7 1559 mmiowb();
66fd8ad5
AH		 1560}
1561
1562static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1563{
1564 struct sdhci_host *host = mmc_priv(mmc);
1565 unsigned long flags;
f75979b7 1566
66fd8ad5
AH		 1567 spin_lock_irqsave(&host->lock, flags);
1568 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1569 spin_unlock_irqrestore(&host->lock, flags);
1570}
1571
66fd8ad5
AH		 1572static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1573 struct mmc_ios *ios)
f2119df6 1574{
f2119df6
AN		 1575 u8 pwr;
1576 u16 clk, ctrl;
1577 u32 present_state;
1578
f2119df6
AN		 1579 /*
1580 * Signal Voltage Switching is only applicable for Host Controllers
1581 * v3.00 and above.
1582 */
1583 if (host->version < SDHCI_SPEC_300)
1584 return 0;
1585
1586 /*
1587 * We first check whether the request is to set signalling voltage
1588 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1589 */
1590 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1591 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1592 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1593 ctrl &= ~SDHCI_CTRL_VDD_180;
1594 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1595
1596 /* Wait for 5ms */
1597 usleep_range(5000, 5500);
1598
1599 /* 3.3V regulator output should be stable within 5 ms */
1600 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1601 if (!(ctrl & SDHCI_CTRL_VDD_180))
1602 return 0;
1603 else {
a3c76eb9 1604 pr_info(DRIVER_NAME ": Switching to 3.3V "
f2119df6
AN		 1605 "signalling voltage failed\n");
1606 return -EIO;
1607 }
1608 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1609 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1610 /* Stop SDCLK */
1611 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1612 clk &= ~SDHCI_CLOCK_CARD_EN;
1613 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1614
1615 /* Check whether DAT[3:0] is 0000 */
1616 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1617 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1618 SDHCI_DATA_LVL_SHIFT)) {
1619 /*
1620 * Enable 1.8V Signal Enable in the Host Control2
1621 * register
1622 */
1623 ctrl |= SDHCI_CTRL_VDD_180;
1624 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1625
1626 /* Wait for 5ms */
1627 usleep_range(5000, 5500);
1628
1629 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1630 if (ctrl & SDHCI_CTRL_VDD_180) {
1631 /* Provide SDCLK again and wait for 1ms*/
1632 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1633 clk |= SDHCI_CLOCK_CARD_EN;
1634 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1635 usleep_range(1000, 1500);
1636
1637 /*
1638 * If DAT[3:0] level is 1111b, then the card
1639 * was successfully switched to 1.8V signaling.
1640 */
1641 present_state = sdhci_readl(host,
1642 SDHCI_PRESENT_STATE);
1643 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1644 SDHCI_DATA_LVL_MASK)
1645 return 0;
1646 }
1647 }
1648
1649 /*
1650 * If we are here, that means the switch to 1.8V signaling
1651 * failed. We power cycle the card, and retry initialization
1652 * sequence by setting S18R to 0.
1653 */
1654 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1655 pwr &= ~SDHCI_POWER_ON;
1656 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1657
1658 /* Wait for 1ms as per the spec */
1659 usleep_range(1000, 1500);
1660 pwr |= SDHCI_POWER_ON;
1661 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1662
a3c76eb9 1663 pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
f2119df6
AN		 1664 "voltage failed, retrying with S18R set to 0\n");
1665 return -EAGAIN;
1666 } else
1667 /* No signal voltage switch required */
1668 return 0;
1669}
1670
66fd8ad5
AH		 1671static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1672 struct mmc_ios *ios)
1673{
1674 struct sdhci_host *host = mmc_priv(mmc);
1675 int err;
1676
1677 if (host->version < SDHCI_SPEC_300)
1678 return 0;
1679 sdhci_runtime_pm_get(host);
1680 err = sdhci_do_start_signal_voltage_switch(host, ios);
1681 sdhci_runtime_pm_put(host);
1682 return err;
1683}
1684
b513ea25
AN		 1685static int sdhci_execute_tuning(struct mmc_host *mmc)
1686{
1687 struct sdhci_host *host;
1688 u16 ctrl;
1689 u32 ier;
1690 int tuning_loop_counter = MAX_TUNING_LOOP;
1691 unsigned long timeout;
1692 int err = 0;
1693
1694 host = mmc_priv(mmc);
1695
66fd8ad5 1696 sdhci_runtime_pm_get(host);
b513ea25
AN		 1697 disable_irq(host->irq);
1698 spin_lock(&host->lock);
1699
1700 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1701
1702 /*
1703 * Host Controller needs tuning only in case of SDR104 mode
1704 * and for SDR50 mode when Use Tuning for SDR50 is set in
1705 * Capabilities register.
1706 */
1707 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1708 (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1709 (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1710 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1711 else {
1712 spin_unlock(&host->lock);
1713 enable_irq(host->irq);
66fd8ad5 1714 sdhci_runtime_pm_put(host);
b513ea25
AN		 1715 return 0;
1716 }
1717
1718 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1719
1720 /*
1721 * As per the Host Controller spec v3.00, tuning command
1722 * generates Buffer Read Ready interrupt, so enable that.
1723 *
1724 * Note: The spec clearly says that when tuning sequence
1725 * is being performed, the controller does not generate
1726 * interrupts other than Buffer Read Ready interrupt. But
1727 * to make sure we don't hit a controller bug, we _only_
1728 * enable Buffer Read Ready interrupt here.
1729 */
1730 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1731 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1732
1733 /*
1734 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1735 * of loops reaches 40 times or a timeout of 150ms occurs.
1736 */
1737 timeout = 150;
1738 do {
1739 struct mmc_command cmd = {0};
66fd8ad5 1740 struct mmc_request mrq = {NULL};
b513ea25
AN		 1741
1742 if (!tuning_loop_counter && !timeout)
1743 break;
1744
1745 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1746 cmd.arg = 0;
1747 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1748 cmd.retries = 0;
1749 cmd.data = NULL;
1750 cmd.error = 0;
1751
1752 mrq.cmd = &cmd;
1753 host->mrq = &mrq;
1754
1755 /*
1756 * In response to CMD19, the card sends 64 bytes of tuning
1757 * block to the Host Controller. So we set the block size
1758 * to 64 here.
1759 */
1760 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1761
1762 /*
1763 * The tuning block is sent by the card to the host controller.
1764 * So we set the TRNS_READ bit in the Transfer Mode register.
1765 * This also takes care of setting DMA Enable and Multi Block
1766 * Select in the same register to 0.
1767 */
1768 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1769
1770 sdhci_send_command(host, &cmd);
1771
1772 host->cmd = NULL;
1773 host->mrq = NULL;
1774
1775 spin_unlock(&host->lock);
1776 enable_irq(host->irq);
1777
1778 /* Wait for Buffer Read Ready interrupt */
1779 wait_event_interruptible_timeout(host->buf_ready_int,
1780 (host->tuning_done == 1),
1781 msecs_to_jiffies(50));
1782 disable_irq(host->irq);
1783 spin_lock(&host->lock);
1784
1785 if (!host->tuning_done) {
a3c76eb9 1786 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1787 "Buffer Read Ready interrupt during tuning "
1788 "procedure, falling back to fixed sampling "
1789 "clock\n");
1790 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1791 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1792 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1793 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1794
1795 err = -EIO;
1796 goto out;
1797 }
1798
1799 host->tuning_done = 0;
1800
1801 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1802 tuning_loop_counter--;
1803 timeout--;
1804 mdelay(1);
1805 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1806
1807 /*
1808 * The Host Driver has exhausted the maximum number of loops allowed,
1809 * so use fixed sampling frequency.
1810 */
1811 if (!tuning_loop_counter || !timeout) {
1812 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1813 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1814 } else {
1815 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 1816 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 1817 " failed, falling back to fixed sampling"
1818 " clock\n");
1819 err = -EIO;
1820 }
1821 }
1822
1823out:
cf2b5eea
AN		 1824 /*
1825 * If this is the very first time we are here, we start the retuning
1826 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1827 * flag won't be set, we check this condition before actually starting
1828 * the timer.
1829 */
1830 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1831 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1832 mod_timer(&host->tuning_timer, jiffies +
1833 host->tuning_count * HZ);
1834 /* Tuning mode 1 limits the maximum data length to 4MB */
1835 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1836 } else {
1837 host->flags &= ~SDHCI_NEEDS_RETUNING;
1838 /* Reload the new initial value for timer */
1839 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1840 mod_timer(&host->tuning_timer, jiffies +
1841 host->tuning_count * HZ);
1842 }
1843
1844 /*
1845 * In case tuning fails, host controllers which support re-tuning can
1846 * try tuning again at a later time, when the re-tuning timer expires.
1847 * So for these controllers, we return 0. Since there might be other
1848 * controllers who do not have this capability, we return error for
1849 * them.
1850 */
1851 if (err && host->tuning_count &&
1852 host->tuning_mode == SDHCI_TUNING_MODE_1)
1853 err = 0;
1854
b513ea25
AN		 1855 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1856 spin_unlock(&host->lock);
1857 enable_irq(host->irq);
66fd8ad5 1858 sdhci_runtime_pm_put(host);
b513ea25
AN		 1859
1860 return err;
1861}
1862
66fd8ad5 1863static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 1864{
4d55c5a1
AN		 1865 u16 ctrl;
1866 unsigned long flags;
1867
4d55c5a1
AN		 1868 /* Host Controller v3.00 defines preset value registers */
1869 if (host->version < SDHCI_SPEC_300)
1870 return;
1871
1872 spin_lock_irqsave(&host->lock, flags);
1873
1874 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1875
1876 /*
1877 * We only enable or disable Preset Value if they are not already
1878 * enabled or disabled respectively. Otherwise, we bail out.
1879 */
1880 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1881 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1882 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 1883 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 1884 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1885 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1886 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 1887 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1
AN		 1888 }
1889
1890 spin_unlock_irqrestore(&host->lock, flags);
1891}
1892
66fd8ad5
AH		 1893static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1894{
1895 struct sdhci_host *host = mmc_priv(mmc);
1896
1897 sdhci_runtime_pm_get(host);
1898 sdhci_do_enable_preset_value(host, enable);
1899 sdhci_runtime_pm_put(host);
1900}
1901
ab7aefd0 1902static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1903 .request = sdhci_request,
1904 .set_ios = sdhci_set_ios,
1905 .get_ro = sdhci_get_ro,
20758b66 1906 .hw_reset = sdhci_hw_reset,
f75979b7 1907 .enable_sdio_irq = sdhci_enable_sdio_irq,
f2119df6 1908 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b513ea25 1909 .execute_tuning = sdhci_execute_tuning,
4d55c5a1 1910 .enable_preset_value = sdhci_enable_preset_value,
d129bceb
PO		 1911};
1912
1913/*****************************************************************************\
1914 * *
1915 * Tasklets *
1916 * *
1917\*****************************************************************************/
1918
1919static void sdhci_tasklet_card(unsigned long param)
1920{
1921 struct sdhci_host *host;
1922 unsigned long flags;
1923
1924 host = (struct sdhci_host*)param;
1925
1926 spin_lock_irqsave(&host->lock, flags);
1927
66fd8ad5
AH		 1928 /* Check host->mrq first in case we are runtime suspended */
1929 if (host->mrq &&
1930 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
a3c76eb9 1931 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 1932 mmc_hostname(host->mmc));
a3c76eb9 1933 pr_err("%s: Resetting controller.\n",
66fd8ad5 1934 mmc_hostname(host->mmc));
d129bceb 1935
66fd8ad5
AH		 1936 sdhci_reset(host, SDHCI_RESET_CMD);
1937 sdhci_reset(host, SDHCI_RESET_DATA);
d129bceb 1938
66fd8ad5
AH		 1939 host->mrq->cmd->error = -ENOMEDIUM;
1940 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 1941 }
1942
1943 spin_unlock_irqrestore(&host->lock, flags);
1944
04cf585d 1945 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1946}
1947
1948static void sdhci_tasklet_finish(unsigned long param)
1949{
1950 struct sdhci_host *host;
1951 unsigned long flags;
1952 struct mmc_request *mrq;
1953
1954 host = (struct sdhci_host*)param;
1955
66fd8ad5
AH		 1956 spin_lock_irqsave(&host->lock, flags);
1957
0c9c99a7
CB		 1958 /*
1959 * If this tasklet gets rescheduled while running, it will
1960 * be run again afterwards but without any active request.
1961 */
66fd8ad5
AH		 1962 if (!host->mrq) {
1963 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 1964 return;
66fd8ad5 1965 }
d129bceb
PO		 1966
1967 del_timer(&host->timer);
1968
1969 mrq = host->mrq;
1970
d129bceb
PO		 1971 /*
1972 * The controller needs a reset of internal state machines
1973 * upon error conditions.
1974 */
1e72859e 1975 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 1976 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 1977 (mrq->data && (mrq->data->error ||
1978 (mrq->data->stop && mrq->data->stop->error))) ||
1979 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1980
1981 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1982 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1983 unsigned int clock;
1984
1985 /* This is to force an update */
1986 clock = host->clock;
1987 host->clock = 0;
1988 sdhci_set_clock(host, clock);
1989 }
1990
1991 /* Spec says we should do both at the same time, but Ricoh
1992 controllers do not like that. */
d129bceb
PO		 1993 sdhci_reset(host, SDHCI_RESET_CMD);
1994 sdhci_reset(host, SDHCI_RESET_DATA);
1995 }
1996
1997 host->mrq = NULL;
1998 host->cmd = NULL;
1999 host->data = NULL;
2000
f9134319 2001#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2002 sdhci_deactivate_led(host);
2f730fec 2003#endif
d129bceb 2004
5f25a66f 2005 mmiowb();
d129bceb
PO		 2006 spin_unlock_irqrestore(&host->lock, flags);
2007
2008 mmc_request_done(host->mmc, mrq);
66fd8ad5 2009 sdhci_runtime_pm_put(host);
d129bceb
PO		 2010}
2011
2012static void sdhci_timeout_timer(unsigned long data)
2013{
2014 struct sdhci_host *host;
2015 unsigned long flags;
2016
2017 host = (struct sdhci_host*)data;
2018
2019 spin_lock_irqsave(&host->lock, flags);
2020
2021 if (host->mrq) {
a3c76eb9 2022 pr_err("%s: Timeout waiting for hardware "
acf1da45 2023 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2024 sdhci_dumpregs(host);
2025
2026 if (host->data) {
17b0429d 2027 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2028 sdhci_finish_data(host);
2029 } else {
2030 if (host->cmd)
17b0429d 2031 host->cmd->error = -ETIMEDOUT;
d129bceb 2032 else
17b0429d 2033 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2034
2035 tasklet_schedule(&host->finish_tasklet);
2036 }
2037 }
2038
5f25a66f 2039 mmiowb();
d129bceb
PO		 2040 spin_unlock_irqrestore(&host->lock, flags);
2041}
2042
cf2b5eea
AN		 2043static void sdhci_tuning_timer(unsigned long data)
2044{
2045 struct sdhci_host *host;
2046 unsigned long flags;
2047
2048 host = (struct sdhci_host *)data;
2049
2050 spin_lock_irqsave(&host->lock, flags);
2051
2052 host->flags |= SDHCI_NEEDS_RETUNING;
2053
2054 spin_unlock_irqrestore(&host->lock, flags);
2055}
2056
d129bceb
PO		 2057/*****************************************************************************\
2058 * *
2059 * Interrupt handling *
2060 * *
2061\*****************************************************************************/
2062
2063static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2064{
2065 BUG_ON(intmask == 0);
2066
2067 if (!host->cmd) {
a3c76eb9 2068 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2069 "though no command operation was in progress.\n",
2070 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2071 sdhci_dumpregs(host);
2072 return;
2073 }
2074
43b58b36 2075 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2076 host->cmd->error = -ETIMEDOUT;
2077 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2078 SDHCI_INT_INDEX))
2079 host->cmd->error = -EILSEQ;
43b58b36 2080
e809517f 2081 if (host->cmd->error) {
d129bceb 2082 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2083 return;
2084 }
2085
2086 /*
2087 * The host can send and interrupt when the busy state has
2088 * ended, allowing us to wait without wasting CPU cycles.
2089 * Unfortunately this is overloaded on the "data complete"
2090 * interrupt, so we need to take some care when handling
2091 * it.
2092 *
2093 * Note: The 1.0 specification is a bit ambiguous about this
2094 * feature so there might be some problems with older
2095 * controllers.
2096 */
2097 if (host->cmd->flags & MMC_RSP_BUSY) {
2098 if (host->cmd->data)
2099 DBG("Cannot wait for busy signal when also "
2100 "doing a data transfer");
f945405c 2101 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2102 return;
f945405c
BD		 2103
2104 /* The controller does not support the end-of-busy IRQ,
2105 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2106 }
2107
2108 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2109 sdhci_finish_command(host);
d129bceb
PO		 2110}
2111
0957c333 2112#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2113static void sdhci_show_adma_error(struct sdhci_host *host)
2114{
2115 const char *name = mmc_hostname(host->mmc);
2116 u8 *desc = host->adma_desc;
2117 __le32 *dma;
2118 __le16 *len;
2119 u8 attr;
2120
2121 sdhci_dumpregs(host);
2122
2123 while (true) {
2124 dma = (__le32 *)(desc + 4);
2125 len = (__le16 *)(desc + 2);
2126 attr = *desc;
2127
2128 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2129 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2130
2131 desc += 8;
2132
2133 if (attr & 2)
2134 break;
2135 }
2136}
2137#else
2138static void sdhci_show_adma_error(struct sdhci_host *host) { }
2139#endif
2140
d129bceb
PO		 2141static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2142{
2143 BUG_ON(intmask == 0);
2144
b513ea25
AN		 2145 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2146 if (intmask & SDHCI_INT_DATA_AVAIL) {
2147 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2148 MMC_SEND_TUNING_BLOCK) {
2149 host->tuning_done = 1;
2150 wake_up(&host->buf_ready_int);
2151 return;
2152 }
2153 }
2154
d129bceb
PO		 2155 if (!host->data) {
2156 /*
e809517f
PO		 2157 * The "data complete" interrupt is also used to
2158 * indicate that a busy state has ended. See comment
2159 * above in sdhci_cmd_irq().
d129bceb 2160 */
e809517f
PO		 2161 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2162 if (intmask & SDHCI_INT_DATA_END) {
2163 sdhci_finish_command(host);
2164 return;
2165 }
2166 }
d129bceb 2167
a3c76eb9 2168 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2169 "though no data operation was in progress.\n",
2170 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2171 sdhci_dumpregs(host);
2172
2173 return;
2174 }
2175
2176 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2177 host->data->error = -ETIMEDOUT;
22113efd
AL		 2178 else if (intmask & SDHCI_INT_DATA_END_BIT)
2179 host->data->error = -EILSEQ;
2180 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2181 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2182 != MMC_BUS_TEST_R)
17b0429d 2183 host->data->error = -EILSEQ;
6882a8c0 2184 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2185 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2186 sdhci_show_adma_error(host);
2134a922 2187 host->data->error = -EIO;
6882a8c0 2188 }
d129bceb 2189
17b0429d 2190 if (host->data->error)
d129bceb
PO		 2191 sdhci_finish_data(host);
2192 else {
a406f5a3 2193 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2194 sdhci_transfer_pio(host);
2195
6ba736a1
PO		 2196 /*
2197 * We currently don't do anything fancy with DMA
2198 * boundaries, but as we can't disable the feature
2199 * we need to at least restart the transfer.
f6a03cbf
MV		 2200 *
2201 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2202 * should return a valid address to continue from, but as
2203 * some controllers are faulty, don't trust them.
6ba736a1 2204 */
f6a03cbf
MV		 2205 if (intmask & SDHCI_INT_DMA_END) {
2206 u32 dmastart, dmanow;
2207 dmastart = sg_dma_address(host->data->sg);
2208 dmanow = dmastart + host->data->bytes_xfered;
2209 /*
2210 * Force update to the next DMA block boundary.
2211 */
2212 dmanow = (dmanow &
2213 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2214 SDHCI_DEFAULT_BOUNDARY_SIZE;
2215 host->data->bytes_xfered = dmanow - dmastart;
2216 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2217 " next 0x%08x\n",
2218 mmc_hostname(host->mmc), dmastart,
2219 host->data->bytes_xfered, dmanow);
2220 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2221 }
6ba736a1 2222
e538fbe8
PO		 2223 if (intmask & SDHCI_INT_DATA_END) {
2224 if (host->cmd) {
2225 /*
2226 * Data managed to finish before the
2227 * command completed. Make sure we do
2228 * things in the proper order.
2229 */
2230 host->data_early = 1;
2231 } else {
2232 sdhci_finish_data(host);
2233 }
2234 }
d129bceb
PO		 2235 }
2236}
2237
7d12e780 2238static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 2239{
2240 irqreturn_t result;
66fd8ad5 2241 struct sdhci_host *host = dev_id;
d129bceb 2242 u32 intmask;
f75979b7 2243 int cardint = 0;
d129bceb
PO		 2244
2245 spin_lock(&host->lock);
2246
66fd8ad5
AH		 2247 if (host->runtime_suspended) {
2248 spin_unlock(&host->lock);
a3c76eb9 2249 pr_warning("%s: got irq while runtime suspended\n",
66fd8ad5
AH		 2250 mmc_hostname(host->mmc));
2251 return IRQ_HANDLED;
2252 }
2253
4e4141a5 2254 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 2255
62df67a5 2256 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2257 result = IRQ_NONE;
2258 goto out;
2259 }
2260
b69c9058
PO		 2261 DBG("*** %s got interrupt: 0x%08x\n",
2262 mmc_hostname(host->mmc), intmask);
d129bceb 2263
3192a28f 2264 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d25928d1
SG		 2265 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2266 SDHCI_CARD_PRESENT;
2267
2268 /*
2269 * There is a observation on i.mx esdhc. INSERT bit will be
2270 * immediately set again when it gets cleared, if a card is
2271 * inserted. We have to mask the irq to prevent interrupt
2272 * storm which will freeze the system. And the REMOVE gets
2273 * the same situation.
2274 *
2275 * More testing are needed here to ensure it works for other
2276 * platforms though.
2277 */
2278 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2279 SDHCI_INT_CARD_REMOVE);
2280 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2281 SDHCI_INT_CARD_INSERT);
2282
4e4141a5 2283 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
d25928d1
SG		 2284 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2285 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 2286 tasklet_schedule(&host->card_tasklet);
3192a28f 2287 }
d129bceb 2288
3192a28f 2289 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 2290 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2291 SDHCI_INT_STATUS);
3192a28f 2292 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 2293 }
2294
2295 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 2296 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2297 SDHCI_INT_STATUS);
3192a28f 2298 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 2299 }
2300
2301 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2302
964f9ce2
PO		 2303 intmask &= ~SDHCI_INT_ERROR;
2304
d129bceb 2305 if (intmask & SDHCI_INT_BUS_POWER) {
a3c76eb9 2306 pr_err("%s: Card is consuming too much power!\n",
d129bceb 2307 mmc_hostname(host->mmc));
4e4141a5 2308 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 2309 }
2310
9d26a5d3 2311 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 2312
f75979b7
PO		 2313 if (intmask & SDHCI_INT_CARD_INT)
2314 cardint = 1;
2315
2316 intmask &= ~SDHCI_INT_CARD_INT;
2317
3192a28f 2318 if (intmask) {
a3c76eb9 2319 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3192a28f 2320 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 2321 sdhci_dumpregs(host);
2322
4e4141a5 2323 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 2324 }
d129bceb
PO		 2325
2326 result = IRQ_HANDLED;
2327
5f25a66f 2328 mmiowb();
d129bceb
PO		 2329out:
2330 spin_unlock(&host->lock);
2331
f75979b7
PO		 2332 /*
2333 * We have to delay this as it calls back into the driver.
2334 */
2335 if (cardint)
2336 mmc_signal_sdio_irq(host->mmc);
2337
d129bceb
PO		 2338 return result;
2339}
2340
2341/*****************************************************************************\
2342 * *
2343 * Suspend/resume *
2344 * *
2345\*****************************************************************************/
2346
2347#ifdef CONFIG_PM
2348
29495aa0 2349int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2350{
b8c86fc5 2351 int ret;
38a60ea2 2352 bool has_tuning_timer;
a715dfc7 2353
7260cf5e
AV		 2354 sdhci_disable_card_detection(host);
2355
cf2b5eea 2356 /* Disable tuning since we are suspending */
38a60ea2
AL		 2357 has_tuning_timer = host->version >= SDHCI_SPEC_300 &&
2358 host->tuning_count && host->tuning_mode == SDHCI_TUNING_MODE_1;
2359 if (has_tuning_timer) {
c6ced0db 2360 del_timer_sync(&host->tuning_timer);
cf2b5eea 2361 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2362 }
2363
1a13f8fa 2364 ret = mmc_suspend_host(host->mmc);
38a60ea2
AL		 2365 if (ret) {
2366 if (has_tuning_timer) {
2367 host->flags |= SDHCI_NEEDS_RETUNING;
2368 mod_timer(&host->tuning_timer, jiffies +
2369 host->tuning_count * HZ);
2370 }
2371
2372 sdhci_enable_card_detection(host);
2373
b8c86fc5 2374 return ret;
38a60ea2 2375 }
a715dfc7 2376
b8c86fc5 2377 free_irq(host->irq, host);
d129bceb 2378
9bea3c85 2379 return ret;
d129bceb
PO		 2380}
2381
b8c86fc5 2382EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2383
b8c86fc5
PO		 2384int sdhci_resume_host(struct sdhci_host *host)
2385{
2386 int ret;
d129bceb 2387
a13abc7b 2388 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2389 if (host->ops->enable_dma)
2390 host->ops->enable_dma(host);
2391 }
d129bceb 2392
b8c86fc5
PO		 2393 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2394 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 2395 if (ret)
2396 return ret;
d129bceb 2397
2f4cbb3d 2398 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
b8c86fc5
PO		 2399 mmiowb();
2400
2401 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 2402 sdhci_enable_card_detection(host);
2403
cf2b5eea
AN		 2404 /* Set the re-tuning expiration flag */
2405 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2406 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2407 host->flags |= SDHCI_NEEDS_RETUNING;
2408
2f4cbb3d 2409 return ret;
d129bceb
PO		 2410}
2411
b8c86fc5 2412EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb 2413
5f619704
DD		 2414void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2415{
2416 u8 val;
2417 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2418 val |= SDHCI_WAKE_ON_INT;
2419 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2420}
2421
2422EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2423
d129bceb
PO		 2424#endif /* CONFIG_PM */
2425
66fd8ad5
AH		 2426#ifdef CONFIG_PM_RUNTIME
2427
2428static int sdhci_runtime_pm_get(struct sdhci_host *host)
2429{
2430 return pm_runtime_get_sync(host->mmc->parent);
2431}
2432
2433static int sdhci_runtime_pm_put(struct sdhci_host *host)
2434{
2435 pm_runtime_mark_last_busy(host->mmc->parent);
2436 return pm_runtime_put_autosuspend(host->mmc->parent);
2437}
2438
2439int sdhci_runtime_suspend_host(struct sdhci_host *host)
2440{
2441 unsigned long flags;
2442 int ret = 0;
2443
2444 /* Disable tuning since we are suspending */
2445 if (host->version >= SDHCI_SPEC_300 &&
2446 host->tuning_mode == SDHCI_TUNING_MODE_1) {
2447 del_timer_sync(&host->tuning_timer);
2448 host->flags &= ~SDHCI_NEEDS_RETUNING;
2449 }
2450
2451 spin_lock_irqsave(&host->lock, flags);
2452 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2453 spin_unlock_irqrestore(&host->lock, flags);
2454
2455 synchronize_irq(host->irq);
2456
2457 spin_lock_irqsave(&host->lock, flags);
2458 host->runtime_suspended = true;
2459 spin_unlock_irqrestore(&host->lock, flags);
2460
2461 return ret;
2462}
2463EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2464
2465int sdhci_runtime_resume_host(struct sdhci_host *host)
2466{
2467 unsigned long flags;
2468 int ret = 0, host_flags = host->flags;
2469
2470 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2471 if (host->ops->enable_dma)
2472 host->ops->enable_dma(host);
2473 }
2474
2475 sdhci_init(host, 0);
2476
2477 /* Force clock and power re-program */
2478 host->pwr = 0;
2479 host->clock = 0;
2480 sdhci_do_set_ios(host, &host->mmc->ios);
2481
2482 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2483 if (host_flags & SDHCI_PV_ENABLED)
2484 sdhci_do_enable_preset_value(host, true);
2485
2486 /* Set the re-tuning expiration flag */
2487 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2488 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2489 host->flags |= SDHCI_NEEDS_RETUNING;
2490
2491 spin_lock_irqsave(&host->lock, flags);
2492
2493 host->runtime_suspended = false;
2494
2495 /* Enable SDIO IRQ */
2496 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2497 sdhci_enable_sdio_irq_nolock(host, true);
2498
2499 /* Enable Card Detection */
2500 sdhci_enable_card_detection(host);
2501
2502 spin_unlock_irqrestore(&host->lock, flags);
2503
2504 return ret;
2505}
2506EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2507
2508#endif
2509
d129bceb
PO		 2510/*****************************************************************************\
2511 * *
b8c86fc5 2512 * Device allocation/registration *
d129bceb
PO		 2513 * *
2514\*****************************************************************************/
2515
b8c86fc5
PO		 2516struct sdhci_host *sdhci_alloc_host(struct device *dev,
2517 size_t priv_size)
d129bceb 2518{
d129bceb
PO		 2519 struct mmc_host *mmc;
2520 struct sdhci_host *host;
2521
b8c86fc5 2522 WARN_ON(dev == NULL);
d129bceb 2523
b8c86fc5 2524 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2525 if (!mmc)
b8c86fc5 2526 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2527
2528 host = mmc_priv(mmc);
2529 host->mmc = mmc;
2530
b8c86fc5
PO		 2531 return host;
2532}
8a4da143 2533
b8c86fc5 2534EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2535
b8c86fc5
PO		 2536int sdhci_add_host(struct sdhci_host *host)
2537{
2538 struct mmc_host *mmc;
f2119df6
AN		 2539 u32 caps[2];
2540 u32 max_current_caps;
2541 unsigned int ocr_avail;
b8c86fc5 2542 int ret;
d129bceb 2543
b8c86fc5
PO		 2544 WARN_ON(host == NULL);
2545 if (host == NULL)
2546 return -EINVAL;
d129bceb 2547
b8c86fc5 2548 mmc = host->mmc;
d129bceb 2549
b8c86fc5
PO		 2550 if (debug_quirks)
2551 host->quirks = debug_quirks;
66fd8ad5
AH		 2552 if (debug_quirks2)
2553 host->quirks2 = debug_quirks2;
d129bceb 2554
d96649ed
PO		 2555 sdhci_reset(host, SDHCI_RESET_ALL);
2556
4e4141a5 2557 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2558 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2559 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2560 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2561 pr_err("%s: Unknown controller version (%d). "
b69c9058 2562 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2563 host->version);
4a965505
PO		 2564 }
2565
f2119df6 2566 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2567 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2568
f2119df6
AN		 2569 caps[1] = (host->version >= SDHCI_SPEC_300) ?
2570 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2571
b8c86fc5 2572 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2573 host->flags |= SDHCI_USE_SDMA;
f2119df6 2574 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2575 DBG("Controller doesn't have SDMA capability\n");
67435274 2576 else
a13abc7b 2577 host->flags |= SDHCI_USE_SDMA;
d129bceb 2578
b8c86fc5 2579 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2580 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2581 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2582 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2583 }
2584
f2119df6
AN		 2585 if ((host->version >= SDHCI_SPEC_200) &&
2586 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2587 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2588
2589 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2590 (host->flags & SDHCI_USE_ADMA)) {
2591 DBG("Disabling ADMA as it is marked broken\n");
2592 host->flags &= ~SDHCI_USE_ADMA;
2593 }
2594
a13abc7b 2595 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2596 if (host->ops->enable_dma) {
2597 if (host->ops->enable_dma(host)) {
a3c76eb9 2598 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2599 "available. Falling back to PIO.\n",
2600 mmc_hostname(mmc));
a13abc7b
RR		 2601 host->flags &=
2602 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2603 }
d129bceb
PO		 2604 }
2605 }
2606
2134a922
PO		 2607 if (host->flags & SDHCI_USE_ADMA) {
2608 /*
2609 * We need to allocate descriptors for all sg entries
2610 * (128) and potentially one alignment transfer for
2611 * each of those entries.
2612 */
2613 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2614 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2615 if (!host->adma_desc || !host->align_buffer) {
2616 kfree(host->adma_desc);
2617 kfree(host->align_buffer);
a3c76eb9 2618 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2619 "buffers. Falling back to standard DMA.\n",
2620 mmc_hostname(mmc));
2621 host->flags &= ~SDHCI_USE_ADMA;
2622 }
2623 }
2624
7659150c
PO		 2625 /*
2626 * If we use DMA, then it's up to the caller to set the DMA
2627 * mask, but PIO does not need the hw shim so we set a new
2628 * mask here in that case.
2629 */
a13abc7b 2630 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2631 host->dma_mask = DMA_BIT_MASK(64);
2632 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2633 }
d129bceb 2634
c4687d5f 2635 if (host->version >= SDHCI_SPEC_300)
f2119df6 2636 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2637 >> SDHCI_CLOCK_BASE_SHIFT;
2638 else
f2119df6 2639 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2640 >> SDHCI_CLOCK_BASE_SHIFT;
2641
4240ff0a 2642 host->max_clk *= 1000000;
f27f47ef
AV		 2643 if (host->max_clk == 0 || host->quirks &
2644 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2645 if (!host->ops->get_max_clock) {
a3c76eb9 2646 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2647 "frequency.\n", mmc_hostname(mmc));
2648 return -ENODEV;
2649 }
2650 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2651 }
d129bceb 2652
c3ed3877
AN		 2653 /*
2654 * In case of Host Controller v3.00, find out whether clock
2655 * multiplier is supported.
2656 */
2657 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2658 SDHCI_CLOCK_MUL_SHIFT;
2659
2660 /*
2661 * In case the value in Clock Multiplier is 0, then programmable
2662 * clock mode is not supported, otherwise the actual clock
2663 * multiplier is one more than the value of Clock Multiplier
2664 * in the Capabilities Register.
2665 */
2666 if (host->clk_mul)
2667 host->clk_mul += 1;
2668
d129bceb
PO		 2669 /*
2670 * Set host parameters.
2671 */
2672 mmc->ops = &sdhci_ops;
c3ed3877 2673 mmc->f_max = host->max_clk;
ce5f036b 2674 if (host->ops->get_min_clock)
a9e58f25 2675 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2676 else if (host->version >= SDHCI_SPEC_300) {
2677 if (host->clk_mul) {
2678 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2679 mmc->f_max = host->max_clk * host->clk_mul;
2680 } else
2681 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2682 } else
0397526d 2683 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2684
272308ca
AS		 2685 host->timeout_clk =
2686 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2687 if (host->timeout_clk == 0) {
2688 if (host->ops->get_timeout_clock) {
2689 host->timeout_clk = host->ops->get_timeout_clock(host);
2690 } else if (!(host->quirks &
2691 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2692 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2693 "frequency.\n", mmc_hostname(mmc));
2694 return -ENODEV;
2695 }
2696 }
2697 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2698 host->timeout_clk *= 1000;
2699
2700 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2701 host->timeout_clk = mmc->f_max / 1000;
272308ca 2702
65be3fef 2703 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
58d1246d 2704
e89d456f
AW		 2705 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2706
2707 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2708 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2709
8edf6371 2710 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2711 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2712 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2713 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2714 host->flags |= SDHCI_AUTO_CMD23;
2715 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2716 } else {
2717 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2718 }
2719
15ec4461
PR		 2720 /*
2721 * A controller may support 8-bit width, but the board itself
2722 * might not have the pins brought out. Boards that support
2723 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2724 * their platform code before calling sdhci_add_host(), and we
2725 * won't assume 8-bit width for hosts without that CAP.
2726 */
5fe23c7f 2727 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2728 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2729
f2119df6 2730 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2731 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2732
176d1ed4
JC		 2733 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2734 mmc_card_is_removable(mmc))
68d1fb7e
AV		 2735 mmc->caps |= MMC_CAP_NEEDS_POLL;
2736
f2119df6
AN		 2737 /* UHS-I mode(s) supported by the host controller. */
2738 if (host->version >= SDHCI_SPEC_300)
2739 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2740
2741 /* SDR104 supports also implies SDR50 support */
2742 if (caps[1] & SDHCI_SUPPORT_SDR104)
2743 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2744 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2745 mmc->caps |= MMC_CAP_UHS_SDR50;
2746
2747 if (caps[1] & SDHCI_SUPPORT_DDR50)
2748 mmc->caps |= MMC_CAP_UHS_DDR50;
2749
b513ea25
AN		 2750 /* Does the host needs tuning for SDR50? */
2751 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2752 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2753
d6d50a15
AN		 2754 /* Driver Type(s) (A, C, D) supported by the host */
2755 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2756 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2757 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2758 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2759 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2760 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2761
bec8726a
G		 2762 /*
2763 * If Power Off Notify capability is enabled by the host,
2764 * set notify to short power off notify timeout value.
2765 */
2766 if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2767 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2768 else
2769 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2770
cf2b5eea
AN		 2771 /* Initial value for re-tuning timer count */
2772 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2773 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2774
2775 /*
2776 * In case Re-tuning Timer is not disabled, the actual value of
2777 * re-tuning timer will be 2 ^ (n - 1).
2778 */
2779 if (host->tuning_count)
2780 host->tuning_count = 1 << (host->tuning_count - 1);
2781
2782 /* Re-tuning mode supported by the Host Controller */
2783 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2784 SDHCI_RETUNING_MODE_SHIFT;
2785
8f230f45 2786 ocr_avail = 0;
f2119df6
AN		 2787 /*
2788 * According to SD Host Controller spec v3.00, if the Host System
2789 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2790 * the value is meaningful only if Voltage Support in the Capabilities
2791 * register is set. The actual current value is 4 times the register
2792 * value.
2793 */
2794 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2795
2796 if (caps[0] & SDHCI_CAN_VDD_330) {
2797 int max_current_330;
2798
8f230f45 2799 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6
AN		 2800
2801 max_current_330 = ((max_current_caps &
2802 SDHCI_MAX_CURRENT_330_MASK) >>
2803 SDHCI_MAX_CURRENT_330_SHIFT) *
2804 SDHCI_MAX_CURRENT_MULTIPLIER;
2805
2806 if (max_current_330 > 150)
2807 mmc->caps |= MMC_CAP_SET_XPC_330;
2808 }
2809 if (caps[0] & SDHCI_CAN_VDD_300) {
2810 int max_current_300;
2811
8f230f45 2812 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6
AN		 2813
2814 max_current_300 = ((max_current_caps &
2815 SDHCI_MAX_CURRENT_300_MASK) >>
2816 SDHCI_MAX_CURRENT_300_SHIFT) *
2817 SDHCI_MAX_CURRENT_MULTIPLIER;
2818
2819 if (max_current_300 > 150)
2820 mmc->caps |= MMC_CAP_SET_XPC_300;
2821 }
2822 if (caps[0] & SDHCI_CAN_VDD_180) {
2823 int max_current_180;
2824
8f230f45
TI		 2825 ocr_avail |= MMC_VDD_165_195;
2826
f2119df6
AN		 2827 max_current_180 = ((max_current_caps &
2828 SDHCI_MAX_CURRENT_180_MASK) >>
2829 SDHCI_MAX_CURRENT_180_SHIFT) *
2830 SDHCI_MAX_CURRENT_MULTIPLIER;
2831
2832 if (max_current_180 > 150)
2833 mmc->caps |= MMC_CAP_SET_XPC_180;
5371c927
AN		 2834
2835 /* Maximum current capabilities of the host at 1.8V */
2836 if (max_current_180 >= 800)
2837 mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2838 else if (max_current_180 >= 600)
2839 mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2840 else if (max_current_180 >= 400)
2841 mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2842 else
2843 mmc->caps |= MMC_CAP_MAX_CURRENT_200;
f2119df6
AN		 2844 }
2845
8f230f45
TI		 2846 mmc->ocr_avail = ocr_avail;
2847 mmc->ocr_avail_sdio = ocr_avail;
2848 if (host->ocr_avail_sdio)
2849 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2850 mmc->ocr_avail_sd = ocr_avail;
2851 if (host->ocr_avail_sd)
2852 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2853 else /* normal SD controllers don't support 1.8V */
2854 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2855 mmc->ocr_avail_mmc = ocr_avail;
2856 if (host->ocr_avail_mmc)
2857 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 2858
2859 if (mmc->ocr_avail == 0) {
a3c76eb9 2860 pr_err("%s: Hardware doesn't report any "
b69c9058 2861 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 2862 return -ENODEV;
146ad66e
PO		 2863 }
2864
d129bceb
PO		 2865 spin_lock_init(&host->lock);
2866
2867 /*
2134a922
PO		 2868 * Maximum number of segments. Depends on if the hardware
2869 * can do scatter/gather or not.
d129bceb 2870 */
2134a922 2871 if (host->flags & SDHCI_USE_ADMA)
a36274e0 2872 mmc->max_segs = 128;
a13abc7b 2873 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 2874 mmc->max_segs = 1;
2134a922 2875 else /* PIO */
a36274e0 2876 mmc->max_segs = 128;
d129bceb
PO		 2877
2878 /*
bab76961 2879 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 2880 * size (512KiB).
d129bceb 2881 */
55db890a 2882 mmc->max_req_size = 524288;
d129bceb
PO		 2883
2884 /*
2885 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 2886 * of bytes. When doing hardware scatter/gather, each entry cannot
2887 * be larger than 64 KiB though.
d129bceb 2888 */
30652aa3
OJ		 2889 if (host->flags & SDHCI_USE_ADMA) {
2890 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2891 mmc->max_seg_size = 65535;
2892 else
2893 mmc->max_seg_size = 65536;
2894 } else {
2134a922 2895 mmc->max_seg_size = mmc->max_req_size;
30652aa3 2896 }
d129bceb 2897
fe4a3c7a
PO		 2898 /*
2899 * Maximum block size. This varies from controller to controller and
2900 * is specified in the capabilities register.
2901 */
0633f654
AV		 2902 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2903 mmc->max_blk_size = 2;
2904 } else {
f2119df6 2905 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 2906 SDHCI_MAX_BLOCK_SHIFT;
2907 if (mmc->max_blk_size >= 3) {
a3c76eb9 2908 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 2909 "assuming 512 bytes\n", mmc_hostname(mmc));
2910 mmc->max_blk_size = 0;
2911 }
2912 }
2913
2914 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 2915
55db890a
PO		 2916 /*
2917 * Maximum block count.
2918 */
1388eefd 2919 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 2920
d129bceb
PO		 2921 /*
2922 * Init tasklets.
2923 */
2924 tasklet_init(&host->card_tasklet,
2925 sdhci_tasklet_card, (unsigned long)host);
2926 tasklet_init(&host->finish_tasklet,
2927 sdhci_tasklet_finish, (unsigned long)host);
2928
e4cad1b5 2929 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 2930
cf2b5eea 2931 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 2932 init_waitqueue_head(&host->buf_ready_int);
2933
cf2b5eea
AN		 2934 /* Initialize re-tuning timer */
2935 init_timer(&host->tuning_timer);
2936 host->tuning_timer.data = (unsigned long)host;
2937 host->tuning_timer.function = sdhci_tuning_timer;
2938 }
2939
dace1453 2940 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 2941 mmc_hostname(mmc), host);
d129bceb 2942 if (ret)
8ef1a143 2943 goto untasklet;
d129bceb 2944
9bea3c85
MS		 2945 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2946 if (IS_ERR(host->vmmc)) {
a3c76eb9 2947 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
9bea3c85 2948 host->vmmc = NULL;
9bea3c85
MS		 2949 }
2950
2f4cbb3d 2951 sdhci_init(host, 0);
d129bceb
PO		 2952
2953#ifdef CONFIG_MMC_DEBUG
2954 sdhci_dumpregs(host);
2955#endif
2956
f9134319 2957#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 2958 snprintf(host->led_name, sizeof(host->led_name),
2959 "%s::", mmc_hostname(mmc));
2960 host->led.name = host->led_name;
2f730fec
PO		 2961 host->led.brightness = LED_OFF;
2962 host->led.default_trigger = mmc_hostname(mmc);
2963 host->led.brightness_set = sdhci_led_control;
2964
b8c86fc5 2965 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 2966 if (ret)
2967 goto reset;
2968#endif
2969
5f25a66f
PO		 2970 mmiowb();
2971
d129bceb
PO		 2972 mmc_add_host(mmc);
2973
a3c76eb9 2974 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 2975 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 2976 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2977 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 2978
7260cf5e
AV		 2979 sdhci_enable_card_detection(host);
2980
d129bceb
PO		 2981 return 0;
2982
f9134319 2983#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2984reset:
2985 sdhci_reset(host, SDHCI_RESET_ALL);
2986 free_irq(host->irq, host);
2987#endif
8ef1a143 2988untasklet:
d129bceb
PO		 2989 tasklet_kill(&host->card_tasklet);
2990 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 2991
2992 return ret;
2993}
2994
b8c86fc5 2995EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 2996
1e72859e 2997void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 2998{
1e72859e
PO		 2999 unsigned long flags;
3000
3001 if (dead) {
3002 spin_lock_irqsave(&host->lock, flags);
3003
3004 host->flags |= SDHCI_DEVICE_DEAD;
3005
3006 if (host->mrq) {
a3c76eb9 3007 pr_err("%s: Controller removed during "
1e72859e
PO		 3008 " transfer!\n", mmc_hostname(host->mmc));
3009
3010 host->mrq->cmd->error = -ENOMEDIUM;
3011 tasklet_schedule(&host->finish_tasklet);
3012 }
3013
3014 spin_unlock_irqrestore(&host->lock, flags);
3015 }
3016
7260cf5e
AV		 3017 sdhci_disable_card_detection(host);
3018
b8c86fc5 3019 mmc_remove_host(host->mmc);
d129bceb 3020
f9134319 3021#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3022 led_classdev_unregister(&host->led);
3023#endif
3024
1e72859e
PO		 3025 if (!dead)
3026 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 3027
3028 free_irq(host->irq, host);
3029
3030 del_timer_sync(&host->timer);
cf2b5eea
AN		 3031 if (host->version >= SDHCI_SPEC_300)
3032 del_timer_sync(&host->tuning_timer);
d129bceb
PO		 3033
3034 tasklet_kill(&host->card_tasklet);
3035 tasklet_kill(&host->finish_tasklet);
2134a922 3036
ceb6143b 3037 if (host->vmmc)
9bea3c85 3038 regulator_put(host->vmmc);
9bea3c85 3039
2134a922
PO		 3040 kfree(host->adma_desc);
3041 kfree(host->align_buffer);
3042
3043 host->adma_desc = NULL;
3044 host->align_buffer = NULL;
d129bceb
PO		 3045}
3046
b8c86fc5 3047EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3048
b8c86fc5 3049void sdhci_free_host(struct sdhci_host *host)
d129bceb 3050{
b8c86fc5 3051 mmc_free_host(host->mmc);
d129bceb
PO		 3052}
3053
b8c86fc5 3054EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3055
3056/*****************************************************************************\
3057 * *
3058 * Driver init/exit *
3059 * *
3060\*****************************************************************************/
3061
3062static int __init sdhci_drv_init(void)
3063{
a3c76eb9 3064 pr_info(DRIVER_NAME
52fbf9c9 3065 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3066 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3067
b8c86fc5 3068 return 0;
d129bceb
PO		 3069}
3070
3071static void __exit sdhci_drv_exit(void)
3072{
d129bceb
PO		 3073}
3074
3075module_init(sdhci_drv_init);
3076module_exit(sdhci_drv_exit);
3077
df673b22 3078module_param(debug_quirks, uint, 0444);
66fd8ad5 3079module_param(debug_quirks2, uint, 0444);
67435274 3080
32710e8f 3081MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3082MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3083MODULE_LICENSE("GPL");
67435274 3084
df673b22 3085MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3086MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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