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Commit | Line | Data |
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d129bceb | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
d129bceb | 3 | * |
b69c9058 | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
d129bceb PO |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
84c46a53 PO |
10 | * |
11 | * Thanks to the following companies for their support: | |
12 | * | |
13 | * - JMicron (hardware and technical support) | |
d129bceb PO |
14 | */ |
15 | ||
d129bceb PO |
16 | #include <linux/delay.h> |
17 | #include <linux/highmem.h> | |
b8c86fc5 | 18 | #include <linux/io.h> |
88b47679 | 19 | #include <linux/module.h> |
d129bceb | 20 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 21 | #include <linux/slab.h> |
11763609 | 22 | #include <linux/scatterlist.h> |
9bea3c85 | 23 | #include <linux/regulator/consumer.h> |
66fd8ad5 | 24 | #include <linux/pm_runtime.h> |
d129bceb | 25 | |
2f730fec PO |
26 | #include <linux/leds.h> |
27 | ||
22113efd | 28 | #include <linux/mmc/mmc.h> |
d129bceb | 29 | #include <linux/mmc/host.h> |
473b095a | 30 | #include <linux/mmc/card.h> |
bec9d4e5 | 31 | #include <linux/mmc/slot-gpio.h> |
d129bceb | 32 | |
d129bceb PO |
33 | #include "sdhci.h" |
34 | ||
35 | #define DRIVER_NAME "sdhci" | |
d129bceb | 36 | |
d129bceb | 37 | #define DBG(f, x...) \ |
c6563178 | 38 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
d129bceb | 39 | |
f9134319 PO |
40 | #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ |
41 | defined(CONFIG_MMC_SDHCI_MODULE)) | |
42 | #define SDHCI_USE_LEDS_CLASS | |
43 | #endif | |
44 | ||
b513ea25 AN |
45 | #define MAX_TUNING_LOOP 40 |
46 | ||
df673b22 | 47 | static unsigned int debug_quirks = 0; |
66fd8ad5 | 48 | static unsigned int debug_quirks2; |
67435274 | 49 | |
d129bceb PO |
50 | static void sdhci_finish_data(struct sdhci_host *); |
51 | ||
d129bceb | 52 | static void sdhci_finish_command(struct sdhci_host *); |
069c9f14 | 53 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); |
cf2b5eea | 54 | static void sdhci_tuning_timer(unsigned long data); |
52983382 | 55 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); |
d129bceb | 56 | |
66fd8ad5 AH |
57 | #ifdef CONFIG_PM_RUNTIME |
58 | static int sdhci_runtime_pm_get(struct sdhci_host *host); | |
59 | static int sdhci_runtime_pm_put(struct sdhci_host *host); | |
f0710a55 AH |
60 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host); |
61 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host); | |
66fd8ad5 AH |
62 | #else |
63 | static inline int sdhci_runtime_pm_get(struct sdhci_host *host) | |
64 | { | |
65 | return 0; | |
66 | } | |
67 | static inline int sdhci_runtime_pm_put(struct sdhci_host *host) | |
68 | { | |
69 | return 0; | |
70 | } | |
f0710a55 AH |
71 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) |
72 | { | |
73 | } | |
74 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) | |
75 | { | |
76 | } | |
66fd8ad5 AH |
77 | #endif |
78 | ||
d129bceb PO |
79 | static void sdhci_dumpregs(struct sdhci_host *host) |
80 | { | |
a3c76eb9 | 81 | pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", |
412ab659 | 82 | mmc_hostname(host->mmc)); |
d129bceb | 83 | |
a3c76eb9 | 84 | pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", |
4e4141a5 AV |
85 | sdhci_readl(host, SDHCI_DMA_ADDRESS), |
86 | sdhci_readw(host, SDHCI_HOST_VERSION)); | |
a3c76eb9 | 87 | pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", |
4e4141a5 AV |
88 | sdhci_readw(host, SDHCI_BLOCK_SIZE), |
89 | sdhci_readw(host, SDHCI_BLOCK_COUNT)); | |
a3c76eb9 | 90 | pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", |
4e4141a5 AV |
91 | sdhci_readl(host, SDHCI_ARGUMENT), |
92 | sdhci_readw(host, SDHCI_TRANSFER_MODE)); | |
a3c76eb9 | 93 | pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", |
4e4141a5 AV |
94 | sdhci_readl(host, SDHCI_PRESENT_STATE), |
95 | sdhci_readb(host, SDHCI_HOST_CONTROL)); | |
a3c76eb9 | 96 | pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", |
4e4141a5 AV |
97 | sdhci_readb(host, SDHCI_POWER_CONTROL), |
98 | sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); | |
a3c76eb9 | 99 | pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", |
4e4141a5 AV |
100 | sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), |
101 | sdhci_readw(host, SDHCI_CLOCK_CONTROL)); | |
a3c76eb9 | 102 | pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", |
4e4141a5 AV |
103 | sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), |
104 | sdhci_readl(host, SDHCI_INT_STATUS)); | |
a3c76eb9 | 105 | pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", |
4e4141a5 AV |
106 | sdhci_readl(host, SDHCI_INT_ENABLE), |
107 | sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); | |
a3c76eb9 | 108 | pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", |
4e4141a5 AV |
109 | sdhci_readw(host, SDHCI_ACMD12_ERR), |
110 | sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); | |
a3c76eb9 | 111 | pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", |
4e4141a5 | 112 | sdhci_readl(host, SDHCI_CAPABILITIES), |
e8120ad1 | 113 | sdhci_readl(host, SDHCI_CAPABILITIES_1)); |
a3c76eb9 | 114 | pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", |
e8120ad1 | 115 | sdhci_readw(host, SDHCI_COMMAND), |
4e4141a5 | 116 | sdhci_readl(host, SDHCI_MAX_CURRENT)); |
a3c76eb9 | 117 | pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", |
f2119df6 | 118 | sdhci_readw(host, SDHCI_HOST_CONTROL2)); |
d129bceb | 119 | |
e57a5f61 AH |
120 | if (host->flags & SDHCI_USE_ADMA) { |
121 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
122 | pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", | |
123 | readl(host->ioaddr + SDHCI_ADMA_ERROR), | |
124 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI), | |
125 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); | |
126 | else | |
127 | pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", | |
128 | readl(host->ioaddr + SDHCI_ADMA_ERROR), | |
129 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); | |
130 | } | |
be3f4ae0 | 131 | |
a3c76eb9 | 132 | pr_debug(DRIVER_NAME ": ===========================================\n"); |
d129bceb PO |
133 | } |
134 | ||
135 | /*****************************************************************************\ | |
136 | * * | |
137 | * Low level functions * | |
138 | * * | |
139 | \*****************************************************************************/ | |
140 | ||
7260cf5e AV |
141 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) |
142 | { | |
5b4f1f6c | 143 | u32 present; |
7260cf5e | 144 | |
c79396c1 | 145 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || |
87b87a3f | 146 | (host->mmc->caps & MMC_CAP_NONREMOVABLE)) |
66fd8ad5 AH |
147 | return; |
148 | ||
5b4f1f6c RK |
149 | if (enable) { |
150 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
151 | SDHCI_CARD_PRESENT; | |
d25928d1 | 152 | |
5b4f1f6c RK |
153 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : |
154 | SDHCI_INT_CARD_INSERT; | |
155 | } else { | |
156 | host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); | |
157 | } | |
b537f94c RK |
158 | |
159 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
160 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
7260cf5e AV |
161 | } |
162 | ||
163 | static void sdhci_enable_card_detection(struct sdhci_host *host) | |
164 | { | |
165 | sdhci_set_card_detection(host, true); | |
166 | } | |
167 | ||
168 | static void sdhci_disable_card_detection(struct sdhci_host *host) | |
169 | { | |
170 | sdhci_set_card_detection(host, false); | |
171 | } | |
172 | ||
03231f9b | 173 | void sdhci_reset(struct sdhci_host *host, u8 mask) |
d129bceb | 174 | { |
e16514d8 | 175 | unsigned long timeout; |
393c1a34 | 176 | |
4e4141a5 | 177 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
d129bceb | 178 | |
f0710a55 | 179 | if (mask & SDHCI_RESET_ALL) { |
d129bceb | 180 | host->clock = 0; |
f0710a55 AH |
181 | /* Reset-all turns off SD Bus Power */ |
182 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) | |
183 | sdhci_runtime_pm_bus_off(host); | |
184 | } | |
d129bceb | 185 | |
e16514d8 PO |
186 | /* Wait max 100 ms */ |
187 | timeout = 100; | |
188 | ||
189 | /* hw clears the bit when it's done */ | |
4e4141a5 | 190 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { |
e16514d8 | 191 | if (timeout == 0) { |
a3c76eb9 | 192 | pr_err("%s: Reset 0x%x never completed.\n", |
e16514d8 PO |
193 | mmc_hostname(host->mmc), (int)mask); |
194 | sdhci_dumpregs(host); | |
195 | return; | |
196 | } | |
197 | timeout--; | |
198 | mdelay(1); | |
d129bceb | 199 | } |
03231f9b RK |
200 | } |
201 | EXPORT_SYMBOL_GPL(sdhci_reset); | |
202 | ||
203 | static void sdhci_do_reset(struct sdhci_host *host, u8 mask) | |
204 | { | |
205 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { | |
206 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
207 | SDHCI_CARD_PRESENT)) | |
208 | return; | |
209 | } | |
063a9dbb | 210 | |
03231f9b | 211 | host->ops->reset(host, mask); |
393c1a34 | 212 | |
da91a8f9 RK |
213 | if (mask & SDHCI_RESET_ALL) { |
214 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { | |
215 | if (host->ops->enable_dma) | |
216 | host->ops->enable_dma(host); | |
217 | } | |
218 | ||
219 | /* Resetting the controller clears many */ | |
220 | host->preset_enabled = false; | |
3abc1e80 | 221 | } |
d129bceb PO |
222 | } |
223 | ||
2f4cbb3d NP |
224 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); |
225 | ||
226 | static void sdhci_init(struct sdhci_host *host, int soft) | |
d129bceb | 227 | { |
2f4cbb3d | 228 | if (soft) |
03231f9b | 229 | sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); |
2f4cbb3d | 230 | else |
03231f9b | 231 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
d129bceb | 232 | |
b537f94c RK |
233 | host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | |
234 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | | |
235 | SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | | |
236 | SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | | |
237 | SDHCI_INT_RESPONSE; | |
238 | ||
239 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
240 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
2f4cbb3d NP |
241 | |
242 | if (soft) { | |
243 | /* force clock reconfiguration */ | |
244 | host->clock = 0; | |
245 | sdhci_set_ios(host->mmc, &host->mmc->ios); | |
246 | } | |
7260cf5e | 247 | } |
d129bceb | 248 | |
7260cf5e AV |
249 | static void sdhci_reinit(struct sdhci_host *host) |
250 | { | |
2f4cbb3d | 251 | sdhci_init(host, 0); |
b67c6b41 AL |
252 | /* |
253 | * Retuning stuffs are affected by different cards inserted and only | |
254 | * applicable to UHS-I cards. So reset these fields to their initial | |
255 | * value when card is removed. | |
256 | */ | |
973905fe AL |
257 | if (host->flags & SDHCI_USING_RETUNING_TIMER) { |
258 | host->flags &= ~SDHCI_USING_RETUNING_TIMER; | |
259 | ||
b67c6b41 AL |
260 | del_timer_sync(&host->tuning_timer); |
261 | host->flags &= ~SDHCI_NEEDS_RETUNING; | |
262 | host->mmc->max_blk_count = | |
263 | (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; | |
264 | } | |
7260cf5e | 265 | sdhci_enable_card_detection(host); |
d129bceb PO |
266 | } |
267 | ||
268 | static void sdhci_activate_led(struct sdhci_host *host) | |
269 | { | |
270 | u8 ctrl; | |
271 | ||
4e4141a5 | 272 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 273 | ctrl |= SDHCI_CTRL_LED; |
4e4141a5 | 274 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
275 | } |
276 | ||
277 | static void sdhci_deactivate_led(struct sdhci_host *host) | |
278 | { | |
279 | u8 ctrl; | |
280 | ||
4e4141a5 | 281 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 282 | ctrl &= ~SDHCI_CTRL_LED; |
4e4141a5 | 283 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
284 | } |
285 | ||
f9134319 | 286 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
287 | static void sdhci_led_control(struct led_classdev *led, |
288 | enum led_brightness brightness) | |
289 | { | |
290 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); | |
291 | unsigned long flags; | |
292 | ||
293 | spin_lock_irqsave(&host->lock, flags); | |
294 | ||
66fd8ad5 AH |
295 | if (host->runtime_suspended) |
296 | goto out; | |
297 | ||
2f730fec PO |
298 | if (brightness == LED_OFF) |
299 | sdhci_deactivate_led(host); | |
300 | else | |
301 | sdhci_activate_led(host); | |
66fd8ad5 | 302 | out: |
2f730fec PO |
303 | spin_unlock_irqrestore(&host->lock, flags); |
304 | } | |
305 | #endif | |
306 | ||
d129bceb PO |
307 | /*****************************************************************************\ |
308 | * * | |
309 | * Core functions * | |
310 | * * | |
311 | \*****************************************************************************/ | |
312 | ||
a406f5a3 | 313 | static void sdhci_read_block_pio(struct sdhci_host *host) |
d129bceb | 314 | { |
7659150c PO |
315 | unsigned long flags; |
316 | size_t blksize, len, chunk; | |
7244b85b | 317 | u32 uninitialized_var(scratch); |
7659150c | 318 | u8 *buf; |
d129bceb | 319 | |
a406f5a3 | 320 | DBG("PIO reading\n"); |
d129bceb | 321 | |
a406f5a3 | 322 | blksize = host->data->blksz; |
7659150c | 323 | chunk = 0; |
d129bceb | 324 | |
7659150c | 325 | local_irq_save(flags); |
d129bceb | 326 | |
a406f5a3 | 327 | while (blksize) { |
7659150c PO |
328 | if (!sg_miter_next(&host->sg_miter)) |
329 | BUG(); | |
d129bceb | 330 | |
7659150c | 331 | len = min(host->sg_miter.length, blksize); |
d129bceb | 332 | |
7659150c PO |
333 | blksize -= len; |
334 | host->sg_miter.consumed = len; | |
14d836e7 | 335 | |
7659150c | 336 | buf = host->sg_miter.addr; |
d129bceb | 337 | |
7659150c PO |
338 | while (len) { |
339 | if (chunk == 0) { | |
4e4141a5 | 340 | scratch = sdhci_readl(host, SDHCI_BUFFER); |
7659150c | 341 | chunk = 4; |
a406f5a3 | 342 | } |
7659150c PO |
343 | |
344 | *buf = scratch & 0xFF; | |
345 | ||
346 | buf++; | |
347 | scratch >>= 8; | |
348 | chunk--; | |
349 | len--; | |
d129bceb | 350 | } |
a406f5a3 | 351 | } |
7659150c PO |
352 | |
353 | sg_miter_stop(&host->sg_miter); | |
354 | ||
355 | local_irq_restore(flags); | |
a406f5a3 | 356 | } |
d129bceb | 357 | |
a406f5a3 PO |
358 | static void sdhci_write_block_pio(struct sdhci_host *host) |
359 | { | |
7659150c PO |
360 | unsigned long flags; |
361 | size_t blksize, len, chunk; | |
362 | u32 scratch; | |
363 | u8 *buf; | |
d129bceb | 364 | |
a406f5a3 PO |
365 | DBG("PIO writing\n"); |
366 | ||
367 | blksize = host->data->blksz; | |
7659150c PO |
368 | chunk = 0; |
369 | scratch = 0; | |
d129bceb | 370 | |
7659150c | 371 | local_irq_save(flags); |
d129bceb | 372 | |
a406f5a3 | 373 | while (blksize) { |
7659150c PO |
374 | if (!sg_miter_next(&host->sg_miter)) |
375 | BUG(); | |
a406f5a3 | 376 | |
7659150c PO |
377 | len = min(host->sg_miter.length, blksize); |
378 | ||
379 | blksize -= len; | |
380 | host->sg_miter.consumed = len; | |
381 | ||
382 | buf = host->sg_miter.addr; | |
d129bceb | 383 | |
7659150c PO |
384 | while (len) { |
385 | scratch |= (u32)*buf << (chunk * 8); | |
386 | ||
387 | buf++; | |
388 | chunk++; | |
389 | len--; | |
390 | ||
391 | if ((chunk == 4) || ((len == 0) && (blksize == 0))) { | |
4e4141a5 | 392 | sdhci_writel(host, scratch, SDHCI_BUFFER); |
7659150c PO |
393 | chunk = 0; |
394 | scratch = 0; | |
d129bceb | 395 | } |
d129bceb PO |
396 | } |
397 | } | |
7659150c PO |
398 | |
399 | sg_miter_stop(&host->sg_miter); | |
400 | ||
401 | local_irq_restore(flags); | |
a406f5a3 PO |
402 | } |
403 | ||
404 | static void sdhci_transfer_pio(struct sdhci_host *host) | |
405 | { | |
406 | u32 mask; | |
407 | ||
408 | BUG_ON(!host->data); | |
409 | ||
7659150c | 410 | if (host->blocks == 0) |
a406f5a3 PO |
411 | return; |
412 | ||
413 | if (host->data->flags & MMC_DATA_READ) | |
414 | mask = SDHCI_DATA_AVAILABLE; | |
415 | else | |
416 | mask = SDHCI_SPACE_AVAILABLE; | |
417 | ||
4a3cba32 PO |
418 | /* |
419 | * Some controllers (JMicron JMB38x) mess up the buffer bits | |
420 | * for transfers < 4 bytes. As long as it is just one block, | |
421 | * we can ignore the bits. | |
422 | */ | |
423 | if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && | |
424 | (host->data->blocks == 1)) | |
425 | mask = ~0; | |
426 | ||
4e4141a5 | 427 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
3e3bf207 AV |
428 | if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) |
429 | udelay(100); | |
430 | ||
a406f5a3 PO |
431 | if (host->data->flags & MMC_DATA_READ) |
432 | sdhci_read_block_pio(host); | |
433 | else | |
434 | sdhci_write_block_pio(host); | |
d129bceb | 435 | |
7659150c PO |
436 | host->blocks--; |
437 | if (host->blocks == 0) | |
a406f5a3 | 438 | break; |
a406f5a3 | 439 | } |
d129bceb | 440 | |
a406f5a3 | 441 | DBG("PIO transfer complete.\n"); |
d129bceb PO |
442 | } |
443 | ||
2134a922 PO |
444 | static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) |
445 | { | |
446 | local_irq_save(*flags); | |
482fce99 | 447 | return kmap_atomic(sg_page(sg)) + sg->offset; |
2134a922 PO |
448 | } |
449 | ||
450 | static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) | |
451 | { | |
482fce99 | 452 | kunmap_atomic(buffer); |
2134a922 PO |
453 | local_irq_restore(*flags); |
454 | } | |
455 | ||
e57a5f61 AH |
456 | static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc, |
457 | dma_addr_t addr, int len, unsigned cmd) | |
118cd17d | 458 | { |
e57a5f61 | 459 | struct sdhci_adma2_64_desc *dma_desc = desc; |
118cd17d | 460 | |
e57a5f61 | 461 | /* 32-bit and 64-bit descriptors have these members in same position */ |
0545230f AH |
462 | dma_desc->cmd = cpu_to_le16(cmd); |
463 | dma_desc->len = cpu_to_le16(len); | |
e57a5f61 AH |
464 | dma_desc->addr_lo = cpu_to_le32((u32)addr); |
465 | ||
466 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
467 | dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32); | |
118cd17d BD |
468 | } |
469 | ||
b5ffa674 AH |
470 | static void sdhci_adma_mark_end(void *desc) |
471 | { | |
e57a5f61 | 472 | struct sdhci_adma2_64_desc *dma_desc = desc; |
b5ffa674 | 473 | |
e57a5f61 | 474 | /* 32-bit and 64-bit descriptors have 'cmd' in same position */ |
0545230f | 475 | dma_desc->cmd |= cpu_to_le16(ADMA2_END); |
b5ffa674 AH |
476 | } |
477 | ||
8f1934ce | 478 | static int sdhci_adma_table_pre(struct sdhci_host *host, |
2134a922 PO |
479 | struct mmc_data *data) |
480 | { | |
481 | int direction; | |
482 | ||
1c3d5f6d AH |
483 | void *desc; |
484 | void *align; | |
2134a922 PO |
485 | dma_addr_t addr; |
486 | dma_addr_t align_addr; | |
487 | int len, offset; | |
488 | ||
489 | struct scatterlist *sg; | |
490 | int i; | |
491 | char *buffer; | |
492 | unsigned long flags; | |
493 | ||
494 | /* | |
495 | * The spec does not specify endianness of descriptor table. | |
496 | * We currently guess that it is LE. | |
497 | */ | |
498 | ||
499 | if (data->flags & MMC_DATA_READ) | |
500 | direction = DMA_FROM_DEVICE; | |
501 | else | |
502 | direction = DMA_TO_DEVICE; | |
503 | ||
2134a922 | 504 | host->align_addr = dma_map_single(mmc_dev(host->mmc), |
76fe379a | 505 | host->align_buffer, host->align_buffer_sz, direction); |
8d8bb39b | 506 | if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) |
8f1934ce | 507 | goto fail; |
76fe379a | 508 | BUG_ON(host->align_addr & host->align_mask); |
2134a922 PO |
509 | |
510 | host->sg_count = dma_map_sg(mmc_dev(host->mmc), | |
511 | data->sg, data->sg_len, direction); | |
8f1934ce PO |
512 | if (host->sg_count == 0) |
513 | goto unmap_align; | |
2134a922 | 514 | |
4efaa6fb | 515 | desc = host->adma_table; |
2134a922 PO |
516 | align = host->align_buffer; |
517 | ||
518 | align_addr = host->align_addr; | |
519 | ||
520 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
521 | addr = sg_dma_address(sg); | |
522 | len = sg_dma_len(sg); | |
523 | ||
524 | /* | |
525 | * The SDHCI specification states that ADMA | |
526 | * addresses must be 32-bit aligned. If they | |
527 | * aren't, then we use a bounce buffer for | |
528 | * the (up to three) bytes that screw up the | |
529 | * alignment. | |
530 | */ | |
76fe379a AH |
531 | offset = (host->align_sz - (addr & host->align_mask)) & |
532 | host->align_mask; | |
2134a922 PO |
533 | if (offset) { |
534 | if (data->flags & MMC_DATA_WRITE) { | |
535 | buffer = sdhci_kmap_atomic(sg, &flags); | |
8be78c6a AH |
536 | WARN_ON(((long)buffer & (PAGE_SIZE - 1)) > |
537 | (PAGE_SIZE - offset)); | |
2134a922 PO |
538 | memcpy(align, buffer, offset); |
539 | sdhci_kunmap_atomic(buffer, &flags); | |
540 | } | |
541 | ||
118cd17d | 542 | /* tran, valid */ |
e57a5f61 | 543 | sdhci_adma_write_desc(host, desc, align_addr, offset, |
739d46dc | 544 | ADMA2_TRAN_VALID); |
2134a922 PO |
545 | |
546 | BUG_ON(offset > 65536); | |
547 | ||
76fe379a AH |
548 | align += host->align_sz; |
549 | align_addr += host->align_sz; | |
2134a922 | 550 | |
76fe379a | 551 | desc += host->desc_sz; |
2134a922 PO |
552 | |
553 | addr += offset; | |
554 | len -= offset; | |
555 | } | |
556 | ||
2134a922 PO |
557 | BUG_ON(len > 65536); |
558 | ||
118cd17d | 559 | /* tran, valid */ |
e57a5f61 | 560 | sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID); |
76fe379a | 561 | desc += host->desc_sz; |
2134a922 PO |
562 | |
563 | /* | |
564 | * If this triggers then we have a calculation bug | |
565 | * somewhere. :/ | |
566 | */ | |
76fe379a | 567 | WARN_ON((desc - host->adma_table) >= host->adma_table_sz); |
2134a922 PO |
568 | } |
569 | ||
70764a90 TA |
570 | if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { |
571 | /* | |
572 | * Mark the last descriptor as the terminating descriptor | |
573 | */ | |
4efaa6fb | 574 | if (desc != host->adma_table) { |
76fe379a | 575 | desc -= host->desc_sz; |
b5ffa674 | 576 | sdhci_adma_mark_end(desc); |
70764a90 TA |
577 | } |
578 | } else { | |
579 | /* | |
580 | * Add a terminating entry. | |
581 | */ | |
2134a922 | 582 | |
70764a90 | 583 | /* nop, end, valid */ |
e57a5f61 | 584 | sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID); |
70764a90 | 585 | } |
2134a922 PO |
586 | |
587 | /* | |
588 | * Resync align buffer as we might have changed it. | |
589 | */ | |
590 | if (data->flags & MMC_DATA_WRITE) { | |
591 | dma_sync_single_for_device(mmc_dev(host->mmc), | |
76fe379a | 592 | host->align_addr, host->align_buffer_sz, direction); |
2134a922 PO |
593 | } |
594 | ||
8f1934ce PO |
595 | return 0; |
596 | ||
8f1934ce PO |
597 | unmap_align: |
598 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
76fe379a | 599 | host->align_buffer_sz, direction); |
8f1934ce PO |
600 | fail: |
601 | return -EINVAL; | |
2134a922 PO |
602 | } |
603 | ||
604 | static void sdhci_adma_table_post(struct sdhci_host *host, | |
605 | struct mmc_data *data) | |
606 | { | |
607 | int direction; | |
608 | ||
609 | struct scatterlist *sg; | |
610 | int i, size; | |
1c3d5f6d | 611 | void *align; |
2134a922 PO |
612 | char *buffer; |
613 | unsigned long flags; | |
de0b65a7 | 614 | bool has_unaligned; |
2134a922 PO |
615 | |
616 | if (data->flags & MMC_DATA_READ) | |
617 | direction = DMA_FROM_DEVICE; | |
618 | else | |
619 | direction = DMA_TO_DEVICE; | |
620 | ||
2134a922 | 621 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, |
76fe379a | 622 | host->align_buffer_sz, direction); |
2134a922 | 623 | |
de0b65a7 RK |
624 | /* Do a quick scan of the SG list for any unaligned mappings */ |
625 | has_unaligned = false; | |
626 | for_each_sg(data->sg, sg, host->sg_count, i) | |
76fe379a | 627 | if (sg_dma_address(sg) & host->align_mask) { |
de0b65a7 RK |
628 | has_unaligned = true; |
629 | break; | |
630 | } | |
631 | ||
632 | if (has_unaligned && data->flags & MMC_DATA_READ) { | |
2134a922 PO |
633 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, |
634 | data->sg_len, direction); | |
635 | ||
636 | align = host->align_buffer; | |
637 | ||
638 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
76fe379a AH |
639 | if (sg_dma_address(sg) & host->align_mask) { |
640 | size = host->align_sz - | |
641 | (sg_dma_address(sg) & host->align_mask); | |
2134a922 PO |
642 | |
643 | buffer = sdhci_kmap_atomic(sg, &flags); | |
8be78c6a AH |
644 | WARN_ON(((long)buffer & (PAGE_SIZE - 1)) > |
645 | (PAGE_SIZE - size)); | |
2134a922 PO |
646 | memcpy(buffer, align, size); |
647 | sdhci_kunmap_atomic(buffer, &flags); | |
648 | ||
76fe379a | 649 | align += host->align_sz; |
2134a922 PO |
650 | } |
651 | } | |
652 | } | |
653 | ||
654 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
655 | data->sg_len, direction); | |
656 | } | |
657 | ||
a3c7778f | 658 | static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
d129bceb | 659 | { |
1c8cde92 | 660 | u8 count; |
a3c7778f | 661 | struct mmc_data *data = cmd->data; |
1c8cde92 | 662 | unsigned target_timeout, current_timeout; |
d129bceb | 663 | |
ee53ab5d PO |
664 | /* |
665 | * If the host controller provides us with an incorrect timeout | |
666 | * value, just skip the check and use 0xE. The hardware may take | |
667 | * longer to time out, but that's much better than having a too-short | |
668 | * timeout value. | |
669 | */ | |
11a2f1b7 | 670 | if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) |
ee53ab5d | 671 | return 0xE; |
e538fbe8 | 672 | |
a3c7778f | 673 | /* Unspecified timeout, assume max */ |
1d4d7744 | 674 | if (!data && !cmd->busy_timeout) |
a3c7778f | 675 | return 0xE; |
d129bceb | 676 | |
a3c7778f AW |
677 | /* timeout in us */ |
678 | if (!data) | |
1d4d7744 | 679 | target_timeout = cmd->busy_timeout * 1000; |
78a2ca27 AS |
680 | else { |
681 | target_timeout = data->timeout_ns / 1000; | |
682 | if (host->clock) | |
683 | target_timeout += data->timeout_clks / host->clock; | |
684 | } | |
81b39802 | 685 | |
1c8cde92 PO |
686 | /* |
687 | * Figure out needed cycles. | |
688 | * We do this in steps in order to fit inside a 32 bit int. | |
689 | * The first step is the minimum timeout, which will have a | |
690 | * minimum resolution of 6 bits: | |
691 | * (1) 2^13*1000 > 2^22, | |
692 | * (2) host->timeout_clk < 2^16 | |
693 | * => | |
694 | * (1) / (2) > 2^6 | |
695 | */ | |
696 | count = 0; | |
697 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; | |
698 | while (current_timeout < target_timeout) { | |
699 | count++; | |
700 | current_timeout <<= 1; | |
701 | if (count >= 0xF) | |
702 | break; | |
703 | } | |
704 | ||
705 | if (count >= 0xF) { | |
09eeff52 CB |
706 | DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", |
707 | mmc_hostname(host->mmc), count, cmd->opcode); | |
1c8cde92 PO |
708 | count = 0xE; |
709 | } | |
710 | ||
ee53ab5d PO |
711 | return count; |
712 | } | |
713 | ||
6aa943ab AV |
714 | static void sdhci_set_transfer_irqs(struct sdhci_host *host) |
715 | { | |
716 | u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; | |
717 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; | |
718 | ||
719 | if (host->flags & SDHCI_REQ_USE_DMA) | |
b537f94c | 720 | host->ier = (host->ier & ~pio_irqs) | dma_irqs; |
6aa943ab | 721 | else |
b537f94c RK |
722 | host->ier = (host->ier & ~dma_irqs) | pio_irqs; |
723 | ||
724 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
725 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
6aa943ab AV |
726 | } |
727 | ||
b45e668a | 728 | static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
ee53ab5d PO |
729 | { |
730 | u8 count; | |
b45e668a AD |
731 | |
732 | if (host->ops->set_timeout) { | |
733 | host->ops->set_timeout(host, cmd); | |
734 | } else { | |
735 | count = sdhci_calc_timeout(host, cmd); | |
736 | sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); | |
737 | } | |
738 | } | |
739 | ||
740 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) | |
741 | { | |
2134a922 | 742 | u8 ctrl; |
a3c7778f | 743 | struct mmc_data *data = cmd->data; |
8f1934ce | 744 | int ret; |
ee53ab5d PO |
745 | |
746 | WARN_ON(host->data); | |
747 | ||
b45e668a AD |
748 | if (data || (cmd->flags & MMC_RSP_BUSY)) |
749 | sdhci_set_timeout(host, cmd); | |
a3c7778f AW |
750 | |
751 | if (!data) | |
ee53ab5d PO |
752 | return; |
753 | ||
754 | /* Sanity checks */ | |
755 | BUG_ON(data->blksz * data->blocks > 524288); | |
756 | BUG_ON(data->blksz > host->mmc->max_blk_size); | |
757 | BUG_ON(data->blocks > 65535); | |
758 | ||
759 | host->data = data; | |
760 | host->data_early = 0; | |
f6a03cbf | 761 | host->data->bytes_xfered = 0; |
ee53ab5d | 762 | |
a13abc7b | 763 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) |
c9fddbc4 PO |
764 | host->flags |= SDHCI_REQ_USE_DMA; |
765 | ||
2134a922 PO |
766 | /* |
767 | * FIXME: This doesn't account for merging when mapping the | |
768 | * scatterlist. | |
769 | */ | |
770 | if (host->flags & SDHCI_REQ_USE_DMA) { | |
771 | int broken, i; | |
772 | struct scatterlist *sg; | |
773 | ||
774 | broken = 0; | |
775 | if (host->flags & SDHCI_USE_ADMA) { | |
776 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
777 | broken = 1; | |
778 | } else { | |
779 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) | |
780 | broken = 1; | |
781 | } | |
782 | ||
783 | if (unlikely(broken)) { | |
784 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
785 | if (sg->length & 0x3) { | |
786 | DBG("Reverting to PIO because of " | |
787 | "transfer size (%d)\n", | |
788 | sg->length); | |
789 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
790 | break; | |
791 | } | |
792 | } | |
793 | } | |
c9fddbc4 PO |
794 | } |
795 | ||
796 | /* | |
797 | * The assumption here being that alignment is the same after | |
798 | * translation to device address space. | |
799 | */ | |
2134a922 PO |
800 | if (host->flags & SDHCI_REQ_USE_DMA) { |
801 | int broken, i; | |
802 | struct scatterlist *sg; | |
803 | ||
804 | broken = 0; | |
805 | if (host->flags & SDHCI_USE_ADMA) { | |
806 | /* | |
807 | * As we use 3 byte chunks to work around | |
808 | * alignment problems, we need to check this | |
809 | * quirk. | |
810 | */ | |
811 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
812 | broken = 1; | |
813 | } else { | |
814 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) | |
815 | broken = 1; | |
816 | } | |
817 | ||
818 | if (unlikely(broken)) { | |
819 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
820 | if (sg->offset & 0x3) { | |
821 | DBG("Reverting to PIO because of " | |
822 | "bad alignment\n"); | |
823 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
824 | break; | |
825 | } | |
826 | } | |
827 | } | |
828 | } | |
829 | ||
8f1934ce PO |
830 | if (host->flags & SDHCI_REQ_USE_DMA) { |
831 | if (host->flags & SDHCI_USE_ADMA) { | |
832 | ret = sdhci_adma_table_pre(host, data); | |
833 | if (ret) { | |
834 | /* | |
835 | * This only happens when someone fed | |
836 | * us an invalid request. | |
837 | */ | |
838 | WARN_ON(1); | |
ebd6d357 | 839 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 840 | } else { |
4e4141a5 AV |
841 | sdhci_writel(host, host->adma_addr, |
842 | SDHCI_ADMA_ADDRESS); | |
e57a5f61 AH |
843 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
844 | sdhci_writel(host, | |
845 | (u64)host->adma_addr >> 32, | |
846 | SDHCI_ADMA_ADDRESS_HI); | |
8f1934ce PO |
847 | } |
848 | } else { | |
c8b3e02e | 849 | int sg_cnt; |
8f1934ce | 850 | |
c8b3e02e | 851 | sg_cnt = dma_map_sg(mmc_dev(host->mmc), |
8f1934ce PO |
852 | data->sg, data->sg_len, |
853 | (data->flags & MMC_DATA_READ) ? | |
854 | DMA_FROM_DEVICE : | |
855 | DMA_TO_DEVICE); | |
c8b3e02e | 856 | if (sg_cnt == 0) { |
8f1934ce PO |
857 | /* |
858 | * This only happens when someone fed | |
859 | * us an invalid request. | |
860 | */ | |
861 | WARN_ON(1); | |
ebd6d357 | 862 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 863 | } else { |
719a61b4 | 864 | WARN_ON(sg_cnt != 1); |
4e4141a5 AV |
865 | sdhci_writel(host, sg_dma_address(data->sg), |
866 | SDHCI_DMA_ADDRESS); | |
8f1934ce PO |
867 | } |
868 | } | |
869 | } | |
870 | ||
2134a922 PO |
871 | /* |
872 | * Always adjust the DMA selection as some controllers | |
873 | * (e.g. JMicron) can't do PIO properly when the selection | |
874 | * is ADMA. | |
875 | */ | |
876 | if (host->version >= SDHCI_SPEC_200) { | |
4e4141a5 | 877 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
2134a922 PO |
878 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
879 | if ((host->flags & SDHCI_REQ_USE_DMA) && | |
e57a5f61 AH |
880 | (host->flags & SDHCI_USE_ADMA)) { |
881 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
882 | ctrl |= SDHCI_CTRL_ADMA64; | |
883 | else | |
884 | ctrl |= SDHCI_CTRL_ADMA32; | |
885 | } else { | |
2134a922 | 886 | ctrl |= SDHCI_CTRL_SDMA; |
e57a5f61 | 887 | } |
4e4141a5 | 888 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
c9fddbc4 PO |
889 | } |
890 | ||
8f1934ce | 891 | if (!(host->flags & SDHCI_REQ_USE_DMA)) { |
da60a91d SAS |
892 | int flags; |
893 | ||
894 | flags = SG_MITER_ATOMIC; | |
895 | if (host->data->flags & MMC_DATA_READ) | |
896 | flags |= SG_MITER_TO_SG; | |
897 | else | |
898 | flags |= SG_MITER_FROM_SG; | |
899 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
7659150c | 900 | host->blocks = data->blocks; |
d129bceb | 901 | } |
c7fa9963 | 902 | |
6aa943ab AV |
903 | sdhci_set_transfer_irqs(host); |
904 | ||
f6a03cbf MV |
905 | /* Set the DMA boundary value and block size */ |
906 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, | |
907 | data->blksz), SDHCI_BLOCK_SIZE); | |
4e4141a5 | 908 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); |
c7fa9963 PO |
909 | } |
910 | ||
911 | static void sdhci_set_transfer_mode(struct sdhci_host *host, | |
e89d456f | 912 | struct mmc_command *cmd) |
c7fa9963 PO |
913 | { |
914 | u16 mode; | |
e89d456f | 915 | struct mmc_data *data = cmd->data; |
c7fa9963 | 916 | |
2b558c13 DA |
917 | if (data == NULL) { |
918 | /* clear Auto CMD settings for no data CMDs */ | |
919 | mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); | |
920 | sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | | |
921 | SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); | |
c7fa9963 | 922 | return; |
2b558c13 | 923 | } |
c7fa9963 | 924 | |
e538fbe8 PO |
925 | WARN_ON(!host->data); |
926 | ||
c7fa9963 | 927 | mode = SDHCI_TRNS_BLK_CNT_EN; |
e89d456f AW |
928 | if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { |
929 | mode |= SDHCI_TRNS_MULTI; | |
930 | /* | |
931 | * If we are sending CMD23, CMD12 never gets sent | |
932 | * on successful completion (so no Auto-CMD12). | |
933 | */ | |
934 | if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) | |
935 | mode |= SDHCI_TRNS_AUTO_CMD12; | |
8edf6371 AW |
936 | else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { |
937 | mode |= SDHCI_TRNS_AUTO_CMD23; | |
938 | sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); | |
939 | } | |
c4512f79 | 940 | } |
8edf6371 | 941 | |
c7fa9963 PO |
942 | if (data->flags & MMC_DATA_READ) |
943 | mode |= SDHCI_TRNS_READ; | |
c9fddbc4 | 944 | if (host->flags & SDHCI_REQ_USE_DMA) |
c7fa9963 PO |
945 | mode |= SDHCI_TRNS_DMA; |
946 | ||
4e4141a5 | 947 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
d129bceb PO |
948 | } |
949 | ||
950 | static void sdhci_finish_data(struct sdhci_host *host) | |
951 | { | |
952 | struct mmc_data *data; | |
d129bceb PO |
953 | |
954 | BUG_ON(!host->data); | |
955 | ||
956 | data = host->data; | |
957 | host->data = NULL; | |
958 | ||
c9fddbc4 | 959 | if (host->flags & SDHCI_REQ_USE_DMA) { |
2134a922 PO |
960 | if (host->flags & SDHCI_USE_ADMA) |
961 | sdhci_adma_table_post(host, data); | |
962 | else { | |
963 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
964 | data->sg_len, (data->flags & MMC_DATA_READ) ? | |
965 | DMA_FROM_DEVICE : DMA_TO_DEVICE); | |
966 | } | |
d129bceb PO |
967 | } |
968 | ||
969 | /* | |
c9b74c5b PO |
970 | * The specification states that the block count register must |
971 | * be updated, but it does not specify at what point in the | |
972 | * data flow. That makes the register entirely useless to read | |
973 | * back so we have to assume that nothing made it to the card | |
974 | * in the event of an error. | |
d129bceb | 975 | */ |
c9b74c5b PO |
976 | if (data->error) |
977 | data->bytes_xfered = 0; | |
d129bceb | 978 | else |
c9b74c5b | 979 | data->bytes_xfered = data->blksz * data->blocks; |
d129bceb | 980 | |
e89d456f AW |
981 | /* |
982 | * Need to send CMD12 if - | |
983 | * a) open-ended multiblock transfer (no CMD23) | |
984 | * b) error in multiblock transfer | |
985 | */ | |
986 | if (data->stop && | |
987 | (data->error || | |
988 | !host->mrq->sbc)) { | |
989 | ||
d129bceb PO |
990 | /* |
991 | * The controller needs a reset of internal state machines | |
992 | * upon error conditions. | |
993 | */ | |
17b0429d | 994 | if (data->error) { |
03231f9b RK |
995 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
996 | sdhci_do_reset(host, SDHCI_RESET_DATA); | |
d129bceb PO |
997 | } |
998 | ||
999 | sdhci_send_command(host, data->stop); | |
1000 | } else | |
1001 | tasklet_schedule(&host->finish_tasklet); | |
1002 | } | |
1003 | ||
c0e55129 | 1004 | void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) |
d129bceb PO |
1005 | { |
1006 | int flags; | |
fd2208d7 | 1007 | u32 mask; |
7cb2c76f | 1008 | unsigned long timeout; |
d129bceb PO |
1009 | |
1010 | WARN_ON(host->cmd); | |
1011 | ||
d129bceb | 1012 | /* Wait max 10 ms */ |
7cb2c76f | 1013 | timeout = 10; |
fd2208d7 PO |
1014 | |
1015 | mask = SDHCI_CMD_INHIBIT; | |
1016 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) | |
1017 | mask |= SDHCI_DATA_INHIBIT; | |
1018 | ||
1019 | /* We shouldn't wait for data inihibit for stop commands, even | |
1020 | though they might use busy signaling */ | |
1021 | if (host->mrq->data && (cmd == host->mrq->data->stop)) | |
1022 | mask &= ~SDHCI_DATA_INHIBIT; | |
1023 | ||
4e4141a5 | 1024 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
7cb2c76f | 1025 | if (timeout == 0) { |
a3c76eb9 | 1026 | pr_err("%s: Controller never released " |
acf1da45 | 1027 | "inhibit bit(s).\n", mmc_hostname(host->mmc)); |
d129bceb | 1028 | sdhci_dumpregs(host); |
17b0429d | 1029 | cmd->error = -EIO; |
d129bceb PO |
1030 | tasklet_schedule(&host->finish_tasklet); |
1031 | return; | |
1032 | } | |
7cb2c76f PO |
1033 | timeout--; |
1034 | mdelay(1); | |
1035 | } | |
d129bceb | 1036 | |
3e1a6892 | 1037 | timeout = jiffies; |
1d4d7744 UH |
1038 | if (!cmd->data && cmd->busy_timeout > 9000) |
1039 | timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; | |
3e1a6892 AH |
1040 | else |
1041 | timeout += 10 * HZ; | |
1042 | mod_timer(&host->timer, timeout); | |
d129bceb PO |
1043 | |
1044 | host->cmd = cmd; | |
e99783a4 | 1045 | host->busy_handle = 0; |
d129bceb | 1046 | |
a3c7778f | 1047 | sdhci_prepare_data(host, cmd); |
d129bceb | 1048 | |
4e4141a5 | 1049 | sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); |
d129bceb | 1050 | |
e89d456f | 1051 | sdhci_set_transfer_mode(host, cmd); |
c7fa9963 | 1052 | |
d129bceb | 1053 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
a3c76eb9 | 1054 | pr_err("%s: Unsupported response type!\n", |
d129bceb | 1055 | mmc_hostname(host->mmc)); |
17b0429d | 1056 | cmd->error = -EINVAL; |
d129bceb PO |
1057 | tasklet_schedule(&host->finish_tasklet); |
1058 | return; | |
1059 | } | |
1060 | ||
1061 | if (!(cmd->flags & MMC_RSP_PRESENT)) | |
1062 | flags = SDHCI_CMD_RESP_NONE; | |
1063 | else if (cmd->flags & MMC_RSP_136) | |
1064 | flags = SDHCI_CMD_RESP_LONG; | |
1065 | else if (cmd->flags & MMC_RSP_BUSY) | |
1066 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
1067 | else | |
1068 | flags = SDHCI_CMD_RESP_SHORT; | |
1069 | ||
1070 | if (cmd->flags & MMC_RSP_CRC) | |
1071 | flags |= SDHCI_CMD_CRC; | |
1072 | if (cmd->flags & MMC_RSP_OPCODE) | |
1073 | flags |= SDHCI_CMD_INDEX; | |
b513ea25 AN |
1074 | |
1075 | /* CMD19 is special in that the Data Present Select should be set */ | |
069c9f14 G |
1076 | if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || |
1077 | cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) | |
d129bceb PO |
1078 | flags |= SDHCI_CMD_DATA; |
1079 | ||
4e4141a5 | 1080 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); |
d129bceb | 1081 | } |
c0e55129 | 1082 | EXPORT_SYMBOL_GPL(sdhci_send_command); |
d129bceb PO |
1083 | |
1084 | static void sdhci_finish_command(struct sdhci_host *host) | |
1085 | { | |
1086 | int i; | |
1087 | ||
1088 | BUG_ON(host->cmd == NULL); | |
1089 | ||
1090 | if (host->cmd->flags & MMC_RSP_PRESENT) { | |
1091 | if (host->cmd->flags & MMC_RSP_136) { | |
1092 | /* CRC is stripped so we need to do some shifting. */ | |
1093 | for (i = 0;i < 4;i++) { | |
4e4141a5 | 1094 | host->cmd->resp[i] = sdhci_readl(host, |
d129bceb PO |
1095 | SDHCI_RESPONSE + (3-i)*4) << 8; |
1096 | if (i != 3) | |
1097 | host->cmd->resp[i] |= | |
4e4141a5 | 1098 | sdhci_readb(host, |
d129bceb PO |
1099 | SDHCI_RESPONSE + (3-i)*4-1); |
1100 | } | |
1101 | } else { | |
4e4141a5 | 1102 | host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); |
d129bceb PO |
1103 | } |
1104 | } | |
1105 | ||
17b0429d | 1106 | host->cmd->error = 0; |
d129bceb | 1107 | |
e89d456f AW |
1108 | /* Finished CMD23, now send actual command. */ |
1109 | if (host->cmd == host->mrq->sbc) { | |
1110 | host->cmd = NULL; | |
1111 | sdhci_send_command(host, host->mrq->cmd); | |
1112 | } else { | |
e538fbe8 | 1113 | |
e89d456f AW |
1114 | /* Processed actual command. */ |
1115 | if (host->data && host->data_early) | |
1116 | sdhci_finish_data(host); | |
d129bceb | 1117 | |
e89d456f AW |
1118 | if (!host->cmd->data) |
1119 | tasklet_schedule(&host->finish_tasklet); | |
1120 | ||
1121 | host->cmd = NULL; | |
1122 | } | |
d129bceb PO |
1123 | } |
1124 | ||
52983382 KL |
1125 | static u16 sdhci_get_preset_value(struct sdhci_host *host) |
1126 | { | |
d975f121 | 1127 | u16 preset = 0; |
52983382 | 1128 | |
d975f121 RK |
1129 | switch (host->timing) { |
1130 | case MMC_TIMING_UHS_SDR12: | |
52983382 KL |
1131 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); |
1132 | break; | |
d975f121 | 1133 | case MMC_TIMING_UHS_SDR25: |
52983382 KL |
1134 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); |
1135 | break; | |
d975f121 | 1136 | case MMC_TIMING_UHS_SDR50: |
52983382 KL |
1137 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); |
1138 | break; | |
d975f121 RK |
1139 | case MMC_TIMING_UHS_SDR104: |
1140 | case MMC_TIMING_MMC_HS200: | |
52983382 KL |
1141 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); |
1142 | break; | |
d975f121 | 1143 | case MMC_TIMING_UHS_DDR50: |
52983382 KL |
1144 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); |
1145 | break; | |
1146 | default: | |
1147 | pr_warn("%s: Invalid UHS-I mode selected\n", | |
1148 | mmc_hostname(host->mmc)); | |
1149 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); | |
1150 | break; | |
1151 | } | |
1152 | return preset; | |
1153 | } | |
1154 | ||
1771059c | 1155 | void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) |
d129bceb | 1156 | { |
c3ed3877 | 1157 | int div = 0; /* Initialized for compiler warning */ |
df16219f | 1158 | int real_div = div, clk_mul = 1; |
c3ed3877 | 1159 | u16 clk = 0; |
7cb2c76f | 1160 | unsigned long timeout; |
d129bceb | 1161 | |
1650d0c7 RK |
1162 | host->mmc->actual_clock = 0; |
1163 | ||
4e4141a5 | 1164 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
1165 | |
1166 | if (clock == 0) | |
373073ef | 1167 | return; |
d129bceb | 1168 | |
85105c53 | 1169 | if (host->version >= SDHCI_SPEC_300) { |
da91a8f9 | 1170 | if (host->preset_enabled) { |
52983382 KL |
1171 | u16 pre_val; |
1172 | ||
1173 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1174 | pre_val = sdhci_get_preset_value(host); | |
1175 | div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) | |
1176 | >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; | |
1177 | if (host->clk_mul && | |
1178 | (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { | |
1179 | clk = SDHCI_PROG_CLOCK_MODE; | |
1180 | real_div = div + 1; | |
1181 | clk_mul = host->clk_mul; | |
1182 | } else { | |
1183 | real_div = max_t(int, 1, div << 1); | |
1184 | } | |
1185 | goto clock_set; | |
1186 | } | |
1187 | ||
c3ed3877 AN |
1188 | /* |
1189 | * Check if the Host Controller supports Programmable Clock | |
1190 | * Mode. | |
1191 | */ | |
1192 | if (host->clk_mul) { | |
52983382 KL |
1193 | for (div = 1; div <= 1024; div++) { |
1194 | if ((host->max_clk * host->clk_mul / div) | |
1195 | <= clock) | |
1196 | break; | |
1197 | } | |
c3ed3877 | 1198 | /* |
52983382 KL |
1199 | * Set Programmable Clock Mode in the Clock |
1200 | * Control register. | |
c3ed3877 | 1201 | */ |
52983382 KL |
1202 | clk = SDHCI_PROG_CLOCK_MODE; |
1203 | real_div = div; | |
1204 | clk_mul = host->clk_mul; | |
1205 | div--; | |
c3ed3877 AN |
1206 | } else { |
1207 | /* Version 3.00 divisors must be a multiple of 2. */ | |
1208 | if (host->max_clk <= clock) | |
1209 | div = 1; | |
1210 | else { | |
1211 | for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; | |
1212 | div += 2) { | |
1213 | if ((host->max_clk / div) <= clock) | |
1214 | break; | |
1215 | } | |
85105c53 | 1216 | } |
df16219f | 1217 | real_div = div; |
c3ed3877 | 1218 | div >>= 1; |
85105c53 ZG |
1219 | } |
1220 | } else { | |
1221 | /* Version 2.00 divisors must be a power of 2. */ | |
0397526d | 1222 | for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { |
85105c53 ZG |
1223 | if ((host->max_clk / div) <= clock) |
1224 | break; | |
1225 | } | |
df16219f | 1226 | real_div = div; |
c3ed3877 | 1227 | div >>= 1; |
d129bceb | 1228 | } |
d129bceb | 1229 | |
52983382 | 1230 | clock_set: |
03d6f5ff | 1231 | if (real_div) |
df16219f | 1232 | host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; |
c3ed3877 | 1233 | clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; |
85105c53 ZG |
1234 | clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) |
1235 | << SDHCI_DIVIDER_HI_SHIFT; | |
d129bceb | 1236 | clk |= SDHCI_CLOCK_INT_EN; |
4e4141a5 | 1237 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb | 1238 | |
27f6cb16 CB |
1239 | /* Wait max 20 ms */ |
1240 | timeout = 20; | |
4e4141a5 | 1241 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
7cb2c76f PO |
1242 | & SDHCI_CLOCK_INT_STABLE)) { |
1243 | if (timeout == 0) { | |
a3c76eb9 | 1244 | pr_err("%s: Internal clock never " |
acf1da45 | 1245 | "stabilised.\n", mmc_hostname(host->mmc)); |
d129bceb PO |
1246 | sdhci_dumpregs(host); |
1247 | return; | |
1248 | } | |
7cb2c76f PO |
1249 | timeout--; |
1250 | mdelay(1); | |
1251 | } | |
d129bceb PO |
1252 | |
1253 | clk |= SDHCI_CLOCK_CARD_EN; | |
4e4141a5 | 1254 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb | 1255 | } |
1771059c | 1256 | EXPORT_SYMBOL_GPL(sdhci_set_clock); |
d129bceb | 1257 | |
24fbb3ca RK |
1258 | static void sdhci_set_power(struct sdhci_host *host, unsigned char mode, |
1259 | unsigned short vdd) | |
146ad66e | 1260 | { |
3a48edc4 | 1261 | struct mmc_host *mmc = host->mmc; |
8364248a | 1262 | u8 pwr = 0; |
146ad66e | 1263 | |
52221610 TK |
1264 | if (!IS_ERR(mmc->supply.vmmc)) { |
1265 | spin_unlock_irq(&host->lock); | |
4e743f1f | 1266 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); |
52221610 TK |
1267 | spin_lock_irq(&host->lock); |
1268 | return; | |
1269 | } | |
1270 | ||
24fbb3ca RK |
1271 | if (mode != MMC_POWER_OFF) { |
1272 | switch (1 << vdd) { | |
ae628903 PO |
1273 | case MMC_VDD_165_195: |
1274 | pwr = SDHCI_POWER_180; | |
1275 | break; | |
1276 | case MMC_VDD_29_30: | |
1277 | case MMC_VDD_30_31: | |
1278 | pwr = SDHCI_POWER_300; | |
1279 | break; | |
1280 | case MMC_VDD_32_33: | |
1281 | case MMC_VDD_33_34: | |
1282 | pwr = SDHCI_POWER_330; | |
1283 | break; | |
1284 | default: | |
1285 | BUG(); | |
1286 | } | |
1287 | } | |
1288 | ||
1289 | if (host->pwr == pwr) | |
e921a8b6 | 1290 | return; |
146ad66e | 1291 | |
ae628903 PO |
1292 | host->pwr = pwr; |
1293 | ||
1294 | if (pwr == 0) { | |
4e4141a5 | 1295 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
f0710a55 AH |
1296 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
1297 | sdhci_runtime_pm_bus_off(host); | |
24fbb3ca | 1298 | vdd = 0; |
e921a8b6 RK |
1299 | } else { |
1300 | /* | |
1301 | * Spec says that we should clear the power reg before setting | |
1302 | * a new value. Some controllers don't seem to like this though. | |
1303 | */ | |
1304 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) | |
1305 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); | |
146ad66e | 1306 | |
e921a8b6 RK |
1307 | /* |
1308 | * At least the Marvell CaFe chip gets confused if we set the | |
1309 | * voltage and set turn on power at the same time, so set the | |
1310 | * voltage first. | |
1311 | */ | |
1312 | if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) | |
1313 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); | |
e08c1694 | 1314 | |
e921a8b6 | 1315 | pwr |= SDHCI_POWER_ON; |
146ad66e | 1316 | |
e921a8b6 | 1317 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
557b0697 | 1318 | |
e921a8b6 RK |
1319 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
1320 | sdhci_runtime_pm_bus_on(host); | |
f0710a55 | 1321 | |
e921a8b6 RK |
1322 | /* |
1323 | * Some controllers need an extra 10ms delay of 10ms before | |
1324 | * they can apply clock after applying power | |
1325 | */ | |
1326 | if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) | |
1327 | mdelay(10); | |
1328 | } | |
146ad66e PO |
1329 | } |
1330 | ||
d129bceb PO |
1331 | /*****************************************************************************\ |
1332 | * * | |
1333 | * MMC callbacks * | |
1334 | * * | |
1335 | \*****************************************************************************/ | |
1336 | ||
1337 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1338 | { | |
1339 | struct sdhci_host *host; | |
505a8680 | 1340 | int present; |
d129bceb | 1341 | unsigned long flags; |
473b095a | 1342 | u32 tuning_opcode; |
d129bceb PO |
1343 | |
1344 | host = mmc_priv(mmc); | |
1345 | ||
66fd8ad5 AH |
1346 | sdhci_runtime_pm_get(host); |
1347 | ||
d129bceb PO |
1348 | spin_lock_irqsave(&host->lock, flags); |
1349 | ||
1350 | WARN_ON(host->mrq != NULL); | |
1351 | ||
f9134319 | 1352 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1353 | sdhci_activate_led(host); |
2f730fec | 1354 | #endif |
e89d456f AW |
1355 | |
1356 | /* | |
1357 | * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED | |
1358 | * requests if Auto-CMD12 is enabled. | |
1359 | */ | |
1360 | if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { | |
c4512f79 JH |
1361 | if (mrq->stop) { |
1362 | mrq->data->stop = NULL; | |
1363 | mrq->stop = NULL; | |
1364 | } | |
1365 | } | |
d129bceb PO |
1366 | |
1367 | host->mrq = mrq; | |
1368 | ||
505a8680 SG |
1369 | /* |
1370 | * Firstly check card presence from cd-gpio. The return could | |
1371 | * be one of the following possibilities: | |
1372 | * negative: cd-gpio is not available | |
1373 | * zero: cd-gpio is used, and card is removed | |
1374 | * one: cd-gpio is used, and card is present | |
1375 | */ | |
1376 | present = mmc_gpio_get_cd(host->mmc); | |
1377 | if (present < 0) { | |
1378 | /* If polling, assume that the card is always present. */ | |
1379 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) | |
1380 | present = 1; | |
1381 | else | |
1382 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
1383 | SDHCI_CARD_PRESENT; | |
bec9d4e5 GL |
1384 | } |
1385 | ||
68d1fb7e | 1386 | if (!present || host->flags & SDHCI_DEVICE_DEAD) { |
17b0429d | 1387 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb | 1388 | tasklet_schedule(&host->finish_tasklet); |
cf2b5eea AN |
1389 | } else { |
1390 | u32 present_state; | |
1391 | ||
1392 | present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
1393 | /* | |
1394 | * Check if the re-tuning timer has already expired and there | |
7756a96d YS |
1395 | * is no on-going data transfer and DAT0 is not busy. If so, |
1396 | * we need to execute tuning procedure before sending command. | |
cf2b5eea AN |
1397 | */ |
1398 | if ((host->flags & SDHCI_NEEDS_RETUNING) && | |
7756a96d YS |
1399 | !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) && |
1400 | (present_state & SDHCI_DATA_0_LVL_MASK)) { | |
14efd957 CB |
1401 | if (mmc->card) { |
1402 | /* eMMC uses cmd21 but sd and sdio use cmd19 */ | |
1403 | tuning_opcode = | |
1404 | mmc->card->type == MMC_TYPE_MMC ? | |
1405 | MMC_SEND_TUNING_BLOCK_HS200 : | |
1406 | MMC_SEND_TUNING_BLOCK; | |
63c21180 CL |
1407 | |
1408 | /* Here we need to set the host->mrq to NULL, | |
1409 | * in case the pending finish_tasklet | |
1410 | * finishes it incorrectly. | |
1411 | */ | |
1412 | host->mrq = NULL; | |
1413 | ||
14efd957 CB |
1414 | spin_unlock_irqrestore(&host->lock, flags); |
1415 | sdhci_execute_tuning(mmc, tuning_opcode); | |
1416 | spin_lock_irqsave(&host->lock, flags); | |
1417 | ||
1418 | /* Restore original mmc_request structure */ | |
1419 | host->mrq = mrq; | |
1420 | } | |
cf2b5eea AN |
1421 | } |
1422 | ||
8edf6371 | 1423 | if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) |
e89d456f AW |
1424 | sdhci_send_command(host, mrq->sbc); |
1425 | else | |
1426 | sdhci_send_command(host, mrq->cmd); | |
cf2b5eea | 1427 | } |
d129bceb | 1428 | |
5f25a66f | 1429 | mmiowb(); |
d129bceb PO |
1430 | spin_unlock_irqrestore(&host->lock, flags); |
1431 | } | |
1432 | ||
2317f56c RK |
1433 | void sdhci_set_bus_width(struct sdhci_host *host, int width) |
1434 | { | |
1435 | u8 ctrl; | |
1436 | ||
1437 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
1438 | if (width == MMC_BUS_WIDTH_8) { | |
1439 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1440 | if (host->version >= SDHCI_SPEC_300) | |
1441 | ctrl |= SDHCI_CTRL_8BITBUS; | |
1442 | } else { | |
1443 | if (host->version >= SDHCI_SPEC_300) | |
1444 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
1445 | if (width == MMC_BUS_WIDTH_4) | |
1446 | ctrl |= SDHCI_CTRL_4BITBUS; | |
1447 | else | |
1448 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1449 | } | |
1450 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
1451 | } | |
1452 | EXPORT_SYMBOL_GPL(sdhci_set_bus_width); | |
1453 | ||
96d7b78c RK |
1454 | void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) |
1455 | { | |
1456 | u16 ctrl_2; | |
1457 | ||
1458 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1459 | /* Select Bus Speed Mode for host */ | |
1460 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
1461 | if ((timing == MMC_TIMING_MMC_HS200) || | |
1462 | (timing == MMC_TIMING_UHS_SDR104)) | |
1463 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; | |
1464 | else if (timing == MMC_TIMING_UHS_SDR12) | |
1465 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; | |
1466 | else if (timing == MMC_TIMING_UHS_SDR25) | |
1467 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; | |
1468 | else if (timing == MMC_TIMING_UHS_SDR50) | |
1469 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; | |
1470 | else if ((timing == MMC_TIMING_UHS_DDR50) || | |
1471 | (timing == MMC_TIMING_MMC_DDR52)) | |
1472 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; | |
1473 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | |
1474 | } | |
1475 | EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); | |
1476 | ||
66fd8ad5 | 1477 | static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) |
d129bceb | 1478 | { |
d129bceb PO |
1479 | unsigned long flags; |
1480 | u8 ctrl; | |
3a48edc4 | 1481 | struct mmc_host *mmc = host->mmc; |
d129bceb | 1482 | |
d129bceb PO |
1483 | spin_lock_irqsave(&host->lock, flags); |
1484 | ||
ceb6143b AH |
1485 | if (host->flags & SDHCI_DEVICE_DEAD) { |
1486 | spin_unlock_irqrestore(&host->lock, flags); | |
3a48edc4 TK |
1487 | if (!IS_ERR(mmc->supply.vmmc) && |
1488 | ios->power_mode == MMC_POWER_OFF) | |
4e743f1f | 1489 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); |
ceb6143b AH |
1490 | return; |
1491 | } | |
1e72859e | 1492 | |
d129bceb PO |
1493 | /* |
1494 | * Reset the chip on each power off. | |
1495 | * Should clear out any weird states. | |
1496 | */ | |
1497 | if (ios->power_mode == MMC_POWER_OFF) { | |
4e4141a5 | 1498 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
7260cf5e | 1499 | sdhci_reinit(host); |
d129bceb PO |
1500 | } |
1501 | ||
52983382 | 1502 | if (host->version >= SDHCI_SPEC_300 && |
372c4634 DA |
1503 | (ios->power_mode == MMC_POWER_UP) && |
1504 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) | |
52983382 KL |
1505 | sdhci_enable_preset_value(host, false); |
1506 | ||
373073ef | 1507 | if (!ios->clock || ios->clock != host->clock) { |
1771059c | 1508 | host->ops->set_clock(host, ios->clock); |
373073ef | 1509 | host->clock = ios->clock; |
03d6f5ff AD |
1510 | |
1511 | if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && | |
1512 | host->clock) { | |
1513 | host->timeout_clk = host->mmc->actual_clock ? | |
1514 | host->mmc->actual_clock / 1000 : | |
1515 | host->clock / 1000; | |
1516 | host->mmc->max_busy_timeout = | |
1517 | host->ops->get_max_timeout_count ? | |
1518 | host->ops->get_max_timeout_count(host) : | |
1519 | 1 << 27; | |
1520 | host->mmc->max_busy_timeout /= host->timeout_clk; | |
1521 | } | |
373073ef | 1522 | } |
d129bceb | 1523 | |
24fbb3ca | 1524 | sdhci_set_power(host, ios->power_mode, ios->vdd); |
d129bceb | 1525 | |
643a81ff PR |
1526 | if (host->ops->platform_send_init_74_clocks) |
1527 | host->ops->platform_send_init_74_clocks(host, ios->power_mode); | |
1528 | ||
2317f56c | 1529 | host->ops->set_bus_width(host, ios->bus_width); |
ae6d6c92 | 1530 | |
15ec4461 | 1531 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
cd9277c0 | 1532 | |
3ab9c8da PR |
1533 | if ((ios->timing == MMC_TIMING_SD_HS || |
1534 | ios->timing == MMC_TIMING_MMC_HS) | |
1535 | && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) | |
cd9277c0 PO |
1536 | ctrl |= SDHCI_CTRL_HISPD; |
1537 | else | |
1538 | ctrl &= ~SDHCI_CTRL_HISPD; | |
1539 | ||
d6d50a15 | 1540 | if (host->version >= SDHCI_SPEC_300) { |
49c468fc | 1541 | u16 clk, ctrl_2; |
49c468fc AN |
1542 | |
1543 | /* In case of UHS-I modes, set High Speed Enable */ | |
069c9f14 | 1544 | if ((ios->timing == MMC_TIMING_MMC_HS200) || |
bb8175a8 | 1545 | (ios->timing == MMC_TIMING_MMC_DDR52) || |
069c9f14 | 1546 | (ios->timing == MMC_TIMING_UHS_SDR50) || |
49c468fc AN |
1547 | (ios->timing == MMC_TIMING_UHS_SDR104) || |
1548 | (ios->timing == MMC_TIMING_UHS_DDR50) || | |
dd8df17f | 1549 | (ios->timing == MMC_TIMING_UHS_SDR25)) |
49c468fc | 1550 | ctrl |= SDHCI_CTRL_HISPD; |
d6d50a15 | 1551 | |
da91a8f9 | 1552 | if (!host->preset_enabled) { |
758535c4 | 1553 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d6d50a15 AN |
1554 | /* |
1555 | * We only need to set Driver Strength if the | |
1556 | * preset value enable is not set. | |
1557 | */ | |
da91a8f9 | 1558 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
d6d50a15 AN |
1559 | ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; |
1560 | if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) | |
1561 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; | |
1562 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) | |
1563 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; | |
1564 | ||
1565 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | |
758535c4 AN |
1566 | } else { |
1567 | /* | |
1568 | * According to SDHC Spec v3.00, if the Preset Value | |
1569 | * Enable in the Host Control 2 register is set, we | |
1570 | * need to reset SD Clock Enable before changing High | |
1571 | * Speed Enable to avoid generating clock gliches. | |
1572 | */ | |
758535c4 AN |
1573 | |
1574 | /* Reset SD Clock Enable */ | |
1575 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1576 | clk &= ~SDHCI_CLOCK_CARD_EN; | |
1577 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
1578 | ||
1579 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
1580 | ||
1581 | /* Re-enable SD Clock */ | |
1771059c | 1582 | host->ops->set_clock(host, host->clock); |
d6d50a15 | 1583 | } |
49c468fc | 1584 | |
49c468fc AN |
1585 | /* Reset SD Clock Enable */ |
1586 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1587 | clk &= ~SDHCI_CLOCK_CARD_EN; | |
1588 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
1589 | ||
96d7b78c | 1590 | host->ops->set_uhs_signaling(host, ios->timing); |
d975f121 | 1591 | host->timing = ios->timing; |
49c468fc | 1592 | |
52983382 KL |
1593 | if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && |
1594 | ((ios->timing == MMC_TIMING_UHS_SDR12) || | |
1595 | (ios->timing == MMC_TIMING_UHS_SDR25) || | |
1596 | (ios->timing == MMC_TIMING_UHS_SDR50) || | |
1597 | (ios->timing == MMC_TIMING_UHS_SDR104) || | |
1598 | (ios->timing == MMC_TIMING_UHS_DDR50))) { | |
1599 | u16 preset; | |
1600 | ||
1601 | sdhci_enable_preset_value(host, true); | |
1602 | preset = sdhci_get_preset_value(host); | |
1603 | ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) | |
1604 | >> SDHCI_PRESET_DRV_SHIFT; | |
1605 | } | |
1606 | ||
49c468fc | 1607 | /* Re-enable SD Clock */ |
1771059c | 1608 | host->ops->set_clock(host, host->clock); |
758535c4 AN |
1609 | } else |
1610 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
d6d50a15 | 1611 | |
b8352260 LD |
1612 | /* |
1613 | * Some (ENE) controllers go apeshit on some ios operation, | |
1614 | * signalling timeout and CRC errors even on CMD0. Resetting | |
1615 | * it on each ios seems to solve the problem. | |
1616 | */ | |
b8c86fc5 | 1617 | if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
03231f9b | 1618 | sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
b8352260 | 1619 | |
5f25a66f | 1620 | mmiowb(); |
d129bceb PO |
1621 | spin_unlock_irqrestore(&host->lock, flags); |
1622 | } | |
1623 | ||
66fd8ad5 AH |
1624 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
1625 | { | |
1626 | struct sdhci_host *host = mmc_priv(mmc); | |
1627 | ||
1628 | sdhci_runtime_pm_get(host); | |
1629 | sdhci_do_set_ios(host, ios); | |
1630 | sdhci_runtime_pm_put(host); | |
1631 | } | |
1632 | ||
94144a46 KL |
1633 | static int sdhci_do_get_cd(struct sdhci_host *host) |
1634 | { | |
1635 | int gpio_cd = mmc_gpio_get_cd(host->mmc); | |
1636 | ||
1637 | if (host->flags & SDHCI_DEVICE_DEAD) | |
1638 | return 0; | |
1639 | ||
1640 | /* If polling/nonremovable, assume that the card is always present. */ | |
1641 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || | |
1642 | (host->mmc->caps & MMC_CAP_NONREMOVABLE)) | |
1643 | return 1; | |
1644 | ||
1645 | /* Try slot gpio detect */ | |
1646 | if (!IS_ERR_VALUE(gpio_cd)) | |
1647 | return !!gpio_cd; | |
1648 | ||
1649 | /* Host native card detect */ | |
1650 | return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); | |
1651 | } | |
1652 | ||
1653 | static int sdhci_get_cd(struct mmc_host *mmc) | |
1654 | { | |
1655 | struct sdhci_host *host = mmc_priv(mmc); | |
1656 | int ret; | |
1657 | ||
1658 | sdhci_runtime_pm_get(host); | |
1659 | ret = sdhci_do_get_cd(host); | |
1660 | sdhci_runtime_pm_put(host); | |
1661 | return ret; | |
1662 | } | |
1663 | ||
66fd8ad5 | 1664 | static int sdhci_check_ro(struct sdhci_host *host) |
d129bceb | 1665 | { |
d129bceb | 1666 | unsigned long flags; |
2dfb579c | 1667 | int is_readonly; |
d129bceb | 1668 | |
d129bceb PO |
1669 | spin_lock_irqsave(&host->lock, flags); |
1670 | ||
1e72859e | 1671 | if (host->flags & SDHCI_DEVICE_DEAD) |
2dfb579c WS |
1672 | is_readonly = 0; |
1673 | else if (host->ops->get_ro) | |
1674 | is_readonly = host->ops->get_ro(host); | |
1e72859e | 1675 | else |
2dfb579c WS |
1676 | is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) |
1677 | & SDHCI_WRITE_PROTECT); | |
d129bceb PO |
1678 | |
1679 | spin_unlock_irqrestore(&host->lock, flags); | |
1680 | ||
2dfb579c WS |
1681 | /* This quirk needs to be replaced by a callback-function later */ |
1682 | return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? | |
1683 | !is_readonly : is_readonly; | |
d129bceb PO |
1684 | } |
1685 | ||
82b0e23a TI |
1686 | #define SAMPLE_COUNT 5 |
1687 | ||
66fd8ad5 | 1688 | static int sdhci_do_get_ro(struct sdhci_host *host) |
82b0e23a | 1689 | { |
82b0e23a TI |
1690 | int i, ro_count; |
1691 | ||
82b0e23a | 1692 | if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) |
66fd8ad5 | 1693 | return sdhci_check_ro(host); |
82b0e23a TI |
1694 | |
1695 | ro_count = 0; | |
1696 | for (i = 0; i < SAMPLE_COUNT; i++) { | |
66fd8ad5 | 1697 | if (sdhci_check_ro(host)) { |
82b0e23a TI |
1698 | if (++ro_count > SAMPLE_COUNT / 2) |
1699 | return 1; | |
1700 | } | |
1701 | msleep(30); | |
1702 | } | |
1703 | return 0; | |
1704 | } | |
1705 | ||
20758b66 AH |
1706 | static void sdhci_hw_reset(struct mmc_host *mmc) |
1707 | { | |
1708 | struct sdhci_host *host = mmc_priv(mmc); | |
1709 | ||
1710 | if (host->ops && host->ops->hw_reset) | |
1711 | host->ops->hw_reset(host); | |
1712 | } | |
1713 | ||
66fd8ad5 | 1714 | static int sdhci_get_ro(struct mmc_host *mmc) |
f75979b7 | 1715 | { |
66fd8ad5 AH |
1716 | struct sdhci_host *host = mmc_priv(mmc); |
1717 | int ret; | |
f75979b7 | 1718 | |
66fd8ad5 AH |
1719 | sdhci_runtime_pm_get(host); |
1720 | ret = sdhci_do_get_ro(host); | |
1721 | sdhci_runtime_pm_put(host); | |
1722 | return ret; | |
1723 | } | |
f75979b7 | 1724 | |
66fd8ad5 AH |
1725 | static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) |
1726 | { | |
be138554 | 1727 | if (!(host->flags & SDHCI_DEVICE_DEAD)) { |
ef104333 | 1728 | if (enable) |
b537f94c | 1729 | host->ier |= SDHCI_INT_CARD_INT; |
ef104333 | 1730 | else |
b537f94c RK |
1731 | host->ier &= ~SDHCI_INT_CARD_INT; |
1732 | ||
1733 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
1734 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
ef104333 RK |
1735 | mmiowb(); |
1736 | } | |
66fd8ad5 AH |
1737 | } |
1738 | ||
1739 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) | |
1740 | { | |
1741 | struct sdhci_host *host = mmc_priv(mmc); | |
1742 | unsigned long flags; | |
f75979b7 | 1743 | |
ef104333 RK |
1744 | sdhci_runtime_pm_get(host); |
1745 | ||
66fd8ad5 | 1746 | spin_lock_irqsave(&host->lock, flags); |
ef104333 RK |
1747 | if (enable) |
1748 | host->flags |= SDHCI_SDIO_IRQ_ENABLED; | |
1749 | else | |
1750 | host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; | |
1751 | ||
66fd8ad5 | 1752 | sdhci_enable_sdio_irq_nolock(host, enable); |
f75979b7 | 1753 | spin_unlock_irqrestore(&host->lock, flags); |
ef104333 RK |
1754 | |
1755 | sdhci_runtime_pm_put(host); | |
f75979b7 PO |
1756 | } |
1757 | ||
20b92a30 | 1758 | static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, |
21f5998f | 1759 | struct mmc_ios *ios) |
f2119df6 | 1760 | { |
3a48edc4 | 1761 | struct mmc_host *mmc = host->mmc; |
20b92a30 | 1762 | u16 ctrl; |
6231f3de | 1763 | int ret; |
f2119df6 | 1764 | |
20b92a30 KL |
1765 | /* |
1766 | * Signal Voltage Switching is only applicable for Host Controllers | |
1767 | * v3.00 and above. | |
1768 | */ | |
1769 | if (host->version < SDHCI_SPEC_300) | |
1770 | return 0; | |
6231f3de | 1771 | |
f2119df6 | 1772 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
f2119df6 | 1773 | |
21f5998f | 1774 | switch (ios->signal_voltage) { |
20b92a30 KL |
1775 | case MMC_SIGNAL_VOLTAGE_330: |
1776 | /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ | |
1777 | ctrl &= ~SDHCI_CTRL_VDD_180; | |
1778 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
f2119df6 | 1779 | |
3a48edc4 TK |
1780 | if (!IS_ERR(mmc->supply.vqmmc)) { |
1781 | ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000, | |
1782 | 3600000); | |
20b92a30 | 1783 | if (ret) { |
6606110d JP |
1784 | pr_warn("%s: Switching to 3.3V signalling voltage failed\n", |
1785 | mmc_hostname(mmc)); | |
20b92a30 KL |
1786 | return -EIO; |
1787 | } | |
1788 | } | |
1789 | /* Wait for 5ms */ | |
1790 | usleep_range(5000, 5500); | |
f2119df6 | 1791 | |
20b92a30 KL |
1792 | /* 3.3V regulator output should be stable within 5 ms */ |
1793 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1794 | if (!(ctrl & SDHCI_CTRL_VDD_180)) | |
1795 | return 0; | |
6231f3de | 1796 | |
6606110d JP |
1797 | pr_warn("%s: 3.3V regulator output did not became stable\n", |
1798 | mmc_hostname(mmc)); | |
20b92a30 KL |
1799 | |
1800 | return -EAGAIN; | |
1801 | case MMC_SIGNAL_VOLTAGE_180: | |
3a48edc4 TK |
1802 | if (!IS_ERR(mmc->supply.vqmmc)) { |
1803 | ret = regulator_set_voltage(mmc->supply.vqmmc, | |
20b92a30 KL |
1804 | 1700000, 1950000); |
1805 | if (ret) { | |
6606110d JP |
1806 | pr_warn("%s: Switching to 1.8V signalling voltage failed\n", |
1807 | mmc_hostname(mmc)); | |
20b92a30 KL |
1808 | return -EIO; |
1809 | } | |
1810 | } | |
6231f3de | 1811 | |
6231f3de PR |
1812 | /* |
1813 | * Enable 1.8V Signal Enable in the Host Control2 | |
1814 | * register | |
1815 | */ | |
20b92a30 KL |
1816 | ctrl |= SDHCI_CTRL_VDD_180; |
1817 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
6231f3de | 1818 | |
20b92a30 KL |
1819 | /* 1.8V regulator output should be stable within 5 ms */ |
1820 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1821 | if (ctrl & SDHCI_CTRL_VDD_180) | |
1822 | return 0; | |
f2119df6 | 1823 | |
6606110d JP |
1824 | pr_warn("%s: 1.8V regulator output did not became stable\n", |
1825 | mmc_hostname(mmc)); | |
f2119df6 | 1826 | |
20b92a30 KL |
1827 | return -EAGAIN; |
1828 | case MMC_SIGNAL_VOLTAGE_120: | |
3a48edc4 TK |
1829 | if (!IS_ERR(mmc->supply.vqmmc)) { |
1830 | ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000, | |
1831 | 1300000); | |
20b92a30 | 1832 | if (ret) { |
6606110d JP |
1833 | pr_warn("%s: Switching to 1.2V signalling voltage failed\n", |
1834 | mmc_hostname(mmc)); | |
20b92a30 | 1835 | return -EIO; |
f2119df6 AN |
1836 | } |
1837 | } | |
6231f3de | 1838 | return 0; |
20b92a30 | 1839 | default: |
f2119df6 AN |
1840 | /* No signal voltage switch required */ |
1841 | return 0; | |
20b92a30 | 1842 | } |
f2119df6 AN |
1843 | } |
1844 | ||
66fd8ad5 | 1845 | static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, |
21f5998f | 1846 | struct mmc_ios *ios) |
66fd8ad5 AH |
1847 | { |
1848 | struct sdhci_host *host = mmc_priv(mmc); | |
1849 | int err; | |
1850 | ||
1851 | if (host->version < SDHCI_SPEC_300) | |
1852 | return 0; | |
1853 | sdhci_runtime_pm_get(host); | |
21f5998f | 1854 | err = sdhci_do_start_signal_voltage_switch(host, ios); |
66fd8ad5 AH |
1855 | sdhci_runtime_pm_put(host); |
1856 | return err; | |
1857 | } | |
1858 | ||
20b92a30 KL |
1859 | static int sdhci_card_busy(struct mmc_host *mmc) |
1860 | { | |
1861 | struct sdhci_host *host = mmc_priv(mmc); | |
1862 | u32 present_state; | |
1863 | ||
1864 | sdhci_runtime_pm_get(host); | |
1865 | /* Check whether DAT[3:0] is 0000 */ | |
1866 | present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
1867 | sdhci_runtime_pm_put(host); | |
1868 | ||
1869 | return !(present_state & SDHCI_DATA_LVL_MASK); | |
1870 | } | |
1871 | ||
069c9f14 | 1872 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) |
b513ea25 | 1873 | { |
4b6f37d3 | 1874 | struct sdhci_host *host = mmc_priv(mmc); |
b513ea25 | 1875 | u16 ctrl; |
b513ea25 | 1876 | int tuning_loop_counter = MAX_TUNING_LOOP; |
b513ea25 | 1877 | int err = 0; |
2b35bd83 | 1878 | unsigned long flags; |
b513ea25 | 1879 | |
66fd8ad5 | 1880 | sdhci_runtime_pm_get(host); |
2b35bd83 | 1881 | spin_lock_irqsave(&host->lock, flags); |
b513ea25 | 1882 | |
b513ea25 | 1883 | /* |
069c9f14 G |
1884 | * The Host Controller needs tuning only in case of SDR104 mode |
1885 | * and for SDR50 mode when Use Tuning for SDR50 is set in the | |
b513ea25 | 1886 | * Capabilities register. |
069c9f14 G |
1887 | * If the Host Controller supports the HS200 mode then the |
1888 | * tuning function has to be executed. | |
b513ea25 | 1889 | */ |
4b6f37d3 RK |
1890 | switch (host->timing) { |
1891 | case MMC_TIMING_MMC_HS200: | |
1892 | case MMC_TIMING_UHS_SDR104: | |
1893 | break; | |
1894 | ||
1895 | case MMC_TIMING_UHS_SDR50: | |
1896 | if (host->flags & SDHCI_SDR50_NEEDS_TUNING || | |
1897 | host->flags & SDHCI_SDR104_NEEDS_TUNING) | |
1898 | break; | |
1899 | /* FALLTHROUGH */ | |
1900 | ||
1901 | default: | |
2b35bd83 | 1902 | spin_unlock_irqrestore(&host->lock, flags); |
66fd8ad5 | 1903 | sdhci_runtime_pm_put(host); |
b513ea25 AN |
1904 | return 0; |
1905 | } | |
1906 | ||
45251812 | 1907 | if (host->ops->platform_execute_tuning) { |
2b35bd83 | 1908 | spin_unlock_irqrestore(&host->lock, flags); |
45251812 DA |
1909 | err = host->ops->platform_execute_tuning(host, opcode); |
1910 | sdhci_runtime_pm_put(host); | |
1911 | return err; | |
1912 | } | |
1913 | ||
4b6f37d3 RK |
1914 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
1915 | ctrl |= SDHCI_CTRL_EXEC_TUNING; | |
b513ea25 AN |
1916 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
1917 | ||
1918 | /* | |
1919 | * As per the Host Controller spec v3.00, tuning command | |
1920 | * generates Buffer Read Ready interrupt, so enable that. | |
1921 | * | |
1922 | * Note: The spec clearly says that when tuning sequence | |
1923 | * is being performed, the controller does not generate | |
1924 | * interrupts other than Buffer Read Ready interrupt. But | |
1925 | * to make sure we don't hit a controller bug, we _only_ | |
1926 | * enable Buffer Read Ready interrupt here. | |
1927 | */ | |
b537f94c RK |
1928 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); |
1929 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); | |
b513ea25 AN |
1930 | |
1931 | /* | |
1932 | * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number | |
1933 | * of loops reaches 40 times or a timeout of 150ms occurs. | |
1934 | */ | |
b513ea25 AN |
1935 | do { |
1936 | struct mmc_command cmd = {0}; | |
66fd8ad5 | 1937 | struct mmc_request mrq = {NULL}; |
b513ea25 | 1938 | |
069c9f14 | 1939 | cmd.opcode = opcode; |
b513ea25 AN |
1940 | cmd.arg = 0; |
1941 | cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; | |
1942 | cmd.retries = 0; | |
1943 | cmd.data = NULL; | |
1944 | cmd.error = 0; | |
1945 | ||
7ce45e95 AC |
1946 | if (tuning_loop_counter-- == 0) |
1947 | break; | |
1948 | ||
b513ea25 AN |
1949 | mrq.cmd = &cmd; |
1950 | host->mrq = &mrq; | |
1951 | ||
1952 | /* | |
1953 | * In response to CMD19, the card sends 64 bytes of tuning | |
1954 | * block to the Host Controller. So we set the block size | |
1955 | * to 64 here. | |
1956 | */ | |
069c9f14 G |
1957 | if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { |
1958 | if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
1959 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), | |
1960 | SDHCI_BLOCK_SIZE); | |
1961 | else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) | |
1962 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), | |
1963 | SDHCI_BLOCK_SIZE); | |
1964 | } else { | |
1965 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), | |
1966 | SDHCI_BLOCK_SIZE); | |
1967 | } | |
b513ea25 AN |
1968 | |
1969 | /* | |
1970 | * The tuning block is sent by the card to the host controller. | |
1971 | * So we set the TRNS_READ bit in the Transfer Mode register. | |
1972 | * This also takes care of setting DMA Enable and Multi Block | |
1973 | * Select in the same register to 0. | |
1974 | */ | |
1975 | sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); | |
1976 | ||
1977 | sdhci_send_command(host, &cmd); | |
1978 | ||
1979 | host->cmd = NULL; | |
1980 | host->mrq = NULL; | |
1981 | ||
2b35bd83 | 1982 | spin_unlock_irqrestore(&host->lock, flags); |
b513ea25 AN |
1983 | /* Wait for Buffer Read Ready interrupt */ |
1984 | wait_event_interruptible_timeout(host->buf_ready_int, | |
1985 | (host->tuning_done == 1), | |
1986 | msecs_to_jiffies(50)); | |
2b35bd83 | 1987 | spin_lock_irqsave(&host->lock, flags); |
b513ea25 AN |
1988 | |
1989 | if (!host->tuning_done) { | |
a3c76eb9 | 1990 | pr_info(DRIVER_NAME ": Timeout waiting for " |
b513ea25 AN |
1991 | "Buffer Read Ready interrupt during tuning " |
1992 | "procedure, falling back to fixed sampling " | |
1993 | "clock\n"); | |
1994 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1995 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; | |
1996 | ctrl &= ~SDHCI_CTRL_EXEC_TUNING; | |
1997 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
1998 | ||
1999 | err = -EIO; | |
2000 | goto out; | |
2001 | } | |
2002 | ||
2003 | host->tuning_done = 0; | |
2004 | ||
2005 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
197160d5 NS |
2006 | |
2007 | /* eMMC spec does not require a delay between tuning cycles */ | |
2008 | if (opcode == MMC_SEND_TUNING_BLOCK) | |
2009 | mdelay(1); | |
b513ea25 AN |
2010 | } while (ctrl & SDHCI_CTRL_EXEC_TUNING); |
2011 | ||
2012 | /* | |
2013 | * The Host Driver has exhausted the maximum number of loops allowed, | |
2014 | * so use fixed sampling frequency. | |
2015 | */ | |
7ce45e95 | 2016 | if (tuning_loop_counter < 0) { |
b513ea25 AN |
2017 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; |
2018 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
7ce45e95 AC |
2019 | } |
2020 | if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { | |
2021 | pr_info(DRIVER_NAME ": Tuning procedure" | |
2022 | " failed, falling back to fixed sampling" | |
2023 | " clock\n"); | |
114f2bf6 | 2024 | err = -EIO; |
b513ea25 AN |
2025 | } |
2026 | ||
2027 | out: | |
cf2b5eea AN |
2028 | /* |
2029 | * If this is the very first time we are here, we start the retuning | |
2030 | * timer. Since only during the first time, SDHCI_NEEDS_RETUNING | |
2031 | * flag won't be set, we check this condition before actually starting | |
2032 | * the timer. | |
2033 | */ | |
2034 | if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count && | |
2035 | (host->tuning_mode == SDHCI_TUNING_MODE_1)) { | |
973905fe | 2036 | host->flags |= SDHCI_USING_RETUNING_TIMER; |
cf2b5eea AN |
2037 | mod_timer(&host->tuning_timer, jiffies + |
2038 | host->tuning_count * HZ); | |
2039 | /* Tuning mode 1 limits the maximum data length to 4MB */ | |
2040 | mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size; | |
2bc02485 | 2041 | } else if (host->flags & SDHCI_USING_RETUNING_TIMER) { |
cf2b5eea AN |
2042 | host->flags &= ~SDHCI_NEEDS_RETUNING; |
2043 | /* Reload the new initial value for timer */ | |
2bc02485 AS |
2044 | mod_timer(&host->tuning_timer, jiffies + |
2045 | host->tuning_count * HZ); | |
cf2b5eea AN |
2046 | } |
2047 | ||
2048 | /* | |
2049 | * In case tuning fails, host controllers which support re-tuning can | |
2050 | * try tuning again at a later time, when the re-tuning timer expires. | |
2051 | * So for these controllers, we return 0. Since there might be other | |
2052 | * controllers who do not have this capability, we return error for | |
973905fe AL |
2053 | * them. SDHCI_USING_RETUNING_TIMER means the host is currently using |
2054 | * a retuning timer to do the retuning for the card. | |
cf2b5eea | 2055 | */ |
973905fe | 2056 | if (err && (host->flags & SDHCI_USING_RETUNING_TIMER)) |
cf2b5eea AN |
2057 | err = 0; |
2058 | ||
b537f94c RK |
2059 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
2060 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
2b35bd83 | 2061 | spin_unlock_irqrestore(&host->lock, flags); |
66fd8ad5 | 2062 | sdhci_runtime_pm_put(host); |
b513ea25 AN |
2063 | |
2064 | return err; | |
2065 | } | |
2066 | ||
52983382 KL |
2067 | |
2068 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) | |
4d55c5a1 | 2069 | { |
4d55c5a1 AN |
2070 | /* Host Controller v3.00 defines preset value registers */ |
2071 | if (host->version < SDHCI_SPEC_300) | |
2072 | return; | |
2073 | ||
4d55c5a1 AN |
2074 | /* |
2075 | * We only enable or disable Preset Value if they are not already | |
2076 | * enabled or disabled respectively. Otherwise, we bail out. | |
2077 | */ | |
da91a8f9 RK |
2078 | if (host->preset_enabled != enable) { |
2079 | u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
2080 | ||
2081 | if (enable) | |
2082 | ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; | |
2083 | else | |
2084 | ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; | |
2085 | ||
4d55c5a1 | 2086 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
da91a8f9 RK |
2087 | |
2088 | if (enable) | |
2089 | host->flags |= SDHCI_PV_ENABLED; | |
2090 | else | |
2091 | host->flags &= ~SDHCI_PV_ENABLED; | |
2092 | ||
2093 | host->preset_enabled = enable; | |
4d55c5a1 | 2094 | } |
66fd8ad5 AH |
2095 | } |
2096 | ||
71e69211 | 2097 | static void sdhci_card_event(struct mmc_host *mmc) |
d129bceb | 2098 | { |
71e69211 | 2099 | struct sdhci_host *host = mmc_priv(mmc); |
d129bceb PO |
2100 | unsigned long flags; |
2101 | ||
722e1280 CD |
2102 | /* First check if client has provided their own card event */ |
2103 | if (host->ops->card_event) | |
2104 | host->ops->card_event(host); | |
2105 | ||
d129bceb PO |
2106 | spin_lock_irqsave(&host->lock, flags); |
2107 | ||
66fd8ad5 | 2108 | /* Check host->mrq first in case we are runtime suspended */ |
9668d765 | 2109 | if (host->mrq && !sdhci_do_get_cd(host)) { |
a3c76eb9 | 2110 | pr_err("%s: Card removed during transfer!\n", |
66fd8ad5 | 2111 | mmc_hostname(host->mmc)); |
a3c76eb9 | 2112 | pr_err("%s: Resetting controller.\n", |
66fd8ad5 | 2113 | mmc_hostname(host->mmc)); |
d129bceb | 2114 | |
03231f9b RK |
2115 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
2116 | sdhci_do_reset(host, SDHCI_RESET_DATA); | |
d129bceb | 2117 | |
66fd8ad5 AH |
2118 | host->mrq->cmd->error = -ENOMEDIUM; |
2119 | tasklet_schedule(&host->finish_tasklet); | |
d129bceb PO |
2120 | } |
2121 | ||
2122 | spin_unlock_irqrestore(&host->lock, flags); | |
71e69211 GL |
2123 | } |
2124 | ||
2125 | static const struct mmc_host_ops sdhci_ops = { | |
2126 | .request = sdhci_request, | |
2127 | .set_ios = sdhci_set_ios, | |
94144a46 | 2128 | .get_cd = sdhci_get_cd, |
71e69211 GL |
2129 | .get_ro = sdhci_get_ro, |
2130 | .hw_reset = sdhci_hw_reset, | |
2131 | .enable_sdio_irq = sdhci_enable_sdio_irq, | |
2132 | .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, | |
2133 | .execute_tuning = sdhci_execute_tuning, | |
71e69211 | 2134 | .card_event = sdhci_card_event, |
20b92a30 | 2135 | .card_busy = sdhci_card_busy, |
71e69211 GL |
2136 | }; |
2137 | ||
2138 | /*****************************************************************************\ | |
2139 | * * | |
2140 | * Tasklets * | |
2141 | * * | |
2142 | \*****************************************************************************/ | |
2143 | ||
d129bceb PO |
2144 | static void sdhci_tasklet_finish(unsigned long param) |
2145 | { | |
2146 | struct sdhci_host *host; | |
2147 | unsigned long flags; | |
2148 | struct mmc_request *mrq; | |
2149 | ||
2150 | host = (struct sdhci_host*)param; | |
2151 | ||
66fd8ad5 AH |
2152 | spin_lock_irqsave(&host->lock, flags); |
2153 | ||
0c9c99a7 CB |
2154 | /* |
2155 | * If this tasklet gets rescheduled while running, it will | |
2156 | * be run again afterwards but without any active request. | |
2157 | */ | |
66fd8ad5 AH |
2158 | if (!host->mrq) { |
2159 | spin_unlock_irqrestore(&host->lock, flags); | |
0c9c99a7 | 2160 | return; |
66fd8ad5 | 2161 | } |
d129bceb PO |
2162 | |
2163 | del_timer(&host->timer); | |
2164 | ||
2165 | mrq = host->mrq; | |
2166 | ||
d129bceb PO |
2167 | /* |
2168 | * The controller needs a reset of internal state machines | |
2169 | * upon error conditions. | |
2170 | */ | |
1e72859e | 2171 | if (!(host->flags & SDHCI_DEVICE_DEAD) && |
b7b4d342 | 2172 | ((mrq->cmd && mrq->cmd->error) || |
fce9d33f AG |
2173 | (mrq->sbc && mrq->sbc->error) || |
2174 | (mrq->data && ((mrq->data->error && !mrq->data->stop) || | |
2175 | (mrq->data->stop && mrq->data->stop->error))) || | |
2176 | (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { | |
645289dc PO |
2177 | |
2178 | /* Some controllers need this kick or reset won't work here */ | |
8213af3b | 2179 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) |
645289dc | 2180 | /* This is to force an update */ |
1771059c | 2181 | host->ops->set_clock(host, host->clock); |
645289dc PO |
2182 | |
2183 | /* Spec says we should do both at the same time, but Ricoh | |
2184 | controllers do not like that. */ | |
03231f9b RK |
2185 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
2186 | sdhci_do_reset(host, SDHCI_RESET_DATA); | |
d129bceb PO |
2187 | } |
2188 | ||
2189 | host->mrq = NULL; | |
2190 | host->cmd = NULL; | |
2191 | host->data = NULL; | |
2192 | ||
f9134319 | 2193 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 2194 | sdhci_deactivate_led(host); |
2f730fec | 2195 | #endif |
d129bceb | 2196 | |
5f25a66f | 2197 | mmiowb(); |
d129bceb PO |
2198 | spin_unlock_irqrestore(&host->lock, flags); |
2199 | ||
2200 | mmc_request_done(host->mmc, mrq); | |
66fd8ad5 | 2201 | sdhci_runtime_pm_put(host); |
d129bceb PO |
2202 | } |
2203 | ||
2204 | static void sdhci_timeout_timer(unsigned long data) | |
2205 | { | |
2206 | struct sdhci_host *host; | |
2207 | unsigned long flags; | |
2208 | ||
2209 | host = (struct sdhci_host*)data; | |
2210 | ||
2211 | spin_lock_irqsave(&host->lock, flags); | |
2212 | ||
2213 | if (host->mrq) { | |
a3c76eb9 | 2214 | pr_err("%s: Timeout waiting for hardware " |
acf1da45 | 2215 | "interrupt.\n", mmc_hostname(host->mmc)); |
d129bceb PO |
2216 | sdhci_dumpregs(host); |
2217 | ||
2218 | if (host->data) { | |
17b0429d | 2219 | host->data->error = -ETIMEDOUT; |
d129bceb PO |
2220 | sdhci_finish_data(host); |
2221 | } else { | |
2222 | if (host->cmd) | |
17b0429d | 2223 | host->cmd->error = -ETIMEDOUT; |
d129bceb | 2224 | else |
17b0429d | 2225 | host->mrq->cmd->error = -ETIMEDOUT; |
d129bceb PO |
2226 | |
2227 | tasklet_schedule(&host->finish_tasklet); | |
2228 | } | |
2229 | } | |
2230 | ||
5f25a66f | 2231 | mmiowb(); |
d129bceb PO |
2232 | spin_unlock_irqrestore(&host->lock, flags); |
2233 | } | |
2234 | ||
cf2b5eea AN |
2235 | static void sdhci_tuning_timer(unsigned long data) |
2236 | { | |
2237 | struct sdhci_host *host; | |
2238 | unsigned long flags; | |
2239 | ||
2240 | host = (struct sdhci_host *)data; | |
2241 | ||
2242 | spin_lock_irqsave(&host->lock, flags); | |
2243 | ||
2244 | host->flags |= SDHCI_NEEDS_RETUNING; | |
2245 | ||
2246 | spin_unlock_irqrestore(&host->lock, flags); | |
2247 | } | |
2248 | ||
d129bceb PO |
2249 | /*****************************************************************************\ |
2250 | * * | |
2251 | * Interrupt handling * | |
2252 | * * | |
2253 | \*****************************************************************************/ | |
2254 | ||
61541397 | 2255 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask) |
d129bceb PO |
2256 | { |
2257 | BUG_ON(intmask == 0); | |
2258 | ||
2259 | if (!host->cmd) { | |
a3c76eb9 | 2260 | pr_err("%s: Got command interrupt 0x%08x even " |
b67ac3f3 PO |
2261 | "though no command operation was in progress.\n", |
2262 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
2263 | sdhci_dumpregs(host); |
2264 | return; | |
2265 | } | |
2266 | ||
43b58b36 | 2267 | if (intmask & SDHCI_INT_TIMEOUT) |
17b0429d PO |
2268 | host->cmd->error = -ETIMEDOUT; |
2269 | else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | | |
2270 | SDHCI_INT_INDEX)) | |
2271 | host->cmd->error = -EILSEQ; | |
43b58b36 | 2272 | |
e809517f | 2273 | if (host->cmd->error) { |
d129bceb | 2274 | tasklet_schedule(&host->finish_tasklet); |
e809517f PO |
2275 | return; |
2276 | } | |
2277 | ||
2278 | /* | |
2279 | * The host can send and interrupt when the busy state has | |
2280 | * ended, allowing us to wait without wasting CPU cycles. | |
2281 | * Unfortunately this is overloaded on the "data complete" | |
2282 | * interrupt, so we need to take some care when handling | |
2283 | * it. | |
2284 | * | |
2285 | * Note: The 1.0 specification is a bit ambiguous about this | |
2286 | * feature so there might be some problems with older | |
2287 | * controllers. | |
2288 | */ | |
2289 | if (host->cmd->flags & MMC_RSP_BUSY) { | |
2290 | if (host->cmd->data) | |
2291 | DBG("Cannot wait for busy signal when also " | |
2292 | "doing a data transfer"); | |
e99783a4 CM |
2293 | else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) |
2294 | && !host->busy_handle) { | |
2295 | /* Mark that command complete before busy is ended */ | |
2296 | host->busy_handle = 1; | |
e809517f | 2297 | return; |
e99783a4 | 2298 | } |
f945405c BD |
2299 | |
2300 | /* The controller does not support the end-of-busy IRQ, | |
2301 | * fall through and take the SDHCI_INT_RESPONSE */ | |
61541397 AH |
2302 | } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && |
2303 | host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) { | |
2304 | *mask &= ~SDHCI_INT_DATA_END; | |
e809517f PO |
2305 | } |
2306 | ||
2307 | if (intmask & SDHCI_INT_RESPONSE) | |
43b58b36 | 2308 | sdhci_finish_command(host); |
d129bceb PO |
2309 | } |
2310 | ||
0957c333 | 2311 | #ifdef CONFIG_MMC_DEBUG |
08621b18 | 2312 | static void sdhci_adma_show_error(struct sdhci_host *host) |
6882a8c0 BD |
2313 | { |
2314 | const char *name = mmc_hostname(host->mmc); | |
1c3d5f6d | 2315 | void *desc = host->adma_table; |
6882a8c0 BD |
2316 | |
2317 | sdhci_dumpregs(host); | |
2318 | ||
2319 | while (true) { | |
e57a5f61 AH |
2320 | struct sdhci_adma2_64_desc *dma_desc = desc; |
2321 | ||
2322 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
2323 | DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n", | |
2324 | name, desc, le32_to_cpu(dma_desc->addr_hi), | |
2325 | le32_to_cpu(dma_desc->addr_lo), | |
2326 | le16_to_cpu(dma_desc->len), | |
2327 | le16_to_cpu(dma_desc->cmd)); | |
2328 | else | |
2329 | DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", | |
2330 | name, desc, le32_to_cpu(dma_desc->addr_lo), | |
2331 | le16_to_cpu(dma_desc->len), | |
2332 | le16_to_cpu(dma_desc->cmd)); | |
6882a8c0 | 2333 | |
76fe379a | 2334 | desc += host->desc_sz; |
6882a8c0 | 2335 | |
0545230f | 2336 | if (dma_desc->cmd & cpu_to_le16(ADMA2_END)) |
6882a8c0 BD |
2337 | break; |
2338 | } | |
2339 | } | |
2340 | #else | |
08621b18 | 2341 | static void sdhci_adma_show_error(struct sdhci_host *host) { } |
6882a8c0 BD |
2342 | #endif |
2343 | ||
d129bceb PO |
2344 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) |
2345 | { | |
069c9f14 | 2346 | u32 command; |
d129bceb PO |
2347 | BUG_ON(intmask == 0); |
2348 | ||
b513ea25 AN |
2349 | /* CMD19 generates _only_ Buffer Read Ready interrupt */ |
2350 | if (intmask & SDHCI_INT_DATA_AVAIL) { | |
069c9f14 G |
2351 | command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); |
2352 | if (command == MMC_SEND_TUNING_BLOCK || | |
2353 | command == MMC_SEND_TUNING_BLOCK_HS200) { | |
b513ea25 AN |
2354 | host->tuning_done = 1; |
2355 | wake_up(&host->buf_ready_int); | |
2356 | return; | |
2357 | } | |
2358 | } | |
2359 | ||
d129bceb PO |
2360 | if (!host->data) { |
2361 | /* | |
e809517f PO |
2362 | * The "data complete" interrupt is also used to |
2363 | * indicate that a busy state has ended. See comment | |
2364 | * above in sdhci_cmd_irq(). | |
d129bceb | 2365 | */ |
e809517f | 2366 | if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { |
c5abd5e8 MC |
2367 | if (intmask & SDHCI_INT_DATA_TIMEOUT) { |
2368 | host->cmd->error = -ETIMEDOUT; | |
2369 | tasklet_schedule(&host->finish_tasklet); | |
2370 | return; | |
2371 | } | |
e809517f | 2372 | if (intmask & SDHCI_INT_DATA_END) { |
e99783a4 CM |
2373 | /* |
2374 | * Some cards handle busy-end interrupt | |
2375 | * before the command completed, so make | |
2376 | * sure we do things in the proper order. | |
2377 | */ | |
2378 | if (host->busy_handle) | |
2379 | sdhci_finish_command(host); | |
2380 | else | |
2381 | host->busy_handle = 1; | |
e809517f PO |
2382 | return; |
2383 | } | |
2384 | } | |
d129bceb | 2385 | |
a3c76eb9 | 2386 | pr_err("%s: Got data interrupt 0x%08x even " |
b67ac3f3 PO |
2387 | "though no data operation was in progress.\n", |
2388 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
2389 | sdhci_dumpregs(host); |
2390 | ||
2391 | return; | |
2392 | } | |
2393 | ||
2394 | if (intmask & SDHCI_INT_DATA_TIMEOUT) | |
17b0429d | 2395 | host->data->error = -ETIMEDOUT; |
22113efd AL |
2396 | else if (intmask & SDHCI_INT_DATA_END_BIT) |
2397 | host->data->error = -EILSEQ; | |
2398 | else if ((intmask & SDHCI_INT_DATA_CRC) && | |
2399 | SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) | |
2400 | != MMC_BUS_TEST_R) | |
17b0429d | 2401 | host->data->error = -EILSEQ; |
6882a8c0 | 2402 | else if (intmask & SDHCI_INT_ADMA_ERROR) { |
a3c76eb9 | 2403 | pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); |
08621b18 | 2404 | sdhci_adma_show_error(host); |
2134a922 | 2405 | host->data->error = -EIO; |
a4071fbb HZ |
2406 | if (host->ops->adma_workaround) |
2407 | host->ops->adma_workaround(host, intmask); | |
6882a8c0 | 2408 | } |
d129bceb | 2409 | |
17b0429d | 2410 | if (host->data->error) |
d129bceb PO |
2411 | sdhci_finish_data(host); |
2412 | else { | |
a406f5a3 | 2413 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
d129bceb PO |
2414 | sdhci_transfer_pio(host); |
2415 | ||
6ba736a1 PO |
2416 | /* |
2417 | * We currently don't do anything fancy with DMA | |
2418 | * boundaries, but as we can't disable the feature | |
2419 | * we need to at least restart the transfer. | |
f6a03cbf MV |
2420 | * |
2421 | * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) | |
2422 | * should return a valid address to continue from, but as | |
2423 | * some controllers are faulty, don't trust them. | |
6ba736a1 | 2424 | */ |
f6a03cbf MV |
2425 | if (intmask & SDHCI_INT_DMA_END) { |
2426 | u32 dmastart, dmanow; | |
2427 | dmastart = sg_dma_address(host->data->sg); | |
2428 | dmanow = dmastart + host->data->bytes_xfered; | |
2429 | /* | |
2430 | * Force update to the next DMA block boundary. | |
2431 | */ | |
2432 | dmanow = (dmanow & | |
2433 | ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + | |
2434 | SDHCI_DEFAULT_BOUNDARY_SIZE; | |
2435 | host->data->bytes_xfered = dmanow - dmastart; | |
2436 | DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," | |
2437 | " next 0x%08x\n", | |
2438 | mmc_hostname(host->mmc), dmastart, | |
2439 | host->data->bytes_xfered, dmanow); | |
2440 | sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); | |
2441 | } | |
6ba736a1 | 2442 | |
e538fbe8 PO |
2443 | if (intmask & SDHCI_INT_DATA_END) { |
2444 | if (host->cmd) { | |
2445 | /* | |
2446 | * Data managed to finish before the | |
2447 | * command completed. Make sure we do | |
2448 | * things in the proper order. | |
2449 | */ | |
2450 | host->data_early = 1; | |
2451 | } else { | |
2452 | sdhci_finish_data(host); | |
2453 | } | |
2454 | } | |
d129bceb PO |
2455 | } |
2456 | } | |
2457 | ||
7d12e780 | 2458 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
d129bceb | 2459 | { |
781e989c | 2460 | irqreturn_t result = IRQ_NONE; |
66fd8ad5 | 2461 | struct sdhci_host *host = dev_id; |
41005003 | 2462 | u32 intmask, mask, unexpected = 0; |
781e989c | 2463 | int max_loops = 16; |
d129bceb PO |
2464 | |
2465 | spin_lock(&host->lock); | |
2466 | ||
be138554 | 2467 | if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { |
66fd8ad5 | 2468 | spin_unlock(&host->lock); |
655bca76 | 2469 | return IRQ_NONE; |
66fd8ad5 AH |
2470 | } |
2471 | ||
4e4141a5 | 2472 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
62df67a5 | 2473 | if (!intmask || intmask == 0xffffffff) { |
d129bceb PO |
2474 | result = IRQ_NONE; |
2475 | goto out; | |
2476 | } | |
2477 | ||
41005003 RK |
2478 | do { |
2479 | /* Clear selected interrupts. */ | |
2480 | mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | | |
2481 | SDHCI_INT_BUS_POWER); | |
2482 | sdhci_writel(host, mask, SDHCI_INT_STATUS); | |
d129bceb | 2483 | |
41005003 RK |
2484 | DBG("*** %s got interrupt: 0x%08x\n", |
2485 | mmc_hostname(host->mmc), intmask); | |
d129bceb | 2486 | |
41005003 RK |
2487 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
2488 | u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
2489 | SDHCI_CARD_PRESENT; | |
d129bceb | 2490 | |
41005003 RK |
2491 | /* |
2492 | * There is a observation on i.mx esdhc. INSERT | |
2493 | * bit will be immediately set again when it gets | |
2494 | * cleared, if a card is inserted. We have to mask | |
2495 | * the irq to prevent interrupt storm which will | |
2496 | * freeze the system. And the REMOVE gets the | |
2497 | * same situation. | |
2498 | * | |
2499 | * More testing are needed here to ensure it works | |
2500 | * for other platforms though. | |
2501 | */ | |
b537f94c RK |
2502 | host->ier &= ~(SDHCI_INT_CARD_INSERT | |
2503 | SDHCI_INT_CARD_REMOVE); | |
2504 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : | |
2505 | SDHCI_INT_CARD_INSERT; | |
2506 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
2507 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
41005003 RK |
2508 | |
2509 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | | |
2510 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); | |
3560db8e RK |
2511 | |
2512 | host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | | |
2513 | SDHCI_INT_CARD_REMOVE); | |
2514 | result = IRQ_WAKE_THREAD; | |
41005003 | 2515 | } |
d129bceb | 2516 | |
41005003 | 2517 | if (intmask & SDHCI_INT_CMD_MASK) |
61541397 AH |
2518 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, |
2519 | &intmask); | |
964f9ce2 | 2520 | |
41005003 RK |
2521 | if (intmask & SDHCI_INT_DATA_MASK) |
2522 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); | |
d129bceb | 2523 | |
41005003 RK |
2524 | if (intmask & SDHCI_INT_BUS_POWER) |
2525 | pr_err("%s: Card is consuming too much power!\n", | |
2526 | mmc_hostname(host->mmc)); | |
3192a28f | 2527 | |
781e989c RK |
2528 | if (intmask & SDHCI_INT_CARD_INT) { |
2529 | sdhci_enable_sdio_irq_nolock(host, false); | |
2530 | host->thread_isr |= SDHCI_INT_CARD_INT; | |
2531 | result = IRQ_WAKE_THREAD; | |
2532 | } | |
f75979b7 | 2533 | |
41005003 RK |
2534 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | |
2535 | SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | | |
2536 | SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | | |
2537 | SDHCI_INT_CARD_INT); | |
f75979b7 | 2538 | |
41005003 RK |
2539 | if (intmask) { |
2540 | unexpected |= intmask; | |
2541 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); | |
2542 | } | |
d129bceb | 2543 | |
781e989c RK |
2544 | if (result == IRQ_NONE) |
2545 | result = IRQ_HANDLED; | |
d129bceb | 2546 | |
41005003 | 2547 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
41005003 | 2548 | } while (intmask && --max_loops); |
d129bceb PO |
2549 | out: |
2550 | spin_unlock(&host->lock); | |
2551 | ||
6379b237 AS |
2552 | if (unexpected) { |
2553 | pr_err("%s: Unexpected interrupt 0x%08x.\n", | |
2554 | mmc_hostname(host->mmc), unexpected); | |
2555 | sdhci_dumpregs(host); | |
2556 | } | |
f75979b7 | 2557 | |
d129bceb PO |
2558 | return result; |
2559 | } | |
2560 | ||
781e989c RK |
2561 | static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) |
2562 | { | |
2563 | struct sdhci_host *host = dev_id; | |
2564 | unsigned long flags; | |
2565 | u32 isr; | |
2566 | ||
2567 | spin_lock_irqsave(&host->lock, flags); | |
2568 | isr = host->thread_isr; | |
2569 | host->thread_isr = 0; | |
2570 | spin_unlock_irqrestore(&host->lock, flags); | |
2571 | ||
3560db8e RK |
2572 | if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
2573 | sdhci_card_event(host->mmc); | |
2574 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); | |
2575 | } | |
2576 | ||
781e989c RK |
2577 | if (isr & SDHCI_INT_CARD_INT) { |
2578 | sdio_run_irqs(host->mmc); | |
2579 | ||
2580 | spin_lock_irqsave(&host->lock, flags); | |
2581 | if (host->flags & SDHCI_SDIO_IRQ_ENABLED) | |
2582 | sdhci_enable_sdio_irq_nolock(host, true); | |
2583 | spin_unlock_irqrestore(&host->lock, flags); | |
2584 | } | |
2585 | ||
2586 | return isr ? IRQ_HANDLED : IRQ_NONE; | |
2587 | } | |
2588 | ||
d129bceb PO |
2589 | /*****************************************************************************\ |
2590 | * * | |
2591 | * Suspend/resume * | |
2592 | * * | |
2593 | \*****************************************************************************/ | |
2594 | ||
2595 | #ifdef CONFIG_PM | |
ad080d79 KL |
2596 | void sdhci_enable_irq_wakeups(struct sdhci_host *host) |
2597 | { | |
2598 | u8 val; | |
2599 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE | |
2600 | | SDHCI_WAKE_ON_INT; | |
2601 | ||
2602 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); | |
2603 | val |= mask ; | |
2604 | /* Avoid fake wake up */ | |
2605 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) | |
2606 | val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); | |
2607 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); | |
2608 | } | |
2609 | EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); | |
2610 | ||
0b10f478 | 2611 | static void sdhci_disable_irq_wakeups(struct sdhci_host *host) |
ad080d79 KL |
2612 | { |
2613 | u8 val; | |
2614 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE | |
2615 | | SDHCI_WAKE_ON_INT; | |
2616 | ||
2617 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); | |
2618 | val &= ~mask; | |
2619 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); | |
2620 | } | |
d129bceb | 2621 | |
29495aa0 | 2622 | int sdhci_suspend_host(struct sdhci_host *host) |
d129bceb | 2623 | { |
7260cf5e AV |
2624 | sdhci_disable_card_detection(host); |
2625 | ||
cf2b5eea | 2626 | /* Disable tuning since we are suspending */ |
973905fe | 2627 | if (host->flags & SDHCI_USING_RETUNING_TIMER) { |
c6ced0db | 2628 | del_timer_sync(&host->tuning_timer); |
cf2b5eea | 2629 | host->flags &= ~SDHCI_NEEDS_RETUNING; |
cf2b5eea AN |
2630 | } |
2631 | ||
ad080d79 | 2632 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
b537f94c RK |
2633 | host->ier = 0; |
2634 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); | |
2635 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); | |
ad080d79 KL |
2636 | free_irq(host->irq, host); |
2637 | } else { | |
2638 | sdhci_enable_irq_wakeups(host); | |
2639 | enable_irq_wake(host->irq); | |
2640 | } | |
4ee14ec6 | 2641 | return 0; |
d129bceb PO |
2642 | } |
2643 | ||
b8c86fc5 | 2644 | EXPORT_SYMBOL_GPL(sdhci_suspend_host); |
d129bceb | 2645 | |
b8c86fc5 PO |
2646 | int sdhci_resume_host(struct sdhci_host *host) |
2647 | { | |
4ee14ec6 | 2648 | int ret = 0; |
d129bceb | 2649 | |
a13abc7b | 2650 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
2651 | if (host->ops->enable_dma) |
2652 | host->ops->enable_dma(host); | |
2653 | } | |
d129bceb | 2654 | |
ad080d79 | 2655 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
781e989c RK |
2656 | ret = request_threaded_irq(host->irq, sdhci_irq, |
2657 | sdhci_thread_irq, IRQF_SHARED, | |
2658 | mmc_hostname(host->mmc), host); | |
ad080d79 KL |
2659 | if (ret) |
2660 | return ret; | |
2661 | } else { | |
2662 | sdhci_disable_irq_wakeups(host); | |
2663 | disable_irq_wake(host->irq); | |
2664 | } | |
d129bceb | 2665 | |
6308d290 AH |
2666 | if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && |
2667 | (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { | |
2668 | /* Card keeps power but host controller does not */ | |
2669 | sdhci_init(host, 0); | |
2670 | host->pwr = 0; | |
2671 | host->clock = 0; | |
2672 | sdhci_do_set_ios(host, &host->mmc->ios); | |
2673 | } else { | |
2674 | sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); | |
2675 | mmiowb(); | |
2676 | } | |
b8c86fc5 | 2677 | |
7260cf5e AV |
2678 | sdhci_enable_card_detection(host); |
2679 | ||
cf2b5eea | 2680 | /* Set the re-tuning expiration flag */ |
973905fe | 2681 | if (host->flags & SDHCI_USING_RETUNING_TIMER) |
cf2b5eea AN |
2682 | host->flags |= SDHCI_NEEDS_RETUNING; |
2683 | ||
2f4cbb3d | 2684 | return ret; |
d129bceb PO |
2685 | } |
2686 | ||
b8c86fc5 | 2687 | EXPORT_SYMBOL_GPL(sdhci_resume_host); |
d129bceb PO |
2688 | #endif /* CONFIG_PM */ |
2689 | ||
66fd8ad5 AH |
2690 | #ifdef CONFIG_PM_RUNTIME |
2691 | ||
2692 | static int sdhci_runtime_pm_get(struct sdhci_host *host) | |
2693 | { | |
2694 | return pm_runtime_get_sync(host->mmc->parent); | |
2695 | } | |
2696 | ||
2697 | static int sdhci_runtime_pm_put(struct sdhci_host *host) | |
2698 | { | |
2699 | pm_runtime_mark_last_busy(host->mmc->parent); | |
2700 | return pm_runtime_put_autosuspend(host->mmc->parent); | |
2701 | } | |
2702 | ||
f0710a55 AH |
2703 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) |
2704 | { | |
2705 | if (host->runtime_suspended || host->bus_on) | |
2706 | return; | |
2707 | host->bus_on = true; | |
2708 | pm_runtime_get_noresume(host->mmc->parent); | |
2709 | } | |
2710 | ||
2711 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) | |
2712 | { | |
2713 | if (host->runtime_suspended || !host->bus_on) | |
2714 | return; | |
2715 | host->bus_on = false; | |
2716 | pm_runtime_put_noidle(host->mmc->parent); | |
2717 | } | |
2718 | ||
66fd8ad5 AH |
2719 | int sdhci_runtime_suspend_host(struct sdhci_host *host) |
2720 | { | |
2721 | unsigned long flags; | |
66fd8ad5 AH |
2722 | |
2723 | /* Disable tuning since we are suspending */ | |
973905fe | 2724 | if (host->flags & SDHCI_USING_RETUNING_TIMER) { |
66fd8ad5 AH |
2725 | del_timer_sync(&host->tuning_timer); |
2726 | host->flags &= ~SDHCI_NEEDS_RETUNING; | |
2727 | } | |
2728 | ||
2729 | spin_lock_irqsave(&host->lock, flags); | |
b537f94c RK |
2730 | host->ier &= SDHCI_INT_CARD_INT; |
2731 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
2732 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
66fd8ad5 AH |
2733 | spin_unlock_irqrestore(&host->lock, flags); |
2734 | ||
781e989c | 2735 | synchronize_hardirq(host->irq); |
66fd8ad5 AH |
2736 | |
2737 | spin_lock_irqsave(&host->lock, flags); | |
2738 | host->runtime_suspended = true; | |
2739 | spin_unlock_irqrestore(&host->lock, flags); | |
2740 | ||
8a125bad | 2741 | return 0; |
66fd8ad5 AH |
2742 | } |
2743 | EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); | |
2744 | ||
2745 | int sdhci_runtime_resume_host(struct sdhci_host *host) | |
2746 | { | |
2747 | unsigned long flags; | |
8a125bad | 2748 | int host_flags = host->flags; |
66fd8ad5 AH |
2749 | |
2750 | if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { | |
2751 | if (host->ops->enable_dma) | |
2752 | host->ops->enable_dma(host); | |
2753 | } | |
2754 | ||
2755 | sdhci_init(host, 0); | |
2756 | ||
2757 | /* Force clock and power re-program */ | |
2758 | host->pwr = 0; | |
2759 | host->clock = 0; | |
2760 | sdhci_do_set_ios(host, &host->mmc->ios); | |
2761 | ||
2762 | sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); | |
52983382 KL |
2763 | if ((host_flags & SDHCI_PV_ENABLED) && |
2764 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { | |
2765 | spin_lock_irqsave(&host->lock, flags); | |
2766 | sdhci_enable_preset_value(host, true); | |
2767 | spin_unlock_irqrestore(&host->lock, flags); | |
2768 | } | |
66fd8ad5 AH |
2769 | |
2770 | /* Set the re-tuning expiration flag */ | |
973905fe | 2771 | if (host->flags & SDHCI_USING_RETUNING_TIMER) |
66fd8ad5 AH |
2772 | host->flags |= SDHCI_NEEDS_RETUNING; |
2773 | ||
2774 | spin_lock_irqsave(&host->lock, flags); | |
2775 | ||
2776 | host->runtime_suspended = false; | |
2777 | ||
2778 | /* Enable SDIO IRQ */ | |
ef104333 | 2779 | if (host->flags & SDHCI_SDIO_IRQ_ENABLED) |
66fd8ad5 AH |
2780 | sdhci_enable_sdio_irq_nolock(host, true); |
2781 | ||
2782 | /* Enable Card Detection */ | |
2783 | sdhci_enable_card_detection(host); | |
2784 | ||
2785 | spin_unlock_irqrestore(&host->lock, flags); | |
2786 | ||
8a125bad | 2787 | return 0; |
66fd8ad5 AH |
2788 | } |
2789 | EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); | |
2790 | ||
2791 | #endif | |
2792 | ||
d129bceb PO |
2793 | /*****************************************************************************\ |
2794 | * * | |
b8c86fc5 | 2795 | * Device allocation/registration * |
d129bceb PO |
2796 | * * |
2797 | \*****************************************************************************/ | |
2798 | ||
b8c86fc5 PO |
2799 | struct sdhci_host *sdhci_alloc_host(struct device *dev, |
2800 | size_t priv_size) | |
d129bceb | 2801 | { |
d129bceb PO |
2802 | struct mmc_host *mmc; |
2803 | struct sdhci_host *host; | |
2804 | ||
b8c86fc5 | 2805 | WARN_ON(dev == NULL); |
d129bceb | 2806 | |
b8c86fc5 | 2807 | mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); |
d129bceb | 2808 | if (!mmc) |
b8c86fc5 | 2809 | return ERR_PTR(-ENOMEM); |
d129bceb PO |
2810 | |
2811 | host = mmc_priv(mmc); | |
2812 | host->mmc = mmc; | |
2813 | ||
b8c86fc5 PO |
2814 | return host; |
2815 | } | |
8a4da143 | 2816 | |
b8c86fc5 | 2817 | EXPORT_SYMBOL_GPL(sdhci_alloc_host); |
d129bceb | 2818 | |
b8c86fc5 PO |
2819 | int sdhci_add_host(struct sdhci_host *host) |
2820 | { | |
2821 | struct mmc_host *mmc; | |
bd6a8c30 | 2822 | u32 caps[2] = {0, 0}; |
f2119df6 AN |
2823 | u32 max_current_caps; |
2824 | unsigned int ocr_avail; | |
f5fa92e5 | 2825 | unsigned int override_timeout_clk; |
b8c86fc5 | 2826 | int ret; |
d129bceb | 2827 | |
b8c86fc5 PO |
2828 | WARN_ON(host == NULL); |
2829 | if (host == NULL) | |
2830 | return -EINVAL; | |
d129bceb | 2831 | |
b8c86fc5 | 2832 | mmc = host->mmc; |
d129bceb | 2833 | |
b8c86fc5 PO |
2834 | if (debug_quirks) |
2835 | host->quirks = debug_quirks; | |
66fd8ad5 AH |
2836 | if (debug_quirks2) |
2837 | host->quirks2 = debug_quirks2; | |
d129bceb | 2838 | |
f5fa92e5 AH |
2839 | override_timeout_clk = host->timeout_clk; |
2840 | ||
03231f9b | 2841 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
d96649ed | 2842 | |
4e4141a5 | 2843 | host->version = sdhci_readw(host, SDHCI_HOST_VERSION); |
2134a922 PO |
2844 | host->version = (host->version & SDHCI_SPEC_VER_MASK) |
2845 | >> SDHCI_SPEC_VER_SHIFT; | |
85105c53 | 2846 | if (host->version > SDHCI_SPEC_300) { |
a3c76eb9 | 2847 | pr_err("%s: Unknown controller version (%d). " |
b69c9058 | 2848 | "You may experience problems.\n", mmc_hostname(mmc), |
2134a922 | 2849 | host->version); |
4a965505 PO |
2850 | } |
2851 | ||
f2119df6 | 2852 | caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : |
ccc92c23 | 2853 | sdhci_readl(host, SDHCI_CAPABILITIES); |
d129bceb | 2854 | |
bd6a8c30 PR |
2855 | if (host->version >= SDHCI_SPEC_300) |
2856 | caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? | |
2857 | host->caps1 : | |
2858 | sdhci_readl(host, SDHCI_CAPABILITIES_1); | |
f2119df6 | 2859 | |
b8c86fc5 | 2860 | if (host->quirks & SDHCI_QUIRK_FORCE_DMA) |
a13abc7b | 2861 | host->flags |= SDHCI_USE_SDMA; |
f2119df6 | 2862 | else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) |
a13abc7b | 2863 | DBG("Controller doesn't have SDMA capability\n"); |
67435274 | 2864 | else |
a13abc7b | 2865 | host->flags |= SDHCI_USE_SDMA; |
d129bceb | 2866 | |
b8c86fc5 | 2867 | if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
a13abc7b | 2868 | (host->flags & SDHCI_USE_SDMA)) { |
cee687ce | 2869 | DBG("Disabling DMA as it is marked broken\n"); |
a13abc7b | 2870 | host->flags &= ~SDHCI_USE_SDMA; |
7c168e3d FT |
2871 | } |
2872 | ||
f2119df6 AN |
2873 | if ((host->version >= SDHCI_SPEC_200) && |
2874 | (caps[0] & SDHCI_CAN_DO_ADMA2)) | |
a13abc7b | 2875 | host->flags |= SDHCI_USE_ADMA; |
2134a922 PO |
2876 | |
2877 | if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && | |
2878 | (host->flags & SDHCI_USE_ADMA)) { | |
2879 | DBG("Disabling ADMA as it is marked broken\n"); | |
2880 | host->flags &= ~SDHCI_USE_ADMA; | |
2881 | } | |
2882 | ||
e57a5f61 AH |
2883 | /* |
2884 | * It is assumed that a 64-bit capable device has set a 64-bit DMA mask | |
2885 | * and *must* do 64-bit DMA. A driver has the opportunity to change | |
2886 | * that during the first call to ->enable_dma(). Similarly | |
2887 | * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to | |
2888 | * implement. | |
2889 | */ | |
2890 | if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT) | |
2891 | host->flags |= SDHCI_USE_64_BIT_DMA; | |
2892 | ||
a13abc7b | 2893 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
2894 | if (host->ops->enable_dma) { |
2895 | if (host->ops->enable_dma(host)) { | |
6606110d | 2896 | pr_warn("%s: No suitable DMA available - falling back to PIO\n", |
b8c86fc5 | 2897 | mmc_hostname(mmc)); |
a13abc7b RR |
2898 | host->flags &= |
2899 | ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); | |
b8c86fc5 | 2900 | } |
d129bceb PO |
2901 | } |
2902 | } | |
2903 | ||
e57a5f61 AH |
2904 | /* SDMA does not support 64-bit DMA */ |
2905 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
2906 | host->flags &= ~SDHCI_USE_SDMA; | |
2907 | ||
2134a922 PO |
2908 | if (host->flags & SDHCI_USE_ADMA) { |
2909 | /* | |
76fe379a AH |
2910 | * The DMA descriptor table size is calculated as the maximum |
2911 | * number of segments times 2, to allow for an alignment | |
2912 | * descriptor for each segment, plus 1 for a nop end descriptor, | |
2913 | * all multipled by the descriptor size. | |
2134a922 | 2914 | */ |
e57a5f61 AH |
2915 | if (host->flags & SDHCI_USE_64_BIT_DMA) { |
2916 | host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * | |
2917 | SDHCI_ADMA2_64_DESC_SZ; | |
2918 | host->align_buffer_sz = SDHCI_MAX_SEGS * | |
2919 | SDHCI_ADMA2_64_ALIGN; | |
2920 | host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; | |
2921 | host->align_sz = SDHCI_ADMA2_64_ALIGN; | |
2922 | host->align_mask = SDHCI_ADMA2_64_ALIGN - 1; | |
2923 | } else { | |
2924 | host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * | |
2925 | SDHCI_ADMA2_32_DESC_SZ; | |
2926 | host->align_buffer_sz = SDHCI_MAX_SEGS * | |
2927 | SDHCI_ADMA2_32_ALIGN; | |
2928 | host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; | |
2929 | host->align_sz = SDHCI_ADMA2_32_ALIGN; | |
2930 | host->align_mask = SDHCI_ADMA2_32_ALIGN - 1; | |
2931 | } | |
4efaa6fb | 2932 | host->adma_table = dma_alloc_coherent(mmc_dev(mmc), |
76fe379a | 2933 | host->adma_table_sz, |
4efaa6fb AH |
2934 | &host->adma_addr, |
2935 | GFP_KERNEL); | |
76fe379a | 2936 | host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL); |
4efaa6fb | 2937 | if (!host->adma_table || !host->align_buffer) { |
76fe379a | 2938 | dma_free_coherent(mmc_dev(mmc), host->adma_table_sz, |
4efaa6fb | 2939 | host->adma_table, host->adma_addr); |
2134a922 | 2940 | kfree(host->align_buffer); |
6606110d | 2941 | pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", |
2134a922 PO |
2942 | mmc_hostname(mmc)); |
2943 | host->flags &= ~SDHCI_USE_ADMA; | |
4efaa6fb | 2944 | host->adma_table = NULL; |
d1e49f77 | 2945 | host->align_buffer = NULL; |
76fe379a | 2946 | } else if (host->adma_addr & host->align_mask) { |
6606110d JP |
2947 | pr_warn("%s: unable to allocate aligned ADMA descriptor\n", |
2948 | mmc_hostname(mmc)); | |
d1e49f77 | 2949 | host->flags &= ~SDHCI_USE_ADMA; |
76fe379a | 2950 | dma_free_coherent(mmc_dev(mmc), host->adma_table_sz, |
4efaa6fb | 2951 | host->adma_table, host->adma_addr); |
d1e49f77 | 2952 | kfree(host->align_buffer); |
4efaa6fb | 2953 | host->adma_table = NULL; |
d1e49f77 | 2954 | host->align_buffer = NULL; |
2134a922 PO |
2955 | } |
2956 | } | |
2957 | ||
7659150c PO |
2958 | /* |
2959 | * If we use DMA, then it's up to the caller to set the DMA | |
2960 | * mask, but PIO does not need the hw shim so we set a new | |
2961 | * mask here in that case. | |
2962 | */ | |
a13abc7b | 2963 | if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { |
7659150c | 2964 | host->dma_mask = DMA_BIT_MASK(64); |
4e743f1f | 2965 | mmc_dev(mmc)->dma_mask = &host->dma_mask; |
7659150c | 2966 | } |
d129bceb | 2967 | |
c4687d5f | 2968 | if (host->version >= SDHCI_SPEC_300) |
f2119df6 | 2969 | host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) |
c4687d5f ZG |
2970 | >> SDHCI_CLOCK_BASE_SHIFT; |
2971 | else | |
f2119df6 | 2972 | host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) |
c4687d5f ZG |
2973 | >> SDHCI_CLOCK_BASE_SHIFT; |
2974 | ||
4240ff0a | 2975 | host->max_clk *= 1000000; |
f27f47ef AV |
2976 | if (host->max_clk == 0 || host->quirks & |
2977 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { | |
4240ff0a | 2978 | if (!host->ops->get_max_clock) { |
a3c76eb9 | 2979 | pr_err("%s: Hardware doesn't specify base clock " |
4240ff0a BD |
2980 | "frequency.\n", mmc_hostname(mmc)); |
2981 | return -ENODEV; | |
2982 | } | |
2983 | host->max_clk = host->ops->get_max_clock(host); | |
8ef1a143 | 2984 | } |
d129bceb | 2985 | |
c3ed3877 AN |
2986 | /* |
2987 | * In case of Host Controller v3.00, find out whether clock | |
2988 | * multiplier is supported. | |
2989 | */ | |
2990 | host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> | |
2991 | SDHCI_CLOCK_MUL_SHIFT; | |
2992 | ||
2993 | /* | |
2994 | * In case the value in Clock Multiplier is 0, then programmable | |
2995 | * clock mode is not supported, otherwise the actual clock | |
2996 | * multiplier is one more than the value of Clock Multiplier | |
2997 | * in the Capabilities Register. | |
2998 | */ | |
2999 | if (host->clk_mul) | |
3000 | host->clk_mul += 1; | |
3001 | ||
d129bceb PO |
3002 | /* |
3003 | * Set host parameters. | |
3004 | */ | |
3005 | mmc->ops = &sdhci_ops; | |
c3ed3877 | 3006 | mmc->f_max = host->max_clk; |
ce5f036b | 3007 | if (host->ops->get_min_clock) |
a9e58f25 | 3008 | mmc->f_min = host->ops->get_min_clock(host); |
c3ed3877 AN |
3009 | else if (host->version >= SDHCI_SPEC_300) { |
3010 | if (host->clk_mul) { | |
3011 | mmc->f_min = (host->max_clk * host->clk_mul) / 1024; | |
3012 | mmc->f_max = host->max_clk * host->clk_mul; | |
3013 | } else | |
3014 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; | |
3015 | } else | |
0397526d | 3016 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; |
15ec4461 | 3017 | |
28aab053 AD |
3018 | if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { |
3019 | host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> | |
3020 | SDHCI_TIMEOUT_CLK_SHIFT; | |
3021 | if (host->timeout_clk == 0) { | |
3022 | if (host->ops->get_timeout_clock) { | |
3023 | host->timeout_clk = | |
3024 | host->ops->get_timeout_clock(host); | |
3025 | } else { | |
3026 | pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", | |
3027 | mmc_hostname(mmc)); | |
3028 | return -ENODEV; | |
3029 | } | |
272308ca | 3030 | } |
272308ca | 3031 | |
28aab053 AD |
3032 | if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) |
3033 | host->timeout_clk *= 1000; | |
272308ca | 3034 | |
28aab053 | 3035 | mmc->max_busy_timeout = host->ops->get_max_timeout_count ? |
a6ff5aeb | 3036 | host->ops->get_max_timeout_count(host) : 1 << 27; |
28aab053 AD |
3037 | mmc->max_busy_timeout /= host->timeout_clk; |
3038 | } | |
58d1246d | 3039 | |
f5fa92e5 AH |
3040 | if (override_timeout_clk) |
3041 | host->timeout_clk = override_timeout_clk; | |
3042 | ||
e89d456f | 3043 | mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; |
781e989c | 3044 | mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; |
e89d456f AW |
3045 | |
3046 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) | |
3047 | host->flags |= SDHCI_AUTO_CMD12; | |
5fe23c7f | 3048 | |
8edf6371 | 3049 | /* Auto-CMD23 stuff only works in ADMA or PIO. */ |
4f3d3e9b | 3050 | if ((host->version >= SDHCI_SPEC_300) && |
8edf6371 | 3051 | ((host->flags & SDHCI_USE_ADMA) || |
4f3d3e9b | 3052 | !(host->flags & SDHCI_USE_SDMA))) { |
8edf6371 AW |
3053 | host->flags |= SDHCI_AUTO_CMD23; |
3054 | DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); | |
3055 | } else { | |
3056 | DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); | |
3057 | } | |
3058 | ||
15ec4461 PR |
3059 | /* |
3060 | * A controller may support 8-bit width, but the board itself | |
3061 | * might not have the pins brought out. Boards that support | |
3062 | * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in | |
3063 | * their platform code before calling sdhci_add_host(), and we | |
3064 | * won't assume 8-bit width for hosts without that CAP. | |
3065 | */ | |
5fe23c7f | 3066 | if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) |
15ec4461 | 3067 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
d129bceb | 3068 | |
63ef5d8c JH |
3069 | if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) |
3070 | mmc->caps &= ~MMC_CAP_CMD23; | |
3071 | ||
f2119df6 | 3072 | if (caps[0] & SDHCI_CAN_DO_HISPD) |
a29e7e18 | 3073 | mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; |
cd9277c0 | 3074 | |
176d1ed4 | 3075 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && |
4e743f1f | 3076 | !(mmc->caps & MMC_CAP_NONREMOVABLE)) |
68d1fb7e AV |
3077 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
3078 | ||
3a48edc4 TK |
3079 | /* If there are external regulators, get them */ |
3080 | if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER) | |
3081 | return -EPROBE_DEFER; | |
3082 | ||
6231f3de | 3083 | /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ |
3a48edc4 TK |
3084 | if (!IS_ERR(mmc->supply.vqmmc)) { |
3085 | ret = regulator_enable(mmc->supply.vqmmc); | |
3086 | if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, | |
3087 | 1950000)) | |
8363c374 KL |
3088 | caps[1] &= ~(SDHCI_SUPPORT_SDR104 | |
3089 | SDHCI_SUPPORT_SDR50 | | |
3090 | SDHCI_SUPPORT_DDR50); | |
a3361aba CB |
3091 | if (ret) { |
3092 | pr_warn("%s: Failed to enable vqmmc regulator: %d\n", | |
3093 | mmc_hostname(mmc), ret); | |
3a48edc4 | 3094 | mmc->supply.vqmmc = NULL; |
a3361aba | 3095 | } |
8363c374 | 3096 | } |
6231f3de | 3097 | |
6a66180a DD |
3098 | if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) |
3099 | caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | | |
3100 | SDHCI_SUPPORT_DDR50); | |
3101 | ||
4188bba0 AC |
3102 | /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ |
3103 | if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | | |
3104 | SDHCI_SUPPORT_DDR50)) | |
f2119df6 AN |
3105 | mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; |
3106 | ||
3107 | /* SDR104 supports also implies SDR50 support */ | |
156e14b1 | 3108 | if (caps[1] & SDHCI_SUPPORT_SDR104) { |
f2119df6 | 3109 | mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; |
156e14b1 GC |
3110 | /* SD3.0: SDR104 is supported so (for eMMC) the caps2 |
3111 | * field can be promoted to support HS200. | |
3112 | */ | |
adc82855 | 3113 | if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) { |
13868bf2 | 3114 | mmc->caps2 |= MMC_CAP2_HS200; |
adc82855 CD |
3115 | if (IS_ERR(mmc->supply.vqmmc) || |
3116 | !regulator_is_supported_voltage | |
3117 | (mmc->supply.vqmmc, 1100000, 1300000)) | |
3118 | mmc->caps2 &= ~MMC_CAP2_HS200_1_2V_SDR; | |
3119 | } | |
156e14b1 | 3120 | } else if (caps[1] & SDHCI_SUPPORT_SDR50) |
f2119df6 AN |
3121 | mmc->caps |= MMC_CAP_UHS_SDR50; |
3122 | ||
9107ebbf MC |
3123 | if ((caps[1] & SDHCI_SUPPORT_DDR50) && |
3124 | !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) | |
f2119df6 AN |
3125 | mmc->caps |= MMC_CAP_UHS_DDR50; |
3126 | ||
069c9f14 | 3127 | /* Does the host need tuning for SDR50? */ |
b513ea25 AN |
3128 | if (caps[1] & SDHCI_USE_SDR50_TUNING) |
3129 | host->flags |= SDHCI_SDR50_NEEDS_TUNING; | |
3130 | ||
156e14b1 | 3131 | /* Does the host need tuning for SDR104 / HS200? */ |
069c9f14 | 3132 | if (mmc->caps2 & MMC_CAP2_HS200) |
156e14b1 | 3133 | host->flags |= SDHCI_SDR104_NEEDS_TUNING; |
069c9f14 | 3134 | |
d6d50a15 AN |
3135 | /* Driver Type(s) (A, C, D) supported by the host */ |
3136 | if (caps[1] & SDHCI_DRIVER_TYPE_A) | |
3137 | mmc->caps |= MMC_CAP_DRIVER_TYPE_A; | |
3138 | if (caps[1] & SDHCI_DRIVER_TYPE_C) | |
3139 | mmc->caps |= MMC_CAP_DRIVER_TYPE_C; | |
3140 | if (caps[1] & SDHCI_DRIVER_TYPE_D) | |
3141 | mmc->caps |= MMC_CAP_DRIVER_TYPE_D; | |
3142 | ||
cf2b5eea AN |
3143 | /* Initial value for re-tuning timer count */ |
3144 | host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> | |
3145 | SDHCI_RETUNING_TIMER_COUNT_SHIFT; | |
3146 | ||
3147 | /* | |
3148 | * In case Re-tuning Timer is not disabled, the actual value of | |
3149 | * re-tuning timer will be 2 ^ (n - 1). | |
3150 | */ | |
3151 | if (host->tuning_count) | |
3152 | host->tuning_count = 1 << (host->tuning_count - 1); | |
3153 | ||
3154 | /* Re-tuning mode supported by the Host Controller */ | |
3155 | host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> | |
3156 | SDHCI_RETUNING_MODE_SHIFT; | |
3157 | ||
8f230f45 | 3158 | ocr_avail = 0; |
bad37e1a | 3159 | |
f2119df6 AN |
3160 | /* |
3161 | * According to SD Host Controller spec v3.00, if the Host System | |
3162 | * can afford more than 150mA, Host Driver should set XPC to 1. Also | |
3163 | * the value is meaningful only if Voltage Support in the Capabilities | |
3164 | * register is set. The actual current value is 4 times the register | |
3165 | * value. | |
3166 | */ | |
3167 | max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); | |
3a48edc4 | 3168 | if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { |
ae906037 | 3169 | int curr = regulator_get_current_limit(mmc->supply.vmmc); |
bad37e1a PR |
3170 | if (curr > 0) { |
3171 | ||
3172 | /* convert to SDHCI_MAX_CURRENT format */ | |
3173 | curr = curr/1000; /* convert to mA */ | |
3174 | curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; | |
3175 | ||
3176 | curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); | |
3177 | max_current_caps = | |
3178 | (curr << SDHCI_MAX_CURRENT_330_SHIFT) | | |
3179 | (curr << SDHCI_MAX_CURRENT_300_SHIFT) | | |
3180 | (curr << SDHCI_MAX_CURRENT_180_SHIFT); | |
3181 | } | |
3182 | } | |
f2119df6 AN |
3183 | |
3184 | if (caps[0] & SDHCI_CAN_VDD_330) { | |
8f230f45 | 3185 | ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; |
f2119df6 | 3186 | |
55c4665e | 3187 | mmc->max_current_330 = ((max_current_caps & |
f2119df6 AN |
3188 | SDHCI_MAX_CURRENT_330_MASK) >> |
3189 | SDHCI_MAX_CURRENT_330_SHIFT) * | |
3190 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
f2119df6 AN |
3191 | } |
3192 | if (caps[0] & SDHCI_CAN_VDD_300) { | |
8f230f45 | 3193 | ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; |
f2119df6 | 3194 | |
55c4665e | 3195 | mmc->max_current_300 = ((max_current_caps & |
f2119df6 AN |
3196 | SDHCI_MAX_CURRENT_300_MASK) >> |
3197 | SDHCI_MAX_CURRENT_300_SHIFT) * | |
3198 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
f2119df6 AN |
3199 | } |
3200 | if (caps[0] & SDHCI_CAN_VDD_180) { | |
8f230f45 TI |
3201 | ocr_avail |= MMC_VDD_165_195; |
3202 | ||
55c4665e | 3203 | mmc->max_current_180 = ((max_current_caps & |
f2119df6 AN |
3204 | SDHCI_MAX_CURRENT_180_MASK) >> |
3205 | SDHCI_MAX_CURRENT_180_SHIFT) * | |
3206 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
f2119df6 AN |
3207 | } |
3208 | ||
52221610 | 3209 | /* If OCR set by external regulators, use it instead */ |
3a48edc4 | 3210 | if (mmc->ocr_avail) |
52221610 | 3211 | ocr_avail = mmc->ocr_avail; |
3a48edc4 | 3212 | |
c0b887b6 | 3213 | if (host->ocr_mask) |
3a48edc4 | 3214 | ocr_avail &= host->ocr_mask; |
c0b887b6 | 3215 | |
8f230f45 TI |
3216 | mmc->ocr_avail = ocr_avail; |
3217 | mmc->ocr_avail_sdio = ocr_avail; | |
3218 | if (host->ocr_avail_sdio) | |
3219 | mmc->ocr_avail_sdio &= host->ocr_avail_sdio; | |
3220 | mmc->ocr_avail_sd = ocr_avail; | |
3221 | if (host->ocr_avail_sd) | |
3222 | mmc->ocr_avail_sd &= host->ocr_avail_sd; | |
3223 | else /* normal SD controllers don't support 1.8V */ | |
3224 | mmc->ocr_avail_sd &= ~MMC_VDD_165_195; | |
3225 | mmc->ocr_avail_mmc = ocr_avail; | |
3226 | if (host->ocr_avail_mmc) | |
3227 | mmc->ocr_avail_mmc &= host->ocr_avail_mmc; | |
146ad66e PO |
3228 | |
3229 | if (mmc->ocr_avail == 0) { | |
a3c76eb9 | 3230 | pr_err("%s: Hardware doesn't report any " |
b69c9058 | 3231 | "support voltages.\n", mmc_hostname(mmc)); |
b8c86fc5 | 3232 | return -ENODEV; |
146ad66e PO |
3233 | } |
3234 | ||
d129bceb PO |
3235 | spin_lock_init(&host->lock); |
3236 | ||
3237 | /* | |
2134a922 PO |
3238 | * Maximum number of segments. Depends on if the hardware |
3239 | * can do scatter/gather or not. | |
d129bceb | 3240 | */ |
2134a922 | 3241 | if (host->flags & SDHCI_USE_ADMA) |
4fb213f8 | 3242 | mmc->max_segs = SDHCI_MAX_SEGS; |
a13abc7b | 3243 | else if (host->flags & SDHCI_USE_SDMA) |
a36274e0 | 3244 | mmc->max_segs = 1; |
2134a922 | 3245 | else /* PIO */ |
4fb213f8 | 3246 | mmc->max_segs = SDHCI_MAX_SEGS; |
d129bceb PO |
3247 | |
3248 | /* | |
bab76961 | 3249 | * Maximum number of sectors in one transfer. Limited by DMA boundary |
55db890a | 3250 | * size (512KiB). |
d129bceb | 3251 | */ |
55db890a | 3252 | mmc->max_req_size = 524288; |
d129bceb PO |
3253 | |
3254 | /* | |
3255 | * Maximum segment size. Could be one segment with the maximum number | |
2134a922 PO |
3256 | * of bytes. When doing hardware scatter/gather, each entry cannot |
3257 | * be larger than 64 KiB though. | |
d129bceb | 3258 | */ |
30652aa3 OJ |
3259 | if (host->flags & SDHCI_USE_ADMA) { |
3260 | if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) | |
3261 | mmc->max_seg_size = 65535; | |
3262 | else | |
3263 | mmc->max_seg_size = 65536; | |
3264 | } else { | |
2134a922 | 3265 | mmc->max_seg_size = mmc->max_req_size; |
30652aa3 | 3266 | } |
d129bceb | 3267 | |
fe4a3c7a PO |
3268 | /* |
3269 | * Maximum block size. This varies from controller to controller and | |
3270 | * is specified in the capabilities register. | |
3271 | */ | |
0633f654 AV |
3272 | if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { |
3273 | mmc->max_blk_size = 2; | |
3274 | } else { | |
f2119df6 | 3275 | mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> |
0633f654 AV |
3276 | SDHCI_MAX_BLOCK_SHIFT; |
3277 | if (mmc->max_blk_size >= 3) { | |
6606110d JP |
3278 | pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", |
3279 | mmc_hostname(mmc)); | |
0633f654 AV |
3280 | mmc->max_blk_size = 0; |
3281 | } | |
3282 | } | |
3283 | ||
3284 | mmc->max_blk_size = 512 << mmc->max_blk_size; | |
fe4a3c7a | 3285 | |
55db890a PO |
3286 | /* |
3287 | * Maximum block count. | |
3288 | */ | |
1388eefd | 3289 | mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; |
55db890a | 3290 | |
d129bceb PO |
3291 | /* |
3292 | * Init tasklets. | |
3293 | */ | |
d129bceb PO |
3294 | tasklet_init(&host->finish_tasklet, |
3295 | sdhci_tasklet_finish, (unsigned long)host); | |
3296 | ||
e4cad1b5 | 3297 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
d129bceb | 3298 | |
cf2b5eea | 3299 | if (host->version >= SDHCI_SPEC_300) { |
b513ea25 AN |
3300 | init_waitqueue_head(&host->buf_ready_int); |
3301 | ||
cf2b5eea AN |
3302 | /* Initialize re-tuning timer */ |
3303 | init_timer(&host->tuning_timer); | |
3304 | host->tuning_timer.data = (unsigned long)host; | |
3305 | host->tuning_timer.function = sdhci_tuning_timer; | |
3306 | } | |
3307 | ||
2af502ca SG |
3308 | sdhci_init(host, 0); |
3309 | ||
781e989c RK |
3310 | ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, |
3311 | IRQF_SHARED, mmc_hostname(mmc), host); | |
0fc81ee3 MB |
3312 | if (ret) { |
3313 | pr_err("%s: Failed to request IRQ %d: %d\n", | |
3314 | mmc_hostname(mmc), host->irq, ret); | |
8ef1a143 | 3315 | goto untasklet; |
0fc81ee3 | 3316 | } |
d129bceb | 3317 | |
d129bceb PO |
3318 | #ifdef CONFIG_MMC_DEBUG |
3319 | sdhci_dumpregs(host); | |
3320 | #endif | |
3321 | ||
f9134319 | 3322 | #ifdef SDHCI_USE_LEDS_CLASS |
5dbace0c HS |
3323 | snprintf(host->led_name, sizeof(host->led_name), |
3324 | "%s::", mmc_hostname(mmc)); | |
3325 | host->led.name = host->led_name; | |
2f730fec PO |
3326 | host->led.brightness = LED_OFF; |
3327 | host->led.default_trigger = mmc_hostname(mmc); | |
3328 | host->led.brightness_set = sdhci_led_control; | |
3329 | ||
b8c86fc5 | 3330 | ret = led_classdev_register(mmc_dev(mmc), &host->led); |
0fc81ee3 MB |
3331 | if (ret) { |
3332 | pr_err("%s: Failed to register LED device: %d\n", | |
3333 | mmc_hostname(mmc), ret); | |
2f730fec | 3334 | goto reset; |
0fc81ee3 | 3335 | } |
2f730fec PO |
3336 | #endif |
3337 | ||
5f25a66f PO |
3338 | mmiowb(); |
3339 | ||
d129bceb PO |
3340 | mmc_add_host(mmc); |
3341 | ||
a3c76eb9 | 3342 | pr_info("%s: SDHCI controller on %s [%s] using %s\n", |
d1b26863 | 3343 | mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), |
e57a5f61 AH |
3344 | (host->flags & SDHCI_USE_ADMA) ? |
3345 | (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : | |
a13abc7b | 3346 | (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); |
d129bceb | 3347 | |
7260cf5e AV |
3348 | sdhci_enable_card_detection(host); |
3349 | ||
d129bceb PO |
3350 | return 0; |
3351 | ||
f9134319 | 3352 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec | 3353 | reset: |
03231f9b | 3354 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
b537f94c RK |
3355 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
3356 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); | |
2f730fec PO |
3357 | free_irq(host->irq, host); |
3358 | #endif | |
8ef1a143 | 3359 | untasklet: |
d129bceb | 3360 | tasklet_kill(&host->finish_tasklet); |
d129bceb PO |
3361 | |
3362 | return ret; | |
3363 | } | |
3364 | ||
b8c86fc5 | 3365 | EXPORT_SYMBOL_GPL(sdhci_add_host); |
d129bceb | 3366 | |
1e72859e | 3367 | void sdhci_remove_host(struct sdhci_host *host, int dead) |
b8c86fc5 | 3368 | { |
3a48edc4 | 3369 | struct mmc_host *mmc = host->mmc; |
1e72859e PO |
3370 | unsigned long flags; |
3371 | ||
3372 | if (dead) { | |
3373 | spin_lock_irqsave(&host->lock, flags); | |
3374 | ||
3375 | host->flags |= SDHCI_DEVICE_DEAD; | |
3376 | ||
3377 | if (host->mrq) { | |
a3c76eb9 | 3378 | pr_err("%s: Controller removed during " |
4e743f1f | 3379 | " transfer!\n", mmc_hostname(mmc)); |
1e72859e PO |
3380 | |
3381 | host->mrq->cmd->error = -ENOMEDIUM; | |
3382 | tasklet_schedule(&host->finish_tasklet); | |
3383 | } | |
3384 | ||
3385 | spin_unlock_irqrestore(&host->lock, flags); | |
3386 | } | |
3387 | ||
7260cf5e AV |
3388 | sdhci_disable_card_detection(host); |
3389 | ||
4e743f1f | 3390 | mmc_remove_host(mmc); |
d129bceb | 3391 | |
f9134319 | 3392 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
3393 | led_classdev_unregister(&host->led); |
3394 | #endif | |
3395 | ||
1e72859e | 3396 | if (!dead) |
03231f9b | 3397 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
d129bceb | 3398 | |
b537f94c RK |
3399 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
3400 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); | |
d129bceb PO |
3401 | free_irq(host->irq, host); |
3402 | ||
3403 | del_timer_sync(&host->timer); | |
3404 | ||
d129bceb | 3405 | tasklet_kill(&host->finish_tasklet); |
2134a922 | 3406 | |
3a48edc4 TK |
3407 | if (!IS_ERR(mmc->supply.vqmmc)) |
3408 | regulator_disable(mmc->supply.vqmmc); | |
6231f3de | 3409 | |
4efaa6fb | 3410 | if (host->adma_table) |
76fe379a | 3411 | dma_free_coherent(mmc_dev(mmc), host->adma_table_sz, |
4efaa6fb | 3412 | host->adma_table, host->adma_addr); |
2134a922 PO |
3413 | kfree(host->align_buffer); |
3414 | ||
4efaa6fb | 3415 | host->adma_table = NULL; |
2134a922 | 3416 | host->align_buffer = NULL; |
d129bceb PO |
3417 | } |
3418 | ||
b8c86fc5 | 3419 | EXPORT_SYMBOL_GPL(sdhci_remove_host); |
d129bceb | 3420 | |
b8c86fc5 | 3421 | void sdhci_free_host(struct sdhci_host *host) |
d129bceb | 3422 | { |
b8c86fc5 | 3423 | mmc_free_host(host->mmc); |
d129bceb PO |
3424 | } |
3425 | ||
b8c86fc5 | 3426 | EXPORT_SYMBOL_GPL(sdhci_free_host); |
d129bceb PO |
3427 | |
3428 | /*****************************************************************************\ | |
3429 | * * | |
3430 | * Driver init/exit * | |
3431 | * * | |
3432 | \*****************************************************************************/ | |
3433 | ||
3434 | static int __init sdhci_drv_init(void) | |
3435 | { | |
a3c76eb9 | 3436 | pr_info(DRIVER_NAME |
52fbf9c9 | 3437 | ": Secure Digital Host Controller Interface driver\n"); |
a3c76eb9 | 3438 | pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
d129bceb | 3439 | |
b8c86fc5 | 3440 | return 0; |
d129bceb PO |
3441 | } |
3442 | ||
3443 | static void __exit sdhci_drv_exit(void) | |
3444 | { | |
d129bceb PO |
3445 | } |
3446 | ||
3447 | module_init(sdhci_drv_init); | |
3448 | module_exit(sdhci_drv_exit); | |
3449 | ||
df673b22 | 3450 | module_param(debug_quirks, uint, 0444); |
66fd8ad5 | 3451 | module_param(debug_quirks2, uint, 0444); |
67435274 | 3452 | |
32710e8f | 3453 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 | 3454 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); |
d129bceb | 3455 | MODULE_LICENSE("GPL"); |
67435274 | 3456 | |
df673b22 | 3457 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |
66fd8ad5 | 3458 | MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); |