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mmc: sdhci: pass the cookie into sdhci_pre_dma_transfer()
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
f9134319
PO		 41#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43#define SDHCI_USE_LEDS_CLASS
44#endif
45
b513ea25
AN		 46#define MAX_TUNING_LOOP 40
47
df673b22 48static unsigned int debug_quirks = 0;
66fd8ad5 49static unsigned int debug_quirks2;
67435274 50
d129bceb
PO		 51static void sdhci_finish_data(struct sdhci_host *);
52
d129bceb 53static void sdhci_finish_command(struct sdhci_host *);
069c9f14 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
04e079cf 56static int sdhci_do_get_cd(struct sdhci_host *host);
d129bceb 57
162d6f98 58#ifdef CONFIG_PM
66fd8ad5
AH		 59static int sdhci_runtime_pm_get(struct sdhci_host *host);
60static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 61static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
62static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 63#else
64static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
65{
66 return 0;
67}
68static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
69{
70 return 0;
71}
f0710a55
AH		 72static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
73{
74}
75static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
76{
77}
66fd8ad5
AH		 78#endif
79
d129bceb
PO		 80static void sdhci_dumpregs(struct sdhci_host *host)
81{
a3c76eb9 82 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 83 mmc_hostname(host->mmc));
d129bceb 84
a3c76eb9 85 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 86 sdhci_readl(host, SDHCI_DMA_ADDRESS),
87 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 88 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 89 sdhci_readw(host, SDHCI_BLOCK_SIZE),
90 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 91 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 92 sdhci_readl(host, SDHCI_ARGUMENT),
93 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 94 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 95 sdhci_readl(host, SDHCI_PRESENT_STATE),
96 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 97 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 98 sdhci_readb(host, SDHCI_POWER_CONTROL),
99 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 100 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 101 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
102 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 103 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 104 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
105 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 106 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 107 sdhci_readl(host, SDHCI_INT_ENABLE),
108 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 109 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 110 sdhci_readw(host, SDHCI_ACMD12_ERR),
111 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 112 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 113 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 114 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 115 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 116 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 117 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 118 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 119 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 120
e57a5f61
AH		 121 if (host->flags & SDHCI_USE_ADMA) {
122 if (host->flags & SDHCI_USE_64_BIT_DMA)
123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
124 readl(host->ioaddr + SDHCI_ADMA_ERROR),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
126 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
127 else
128 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
129 readl(host->ioaddr + SDHCI_ADMA_ERROR),
130 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
131 }
be3f4ae0 132
a3c76eb9 133 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 134}
135
136/*****************************************************************************\
137 * *
138 * Low level functions *
139 * *
140\*****************************************************************************/
141
7260cf5e
AV		 142static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
143{
5b4f1f6c 144 u32 present;
7260cf5e 145
c79396c1 146 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 147 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 148 return;
149
5b4f1f6c
RK		 150 if (enable) {
151 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
152 SDHCI_CARD_PRESENT;
d25928d1 153
5b4f1f6c
RK		 154 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
155 SDHCI_INT_CARD_INSERT;
156 } else {
157 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
158 }
b537f94c
RK		 159
160 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
161 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 162}
163
164static void sdhci_enable_card_detection(struct sdhci_host *host)
165{
166 sdhci_set_card_detection(host, true);
167}
168
169static void sdhci_disable_card_detection(struct sdhci_host *host)
170{
171 sdhci_set_card_detection(host, false);
172}
173
03231f9b 174void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 175{
e16514d8 176 unsigned long timeout;
393c1a34 177
4e4141a5 178 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 179
f0710a55 180 if (mask & SDHCI_RESET_ALL) {
d129bceb 181 host->clock = 0;
f0710a55
AH		 182 /* Reset-all turns off SD Bus Power */
183 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
184 sdhci_runtime_pm_bus_off(host);
185 }
d129bceb 186
e16514d8
PO		 187 /* Wait max 100 ms */
188 timeout = 100;
189
190 /* hw clears the bit when it's done */
4e4141a5 191 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 192 if (timeout == 0) {
a3c76eb9 193 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 194 mmc_hostname(host->mmc), (int)mask);
195 sdhci_dumpregs(host);
196 return;
197 }
198 timeout--;
199 mdelay(1);
d129bceb 200 }
03231f9b
RK		 201}
202EXPORT_SYMBOL_GPL(sdhci_reset);
203
204static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
205{
206 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
135b0a28 207 if (!sdhci_do_get_cd(host))
03231f9b
RK		 208 return;
209 }
063a9dbb 210
03231f9b 211 host->ops->reset(host, mask);
393c1a34 212
da91a8f9
RK		 213 if (mask & SDHCI_RESET_ALL) {
214 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
215 if (host->ops->enable_dma)
216 host->ops->enable_dma(host);
217 }
218
219 /* Resetting the controller clears many */
220 host->preset_enabled = false;
3abc1e80 221 }
d129bceb
PO		 222}
223
2f4cbb3d
NP		 224static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
225
226static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 227{
2f4cbb3d 228 if (soft)
03231f9b 229 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 230 else
03231f9b 231 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 232
b537f94c
RK		 233 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
235 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
236 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
237 SDHCI_INT_RESPONSE;
238
239 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
240 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 241
242 if (soft) {
243 /* force clock reconfiguration */
244 host->clock = 0;
245 sdhci_set_ios(host->mmc, &host->mmc->ios);
246 }
7260cf5e 247}
d129bceb 248
7260cf5e
AV		 249static void sdhci_reinit(struct sdhci_host *host)
250{
2f4cbb3d 251 sdhci_init(host, 0);
7260cf5e 252 sdhci_enable_card_detection(host);
d129bceb
PO		 253}
254
255static void sdhci_activate_led(struct sdhci_host *host)
256{
257 u8 ctrl;
258
4e4141a5 259 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 260 ctrl |= SDHCI_CTRL_LED;
4e4141a5 261 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 262}
263
264static void sdhci_deactivate_led(struct sdhci_host *host)
265{
266 u8 ctrl;
267
4e4141a5 268 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 269 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 270 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 271}
272
f9134319 273#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 274static void sdhci_led_control(struct led_classdev *led,
275 enum led_brightness brightness)
276{
277 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
278 unsigned long flags;
279
280 spin_lock_irqsave(&host->lock, flags);
281
66fd8ad5
AH		 282 if (host->runtime_suspended)
283 goto out;
284
2f730fec
PO		 285 if (brightness == LED_OFF)
286 sdhci_deactivate_led(host);
287 else
288 sdhci_activate_led(host);
66fd8ad5 289out:
2f730fec
PO		 290 spin_unlock_irqrestore(&host->lock, flags);
291}
292#endif
293
d129bceb
PO		 294/*****************************************************************************\
295 * *
296 * Core functions *
297 * *
298\*****************************************************************************/
299
a406f5a3 300static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 301{
7659150c
PO		 302 unsigned long flags;
303 size_t blksize, len, chunk;
7244b85b 304 u32 uninitialized_var(scratch);
7659150c 305 u8 *buf;
d129bceb 306
a406f5a3 307 DBG("PIO reading\n");
d129bceb 308
a406f5a3 309 blksize = host->data->blksz;
7659150c 310 chunk = 0;
d129bceb 311
7659150c 312 local_irq_save(flags);
d129bceb 313
a406f5a3 314 while (blksize) {
bf3a35ac 315 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 316
7659150c 317 len = min(host->sg_miter.length, blksize);
d129bceb 318
7659150c
PO		 319 blksize -= len;
320 host->sg_miter.consumed = len;
14d836e7 321
7659150c 322 buf = host->sg_miter.addr;
d129bceb 323
7659150c
PO		 324 while (len) {
325 if (chunk == 0) {
4e4141a5 326 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 327 chunk = 4;
a406f5a3 328 }
7659150c
PO		 329
330 *buf = scratch & 0xFF;
331
332 buf++;
333 scratch >>= 8;
334 chunk--;
335 len--;
d129bceb 336 }
a406f5a3 337 }
7659150c
PO		 338
339 sg_miter_stop(&host->sg_miter);
340
341 local_irq_restore(flags);
a406f5a3 342}
d129bceb 343
a406f5a3
PO		 344static void sdhci_write_block_pio(struct sdhci_host *host)
345{
7659150c
PO		 346 unsigned long flags;
347 size_t blksize, len, chunk;
348 u32 scratch;
349 u8 *buf;
d129bceb 350
a406f5a3
PO		 351 DBG("PIO writing\n");
352
353 blksize = host->data->blksz;
7659150c
PO		 354 chunk = 0;
355 scratch = 0;
d129bceb 356
7659150c 357 local_irq_save(flags);
d129bceb 358
a406f5a3 359 while (blksize) {
bf3a35ac 360 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 361
7659150c
PO		 362 len = min(host->sg_miter.length, blksize);
363
364 blksize -= len;
365 host->sg_miter.consumed = len;
366
367 buf = host->sg_miter.addr;
d129bceb 368
7659150c
PO		 369 while (len) {
370 scratch |= (u32)*buf << (chunk * 8);
371
372 buf++;
373 chunk++;
374 len--;
375
376 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 377 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 378 chunk = 0;
379 scratch = 0;
d129bceb 380 }
d129bceb
PO		 381 }
382 }
7659150c
PO		 383
384 sg_miter_stop(&host->sg_miter);
385
386 local_irq_restore(flags);
a406f5a3
PO		 387}
388
389static void sdhci_transfer_pio(struct sdhci_host *host)
390{
391 u32 mask;
392
393 BUG_ON(!host->data);
394
7659150c 395 if (host->blocks == 0)
a406f5a3
PO		 396 return;
397
398 if (host->data->flags & MMC_DATA_READ)
399 mask = SDHCI_DATA_AVAILABLE;
400 else
401 mask = SDHCI_SPACE_AVAILABLE;
402
4a3cba32
PO		 403 /*
404 * Some controllers (JMicron JMB38x) mess up the buffer bits
405 * for transfers < 4 bytes. As long as it is just one block,
406 * we can ignore the bits.
407 */
408 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
409 (host->data->blocks == 1))
410 mask = ~0;
411
4e4141a5 412 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 413 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
414 udelay(100);
415
a406f5a3
PO		 416 if (host->data->flags & MMC_DATA_READ)
417 sdhci_read_block_pio(host);
418 else
419 sdhci_write_block_pio(host);
d129bceb 420
7659150c
PO		 421 host->blocks--;
422 if (host->blocks == 0)
a406f5a3 423 break;
a406f5a3 424 }
d129bceb 425
a406f5a3 426 DBG("PIO transfer complete.\n");
d129bceb
PO		 427}
428
48857d9b 429static int sdhci_pre_dma_transfer(struct sdhci_host *host,
c0999b72 430 struct mmc_data *data, int cookie)
48857d9b
RK		 431{
432 int sg_count;
433
434 if (data->host_cookie == COOKIE_MAPPED) {
435 data->host_cookie = COOKIE_GIVEN;
436 return data->sg_count;
437 }
438
439 WARN_ON(data->host_cookie == COOKIE_GIVEN);
440
441 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
442 data->flags & MMC_DATA_WRITE ?
443 DMA_TO_DEVICE : DMA_FROM_DEVICE);
444
445 if (sg_count == 0)
446 return -ENOSPC;
447
448 data->sg_count = sg_count;
c0999b72 449 data->host_cookie = cookie;
48857d9b
RK		 450
451 return sg_count;
452}
453
2134a922
PO		 454static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
455{
456 local_irq_save(*flags);
482fce99 457 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 458}
459
460static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
461{
482fce99 462 kunmap_atomic(buffer);
2134a922
PO		 463 local_irq_restore(*flags);
464}
465
e57a5f61
AH		 466static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
467 dma_addr_t addr, int len, unsigned cmd)
118cd17d 468{
e57a5f61 469 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 470
e57a5f61 471 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 472 dma_desc->cmd = cpu_to_le16(cmd);
473 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 474 dma_desc->addr_lo = cpu_to_le32((u32)addr);
475
476 if (host->flags & SDHCI_USE_64_BIT_DMA)
477 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 478}
479
b5ffa674
AH		 480static void sdhci_adma_mark_end(void *desc)
481{
e57a5f61 482 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 483
e57a5f61 484 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 485 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 486}
487
60c64762
RK		 488static void sdhci_adma_table_pre(struct sdhci_host *host,
489 struct mmc_data *data, int sg_count)
2134a922 490{
2134a922 491 struct scatterlist *sg;
2134a922 492 unsigned long flags;
acc3ad13
RK		 493 dma_addr_t addr, align_addr;
494 void *desc, *align;
495 char *buffer;
496 int len, offset, i;
2134a922
PO		 497
498 /*
499 * The spec does not specify endianness of descriptor table.
500 * We currently guess that it is LE.
501 */
502
60c64762 503 host->sg_count = sg_count;
2134a922 504
4efaa6fb 505 desc = host->adma_table;
2134a922
PO		 506 align = host->align_buffer;
507
508 align_addr = host->align_addr;
509
510 for_each_sg(data->sg, sg, host->sg_count, i) {
511 addr = sg_dma_address(sg);
512 len = sg_dma_len(sg);
513
514 /*
acc3ad13
RK		 515 * The SDHCI specification states that ADMA addresses must
516 * be 32-bit aligned. If they aren't, then we use a bounce
517 * buffer for the (up to three) bytes that screw up the
2134a922
PO		 518 * alignment.
519 */
04a5ae6f
AH		 520 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
521 SDHCI_ADMA2_MASK;
2134a922
PO		 522 if (offset) {
523 if (data->flags & MMC_DATA_WRITE) {
524 buffer = sdhci_kmap_atomic(sg, &flags);
525 memcpy(align, buffer, offset);
526 sdhci_kunmap_atomic(buffer, &flags);
527 }
528
118cd17d 529 /* tran, valid */
e57a5f61 530 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 531 ADMA2_TRAN_VALID);
2134a922
PO		 532
533 BUG_ON(offset > 65536);
534
04a5ae6f
AH		 535 align += SDHCI_ADMA2_ALIGN;
536 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 537
76fe379a 538 desc += host->desc_sz;
2134a922
PO		 539
540 addr += offset;
541 len -= offset;
542 }
543
2134a922
PO		 544 BUG_ON(len > 65536);
545
347ea32d
AH		 546 if (len) {
547 /* tran, valid */
548 sdhci_adma_write_desc(host, desc, addr, len,
549 ADMA2_TRAN_VALID);
550 desc += host->desc_sz;
551 }
2134a922
PO		 552
553 /*
554 * If this triggers then we have a calculation bug
555 * somewhere. :/
556 */
76fe379a 557 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 558 }
559
70764a90 560 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
acc3ad13 561 /* Mark the last descriptor as the terminating descriptor */
4efaa6fb 562 if (desc != host->adma_table) {
76fe379a 563 desc -= host->desc_sz;
b5ffa674 564 sdhci_adma_mark_end(desc);
70764a90
TA		 565 }
566 } else {
acc3ad13 567 /* Add a terminating entry - nop, end, valid */
e57a5f61 568 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 569 }
2134a922
PO		 570}
571
572static void sdhci_adma_table_post(struct sdhci_host *host,
573 struct mmc_data *data)
574{
2134a922
PO		 575 struct scatterlist *sg;
576 int i, size;
1c3d5f6d 577 void *align;
2134a922
PO		 578 char *buffer;
579 unsigned long flags;
580
47fa9613
RK		 581 if (data->flags & MMC_DATA_READ) {
582 bool has_unaligned = false;
de0b65a7 583
47fa9613
RK		 584 /* Do a quick scan of the SG list for any unaligned mappings */
585 for_each_sg(data->sg, sg, host->sg_count, i)
586 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
587 has_unaligned = true;
588 break;
589 }
2134a922 590
47fa9613
RK		 591 if (has_unaligned) {
592 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
f55c98f7 593 data->sg_len, DMA_FROM_DEVICE);
2134a922 594
47fa9613 595 align = host->align_buffer;
2134a922 596
47fa9613
RK		 597 for_each_sg(data->sg, sg, host->sg_count, i) {
598 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
599 size = SDHCI_ADMA2_ALIGN -
600 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
601
602 buffer = sdhci_kmap_atomic(sg, &flags);
603 memcpy(buffer, align, size);
604 sdhci_kunmap_atomic(buffer, &flags);
2134a922 605
47fa9613
RK		 606 align += SDHCI_ADMA2_ALIGN;
607 }
2134a922
PO		 608 }
609 }
610 }
2134a922
PO		 611}
612
a3c7778f 613static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 614{
1c8cde92 615 u8 count;
a3c7778f 616 struct mmc_data *data = cmd->data;
1c8cde92 617 unsigned target_timeout, current_timeout;
d129bceb 618
ee53ab5d
PO		 619 /*
620 * If the host controller provides us with an incorrect timeout
621 * value, just skip the check and use 0xE. The hardware may take
622 * longer to time out, but that's much better than having a too-short
623 * timeout value.
624 */
11a2f1b7 625 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 626 return 0xE;
e538fbe8 627
a3c7778f 628 /* Unspecified timeout, assume max */
1d4d7744 629 if (!data && !cmd->busy_timeout)
a3c7778f 630 return 0xE;
d129bceb 631
a3c7778f
AW		 632 /* timeout in us */
633 if (!data)
1d4d7744 634 target_timeout = cmd->busy_timeout * 1000;
78a2ca27 635 else {
fafcfda9 636 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
7f05538a
RK		 637 if (host->clock && data->timeout_clks) {
638 unsigned long long val;
639
640 /*
641 * data->timeout_clks is in units of clock cycles.
642 * host->clock is in Hz. target_timeout is in us.
643 * Hence, us = 1000000 * cycles / Hz. Round up.
644 */
645 val = 1000000 * data->timeout_clks;
646 if (do_div(val, host->clock))
647 target_timeout++;
648 target_timeout += val;
649 }
78a2ca27 650 }
81b39802 651
1c8cde92
PO		 652 /*
653 * Figure out needed cycles.
654 * We do this in steps in order to fit inside a 32 bit int.
655 * The first step is the minimum timeout, which will have a
656 * minimum resolution of 6 bits:
657 * (1) 2^13*1000 > 2^22,
658 * (2) host->timeout_clk < 2^16
659 * =>
660 * (1) / (2) > 2^6
661 */
662 count = 0;
663 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
664 while (current_timeout < target_timeout) {
665 count++;
666 current_timeout <<= 1;
667 if (count >= 0xF)
668 break;
669 }
670
671 if (count >= 0xF) {
09eeff52
CB		 672 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
673 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 674 count = 0xE;
675 }
676
ee53ab5d
PO		 677 return count;
678}
679
6aa943ab
AV		 680static void sdhci_set_transfer_irqs(struct sdhci_host *host)
681{
682 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
683 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
684
685 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 686 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 687 else
b537f94c
RK		 688 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
689
690 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
691 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 692}
693
b45e668a 694static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 695{
696 u8 count;
b45e668a
AD		 697
698 if (host->ops->set_timeout) {
699 host->ops->set_timeout(host, cmd);
700 } else {
701 count = sdhci_calc_timeout(host, cmd);
702 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
703 }
704}
705
706static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
707{
2134a922 708 u8 ctrl;
a3c7778f 709 struct mmc_data *data = cmd->data;
ee53ab5d
PO		 710
711 WARN_ON(host->data);
712
b45e668a
AD		 713 if (data || (cmd->flags & MMC_RSP_BUSY))
714 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 715
716 if (!data)
ee53ab5d
PO		 717 return;
718
719 /* Sanity checks */
720 BUG_ON(data->blksz * data->blocks > 524288);
721 BUG_ON(data->blksz > host->mmc->max_blk_size);
722 BUG_ON(data->blocks > 65535);
723
724 host->data = data;
725 host->data_early = 0;
f6a03cbf 726 host->data->bytes_xfered = 0;
ee53ab5d 727
a13abc7b 728 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 729 host->flags |= SDHCI_REQ_USE_DMA;
730
2134a922
PO		 731 /*
732 * FIXME: This doesn't account for merging when mapping the
733 * scatterlist.
734 */
735 if (host->flags & SDHCI_REQ_USE_DMA) {
736 int broken, i;
737 struct scatterlist *sg;
738
739 broken = 0;
740 if (host->flags & SDHCI_USE_ADMA) {
741 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
742 broken = 1;
743 } else {
744 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
745 broken = 1;
746 }
747
748 if (unlikely(broken)) {
749 for_each_sg(data->sg, sg, data->sg_len, i) {
750 if (sg->length & 0x3) {
2e4456f0 751 DBG("Reverting to PIO because of transfer size (%d)\n",
2134a922
PO		 752 sg->length);
753 host->flags &= ~SDHCI_REQ_USE_DMA;
754 break;
755 }
756 }
757 }
c9fddbc4
PO		 758 }
759
760 /*
761 * The assumption here being that alignment is the same after
762 * translation to device address space.
763 */
2134a922
PO		 764 if (host->flags & SDHCI_REQ_USE_DMA) {
765 int broken, i;
766 struct scatterlist *sg;
767
768 broken = 0;
769 if (host->flags & SDHCI_USE_ADMA) {
770 /*
771 * As we use 3 byte chunks to work around
772 * alignment problems, we need to check this
773 * quirk.
774 */
775 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
776 broken = 1;
777 } else {
778 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
779 broken = 1;
780 }
781
782 if (unlikely(broken)) {
783 for_each_sg(data->sg, sg, data->sg_len, i) {
784 if (sg->offset & 0x3) {
2e4456f0 785 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 786 host->flags &= ~SDHCI_REQ_USE_DMA;
787 break;
788 }
789 }
790 }
791 }
792
8f1934ce 793 if (host->flags & SDHCI_REQ_USE_DMA) {
c0999b72 794 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
60c64762
RK		 795
796 if (sg_cnt <= 0) {
797 /*
798 * This only happens when someone fed
799 * us an invalid request.
800 */
801 WARN_ON(1);
802 host->flags &= ~SDHCI_REQ_USE_DMA;
803 } else if (host->flags & SDHCI_USE_ADMA) {
804 sdhci_adma_table_pre(host, data, sg_cnt);
805
806 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
807 if (host->flags & SDHCI_USE_64_BIT_DMA)
808 sdhci_writel(host,
809 (u64)host->adma_addr >> 32,
810 SDHCI_ADMA_ADDRESS_HI);
8f1934ce 811 } else {
60c64762
RK		 812 WARN_ON(sg_cnt != 1);
813 sdhci_writel(host, sg_dma_address(data->sg),
814 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 815 }
816 }
817
2134a922
PO		 818 /*
819 * Always adjust the DMA selection as some controllers
820 * (e.g. JMicron) can't do PIO properly when the selection
821 * is ADMA.
822 */
823 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 824 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 825 ctrl &= ~SDHCI_CTRL_DMA_MASK;
826 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 827 (host->flags & SDHCI_USE_ADMA)) {
828 if (host->flags & SDHCI_USE_64_BIT_DMA)
829 ctrl |= SDHCI_CTRL_ADMA64;
830 else
831 ctrl |= SDHCI_CTRL_ADMA32;
832 } else {
2134a922 833 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 834 }
4e4141a5 835 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 836 }
837
8f1934ce 838 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 839 int flags;
840
841 flags = SG_MITER_ATOMIC;
842 if (host->data->flags & MMC_DATA_READ)
843 flags |= SG_MITER_TO_SG;
844 else
845 flags |= SG_MITER_FROM_SG;
846 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 847 host->blocks = data->blocks;
d129bceb 848 }
c7fa9963 849
6aa943ab
AV		 850 sdhci_set_transfer_irqs(host);
851
f6a03cbf
MV		 852 /* Set the DMA boundary value and block size */
853 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
854 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 855 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 856}
857
858static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 859 struct mmc_command *cmd)
c7fa9963 860{
d3fc5d71 861 u16 mode = 0;
e89d456f 862 struct mmc_data *data = cmd->data;
c7fa9963 863
2b558c13 864 if (data == NULL) {
9b8ffea6
VW		 865 if (host->quirks2 &
866 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
867 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
868 } else {
2b558c13 869 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 870 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
871 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 872 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 873 }
c7fa9963 874 return;
2b558c13 875 }
c7fa9963 876
e538fbe8
PO		 877 WARN_ON(!host->data);
878
d3fc5d71
VY		 879 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
880 mode = SDHCI_TRNS_BLK_CNT_EN;
881
e89d456f 882 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 883 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 884 /*
885 * If we are sending CMD23, CMD12 never gets sent
886 * on successful completion (so no Auto-CMD12).
887 */
85cc1c33
CD		 888 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
889 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 890 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 891 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
892 mode |= SDHCI_TRNS_AUTO_CMD23;
893 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
894 }
c4512f79 895 }
8edf6371 896
c7fa9963
PO		 897 if (data->flags & MMC_DATA_READ)
898 mode |= SDHCI_TRNS_READ;
c9fddbc4 899 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 900 mode |= SDHCI_TRNS_DMA;
901
4e4141a5 902 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 903}
904
905static void sdhci_finish_data(struct sdhci_host *host)
906{
907 struct mmc_data *data;
d129bceb
PO		 908
909 BUG_ON(!host->data);
910
911 data = host->data;
912 host->data = NULL;
913
c9fddbc4 914 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 915 if (host->flags & SDHCI_USE_ADMA)
916 sdhci_adma_table_post(host, data);
f55c98f7
RK		 917
918 if (data->host_cookie == COOKIE_MAPPED) {
919 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
920 (data->flags & MMC_DATA_READ) ?
921 DMA_FROM_DEVICE : DMA_TO_DEVICE);
922 data->host_cookie = COOKIE_UNMAPPED;
2134a922 923 }
d129bceb
PO		 924 }
925
926 /*
c9b74c5b
PO		 927 * The specification states that the block count register must
928 * be updated, but it does not specify at what point in the
929 * data flow. That makes the register entirely useless to read
930 * back so we have to assume that nothing made it to the card
931 * in the event of an error.
d129bceb 932 */
c9b74c5b
PO		 933 if (data->error)
934 data->bytes_xfered = 0;
d129bceb 935 else
c9b74c5b 936 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 937
e89d456f
AW		 938 /*
939 * Need to send CMD12 if -
940 * a) open-ended multiblock transfer (no CMD23)
941 * b) error in multiblock transfer
942 */
943 if (data->stop &&
944 (data->error ||
945 !host->mrq->sbc)) {
946
d129bceb
PO		 947 /*
948 * The controller needs a reset of internal state machines
949 * upon error conditions.
950 */
17b0429d 951 if (data->error) {
03231f9b
RK		 952 sdhci_do_reset(host, SDHCI_RESET_CMD);
953 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 954 }
955
956 sdhci_send_command(host, data->stop);
957 } else
958 tasklet_schedule(&host->finish_tasklet);
959}
960
c0e55129 961void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 962{
963 int flags;
fd2208d7 964 u32 mask;
7cb2c76f 965 unsigned long timeout;
d129bceb
PO		 966
967 WARN_ON(host->cmd);
968
96776200
RK		 969 /* Initially, a command has no error */
970 cmd->error = 0;
971
d129bceb 972 /* Wait max 10 ms */
7cb2c76f 973 timeout = 10;
fd2208d7
PO		 974
975 mask = SDHCI_CMD_INHIBIT;
976 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
977 mask |= SDHCI_DATA_INHIBIT;
978
979 /* We shouldn't wait for data inihibit for stop commands, even
980 though they might use busy signaling */
981 if (host->mrq->data && (cmd == host->mrq->data->stop))
982 mask &= ~SDHCI_DATA_INHIBIT;
983
4e4141a5 984 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 985 if (timeout == 0) {
2e4456f0
MV		 986 pr_err("%s: Controller never released inhibit bit(s).\n",
987 mmc_hostname(host->mmc));
d129bceb 988 sdhci_dumpregs(host);
17b0429d 989 cmd->error = -EIO;
d129bceb
PO		 990 tasklet_schedule(&host->finish_tasklet);
991 return;
992 }
7cb2c76f
PO		 993 timeout--;
994 mdelay(1);
995 }
d129bceb 996
3e1a6892 997 timeout = jiffies;
1d4d7744
UH		 998 if (!cmd->data && cmd->busy_timeout > 9000)
999 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1000 else
1001 timeout += 10 * HZ;
1002 mod_timer(&host->timer, timeout);
d129bceb
PO		 1003
1004 host->cmd = cmd;
e99783a4 1005 host->busy_handle = 0;
d129bceb 1006
a3c7778f 1007 sdhci_prepare_data(host, cmd);
d129bceb 1008
4e4141a5 1009 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1010
e89d456f 1011 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1012
d129bceb 1013 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1014 pr_err("%s: Unsupported response type!\n",
d129bceb 1015 mmc_hostname(host->mmc));
17b0429d 1016 cmd->error = -EINVAL;
d129bceb
PO		 1017 tasklet_schedule(&host->finish_tasklet);
1018 return;
1019 }
1020
1021 if (!(cmd->flags & MMC_RSP_PRESENT))
1022 flags = SDHCI_CMD_RESP_NONE;
1023 else if (cmd->flags & MMC_RSP_136)
1024 flags = SDHCI_CMD_RESP_LONG;
1025 else if (cmd->flags & MMC_RSP_BUSY)
1026 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1027 else
1028 flags = SDHCI_CMD_RESP_SHORT;
1029
1030 if (cmd->flags & MMC_RSP_CRC)
1031 flags |= SDHCI_CMD_CRC;
1032 if (cmd->flags & MMC_RSP_OPCODE)
1033 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1034
1035 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1036 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1037 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1038 flags |= SDHCI_CMD_DATA;
1039
4e4141a5 1040 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1041}
c0e55129 1042EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1043
1044static void sdhci_finish_command(struct sdhci_host *host)
1045{
1046 int i;
1047
1048 BUG_ON(host->cmd == NULL);
1049
1050 if (host->cmd->flags & MMC_RSP_PRESENT) {
1051 if (host->cmd->flags & MMC_RSP_136) {
1052 /* CRC is stripped so we need to do some shifting. */
1053 for (i = 0;i < 4;i++) {
4e4141a5 1054 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1055 SDHCI_RESPONSE + (3-i)*4) << 8;
1056 if (i != 3)
1057 host->cmd->resp[i] |=
4e4141a5 1058 sdhci_readb(host,
d129bceb
PO		 1059 SDHCI_RESPONSE + (3-i)*4-1);
1060 }
1061 } else {
4e4141a5 1062 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1063 }
1064 }
1065
e89d456f
AW		 1066 /* Finished CMD23, now send actual command. */
1067 if (host->cmd == host->mrq->sbc) {
1068 host->cmd = NULL;
1069 sdhci_send_command(host, host->mrq->cmd);
1070 } else {
e538fbe8 1071
e89d456f
AW		 1072 /* Processed actual command. */
1073 if (host->data && host->data_early)
1074 sdhci_finish_data(host);
d129bceb 1075
e89d456f
AW		 1076 if (!host->cmd->data)
1077 tasklet_schedule(&host->finish_tasklet);
1078
1079 host->cmd = NULL;
1080 }
d129bceb
PO		 1081}
1082
52983382
KL		 1083static u16 sdhci_get_preset_value(struct sdhci_host *host)
1084{
d975f121 1085 u16 preset = 0;
52983382 1086
d975f121
RK		 1087 switch (host->timing) {
1088 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1089 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1090 break;
d975f121 1091 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1092 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1093 break;
d975f121 1094 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1095 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1096 break;
d975f121
RK		 1097 case MMC_TIMING_UHS_SDR104:
1098 case MMC_TIMING_MMC_HS200:
52983382
KL		 1099 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1100 break;
d975f121 1101 case MMC_TIMING_UHS_DDR50:
0dafa60e 1102 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1103 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1104 break;
e9fb05d5
AH		 1105 case MMC_TIMING_MMC_HS400:
1106 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1107 break;
52983382
KL		 1108 default:
1109 pr_warn("%s: Invalid UHS-I mode selected\n",
1110 mmc_hostname(host->mmc));
1111 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1112 break;
1113 }
1114 return preset;
1115}
1116
1771059c 1117void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1118{
c3ed3877 1119 int div = 0; /* Initialized for compiler warning */
df16219f 1120 int real_div = div, clk_mul = 1;
c3ed3877 1121 u16 clk = 0;
7cb2c76f 1122 unsigned long timeout;
5497159c 1123 bool switch_base_clk = false;
d129bceb 1124
1650d0c7
RK		 1125 host->mmc->actual_clock = 0;
1126
4e4141a5 1127 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
af951761 1128 if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1129 mdelay(1);
d129bceb
PO		 1130
1131 if (clock == 0)
373073ef 1132 return;
d129bceb 1133
85105c53 1134 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1135 if (host->preset_enabled) {
52983382
KL		 1136 u16 pre_val;
1137
1138 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1139 pre_val = sdhci_get_preset_value(host);
1140 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1141 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1142 if (host->clk_mul &&
1143 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1144 clk = SDHCI_PROG_CLOCK_MODE;
1145 real_div = div + 1;
1146 clk_mul = host->clk_mul;
1147 } else {
1148 real_div = max_t(int, 1, div << 1);
1149 }
1150 goto clock_set;
1151 }
1152
c3ed3877
AN		 1153 /*
1154 * Check if the Host Controller supports Programmable Clock
1155 * Mode.
1156 */
1157 if (host->clk_mul) {
52983382
KL		 1158 for (div = 1; div <= 1024; div++) {
1159 if ((host->max_clk * host->clk_mul / div)
1160 <= clock)
1161 break;
1162 }
5497159c 1163 if ((host->max_clk * host->clk_mul / div) <= clock) {
1164 /*
1165 * Set Programmable Clock Mode in the Clock
1166 * Control register.
1167 */
1168 clk = SDHCI_PROG_CLOCK_MODE;
1169 real_div = div;
1170 clk_mul = host->clk_mul;
1171 div--;
1172 } else {
1173 /*
1174 * Divisor can be too small to reach clock
1175 * speed requirement. Then use the base clock.
1176 */
1177 switch_base_clk = true;
1178 }
1179 }
1180
1181 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1182 /* Version 3.00 divisors must be a multiple of 2. */
1183 if (host->max_clk <= clock)
1184 div = 1;
1185 else {
1186 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1187 div += 2) {
1188 if ((host->max_clk / div) <= clock)
1189 break;
1190 }
85105c53 1191 }
df16219f 1192 real_div = div;
c3ed3877 1193 div >>= 1;
d1955c3a
SG		 1194 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1195 && !div && host->max_clk <= 25000000)
1196 div = 1;
85105c53
ZG		 1197 }
1198 } else {
1199 /* Version 2.00 divisors must be a power of 2. */
0397526d 1200 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1201 if ((host->max_clk / div) <= clock)
1202 break;
1203 }
df16219f 1204 real_div = div;
c3ed3877 1205 div >>= 1;
d129bceb 1206 }
d129bceb 1207
52983382 1208clock_set:
03d6f5ff 1209 if (real_div)
df16219f 1210 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1211 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1212 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1213 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1214 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1215 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1216
27f6cb16
CB		 1217 /* Wait max 20 ms */
1218 timeout = 20;
4e4141a5 1219 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1220 & SDHCI_CLOCK_INT_STABLE)) {
1221 if (timeout == 0) {
2e4456f0
MV		 1222 pr_err("%s: Internal clock never stabilised.\n",
1223 mmc_hostname(host->mmc));
d129bceb
PO		 1224 sdhci_dumpregs(host);
1225 return;
1226 }
7cb2c76f
PO		 1227 timeout--;
1228 mdelay(1);
1229 }
d129bceb
PO		 1230
1231 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1232 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1233}
1771059c 1234EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1235
24fbb3ca
RK		 1236static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1237 unsigned short vdd)
146ad66e 1238{
3a48edc4 1239 struct mmc_host *mmc = host->mmc;
8364248a 1240 u8 pwr = 0;
146ad66e 1241
24fbb3ca
RK		 1242 if (mode != MMC_POWER_OFF) {
1243 switch (1 << vdd) {
ae628903
PO		 1244 case MMC_VDD_165_195:
1245 pwr = SDHCI_POWER_180;
1246 break;
1247 case MMC_VDD_29_30:
1248 case MMC_VDD_30_31:
1249 pwr = SDHCI_POWER_300;
1250 break;
1251 case MMC_VDD_32_33:
1252 case MMC_VDD_33_34:
1253 pwr = SDHCI_POWER_330;
1254 break;
1255 default:
9d5de93f
AH		 1256 WARN(1, "%s: Invalid vdd %#x\n",
1257 mmc_hostname(host->mmc), vdd);
1258 break;
ae628903
PO		 1259 }
1260 }
1261
1262 if (host->pwr == pwr)
e921a8b6 1263 return;
146ad66e 1264
ae628903
PO		 1265 host->pwr = pwr;
1266
1267 if (pwr == 0) {
4e4141a5 1268 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1269 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1270 sdhci_runtime_pm_bus_off(host);
24fbb3ca 1271 vdd = 0;
e921a8b6
RK		 1272 } else {
1273 /*
1274 * Spec says that we should clear the power reg before setting
1275 * a new value. Some controllers don't seem to like this though.
1276 */
1277 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1278 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1279
e921a8b6
RK		 1280 /*
1281 * At least the Marvell CaFe chip gets confused if we set the
1282 * voltage and set turn on power at the same time, so set the
1283 * voltage first.
1284 */
1285 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1286 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1287
e921a8b6 1288 pwr |= SDHCI_POWER_ON;
146ad66e 1289
e921a8b6 1290 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1291
e921a8b6
RK		 1292 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1293 sdhci_runtime_pm_bus_on(host);
f0710a55 1294
e921a8b6
RK		 1295 /*
1296 * Some controllers need an extra 10ms delay of 10ms before
1297 * they can apply clock after applying power
1298 */
1299 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1300 mdelay(10);
1301 }
918f4cbd
JZ		 1302
1303 if (!IS_ERR(mmc->supply.vmmc)) {
1304 spin_unlock_irq(&host->lock);
1305 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1306 spin_lock_irq(&host->lock);
1307 }
146ad66e
PO		 1308}
1309
d129bceb
PO		 1310/*****************************************************************************\
1311 * *
1312 * MMC callbacks *
1313 * *
1314\*****************************************************************************/
1315
1316static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1317{
1318 struct sdhci_host *host;
505a8680 1319 int present;
d129bceb
PO		 1320 unsigned long flags;
1321
1322 host = mmc_priv(mmc);
1323
66fd8ad5
AH		 1324 sdhci_runtime_pm_get(host);
1325
04e079cf 1326 /* Firstly check card presence */
8d28b7a7 1327 present = mmc->ops->get_cd(mmc);
2836766a 1328
d129bceb
PO		 1329 spin_lock_irqsave(&host->lock, flags);
1330
1331 WARN_ON(host->mrq != NULL);
1332
f9134319 1333#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1334 sdhci_activate_led(host);
2f730fec 1335#endif
e89d456f
AW		 1336
1337 /*
1338 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1339 * requests if Auto-CMD12 is enabled.
1340 */
1341 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1342 if (mrq->stop) {
1343 mrq->data->stop = NULL;
1344 mrq->stop = NULL;
1345 }
1346 }
d129bceb
PO		 1347
1348 host->mrq = mrq;
1349
68d1fb7e 1350 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1351 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1352 tasklet_schedule(&host->finish_tasklet);
cf2b5eea 1353 } else {
8edf6371 1354 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1355 sdhci_send_command(host, mrq->sbc);
1356 else
1357 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1358 }
d129bceb 1359
5f25a66f 1360 mmiowb();
d129bceb
PO		 1361 spin_unlock_irqrestore(&host->lock, flags);
1362}
1363
2317f56c
RK		 1364void sdhci_set_bus_width(struct sdhci_host *host, int width)
1365{
1366 u8 ctrl;
1367
1368 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1369 if (width == MMC_BUS_WIDTH_8) {
1370 ctrl &= ~SDHCI_CTRL_4BITBUS;
1371 if (host->version >= SDHCI_SPEC_300)
1372 ctrl |= SDHCI_CTRL_8BITBUS;
1373 } else {
1374 if (host->version >= SDHCI_SPEC_300)
1375 ctrl &= ~SDHCI_CTRL_8BITBUS;
1376 if (width == MMC_BUS_WIDTH_4)
1377 ctrl |= SDHCI_CTRL_4BITBUS;
1378 else
1379 ctrl &= ~SDHCI_CTRL_4BITBUS;
1380 }
1381 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1382}
1383EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1384
96d7b78c
RK		 1385void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1386{
1387 u16 ctrl_2;
1388
1389 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1390 /* Select Bus Speed Mode for host */
1391 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1392 if ((timing == MMC_TIMING_MMC_HS200) ||
1393 (timing == MMC_TIMING_UHS_SDR104))
1394 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1395 else if (timing == MMC_TIMING_UHS_SDR12)
1396 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1397 else if (timing == MMC_TIMING_UHS_SDR25)
1398 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1399 else if (timing == MMC_TIMING_UHS_SDR50)
1400 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1401 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1402 (timing == MMC_TIMING_MMC_DDR52))
1403 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1404 else if (timing == MMC_TIMING_MMC_HS400)
1405 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1406 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1407}
1408EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1409
66fd8ad5 1410static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1411{
d129bceb
PO		 1412 unsigned long flags;
1413 u8 ctrl;
3a48edc4 1414 struct mmc_host *mmc = host->mmc;
d129bceb 1415
d129bceb
PO		 1416 spin_lock_irqsave(&host->lock, flags);
1417
ceb6143b
AH		 1418 if (host->flags & SDHCI_DEVICE_DEAD) {
1419 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1420 if (!IS_ERR(mmc->supply.vmmc) &&
1421 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1422 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1423 return;
1424 }
1e72859e 1425
d129bceb
PO		 1426 /*
1427 * Reset the chip on each power off.
1428 * Should clear out any weird states.
1429 */
1430 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1431 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1432 sdhci_reinit(host);
d129bceb
PO		 1433 }
1434
52983382 1435 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1436 (ios->power_mode == MMC_POWER_UP) &&
1437 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1438 sdhci_enable_preset_value(host, false);
1439
373073ef 1440 if (!ios->clock || ios->clock != host->clock) {
1771059c 1441 host->ops->set_clock(host, ios->clock);
373073ef 1442 host->clock = ios->clock;
03d6f5ff
AD		 1443
1444 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1445 host->clock) {
1446 host->timeout_clk = host->mmc->actual_clock ?
1447 host->mmc->actual_clock / 1000 :
1448 host->clock / 1000;
1449 host->mmc->max_busy_timeout =
1450 host->ops->get_max_timeout_count ?
1451 host->ops->get_max_timeout_count(host) :
1452 1 << 27;
1453 host->mmc->max_busy_timeout /= host->timeout_clk;
1454 }
373073ef 1455 }
d129bceb 1456
24fbb3ca 1457 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1458
643a81ff
PR		 1459 if (host->ops->platform_send_init_74_clocks)
1460 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1461
2317f56c 1462 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1463
15ec4461 1464 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1465
3ab9c8da
PR		 1466 if ((ios->timing == MMC_TIMING_SD_HS ||
1467 ios->timing == MMC_TIMING_MMC_HS)
1468 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1469 ctrl |= SDHCI_CTRL_HISPD;
1470 else
1471 ctrl &= ~SDHCI_CTRL_HISPD;
1472
d6d50a15 1473 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1474 u16 clk, ctrl_2;
49c468fc
AN		 1475
1476 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1477 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1478 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1479 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1480 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1481 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1482 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1483 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1484 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1485
da91a8f9 1486 if (!host->preset_enabled) {
758535c4 1487 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1488 /*
1489 * We only need to set Driver Strength if the
1490 * preset value enable is not set.
1491 */
da91a8f9 1492 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1493 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1494 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1495 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1496 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1497 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1498 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1499 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1500 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1501 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1502 else {
2e4456f0
MV		 1503 pr_warn("%s: invalid driver type, default to driver type B\n",
1504 mmc_hostname(mmc));
43e943a0
PG		 1505 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1506 }
d6d50a15
AN		 1507
1508 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1509 } else {
1510 /*
1511 * According to SDHC Spec v3.00, if the Preset Value
1512 * Enable in the Host Control 2 register is set, we
1513 * need to reset SD Clock Enable before changing High
1514 * Speed Enable to avoid generating clock gliches.
1515 */
758535c4
AN		 1516
1517 /* Reset SD Clock Enable */
1518 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1519 clk &= ~SDHCI_CLOCK_CARD_EN;
1520 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1521
1522 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1523
1524 /* Re-enable SD Clock */
1771059c 1525 host->ops->set_clock(host, host->clock);
d6d50a15 1526 }
49c468fc 1527
49c468fc
AN		 1528 /* Reset SD Clock Enable */
1529 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1530 clk &= ~SDHCI_CLOCK_CARD_EN;
1531 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1532
96d7b78c 1533 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1534 host->timing = ios->timing;
49c468fc 1535
52983382
KL		 1536 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1537 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1538 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1539 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1540 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 1541 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1542 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 1543 u16 preset;
1544
1545 sdhci_enable_preset_value(host, true);
1546 preset = sdhci_get_preset_value(host);
1547 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1548 >> SDHCI_PRESET_DRV_SHIFT;
1549 }
1550
49c468fc 1551 /* Re-enable SD Clock */
1771059c 1552 host->ops->set_clock(host, host->clock);
758535c4
AN		 1553 } else
1554 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1555
b8352260
LD		 1556 /*
1557 * Some (ENE) controllers go apeshit on some ios operation,
1558 * signalling timeout and CRC errors even on CMD0. Resetting
1559 * it on each ios seems to solve the problem.
1560 */
c63705e1 1561 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1562 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1563
5f25a66f 1564 mmiowb();
d129bceb
PO		 1565 spin_unlock_irqrestore(&host->lock, flags);
1566}
1567
66fd8ad5
AH		 1568static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1569{
1570 struct sdhci_host *host = mmc_priv(mmc);
1571
1572 sdhci_runtime_pm_get(host);
1573 sdhci_do_set_ios(host, ios);
1574 sdhci_runtime_pm_put(host);
1575}
1576
94144a46
KL		 1577static int sdhci_do_get_cd(struct sdhci_host *host)
1578{
1579 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1580
1581 if (host->flags & SDHCI_DEVICE_DEAD)
1582 return 0;
1583
88af5655
II		 1584 /* If nonremovable, assume that the card is always present. */
1585 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
94144a46
KL		 1586 return 1;
1587
88af5655
II		 1588 /*
1589 * Try slot gpio detect, if defined it take precedence
1590 * over build in controller functionality
1591 */
94144a46
KL		 1592 if (!IS_ERR_VALUE(gpio_cd))
1593 return !!gpio_cd;
1594
88af5655
II		 1595 /* If polling, assume that the card is always present. */
1596 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1597 return 1;
1598
94144a46
KL		 1599 /* Host native card detect */
1600 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1601}
1602
1603static int sdhci_get_cd(struct mmc_host *mmc)
1604{
1605 struct sdhci_host *host = mmc_priv(mmc);
1606 int ret;
1607
1608 sdhci_runtime_pm_get(host);
1609 ret = sdhci_do_get_cd(host);
1610 sdhci_runtime_pm_put(host);
1611 return ret;
1612}
1613
66fd8ad5 1614static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1615{
d129bceb 1616 unsigned long flags;
2dfb579c 1617 int is_readonly;
d129bceb 1618
d129bceb
PO		 1619 spin_lock_irqsave(&host->lock, flags);
1620
1e72859e 1621 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1622 is_readonly = 0;
1623 else if (host->ops->get_ro)
1624 is_readonly = host->ops->get_ro(host);
1e72859e 1625 else
2dfb579c
WS		 1626 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1627 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1628
1629 spin_unlock_irqrestore(&host->lock, flags);
1630
2dfb579c
WS		 1631 /* This quirk needs to be replaced by a callback-function later */
1632 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1633 !is_readonly : is_readonly;
d129bceb
PO		 1634}
1635
82b0e23a
TI		 1636#define SAMPLE_COUNT 5
1637
66fd8ad5 1638static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1639{
82b0e23a
TI		 1640 int i, ro_count;
1641
82b0e23a 1642 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1643 return sdhci_check_ro(host);
82b0e23a
TI		 1644
1645 ro_count = 0;
1646 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1647 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1648 if (++ro_count > SAMPLE_COUNT / 2)
1649 return 1;
1650 }
1651 msleep(30);
1652 }
1653 return 0;
1654}
1655
20758b66
AH		 1656static void sdhci_hw_reset(struct mmc_host *mmc)
1657{
1658 struct sdhci_host *host = mmc_priv(mmc);
1659
1660 if (host->ops && host->ops->hw_reset)
1661 host->ops->hw_reset(host);
1662}
1663
66fd8ad5 1664static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1665{
66fd8ad5
AH		 1666 struct sdhci_host *host = mmc_priv(mmc);
1667 int ret;
f75979b7 1668
66fd8ad5
AH		 1669 sdhci_runtime_pm_get(host);
1670 ret = sdhci_do_get_ro(host);
1671 sdhci_runtime_pm_put(host);
1672 return ret;
1673}
f75979b7 1674
66fd8ad5
AH		 1675static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1676{
be138554 1677 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1678 if (enable)
b537f94c 1679 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1680 else
b537f94c
RK		 1681 host->ier &= ~SDHCI_INT_CARD_INT;
1682
1683 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1684 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1685 mmiowb();
1686 }
66fd8ad5
AH		 1687}
1688
1689static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1690{
1691 struct sdhci_host *host = mmc_priv(mmc);
1692 unsigned long flags;
f75979b7 1693
ef104333
RK		 1694 sdhci_runtime_pm_get(host);
1695
66fd8ad5 1696 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1697 if (enable)
1698 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1699 else
1700 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1701
66fd8ad5 1702 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1703 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1704
1705 sdhci_runtime_pm_put(host);
f75979b7
PO		 1706}
1707
20b92a30 1708static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1709 struct mmc_ios *ios)
f2119df6 1710{
3a48edc4 1711 struct mmc_host *mmc = host->mmc;
20b92a30 1712 u16 ctrl;
6231f3de 1713 int ret;
f2119df6 1714
20b92a30
KL		 1715 /*
1716 * Signal Voltage Switching is only applicable for Host Controllers
1717 * v3.00 and above.
1718 */
1719 if (host->version < SDHCI_SPEC_300)
1720 return 0;
6231f3de 1721
f2119df6 1722 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1723
21f5998f 1724 switch (ios->signal_voltage) {
20b92a30
KL		 1725 case MMC_SIGNAL_VOLTAGE_330:
1726 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1727 ctrl &= ~SDHCI_CTRL_VDD_180;
1728 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1729
3a48edc4
TK		 1730 if (!IS_ERR(mmc->supply.vqmmc)) {
1731 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1732 3600000);
20b92a30 1733 if (ret) {
6606110d
JP		 1734 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1735 mmc_hostname(mmc));
20b92a30
KL		 1736 return -EIO;
1737 }
1738 }
1739 /* Wait for 5ms */
1740 usleep_range(5000, 5500);
f2119df6 1741
20b92a30
KL		 1742 /* 3.3V regulator output should be stable within 5 ms */
1743 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1744 if (!(ctrl & SDHCI_CTRL_VDD_180))
1745 return 0;
6231f3de 1746
6606110d
JP		 1747 pr_warn("%s: 3.3V regulator output did not became stable\n",
1748 mmc_hostname(mmc));
20b92a30
KL		 1749
1750 return -EAGAIN;
1751 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1752 if (!IS_ERR(mmc->supply.vqmmc)) {
1753 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1754 1700000, 1950000);
1755 if (ret) {
6606110d
JP		 1756 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1757 mmc_hostname(mmc));
20b92a30
KL		 1758 return -EIO;
1759 }
1760 }
6231f3de 1761
6231f3de
PR		 1762 /*
1763 * Enable 1.8V Signal Enable in the Host Control2
1764 * register
1765 */
20b92a30
KL		 1766 ctrl |= SDHCI_CTRL_VDD_180;
1767 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1768
9d967a61
VY		 1769 /* Some controller need to do more when switching */
1770 if (host->ops->voltage_switch)
1771 host->ops->voltage_switch(host);
1772
20b92a30
KL		 1773 /* 1.8V regulator output should be stable within 5 ms */
1774 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1775 if (ctrl & SDHCI_CTRL_VDD_180)
1776 return 0;
f2119df6 1777
6606110d
JP		 1778 pr_warn("%s: 1.8V regulator output did not became stable\n",
1779 mmc_hostname(mmc));
f2119df6 1780
20b92a30
KL		 1781 return -EAGAIN;
1782 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1783 if (!IS_ERR(mmc->supply.vqmmc)) {
1784 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1785 1300000);
20b92a30 1786 if (ret) {
6606110d
JP		 1787 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1788 mmc_hostname(mmc));
20b92a30 1789 return -EIO;
f2119df6
AN		 1790 }
1791 }
6231f3de 1792 return 0;
20b92a30 1793 default:
f2119df6
AN		 1794 /* No signal voltage switch required */
1795 return 0;
20b92a30 1796 }
f2119df6
AN		 1797}
1798
66fd8ad5 1799static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1800 struct mmc_ios *ios)
66fd8ad5
AH		 1801{
1802 struct sdhci_host *host = mmc_priv(mmc);
1803 int err;
1804
1805 if (host->version < SDHCI_SPEC_300)
1806 return 0;
1807 sdhci_runtime_pm_get(host);
21f5998f 1808 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1809 sdhci_runtime_pm_put(host);
1810 return err;
1811}
1812
20b92a30
KL		 1813static int sdhci_card_busy(struct mmc_host *mmc)
1814{
1815 struct sdhci_host *host = mmc_priv(mmc);
1816 u32 present_state;
1817
1818 sdhci_runtime_pm_get(host);
1819 /* Check whether DAT[3:0] is 0000 */
1820 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1821 sdhci_runtime_pm_put(host);
1822
1823 return !(present_state & SDHCI_DATA_LVL_MASK);
1824}
1825
b5540ce1
AH		 1826static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1827{
1828 struct sdhci_host *host = mmc_priv(mmc);
1829 unsigned long flags;
1830
1831 spin_lock_irqsave(&host->lock, flags);
1832 host->flags |= SDHCI_HS400_TUNING;
1833 spin_unlock_irqrestore(&host->lock, flags);
1834
1835 return 0;
1836}
1837
069c9f14 1838static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1839{
4b6f37d3 1840 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1841 u16 ctrl;
b513ea25 1842 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1843 int err = 0;
2b35bd83 1844 unsigned long flags;
38e40bf5 1845 unsigned int tuning_count = 0;
b5540ce1 1846 bool hs400_tuning;
b513ea25 1847
66fd8ad5 1848 sdhci_runtime_pm_get(host);
2b35bd83 1849 spin_lock_irqsave(&host->lock, flags);
b513ea25 1850
b5540ce1
AH		 1851 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1852 host->flags &= ~SDHCI_HS400_TUNING;
1853
38e40bf5
AH		 1854 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1855 tuning_count = host->tuning_count;
1856
b513ea25 1857 /*
9faac7b9
WY		 1858 * The Host Controller needs tuning in case of SDR104 and DDR50
1859 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1860 * the Capabilities register.
069c9f14
G		 1861 * If the Host Controller supports the HS200 mode then the
1862 * tuning function has to be executed.
b513ea25 1863 */
4b6f37d3 1864 switch (host->timing) {
b5540ce1 1865 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1866 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1867 err = -EINVAL;
1868 goto out_unlock;
1869
4b6f37d3 1870 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1871 /*
1872 * Periodic re-tuning for HS400 is not expected to be needed, so
1873 * disable it here.
1874 */
1875 if (hs400_tuning)
1876 tuning_count = 0;
1877 break;
1878
4b6f37d3 1879 case MMC_TIMING_UHS_SDR104:
9faac7b9 1880 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 1881 break;
1882
1883 case MMC_TIMING_UHS_SDR50:
1884 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1885 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1886 break;
1887 /* FALLTHROUGH */
1888
1889 default:
d519c863 1890 goto out_unlock;
b513ea25
AN		 1891 }
1892
45251812 1893 if (host->ops->platform_execute_tuning) {
2b35bd83 1894 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1895 err = host->ops->platform_execute_tuning(host, opcode);
1896 sdhci_runtime_pm_put(host);
1897 return err;
1898 }
1899
4b6f37d3
RK		 1900 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1901 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 1902 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1903 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 1904 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1905
1906 /*
1907 * As per the Host Controller spec v3.00, tuning command
1908 * generates Buffer Read Ready interrupt, so enable that.
1909 *
1910 * Note: The spec clearly says that when tuning sequence
1911 * is being performed, the controller does not generate
1912 * interrupts other than Buffer Read Ready interrupt. But
1913 * to make sure we don't hit a controller bug, we _only_
1914 * enable Buffer Read Ready interrupt here.
1915 */
b537f94c
RK		 1916 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1917 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1918
1919 /*
1920 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1921 * of loops reaches 40 times or a timeout of 150ms occurs.
1922 */
b513ea25
AN		 1923 do {
1924 struct mmc_command cmd = {0};
66fd8ad5 1925 struct mmc_request mrq = {NULL};
b513ea25 1926
069c9f14 1927 cmd.opcode = opcode;
b513ea25
AN		 1928 cmd.arg = 0;
1929 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1930 cmd.retries = 0;
1931 cmd.data = NULL;
1932 cmd.error = 0;
1933
7ce45e95
AC		 1934 if (tuning_loop_counter-- == 0)
1935 break;
1936
b513ea25
AN		 1937 mrq.cmd = &cmd;
1938 host->mrq = &mrq;
1939
1940 /*
1941 * In response to CMD19, the card sends 64 bytes of tuning
1942 * block to the Host Controller. So we set the block size
1943 * to 64 here.
1944 */
069c9f14
G		 1945 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1946 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1947 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1948 SDHCI_BLOCK_SIZE);
1949 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1950 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1951 SDHCI_BLOCK_SIZE);
1952 } else {
1953 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1954 SDHCI_BLOCK_SIZE);
1955 }
b513ea25
AN		 1956
1957 /*
1958 * The tuning block is sent by the card to the host controller.
1959 * So we set the TRNS_READ bit in the Transfer Mode register.
1960 * This also takes care of setting DMA Enable and Multi Block
1961 * Select in the same register to 0.
1962 */
1963 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1964
1965 sdhci_send_command(host, &cmd);
1966
1967 host->cmd = NULL;
1968 host->mrq = NULL;
1969
2b35bd83 1970 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1971 /* Wait for Buffer Read Ready interrupt */
1972 wait_event_interruptible_timeout(host->buf_ready_int,
1973 (host->tuning_done == 1),
1974 msecs_to_jiffies(50));
2b35bd83 1975 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1976
1977 if (!host->tuning_done) {
2e4456f0 1978 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
b513ea25
AN		 1979 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1980 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1981 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1982 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1983
1984 err = -EIO;
1985 goto out;
1986 }
1987
1988 host->tuning_done = 0;
1989
1990 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 1991
1992 /* eMMC spec does not require a delay between tuning cycles */
1993 if (opcode == MMC_SEND_TUNING_BLOCK)
1994 mdelay(1);
b513ea25
AN		 1995 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1996
1997 /*
1998 * The Host Driver has exhausted the maximum number of loops allowed,
1999 * so use fixed sampling frequency.
2000 */
7ce45e95 2001 if (tuning_loop_counter < 0) {
b513ea25
AN		 2002 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2003 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2004 }
2005 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2e4456f0 2006 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
114f2bf6 2007 err = -EIO;
b513ea25
AN		 2008 }
2009
2010out:
38e40bf5 2011 if (tuning_count) {
66c39dfc
AH		 2012 /*
2013 * In case tuning fails, host controllers which support
2014 * re-tuning can try tuning again at a later time, when the
2015 * re-tuning timer expires. So for these controllers, we
2016 * return 0. Since there might be other controllers who do not
2017 * have this capability, we return error for them.
2018 */
2019 err = 0;
cf2b5eea
AN		 2020 }
2021
66c39dfc 2022 host->mmc->retune_period = err ? 0 : tuning_count;
cf2b5eea 2023
b537f94c
RK		 2024 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2025 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2026out_unlock:
2b35bd83 2027 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2028 sdhci_runtime_pm_put(host);
b513ea25
AN		 2029
2030 return err;
2031}
2032
cb849648
AH		 2033static int sdhci_select_drive_strength(struct mmc_card *card,
2034 unsigned int max_dtr, int host_drv,
2035 int card_drv, int *drv_type)
2036{
2037 struct sdhci_host *host = mmc_priv(card->host);
2038
2039 if (!host->ops->select_drive_strength)
2040 return 0;
2041
2042 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2043 card_drv, drv_type);
2044}
52983382
KL		 2045
2046static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2047{
4d55c5a1
AN		 2048 /* Host Controller v3.00 defines preset value registers */
2049 if (host->version < SDHCI_SPEC_300)
2050 return;
2051
4d55c5a1
AN		 2052 /*
2053 * We only enable or disable Preset Value if they are not already
2054 * enabled or disabled respectively. Otherwise, we bail out.
2055 */
da91a8f9
RK		 2056 if (host->preset_enabled != enable) {
2057 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2058
2059 if (enable)
2060 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2061 else
2062 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2063
4d55c5a1 2064 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2065
2066 if (enable)
2067 host->flags |= SDHCI_PV_ENABLED;
2068 else
2069 host->flags &= ~SDHCI_PV_ENABLED;
2070
2071 host->preset_enabled = enable;
4d55c5a1 2072 }
66fd8ad5
AH		 2073}
2074
348487cb
HC		 2075static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2076 int err)
2077{
2078 struct sdhci_host *host = mmc_priv(mmc);
2079 struct mmc_data *data = mrq->data;
2080
771a3dc2
RK		 2081 if (data->host_cookie == COOKIE_GIVEN ||
2082 data->host_cookie == COOKIE_MAPPED)
2083 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2084 data->flags & MMC_DATA_WRITE ?
2085 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2086
2087 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2088}
2089
348487cb
HC		 2090static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2091 bool is_first_req)
2092{
2093 struct sdhci_host *host = mmc_priv(mmc);
2094
d31911b9 2095 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2096
2097 if (host->flags & SDHCI_REQ_USE_DMA)
c0999b72 2098 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_MAPPED);
348487cb
HC		 2099}
2100
71e69211 2101static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2102{
71e69211 2103 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2104 unsigned long flags;
2836766a 2105 int present;
d129bceb 2106
722e1280
CD		 2107 /* First check if client has provided their own card event */
2108 if (host->ops->card_event)
2109 host->ops->card_event(host);
2110
2836766a
KK		 2111 present = sdhci_do_get_cd(host);
2112
d129bceb
PO		 2113 spin_lock_irqsave(&host->lock, flags);
2114
66fd8ad5 2115 /* Check host->mrq first in case we are runtime suspended */
2836766a 2116 if (host->mrq && !present) {
a3c76eb9 2117 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2118 mmc_hostname(host->mmc));
a3c76eb9 2119 pr_err("%s: Resetting controller.\n",
66fd8ad5 2120 mmc_hostname(host->mmc));
d129bceb 2121
03231f9b
RK		 2122 sdhci_do_reset(host, SDHCI_RESET_CMD);
2123 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2124
66fd8ad5
AH		 2125 host->mrq->cmd->error = -ENOMEDIUM;
2126 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2127 }
2128
2129 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2130}
2131
2132static const struct mmc_host_ops sdhci_ops = {
2133 .request = sdhci_request,
348487cb
HC		 2134 .post_req = sdhci_post_req,
2135 .pre_req = sdhci_pre_req,
71e69211 2136 .set_ios = sdhci_set_ios,
94144a46 2137 .get_cd = sdhci_get_cd,
71e69211
GL		 2138 .get_ro = sdhci_get_ro,
2139 .hw_reset = sdhci_hw_reset,
2140 .enable_sdio_irq = sdhci_enable_sdio_irq,
2141 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2142 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2143 .execute_tuning = sdhci_execute_tuning,
cb849648 2144 .select_drive_strength = sdhci_select_drive_strength,
71e69211 2145 .card_event = sdhci_card_event,
20b92a30 2146 .card_busy = sdhci_card_busy,
71e69211
GL		 2147};
2148
2149/*****************************************************************************\
2150 * *
2151 * Tasklets *
2152 * *
2153\*****************************************************************************/
2154
d129bceb
PO		 2155static void sdhci_tasklet_finish(unsigned long param)
2156{
2157 struct sdhci_host *host;
2158 unsigned long flags;
2159 struct mmc_request *mrq;
2160
2161 host = (struct sdhci_host*)param;
2162
66fd8ad5
AH		 2163 spin_lock_irqsave(&host->lock, flags);
2164
0c9c99a7
CB		 2165 /*
2166 * If this tasklet gets rescheduled while running, it will
2167 * be run again afterwards but without any active request.
2168 */
66fd8ad5
AH		 2169 if (!host->mrq) {
2170 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2171 return;
66fd8ad5 2172 }
d129bceb
PO		 2173
2174 del_timer(&host->timer);
2175
2176 mrq = host->mrq;
2177
054cedff
RK		 2178 /*
2179 * Always unmap the data buffers if they were mapped by
2180 * sdhci_prepare_data() whenever we finish with a request.
2181 * This avoids leaking DMA mappings on error.
2182 */
2183 if (host->flags & SDHCI_REQ_USE_DMA) {
2184 struct mmc_data *data = mrq->data;
2185
2186 if (data && data->host_cookie == COOKIE_MAPPED) {
2187 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2188 (data->flags & MMC_DATA_READ) ?
2189 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2190 data->host_cookie = COOKIE_UNMAPPED;
2191 }
2192 }
2193
d129bceb
PO		 2194 /*
2195 * The controller needs a reset of internal state machines
2196 * upon error conditions.
2197 */
1e72859e 2198 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2199 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2200 (mrq->sbc && mrq->sbc->error) ||
2201 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2202 (mrq->data->stop && mrq->data->stop->error))) ||
2203 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2204
2205 /* Some controllers need this kick or reset won't work here */
8213af3b 2206 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2207 /* This is to force an update */
1771059c 2208 host->ops->set_clock(host, host->clock);
645289dc
PO		 2209
2210 /* Spec says we should do both at the same time, but Ricoh
2211 controllers do not like that. */
03231f9b
RK		 2212 sdhci_do_reset(host, SDHCI_RESET_CMD);
2213 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2214 }
2215
2216 host->mrq = NULL;
2217 host->cmd = NULL;
2218 host->data = NULL;
2219
f9134319 2220#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2221 sdhci_deactivate_led(host);
2f730fec 2222#endif
d129bceb 2223
5f25a66f 2224 mmiowb();
d129bceb
PO		 2225 spin_unlock_irqrestore(&host->lock, flags);
2226
2227 mmc_request_done(host->mmc, mrq);
66fd8ad5 2228 sdhci_runtime_pm_put(host);
d129bceb
PO		 2229}
2230
2231static void sdhci_timeout_timer(unsigned long data)
2232{
2233 struct sdhci_host *host;
2234 unsigned long flags;
2235
2236 host = (struct sdhci_host*)data;
2237
2238 spin_lock_irqsave(&host->lock, flags);
2239
2240 if (host->mrq) {
2e4456f0
MV		 2241 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2242 mmc_hostname(host->mmc));
d129bceb
PO		 2243 sdhci_dumpregs(host);
2244
2245 if (host->data) {
17b0429d 2246 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2247 sdhci_finish_data(host);
2248 } else {
2249 if (host->cmd)
17b0429d 2250 host->cmd->error = -ETIMEDOUT;
d129bceb 2251 else
17b0429d 2252 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2253
2254 tasklet_schedule(&host->finish_tasklet);
2255 }
2256 }
2257
5f25a66f 2258 mmiowb();
d129bceb
PO		 2259 spin_unlock_irqrestore(&host->lock, flags);
2260}
2261
2262/*****************************************************************************\
2263 * *
2264 * Interrupt handling *
2265 * *
2266\*****************************************************************************/
2267
61541397 2268static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb
PO		 2269{
2270 BUG_ON(intmask == 0);
2271
2272 if (!host->cmd) {
2e4456f0
MV		 2273 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2274 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2275 sdhci_dumpregs(host);
2276 return;
2277 }
2278
ec014cba
RK		 2279 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2280 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2281 if (intmask & SDHCI_INT_TIMEOUT)
2282 host->cmd->error = -ETIMEDOUT;
2283 else
2284 host->cmd->error = -EILSEQ;
43b58b36 2285
71fcbda0
RK		 2286 /*
2287 * If this command initiates a data phase and a response
2288 * CRC error is signalled, the card can start transferring
2289 * data - the card may have received the command without
2290 * error. We must not terminate the mmc_request early.
2291 *
2292 * If the card did not receive the command or returned an
2293 * error which prevented it sending data, the data phase
2294 * will time out.
2295 */
2296 if (host->cmd->data &&
2297 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2298 SDHCI_INT_CRC) {
2299 host->cmd = NULL;
2300 return;
2301 }
2302
d129bceb 2303 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2304 return;
2305 }
2306
2307 /*
2308 * The host can send and interrupt when the busy state has
2309 * ended, allowing us to wait without wasting CPU cycles.
2310 * Unfortunately this is overloaded on the "data complete"
2311 * interrupt, so we need to take some care when handling
2312 * it.
2313 *
2314 * Note: The 1.0 specification is a bit ambiguous about this
2315 * feature so there might be some problems with older
2316 * controllers.
2317 */
2318 if (host->cmd->flags & MMC_RSP_BUSY) {
2319 if (host->cmd->data)
2e4456f0 2320 DBG("Cannot wait for busy signal when also doing a data transfer");
e99783a4
CM		 2321 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2322 && !host->busy_handle) {
2323 /* Mark that command complete before busy is ended */
2324 host->busy_handle = 1;
e809517f 2325 return;
e99783a4 2326 }
f945405c
BD		 2327
2328 /* The controller does not support the end-of-busy IRQ,
2329 * fall through and take the SDHCI_INT_RESPONSE */
61541397
AH		 2330 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2331 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2332 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2333 }
2334
2335 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2336 sdhci_finish_command(host);
d129bceb
PO		 2337}
2338
0957c333 2339#ifdef CONFIG_MMC_DEBUG
08621b18 2340static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2341{
2342 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2343 void *desc = host->adma_table;
6882a8c0
BD		 2344
2345 sdhci_dumpregs(host);
2346
2347 while (true) {
e57a5f61
AH		 2348 struct sdhci_adma2_64_desc *dma_desc = desc;
2349
2350 if (host->flags & SDHCI_USE_64_BIT_DMA)
2351 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2352 name, desc, le32_to_cpu(dma_desc->addr_hi),
2353 le32_to_cpu(dma_desc->addr_lo),
2354 le16_to_cpu(dma_desc->len),
2355 le16_to_cpu(dma_desc->cmd));
2356 else
2357 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2358 name, desc, le32_to_cpu(dma_desc->addr_lo),
2359 le16_to_cpu(dma_desc->len),
2360 le16_to_cpu(dma_desc->cmd));
6882a8c0 2361
76fe379a 2362 desc += host->desc_sz;
6882a8c0 2363
0545230f 2364 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2365 break;
2366 }
2367}
2368#else
08621b18 2369static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2370#endif
2371
d129bceb
PO		 2372static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2373{
069c9f14 2374 u32 command;
d129bceb
PO		 2375 BUG_ON(intmask == 0);
2376
b513ea25
AN		 2377 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2378 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2379 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2380 if (command == MMC_SEND_TUNING_BLOCK ||
2381 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2382 host->tuning_done = 1;
2383 wake_up(&host->buf_ready_int);
2384 return;
2385 }
2386 }
2387
d129bceb
PO		 2388 if (!host->data) {
2389 /*
e809517f
PO		 2390 * The "data complete" interrupt is also used to
2391 * indicate that a busy state has ended. See comment
2392 * above in sdhci_cmd_irq().
d129bceb 2393 */
e809517f 2394 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2395 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2396 host->cmd->error = -ETIMEDOUT;
2397 tasklet_schedule(&host->finish_tasklet);
2398 return;
2399 }
e809517f 2400 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2401 /*
2402 * Some cards handle busy-end interrupt
2403 * before the command completed, so make
2404 * sure we do things in the proper order.
2405 */
2406 if (host->busy_handle)
2407 sdhci_finish_command(host);
2408 else
2409 host->busy_handle = 1;
e809517f
PO		 2410 return;
2411 }
2412 }
d129bceb 2413
2e4456f0
MV		 2414 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2415 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2416 sdhci_dumpregs(host);
2417
2418 return;
2419 }
2420
2421 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2422 host->data->error = -ETIMEDOUT;
22113efd
AL		 2423 else if (intmask & SDHCI_INT_DATA_END_BIT)
2424 host->data->error = -EILSEQ;
2425 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2426 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2427 != MMC_BUS_TEST_R)
17b0429d 2428 host->data->error = -EILSEQ;
6882a8c0 2429 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2430 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2431 sdhci_adma_show_error(host);
2134a922 2432 host->data->error = -EIO;
a4071fbb
HZ		 2433 if (host->ops->adma_workaround)
2434 host->ops->adma_workaround(host, intmask);
6882a8c0 2435 }
d129bceb 2436
17b0429d 2437 if (host->data->error)
d129bceb
PO		 2438 sdhci_finish_data(host);
2439 else {
a406f5a3 2440 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2441 sdhci_transfer_pio(host);
2442
6ba736a1
PO		 2443 /*
2444 * We currently don't do anything fancy with DMA
2445 * boundaries, but as we can't disable the feature
2446 * we need to at least restart the transfer.
f6a03cbf
MV		 2447 *
2448 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2449 * should return a valid address to continue from, but as
2450 * some controllers are faulty, don't trust them.
6ba736a1 2451 */
f6a03cbf
MV		 2452 if (intmask & SDHCI_INT_DMA_END) {
2453 u32 dmastart, dmanow;
2454 dmastart = sg_dma_address(host->data->sg);
2455 dmanow = dmastart + host->data->bytes_xfered;
2456 /*
2457 * Force update to the next DMA block boundary.
2458 */
2459 dmanow = (dmanow &
2460 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2461 SDHCI_DEFAULT_BOUNDARY_SIZE;
2462 host->data->bytes_xfered = dmanow - dmastart;
2463 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2464 " next 0x%08x\n",
2465 mmc_hostname(host->mmc), dmastart,
2466 host->data->bytes_xfered, dmanow);
2467 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2468 }
6ba736a1 2469
e538fbe8
PO		 2470 if (intmask & SDHCI_INT_DATA_END) {
2471 if (host->cmd) {
2472 /*
2473 * Data managed to finish before the
2474 * command completed. Make sure we do
2475 * things in the proper order.
2476 */
2477 host->data_early = 1;
2478 } else {
2479 sdhci_finish_data(host);
2480 }
2481 }
d129bceb
PO		 2482 }
2483}
2484
7d12e780 2485static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2486{
781e989c 2487 irqreturn_t result = IRQ_NONE;
66fd8ad5 2488 struct sdhci_host *host = dev_id;
41005003 2489 u32 intmask, mask, unexpected = 0;
781e989c 2490 int max_loops = 16;
d129bceb
PO		 2491
2492 spin_lock(&host->lock);
2493
be138554 2494 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2495 spin_unlock(&host->lock);
655bca76 2496 return IRQ_NONE;
66fd8ad5
AH		 2497 }
2498
4e4141a5 2499 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2500 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2501 result = IRQ_NONE;
2502 goto out;
2503 }
2504
41005003
RK		 2505 do {
2506 /* Clear selected interrupts. */
2507 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2508 SDHCI_INT_BUS_POWER);
2509 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2510
41005003
RK		 2511 DBG("*** %s got interrupt: 0x%08x\n",
2512 mmc_hostname(host->mmc), intmask);
d129bceb 2513
41005003
RK		 2514 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2515 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2516 SDHCI_CARD_PRESENT;
d129bceb 2517
41005003
RK		 2518 /*
2519 * There is a observation on i.mx esdhc. INSERT
2520 * bit will be immediately set again when it gets
2521 * cleared, if a card is inserted. We have to mask
2522 * the irq to prevent interrupt storm which will
2523 * freeze the system. And the REMOVE gets the
2524 * same situation.
2525 *
2526 * More testing are needed here to ensure it works
2527 * for other platforms though.
2528 */
b537f94c
RK		 2529 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2530 SDHCI_INT_CARD_REMOVE);
2531 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2532 SDHCI_INT_CARD_INSERT;
2533 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2534 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2535
2536 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2537 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2538
2539 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2540 SDHCI_INT_CARD_REMOVE);
2541 result = IRQ_WAKE_THREAD;
41005003 2542 }
d129bceb 2543
41005003 2544 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2545 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2546 &intmask);
964f9ce2 2547
41005003
RK		 2548 if (intmask & SDHCI_INT_DATA_MASK)
2549 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2550
41005003
RK		 2551 if (intmask & SDHCI_INT_BUS_POWER)
2552 pr_err("%s: Card is consuming too much power!\n",
2553 mmc_hostname(host->mmc));
3192a28f 2554
781e989c
RK		 2555 if (intmask & SDHCI_INT_CARD_INT) {
2556 sdhci_enable_sdio_irq_nolock(host, false);
2557 host->thread_isr |= SDHCI_INT_CARD_INT;
2558 result = IRQ_WAKE_THREAD;
2559 }
f75979b7 2560
41005003
RK		 2561 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2562 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2563 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2564 SDHCI_INT_CARD_INT);
f75979b7 2565
41005003
RK		 2566 if (intmask) {
2567 unexpected |= intmask;
2568 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2569 }
d129bceb 2570
781e989c
RK		 2571 if (result == IRQ_NONE)
2572 result = IRQ_HANDLED;
d129bceb 2573
41005003 2574 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2575 } while (intmask && --max_loops);
d129bceb
PO		 2576out:
2577 spin_unlock(&host->lock);
2578
6379b237
AS		 2579 if (unexpected) {
2580 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2581 mmc_hostname(host->mmc), unexpected);
2582 sdhci_dumpregs(host);
2583 }
f75979b7 2584
d129bceb
PO		 2585 return result;
2586}
2587
781e989c
RK		 2588static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2589{
2590 struct sdhci_host *host = dev_id;
2591 unsigned long flags;
2592 u32 isr;
2593
2594 spin_lock_irqsave(&host->lock, flags);
2595 isr = host->thread_isr;
2596 host->thread_isr = 0;
2597 spin_unlock_irqrestore(&host->lock, flags);
2598
3560db8e
RK		 2599 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2600 sdhci_card_event(host->mmc);
2601 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2602 }
2603
781e989c
RK		 2604 if (isr & SDHCI_INT_CARD_INT) {
2605 sdio_run_irqs(host->mmc);
2606
2607 spin_lock_irqsave(&host->lock, flags);
2608 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2609 sdhci_enable_sdio_irq_nolock(host, true);
2610 spin_unlock_irqrestore(&host->lock, flags);
2611 }
2612
2613 return isr ? IRQ_HANDLED : IRQ_NONE;
2614}
2615
d129bceb
PO		 2616/*****************************************************************************\
2617 * *
2618 * Suspend/resume *
2619 * *
2620\*****************************************************************************/
2621
2622#ifdef CONFIG_PM
ad080d79
KL		 2623void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2624{
2625 u8 val;
2626 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2627 | SDHCI_WAKE_ON_INT;
2628
2629 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2630 val |= mask ;
2631 /* Avoid fake wake up */
2632 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2633 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2634 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2635}
2636EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2637
0b10f478 2638static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2639{
2640 u8 val;
2641 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2642 | SDHCI_WAKE_ON_INT;
2643
2644 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2645 val &= ~mask;
2646 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2647}
d129bceb 2648
29495aa0 2649int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2650{
7260cf5e
AV		 2651 sdhci_disable_card_detection(host);
2652
66c39dfc
AH		 2653 mmc_retune_timer_stop(host->mmc);
2654 mmc_retune_needed(host->mmc);
cf2b5eea 2655
ad080d79 2656 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2657 host->ier = 0;
2658 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2659 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2660 free_irq(host->irq, host);
2661 } else {
2662 sdhci_enable_irq_wakeups(host);
2663 enable_irq_wake(host->irq);
2664 }
4ee14ec6 2665 return 0;
d129bceb
PO		 2666}
2667
b8c86fc5 2668EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2669
b8c86fc5
PO		 2670int sdhci_resume_host(struct sdhci_host *host)
2671{
4ee14ec6 2672 int ret = 0;
d129bceb 2673
a13abc7b 2674 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2675 if (host->ops->enable_dma)
2676 host->ops->enable_dma(host);
2677 }
d129bceb 2678
6308d290
AH		 2679 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2680 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2681 /* Card keeps power but host controller does not */
2682 sdhci_init(host, 0);
2683 host->pwr = 0;
2684 host->clock = 0;
2685 sdhci_do_set_ios(host, &host->mmc->ios);
2686 } else {
2687 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2688 mmiowb();
2689 }
b8c86fc5 2690
14a7b416
HC		 2691 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2692 ret = request_threaded_irq(host->irq, sdhci_irq,
2693 sdhci_thread_irq, IRQF_SHARED,
2694 mmc_hostname(host->mmc), host);
2695 if (ret)
2696 return ret;
2697 } else {
2698 sdhci_disable_irq_wakeups(host);
2699 disable_irq_wake(host->irq);
2700 }
2701
7260cf5e
AV		 2702 sdhci_enable_card_detection(host);
2703
2f4cbb3d 2704 return ret;
d129bceb
PO		 2705}
2706
b8c86fc5 2707EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5
AH		 2708
2709static int sdhci_runtime_pm_get(struct sdhci_host *host)
2710{
2711 return pm_runtime_get_sync(host->mmc->parent);
2712}
2713
2714static int sdhci_runtime_pm_put(struct sdhci_host *host)
2715{
2716 pm_runtime_mark_last_busy(host->mmc->parent);
2717 return pm_runtime_put_autosuspend(host->mmc->parent);
2718}
2719
f0710a55
AH		 2720static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2721{
5c671c41 2722 if (host->bus_on)
f0710a55
AH		 2723 return;
2724 host->bus_on = true;
2725 pm_runtime_get_noresume(host->mmc->parent);
2726}
2727
2728static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2729{
5c671c41 2730 if (!host->bus_on)
f0710a55
AH		 2731 return;
2732 host->bus_on = false;
2733 pm_runtime_put_noidle(host->mmc->parent);
2734}
2735
66fd8ad5
AH		 2736int sdhci_runtime_suspend_host(struct sdhci_host *host)
2737{
2738 unsigned long flags;
66fd8ad5 2739
66c39dfc
AH		 2740 mmc_retune_timer_stop(host->mmc);
2741 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2742
2743 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2744 host->ier &= SDHCI_INT_CARD_INT;
2745 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2746 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2747 spin_unlock_irqrestore(&host->lock, flags);
2748
781e989c 2749 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2750
2751 spin_lock_irqsave(&host->lock, flags);
2752 host->runtime_suspended = true;
2753 spin_unlock_irqrestore(&host->lock, flags);
2754
8a125bad 2755 return 0;
66fd8ad5
AH		 2756}
2757EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2758
2759int sdhci_runtime_resume_host(struct sdhci_host *host)
2760{
2761 unsigned long flags;
8a125bad 2762 int host_flags = host->flags;
66fd8ad5
AH		 2763
2764 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2765 if (host->ops->enable_dma)
2766 host->ops->enable_dma(host);
2767 }
2768
2769 sdhci_init(host, 0);
2770
2771 /* Force clock and power re-program */
2772 host->pwr = 0;
2773 host->clock = 0;
3396e736 2774 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
66fd8ad5
AH		 2775 sdhci_do_set_ios(host, &host->mmc->ios);
2776
52983382
KL		 2777 if ((host_flags & SDHCI_PV_ENABLED) &&
2778 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2779 spin_lock_irqsave(&host->lock, flags);
2780 sdhci_enable_preset_value(host, true);
2781 spin_unlock_irqrestore(&host->lock, flags);
2782 }
66fd8ad5 2783
66fd8ad5
AH		 2784 spin_lock_irqsave(&host->lock, flags);
2785
2786 host->runtime_suspended = false;
2787
2788 /* Enable SDIO IRQ */
ef104333 2789 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2790 sdhci_enable_sdio_irq_nolock(host, true);
2791
2792 /* Enable Card Detection */
2793 sdhci_enable_card_detection(host);
2794
2795 spin_unlock_irqrestore(&host->lock, flags);
2796
8a125bad 2797 return 0;
66fd8ad5
AH		 2798}
2799EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2800
162d6f98 2801#endif /* CONFIG_PM */
66fd8ad5 2802
d129bceb
PO		 2803/*****************************************************************************\
2804 * *
b8c86fc5 2805 * Device allocation/registration *
d129bceb
PO		 2806 * *
2807\*****************************************************************************/
2808
b8c86fc5
PO		 2809struct sdhci_host *sdhci_alloc_host(struct device *dev,
2810 size_t priv_size)
d129bceb 2811{
d129bceb
PO		 2812 struct mmc_host *mmc;
2813 struct sdhci_host *host;
2814
b8c86fc5 2815 WARN_ON(dev == NULL);
d129bceb 2816
b8c86fc5 2817 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2818 if (!mmc)
b8c86fc5 2819 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2820
2821 host = mmc_priv(mmc);
2822 host->mmc = mmc;
bf60e592
AH		 2823 host->mmc_host_ops = sdhci_ops;
2824 mmc->ops = &host->mmc_host_ops;
d129bceb 2825
b8c86fc5
PO		 2826 return host;
2827}
8a4da143 2828
b8c86fc5 2829EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2830
b8c86fc5
PO		 2831int sdhci_add_host(struct sdhci_host *host)
2832{
2833 struct mmc_host *mmc;
bd6a8c30 2834 u32 caps[2] = {0, 0};
f2119df6
AN		 2835 u32 max_current_caps;
2836 unsigned int ocr_avail;
f5fa92e5 2837 unsigned int override_timeout_clk;
59241757 2838 u32 max_clk;
b8c86fc5 2839 int ret;
d129bceb 2840
b8c86fc5
PO		 2841 WARN_ON(host == NULL);
2842 if (host == NULL)
2843 return -EINVAL;
d129bceb 2844
b8c86fc5 2845 mmc = host->mmc;
d129bceb 2846
b8c86fc5
PO		 2847 if (debug_quirks)
2848 host->quirks = debug_quirks;
66fd8ad5
AH		 2849 if (debug_quirks2)
2850 host->quirks2 = debug_quirks2;
d129bceb 2851
f5fa92e5
AH		 2852 override_timeout_clk = host->timeout_clk;
2853
03231f9b 2854 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2855
4e4141a5 2856 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2857 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2858 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2859 if (host->version > SDHCI_SPEC_300) {
2e4456f0
MV		 2860 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2861 mmc_hostname(mmc), host->version);
4a965505
PO		 2862 }
2863
f2119df6 2864 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2865 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2866
bd6a8c30
PR		 2867 if (host->version >= SDHCI_SPEC_300)
2868 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2869 host->caps1 :
2870 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2871
b8c86fc5 2872 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2873 host->flags |= SDHCI_USE_SDMA;
f2119df6 2874 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2875 DBG("Controller doesn't have SDMA capability\n");
67435274 2876 else
a13abc7b 2877 host->flags |= SDHCI_USE_SDMA;
d129bceb 2878
b8c86fc5 2879 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2880 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2881 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2882 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2883 }
2884
f2119df6
AN		 2885 if ((host->version >= SDHCI_SPEC_200) &&
2886 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2887 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2888
2889 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2890 (host->flags & SDHCI_USE_ADMA)) {
2891 DBG("Disabling ADMA as it is marked broken\n");
2892 host->flags &= ~SDHCI_USE_ADMA;
2893 }
2894
e57a5f61
AH		 2895 /*
2896 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2897 * and *must* do 64-bit DMA. A driver has the opportunity to change
2898 * that during the first call to ->enable_dma(). Similarly
2899 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2900 * implement.
2901 */
5eaa7476 2902 if (caps[0] & SDHCI_CAN_64BIT)
e57a5f61
AH		 2903 host->flags |= SDHCI_USE_64_BIT_DMA;
2904
a13abc7b 2905 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2906 if (host->ops->enable_dma) {
2907 if (host->ops->enable_dma(host)) {
6606110d 2908 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
b8c86fc5 2909 mmc_hostname(mmc));
a13abc7b
RR		 2910 host->flags &=
2911 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2912 }
d129bceb
PO		 2913 }
2914 }
2915
e57a5f61
AH		 2916 /* SDMA does not support 64-bit DMA */
2917 if (host->flags & SDHCI_USE_64_BIT_DMA)
2918 host->flags &= ~SDHCI_USE_SDMA;
2919
2134a922 2920 if (host->flags & SDHCI_USE_ADMA) {
e66e61cb
RK		 2921 dma_addr_t dma;
2922 void *buf;
2923
2134a922 2924 /*
76fe379a
AH		 2925 * The DMA descriptor table size is calculated as the maximum
2926 * number of segments times 2, to allow for an alignment
2927 * descriptor for each segment, plus 1 for a nop end descriptor,
2928 * all multipled by the descriptor size.
2134a922 2929 */
e57a5f61
AH		 2930 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2931 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2932 SDHCI_ADMA2_64_DESC_SZ;
e57a5f61 2933 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
e57a5f61
AH		 2934 } else {
2935 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2936 SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2937 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2938 }
e66e61cb 2939
04a5ae6f 2940 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
e66e61cb
RK		 2941 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
2942 host->adma_table_sz, &dma, GFP_KERNEL);
2943 if (!buf) {
6606110d 2944 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 2945 mmc_hostname(mmc));
2946 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 2947 } else if ((dma + host->align_buffer_sz) &
2948 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 2949 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2950 mmc_hostname(mmc));
d1e49f77 2951 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 2952 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
2953 host->adma_table_sz, buf, dma);
2954 } else {
2955 host->align_buffer = buf;
2956 host->align_addr = dma;
edd63fcc 2957
e66e61cb
RK		 2958 host->adma_table = buf + host->align_buffer_sz;
2959 host->adma_addr = dma + host->align_buffer_sz;
2960 }
2134a922
PO		 2961 }
2962
7659150c
PO		 2963 /*
2964 * If we use DMA, then it's up to the caller to set the DMA
2965 * mask, but PIO does not need the hw shim so we set a new
2966 * mask here in that case.
2967 */
a13abc7b 2968 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 2969 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 2970 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 2971 }
d129bceb 2972
c4687d5f 2973 if (host->version >= SDHCI_SPEC_300)
f2119df6 2974 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2975 >> SDHCI_CLOCK_BASE_SHIFT;
2976 else
f2119df6 2977 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2978 >> SDHCI_CLOCK_BASE_SHIFT;
2979
4240ff0a 2980 host->max_clk *= 1000000;
f27f47ef
AV		 2981 if (host->max_clk == 0 || host->quirks &
2982 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2983 if (!host->ops->get_max_clock) {
2e4456f0
MV		 2984 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
2985 mmc_hostname(mmc));
4240ff0a
BD		 2986 return -ENODEV;
2987 }
2988 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2989 }
d129bceb 2990
c3ed3877
AN		 2991 /*
2992 * In case of Host Controller v3.00, find out whether clock
2993 * multiplier is supported.
2994 */
2995 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2996 SDHCI_CLOCK_MUL_SHIFT;
2997
2998 /*
2999 * In case the value in Clock Multiplier is 0, then programmable
3000 * clock mode is not supported, otherwise the actual clock
3001 * multiplier is one more than the value of Clock Multiplier
3002 * in the Capabilities Register.
3003 */
3004 if (host->clk_mul)
3005 host->clk_mul += 1;
3006
d129bceb
PO		 3007 /*
3008 * Set host parameters.
3009 */
59241757
DA		 3010 max_clk = host->max_clk;
3011
ce5f036b 3012 if (host->ops->get_min_clock)
a9e58f25 3013 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3014 else if (host->version >= SDHCI_SPEC_300) {
3015 if (host->clk_mul) {
3016 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3017 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3018 } else
3019 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3020 } else
0397526d 3021 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3022
59241757
DA		 3023 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3024 mmc->f_max = max_clk;
3025
28aab053
AD		 3026 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3027 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3028 SDHCI_TIMEOUT_CLK_SHIFT;
3029 if (host->timeout_clk == 0) {
3030 if (host->ops->get_timeout_clock) {
3031 host->timeout_clk =
3032 host->ops->get_timeout_clock(host);
3033 } else {
3034 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3035 mmc_hostname(mmc));
3036 return -ENODEV;
3037 }
272308ca 3038 }
272308ca 3039
28aab053
AD		 3040 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3041 host->timeout_clk *= 1000;
272308ca 3042
28aab053 3043 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3044 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3045 mmc->max_busy_timeout /= host->timeout_clk;
3046 }
58d1246d 3047
f5fa92e5
AH		 3048 if (override_timeout_clk)
3049 host->timeout_clk = override_timeout_clk;
3050
e89d456f 3051 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3052 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3053
3054 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3055 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3056
8edf6371 3057 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3058 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3059 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3060 !(host->flags & SDHCI_USE_SDMA)) &&
3061 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3062 host->flags |= SDHCI_AUTO_CMD23;
3063 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3064 } else {
3065 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3066 }
3067
15ec4461
PR		 3068 /*
3069 * A controller may support 8-bit width, but the board itself
3070 * might not have the pins brought out. Boards that support
3071 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3072 * their platform code before calling sdhci_add_host(), and we
3073 * won't assume 8-bit width for hosts without that CAP.
3074 */
5fe23c7f 3075 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3076 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3077
63ef5d8c
JH		 3078 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3079 mmc->caps &= ~MMC_CAP_CMD23;
3080
f2119df6 3081 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 3082 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3083
176d1ed4 3084 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
c31d22eb
II		 3085 !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3086 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
68d1fb7e
AV		 3087 mmc->caps |= MMC_CAP_NEEDS_POLL;
3088
3a48edc4
TK		 3089 /* If there are external regulators, get them */
3090 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3091 return -EPROBE_DEFER;
3092
6231f3de 3093 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3094 if (!IS_ERR(mmc->supply.vqmmc)) {
3095 ret = regulator_enable(mmc->supply.vqmmc);
3096 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3097 1950000))
8363c374
KL		 3098 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3099 SDHCI_SUPPORT_SDR50 |
3100 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3101 if (ret) {
3102 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3103 mmc_hostname(mmc), ret);
4bb74313 3104 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3105 }
8363c374 3106 }
6231f3de 3107
6a66180a
DD		 3108 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3109 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3110 SDHCI_SUPPORT_DDR50);
3111
4188bba0
AC		 3112 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3113 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3114 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3115 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3116
3117 /* SDR104 supports also implies SDR50 support */
156e14b1 3118 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3119 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3120 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3121 * field can be promoted to support HS200.
3122 */
549c0b18 3123 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3124 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3125 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3126 mmc->caps |= MMC_CAP_UHS_SDR50;
3127
e9fb05d5
AH		 3128 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3129 (caps[1] & SDHCI_SUPPORT_HS400))
3130 mmc->caps2 |= MMC_CAP2_HS400;
3131
549c0b18
AH		 3132 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3133 (IS_ERR(mmc->supply.vqmmc) ||
3134 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3135 1300000)))
3136 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3137
9107ebbf
MC		 3138 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3139 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3140 mmc->caps |= MMC_CAP_UHS_DDR50;
3141
069c9f14 3142 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3143 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3144 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3145
156e14b1 3146 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3147 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3148 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3149
d6d50a15
AN		 3150 /* Driver Type(s) (A, C, D) supported by the host */
3151 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3152 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3153 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3154 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3155 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3156 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3157
cf2b5eea
AN		 3158 /* Initial value for re-tuning timer count */
3159 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3160 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3161
3162 /*
3163 * In case Re-tuning Timer is not disabled, the actual value of
3164 * re-tuning timer will be 2 ^ (n - 1).
3165 */
3166 if (host->tuning_count)
3167 host->tuning_count = 1 << (host->tuning_count - 1);
3168
3169 /* Re-tuning mode supported by the Host Controller */
3170 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3171 SDHCI_RETUNING_MODE_SHIFT;
3172
8f230f45 3173 ocr_avail = 0;
bad37e1a 3174
f2119df6
AN		 3175 /*
3176 * According to SD Host Controller spec v3.00, if the Host System
3177 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3178 * the value is meaningful only if Voltage Support in the Capabilities
3179 * register is set. The actual current value is 4 times the register
3180 * value.
3181 */
3182 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3183 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3184 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3185 if (curr > 0) {
3186
3187 /* convert to SDHCI_MAX_CURRENT format */
3188 curr = curr/1000; /* convert to mA */
3189 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3190
3191 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3192 max_current_caps =
3193 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3194 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3195 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3196 }
3197 }
f2119df6
AN		 3198
3199 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3200 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3201
55c4665e 3202 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3203 SDHCI_MAX_CURRENT_330_MASK) >>
3204 SDHCI_MAX_CURRENT_330_SHIFT) *
3205 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3206 }
3207 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3208 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3209
55c4665e 3210 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3211 SDHCI_MAX_CURRENT_300_MASK) >>
3212 SDHCI_MAX_CURRENT_300_SHIFT) *
3213 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3214 }
3215 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3216 ocr_avail |= MMC_VDD_165_195;
3217
55c4665e 3218 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3219 SDHCI_MAX_CURRENT_180_MASK) >>
3220 SDHCI_MAX_CURRENT_180_SHIFT) *
3221 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3222 }
3223
5fd26c7e
UH		 3224 /* If OCR set by host, use it instead. */
3225 if (host->ocr_mask)
3226 ocr_avail = host->ocr_mask;
3227
3228 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3229 if (mmc->ocr_avail)
52221610 3230 ocr_avail = mmc->ocr_avail;
3a48edc4 3231
8f230f45
TI		 3232 mmc->ocr_avail = ocr_avail;
3233 mmc->ocr_avail_sdio = ocr_avail;
3234 if (host->ocr_avail_sdio)
3235 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3236 mmc->ocr_avail_sd = ocr_avail;
3237 if (host->ocr_avail_sd)
3238 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3239 else /* normal SD controllers don't support 1.8V */
3240 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3241 mmc->ocr_avail_mmc = ocr_avail;
3242 if (host->ocr_avail_mmc)
3243 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3244
3245 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 3246 pr_err("%s: Hardware doesn't report any support voltages.\n",
3247 mmc_hostname(mmc));
b8c86fc5 3248 return -ENODEV;
146ad66e
PO		 3249 }
3250
d129bceb
PO		 3251 spin_lock_init(&host->lock);
3252
3253 /*
2134a922
PO		 3254 * Maximum number of segments. Depends on if the hardware
3255 * can do scatter/gather or not.
d129bceb 3256 */
2134a922 3257 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3258 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3259 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3260 mmc->max_segs = 1;
2134a922 3261 else /* PIO */
4fb213f8 3262 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3263
3264 /*
ac00531d
AH		 3265 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3266 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3267 * is less anyway.
d129bceb 3268 */
55db890a 3269 mmc->max_req_size = 524288;
d129bceb
PO		 3270
3271 /*
3272 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3273 * of bytes. When doing hardware scatter/gather, each entry cannot
3274 * be larger than 64 KiB though.
d129bceb 3275 */
30652aa3
OJ		 3276 if (host->flags & SDHCI_USE_ADMA) {
3277 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3278 mmc->max_seg_size = 65535;
3279 else
3280 mmc->max_seg_size = 65536;
3281 } else {
2134a922 3282 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3283 }
d129bceb 3284
fe4a3c7a
PO		 3285 /*
3286 * Maximum block size. This varies from controller to controller and
3287 * is specified in the capabilities register.
3288 */
0633f654
AV		 3289 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3290 mmc->max_blk_size = 2;
3291 } else {
f2119df6 3292 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3293 SDHCI_MAX_BLOCK_SHIFT;
3294 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3295 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3296 mmc_hostname(mmc));
0633f654
AV		 3297 mmc->max_blk_size = 0;
3298 }
3299 }
3300
3301 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3302
55db890a
PO		 3303 /*
3304 * Maximum block count.
3305 */
1388eefd 3306 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3307
d129bceb
PO		 3308 /*
3309 * Init tasklets.
3310 */
d129bceb
PO		 3311 tasklet_init(&host->finish_tasklet,
3312 sdhci_tasklet_finish, (unsigned long)host);
3313
e4cad1b5 3314 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3315
250fb7b4 3316 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3317
2af502ca
SG		 3318 sdhci_init(host, 0);
3319
781e989c
RK		 3320 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3321 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3322 if (ret) {
3323 pr_err("%s: Failed to request IRQ %d: %d\n",
3324 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3325 goto untasklet;
0fc81ee3 3326 }
d129bceb 3327
d129bceb
PO		 3328#ifdef CONFIG_MMC_DEBUG
3329 sdhci_dumpregs(host);
3330#endif
3331
f9134319 3332#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3333 snprintf(host->led_name, sizeof(host->led_name),
3334 "%s::", mmc_hostname(mmc));
3335 host->led.name = host->led_name;
2f730fec
PO		 3336 host->led.brightness = LED_OFF;
3337 host->led.default_trigger = mmc_hostname(mmc);
3338 host->led.brightness_set = sdhci_led_control;
3339
b8c86fc5 3340 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3341 if (ret) {
3342 pr_err("%s: Failed to register LED device: %d\n",
3343 mmc_hostname(mmc), ret);
2f730fec 3344 goto reset;
0fc81ee3 3345 }
2f730fec
PO		 3346#endif
3347
5f25a66f
PO		 3348 mmiowb();
3349
d129bceb
PO		 3350 mmc_add_host(mmc);
3351
a3c76eb9 3352 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3353 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3354 (host->flags & SDHCI_USE_ADMA) ?
3355 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3356 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3357
7260cf5e
AV		 3358 sdhci_enable_card_detection(host);
3359
d129bceb
PO		 3360 return 0;
3361
f9134319 3362#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3363reset:
03231f9b 3364 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3365 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3366 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3367 free_irq(host->irq, host);
3368#endif
8ef1a143 3369untasklet:
d129bceb 3370 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3371
3372 return ret;
3373}
3374
b8c86fc5 3375EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3376
1e72859e 3377void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3378{
3a48edc4 3379 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3380 unsigned long flags;
3381
3382 if (dead) {
3383 spin_lock_irqsave(&host->lock, flags);
3384
3385 host->flags |= SDHCI_DEVICE_DEAD;
3386
3387 if (host->mrq) {
a3c76eb9 3388 pr_err("%s: Controller removed during "
4e743f1f 3389 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3390
3391 host->mrq->cmd->error = -ENOMEDIUM;
3392 tasklet_schedule(&host->finish_tasklet);
3393 }
3394
3395 spin_unlock_irqrestore(&host->lock, flags);
3396 }
3397
7260cf5e
AV		 3398 sdhci_disable_card_detection(host);
3399
4e743f1f 3400 mmc_remove_host(mmc);
d129bceb 3401
f9134319 3402#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3403 led_classdev_unregister(&host->led);
3404#endif
3405
1e72859e 3406 if (!dead)
03231f9b 3407 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3408
b537f94c
RK		 3409 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3410 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3411 free_irq(host->irq, host);
3412
3413 del_timer_sync(&host->timer);
3414
d129bceb 3415 tasklet_kill(&host->finish_tasklet);
2134a922 3416
3a48edc4
TK		 3417 if (!IS_ERR(mmc->supply.vqmmc))
3418 regulator_disable(mmc->supply.vqmmc);
6231f3de 3419
edd63fcc 3420 if (host->align_buffer)
e66e61cb
RK		 3421 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3422 host->adma_table_sz, host->align_buffer,
3423 host->align_addr);
2134a922 3424
4efaa6fb 3425 host->adma_table = NULL;
2134a922 3426 host->align_buffer = NULL;
d129bceb
PO		 3427}
3428
b8c86fc5 3429EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3430
b8c86fc5 3431void sdhci_free_host(struct sdhci_host *host)
d129bceb 3432{
b8c86fc5 3433 mmc_free_host(host->mmc);
d129bceb
PO		 3434}
3435
b8c86fc5 3436EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3437
3438/*****************************************************************************\
3439 * *
3440 * Driver init/exit *
3441 * *
3442\*****************************************************************************/
3443
3444static int __init sdhci_drv_init(void)
3445{
a3c76eb9 3446 pr_info(DRIVER_NAME
52fbf9c9 3447 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3448 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3449
b8c86fc5 3450 return 0;
d129bceb
PO		 3451}
3452
3453static void __exit sdhci_drv_exit(void)
3454{
d129bceb
PO		 3455}
3456
3457module_init(sdhci_drv_init);
3458module_exit(sdhci_drv_exit);
3459
df673b22 3460module_param(debug_quirks, uint, 0444);
66fd8ad5 3461module_param(debug_quirks2, uint, 0444);
67435274 3462
32710e8f 3463MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3464MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3465MODULE_LICENSE("GPL");
67435274 3466
df673b22 3467MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3468MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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