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Commit | Line | Data |
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d129bceb | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
d129bceb | 3 | * |
b69c9058 | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
d129bceb PO |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
84c46a53 PO |
10 | * |
11 | * Thanks to the following companies for their support: | |
12 | * | |
13 | * - JMicron (hardware and technical support) | |
d129bceb PO |
14 | */ |
15 | ||
d129bceb PO |
16 | #include <linux/delay.h> |
17 | #include <linux/highmem.h> | |
b8c86fc5 | 18 | #include <linux/io.h> |
d129bceb | 19 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
11763609 | 21 | #include <linux/scatterlist.h> |
9bea3c85 | 22 | #include <linux/regulator/consumer.h> |
d129bceb | 23 | |
2f730fec PO |
24 | #include <linux/leds.h> |
25 | ||
d129bceb | 26 | #include <linux/mmc/host.h> |
d129bceb | 27 | |
d129bceb PO |
28 | #include "sdhci.h" |
29 | ||
30 | #define DRIVER_NAME "sdhci" | |
d129bceb | 31 | |
d129bceb | 32 | #define DBG(f, x...) \ |
c6563178 | 33 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
d129bceb | 34 | |
f9134319 PO |
35 | #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ |
36 | defined(CONFIG_MMC_SDHCI_MODULE)) | |
37 | #define SDHCI_USE_LEDS_CLASS | |
38 | #endif | |
39 | ||
df673b22 | 40 | static unsigned int debug_quirks = 0; |
67435274 | 41 | |
d129bceb PO |
42 | static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *); |
43 | static void sdhci_finish_data(struct sdhci_host *); | |
44 | ||
45 | static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); | |
46 | static void sdhci_finish_command(struct sdhci_host *); | |
47 | ||
48 | static void sdhci_dumpregs(struct sdhci_host *host) | |
49 | { | |
50 | printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n"); | |
51 | ||
52 | printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", | |
4e4141a5 AV |
53 | sdhci_readl(host, SDHCI_DMA_ADDRESS), |
54 | sdhci_readw(host, SDHCI_HOST_VERSION)); | |
d129bceb | 55 | printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", |
4e4141a5 AV |
56 | sdhci_readw(host, SDHCI_BLOCK_SIZE), |
57 | sdhci_readw(host, SDHCI_BLOCK_COUNT)); | |
d129bceb | 58 | printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", |
4e4141a5 AV |
59 | sdhci_readl(host, SDHCI_ARGUMENT), |
60 | sdhci_readw(host, SDHCI_TRANSFER_MODE)); | |
d129bceb | 61 | printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", |
4e4141a5 AV |
62 | sdhci_readl(host, SDHCI_PRESENT_STATE), |
63 | sdhci_readb(host, SDHCI_HOST_CONTROL)); | |
d129bceb | 64 | printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", |
4e4141a5 AV |
65 | sdhci_readb(host, SDHCI_POWER_CONTROL), |
66 | sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); | |
d129bceb | 67 | printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", |
4e4141a5 AV |
68 | sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), |
69 | sdhci_readw(host, SDHCI_CLOCK_CONTROL)); | |
d129bceb | 70 | printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", |
4e4141a5 AV |
71 | sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), |
72 | sdhci_readl(host, SDHCI_INT_STATUS)); | |
d129bceb | 73 | printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", |
4e4141a5 AV |
74 | sdhci_readl(host, SDHCI_INT_ENABLE), |
75 | sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); | |
d129bceb | 76 | printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", |
4e4141a5 AV |
77 | sdhci_readw(host, SDHCI_ACMD12_ERR), |
78 | sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); | |
d129bceb | 79 | printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n", |
4e4141a5 AV |
80 | sdhci_readl(host, SDHCI_CAPABILITIES), |
81 | sdhci_readl(host, SDHCI_MAX_CURRENT)); | |
d129bceb | 82 | |
be3f4ae0 BD |
83 | if (host->flags & SDHCI_USE_ADMA) |
84 | printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", | |
85 | readl(host->ioaddr + SDHCI_ADMA_ERROR), | |
86 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); | |
87 | ||
d129bceb PO |
88 | printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n"); |
89 | } | |
90 | ||
91 | /*****************************************************************************\ | |
92 | * * | |
93 | * Low level functions * | |
94 | * * | |
95 | \*****************************************************************************/ | |
96 | ||
7260cf5e AV |
97 | static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) |
98 | { | |
99 | u32 ier; | |
100 | ||
101 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); | |
102 | ier &= ~clear; | |
103 | ier |= set; | |
104 | sdhci_writel(host, ier, SDHCI_INT_ENABLE); | |
105 | sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); | |
106 | } | |
107 | ||
108 | static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs) | |
109 | { | |
110 | sdhci_clear_set_irqs(host, 0, irqs); | |
111 | } | |
112 | ||
113 | static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs) | |
114 | { | |
115 | sdhci_clear_set_irqs(host, irqs, 0); | |
116 | } | |
117 | ||
118 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) | |
119 | { | |
120 | u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; | |
121 | ||
68d1fb7e AV |
122 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) |
123 | return; | |
124 | ||
7260cf5e AV |
125 | if (enable) |
126 | sdhci_unmask_irqs(host, irqs); | |
127 | else | |
128 | sdhci_mask_irqs(host, irqs); | |
129 | } | |
130 | ||
131 | static void sdhci_enable_card_detection(struct sdhci_host *host) | |
132 | { | |
133 | sdhci_set_card_detection(host, true); | |
134 | } | |
135 | ||
136 | static void sdhci_disable_card_detection(struct sdhci_host *host) | |
137 | { | |
138 | sdhci_set_card_detection(host, false); | |
139 | } | |
140 | ||
d129bceb PO |
141 | static void sdhci_reset(struct sdhci_host *host, u8 mask) |
142 | { | |
e16514d8 | 143 | unsigned long timeout; |
063a9dbb | 144 | u32 uninitialized_var(ier); |
e16514d8 | 145 | |
b8c86fc5 | 146 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { |
4e4141a5 | 147 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & |
8a4da143 PO |
148 | SDHCI_CARD_PRESENT)) |
149 | return; | |
150 | } | |
151 | ||
063a9dbb AV |
152 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) |
153 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); | |
154 | ||
4e4141a5 | 155 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
d129bceb | 156 | |
e16514d8 | 157 | if (mask & SDHCI_RESET_ALL) |
d129bceb PO |
158 | host->clock = 0; |
159 | ||
e16514d8 PO |
160 | /* Wait max 100 ms */ |
161 | timeout = 100; | |
162 | ||
163 | /* hw clears the bit when it's done */ | |
4e4141a5 | 164 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { |
e16514d8 | 165 | if (timeout == 0) { |
acf1da45 | 166 | printk(KERN_ERR "%s: Reset 0x%x never completed.\n", |
e16514d8 PO |
167 | mmc_hostname(host->mmc), (int)mask); |
168 | sdhci_dumpregs(host); | |
169 | return; | |
170 | } | |
171 | timeout--; | |
172 | mdelay(1); | |
d129bceb | 173 | } |
063a9dbb AV |
174 | |
175 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) | |
176 | sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier); | |
d129bceb PO |
177 | } |
178 | ||
2f4cbb3d NP |
179 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); |
180 | ||
181 | static void sdhci_init(struct sdhci_host *host, int soft) | |
d129bceb | 182 | { |
2f4cbb3d NP |
183 | if (soft) |
184 | sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); | |
185 | else | |
186 | sdhci_reset(host, SDHCI_RESET_ALL); | |
d129bceb | 187 | |
7260cf5e AV |
188 | sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, |
189 | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | | |
3192a28f PO |
190 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | |
191 | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | | |
6aa943ab | 192 | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); |
2f4cbb3d NP |
193 | |
194 | if (soft) { | |
195 | /* force clock reconfiguration */ | |
196 | host->clock = 0; | |
197 | sdhci_set_ios(host->mmc, &host->mmc->ios); | |
198 | } | |
7260cf5e | 199 | } |
d129bceb | 200 | |
7260cf5e AV |
201 | static void sdhci_reinit(struct sdhci_host *host) |
202 | { | |
2f4cbb3d | 203 | sdhci_init(host, 0); |
7260cf5e | 204 | sdhci_enable_card_detection(host); |
d129bceb PO |
205 | } |
206 | ||
207 | static void sdhci_activate_led(struct sdhci_host *host) | |
208 | { | |
209 | u8 ctrl; | |
210 | ||
4e4141a5 | 211 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 212 | ctrl |= SDHCI_CTRL_LED; |
4e4141a5 | 213 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
214 | } |
215 | ||
216 | static void sdhci_deactivate_led(struct sdhci_host *host) | |
217 | { | |
218 | u8 ctrl; | |
219 | ||
4e4141a5 | 220 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 221 | ctrl &= ~SDHCI_CTRL_LED; |
4e4141a5 | 222 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
223 | } |
224 | ||
f9134319 | 225 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
226 | static void sdhci_led_control(struct led_classdev *led, |
227 | enum led_brightness brightness) | |
228 | { | |
229 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); | |
230 | unsigned long flags; | |
231 | ||
232 | spin_lock_irqsave(&host->lock, flags); | |
233 | ||
234 | if (brightness == LED_OFF) | |
235 | sdhci_deactivate_led(host); | |
236 | else | |
237 | sdhci_activate_led(host); | |
238 | ||
239 | spin_unlock_irqrestore(&host->lock, flags); | |
240 | } | |
241 | #endif | |
242 | ||
d129bceb PO |
243 | /*****************************************************************************\ |
244 | * * | |
245 | * Core functions * | |
246 | * * | |
247 | \*****************************************************************************/ | |
248 | ||
a406f5a3 | 249 | static void sdhci_read_block_pio(struct sdhci_host *host) |
d129bceb | 250 | { |
7659150c PO |
251 | unsigned long flags; |
252 | size_t blksize, len, chunk; | |
7244b85b | 253 | u32 uninitialized_var(scratch); |
7659150c | 254 | u8 *buf; |
d129bceb | 255 | |
a406f5a3 | 256 | DBG("PIO reading\n"); |
d129bceb | 257 | |
a406f5a3 | 258 | blksize = host->data->blksz; |
7659150c | 259 | chunk = 0; |
d129bceb | 260 | |
7659150c | 261 | local_irq_save(flags); |
d129bceb | 262 | |
a406f5a3 | 263 | while (blksize) { |
7659150c PO |
264 | if (!sg_miter_next(&host->sg_miter)) |
265 | BUG(); | |
d129bceb | 266 | |
7659150c | 267 | len = min(host->sg_miter.length, blksize); |
d129bceb | 268 | |
7659150c PO |
269 | blksize -= len; |
270 | host->sg_miter.consumed = len; | |
14d836e7 | 271 | |
7659150c | 272 | buf = host->sg_miter.addr; |
d129bceb | 273 | |
7659150c PO |
274 | while (len) { |
275 | if (chunk == 0) { | |
4e4141a5 | 276 | scratch = sdhci_readl(host, SDHCI_BUFFER); |
7659150c | 277 | chunk = 4; |
a406f5a3 | 278 | } |
7659150c PO |
279 | |
280 | *buf = scratch & 0xFF; | |
281 | ||
282 | buf++; | |
283 | scratch >>= 8; | |
284 | chunk--; | |
285 | len--; | |
d129bceb | 286 | } |
a406f5a3 | 287 | } |
7659150c PO |
288 | |
289 | sg_miter_stop(&host->sg_miter); | |
290 | ||
291 | local_irq_restore(flags); | |
a406f5a3 | 292 | } |
d129bceb | 293 | |
a406f5a3 PO |
294 | static void sdhci_write_block_pio(struct sdhci_host *host) |
295 | { | |
7659150c PO |
296 | unsigned long flags; |
297 | size_t blksize, len, chunk; | |
298 | u32 scratch; | |
299 | u8 *buf; | |
d129bceb | 300 | |
a406f5a3 PO |
301 | DBG("PIO writing\n"); |
302 | ||
303 | blksize = host->data->blksz; | |
7659150c PO |
304 | chunk = 0; |
305 | scratch = 0; | |
d129bceb | 306 | |
7659150c | 307 | local_irq_save(flags); |
d129bceb | 308 | |
a406f5a3 | 309 | while (blksize) { |
7659150c PO |
310 | if (!sg_miter_next(&host->sg_miter)) |
311 | BUG(); | |
a406f5a3 | 312 | |
7659150c PO |
313 | len = min(host->sg_miter.length, blksize); |
314 | ||
315 | blksize -= len; | |
316 | host->sg_miter.consumed = len; | |
317 | ||
318 | buf = host->sg_miter.addr; | |
d129bceb | 319 | |
7659150c PO |
320 | while (len) { |
321 | scratch |= (u32)*buf << (chunk * 8); | |
322 | ||
323 | buf++; | |
324 | chunk++; | |
325 | len--; | |
326 | ||
327 | if ((chunk == 4) || ((len == 0) && (blksize == 0))) { | |
4e4141a5 | 328 | sdhci_writel(host, scratch, SDHCI_BUFFER); |
7659150c PO |
329 | chunk = 0; |
330 | scratch = 0; | |
d129bceb | 331 | } |
d129bceb PO |
332 | } |
333 | } | |
7659150c PO |
334 | |
335 | sg_miter_stop(&host->sg_miter); | |
336 | ||
337 | local_irq_restore(flags); | |
a406f5a3 PO |
338 | } |
339 | ||
340 | static void sdhci_transfer_pio(struct sdhci_host *host) | |
341 | { | |
342 | u32 mask; | |
343 | ||
344 | BUG_ON(!host->data); | |
345 | ||
7659150c | 346 | if (host->blocks == 0) |
a406f5a3 PO |
347 | return; |
348 | ||
349 | if (host->data->flags & MMC_DATA_READ) | |
350 | mask = SDHCI_DATA_AVAILABLE; | |
351 | else | |
352 | mask = SDHCI_SPACE_AVAILABLE; | |
353 | ||
4a3cba32 PO |
354 | /* |
355 | * Some controllers (JMicron JMB38x) mess up the buffer bits | |
356 | * for transfers < 4 bytes. As long as it is just one block, | |
357 | * we can ignore the bits. | |
358 | */ | |
359 | if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && | |
360 | (host->data->blocks == 1)) | |
361 | mask = ~0; | |
362 | ||
4e4141a5 | 363 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
3e3bf207 AV |
364 | if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) |
365 | udelay(100); | |
366 | ||
a406f5a3 PO |
367 | if (host->data->flags & MMC_DATA_READ) |
368 | sdhci_read_block_pio(host); | |
369 | else | |
370 | sdhci_write_block_pio(host); | |
d129bceb | 371 | |
7659150c PO |
372 | host->blocks--; |
373 | if (host->blocks == 0) | |
a406f5a3 | 374 | break; |
a406f5a3 | 375 | } |
d129bceb | 376 | |
a406f5a3 | 377 | DBG("PIO transfer complete.\n"); |
d129bceb PO |
378 | } |
379 | ||
2134a922 PO |
380 | static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) |
381 | { | |
382 | local_irq_save(*flags); | |
383 | return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; | |
384 | } | |
385 | ||
386 | static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) | |
387 | { | |
388 | kunmap_atomic(buffer, KM_BIO_SRC_IRQ); | |
389 | local_irq_restore(*flags); | |
390 | } | |
391 | ||
118cd17d BD |
392 | static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) |
393 | { | |
9e506f35 BD |
394 | __le32 *dataddr = (__le32 __force *)(desc + 4); |
395 | __le16 *cmdlen = (__le16 __force *)desc; | |
118cd17d | 396 | |
9e506f35 BD |
397 | /* SDHCI specification says ADMA descriptors should be 4 byte |
398 | * aligned, so using 16 or 32bit operations should be safe. */ | |
118cd17d | 399 | |
9e506f35 BD |
400 | cmdlen[0] = cpu_to_le16(cmd); |
401 | cmdlen[1] = cpu_to_le16(len); | |
402 | ||
403 | dataddr[0] = cpu_to_le32(addr); | |
118cd17d BD |
404 | } |
405 | ||
8f1934ce | 406 | static int sdhci_adma_table_pre(struct sdhci_host *host, |
2134a922 PO |
407 | struct mmc_data *data) |
408 | { | |
409 | int direction; | |
410 | ||
411 | u8 *desc; | |
412 | u8 *align; | |
413 | dma_addr_t addr; | |
414 | dma_addr_t align_addr; | |
415 | int len, offset; | |
416 | ||
417 | struct scatterlist *sg; | |
418 | int i; | |
419 | char *buffer; | |
420 | unsigned long flags; | |
421 | ||
422 | /* | |
423 | * The spec does not specify endianness of descriptor table. | |
424 | * We currently guess that it is LE. | |
425 | */ | |
426 | ||
427 | if (data->flags & MMC_DATA_READ) | |
428 | direction = DMA_FROM_DEVICE; | |
429 | else | |
430 | direction = DMA_TO_DEVICE; | |
431 | ||
432 | /* | |
433 | * The ADMA descriptor table is mapped further down as we | |
434 | * need to fill it with data first. | |
435 | */ | |
436 | ||
437 | host->align_addr = dma_map_single(mmc_dev(host->mmc), | |
438 | host->align_buffer, 128 * 4, direction); | |
8d8bb39b | 439 | if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) |
8f1934ce | 440 | goto fail; |
2134a922 PO |
441 | BUG_ON(host->align_addr & 0x3); |
442 | ||
443 | host->sg_count = dma_map_sg(mmc_dev(host->mmc), | |
444 | data->sg, data->sg_len, direction); | |
8f1934ce PO |
445 | if (host->sg_count == 0) |
446 | goto unmap_align; | |
2134a922 PO |
447 | |
448 | desc = host->adma_desc; | |
449 | align = host->align_buffer; | |
450 | ||
451 | align_addr = host->align_addr; | |
452 | ||
453 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
454 | addr = sg_dma_address(sg); | |
455 | len = sg_dma_len(sg); | |
456 | ||
457 | /* | |
458 | * The SDHCI specification states that ADMA | |
459 | * addresses must be 32-bit aligned. If they | |
460 | * aren't, then we use a bounce buffer for | |
461 | * the (up to three) bytes that screw up the | |
462 | * alignment. | |
463 | */ | |
464 | offset = (4 - (addr & 0x3)) & 0x3; | |
465 | if (offset) { | |
466 | if (data->flags & MMC_DATA_WRITE) { | |
467 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 468 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
469 | memcpy(align, buffer, offset); |
470 | sdhci_kunmap_atomic(buffer, &flags); | |
471 | } | |
472 | ||
118cd17d BD |
473 | /* tran, valid */ |
474 | sdhci_set_adma_desc(desc, align_addr, offset, 0x21); | |
2134a922 PO |
475 | |
476 | BUG_ON(offset > 65536); | |
477 | ||
2134a922 PO |
478 | align += 4; |
479 | align_addr += 4; | |
480 | ||
481 | desc += 8; | |
482 | ||
483 | addr += offset; | |
484 | len -= offset; | |
485 | } | |
486 | ||
2134a922 PO |
487 | BUG_ON(len > 65536); |
488 | ||
118cd17d BD |
489 | /* tran, valid */ |
490 | sdhci_set_adma_desc(desc, addr, len, 0x21); | |
2134a922 PO |
491 | desc += 8; |
492 | ||
493 | /* | |
494 | * If this triggers then we have a calculation bug | |
495 | * somewhere. :/ | |
496 | */ | |
497 | WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); | |
498 | } | |
499 | ||
70764a90 TA |
500 | if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { |
501 | /* | |
502 | * Mark the last descriptor as the terminating descriptor | |
503 | */ | |
504 | if (desc != host->adma_desc) { | |
505 | desc -= 8; | |
506 | desc[0] |= 0x2; /* end */ | |
507 | } | |
508 | } else { | |
509 | /* | |
510 | * Add a terminating entry. | |
511 | */ | |
2134a922 | 512 | |
70764a90 TA |
513 | /* nop, end, valid */ |
514 | sdhci_set_adma_desc(desc, 0, 0, 0x3); | |
515 | } | |
2134a922 PO |
516 | |
517 | /* | |
518 | * Resync align buffer as we might have changed it. | |
519 | */ | |
520 | if (data->flags & MMC_DATA_WRITE) { | |
521 | dma_sync_single_for_device(mmc_dev(host->mmc), | |
522 | host->align_addr, 128 * 4, direction); | |
523 | } | |
524 | ||
525 | host->adma_addr = dma_map_single(mmc_dev(host->mmc), | |
526 | host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE); | |
980167b7 | 527 | if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr)) |
8f1934ce | 528 | goto unmap_entries; |
2134a922 | 529 | BUG_ON(host->adma_addr & 0x3); |
8f1934ce PO |
530 | |
531 | return 0; | |
532 | ||
533 | unmap_entries: | |
534 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
535 | data->sg_len, direction); | |
536 | unmap_align: | |
537 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
538 | 128 * 4, direction); | |
539 | fail: | |
540 | return -EINVAL; | |
2134a922 PO |
541 | } |
542 | ||
543 | static void sdhci_adma_table_post(struct sdhci_host *host, | |
544 | struct mmc_data *data) | |
545 | { | |
546 | int direction; | |
547 | ||
548 | struct scatterlist *sg; | |
549 | int i, size; | |
550 | u8 *align; | |
551 | char *buffer; | |
552 | unsigned long flags; | |
553 | ||
554 | if (data->flags & MMC_DATA_READ) | |
555 | direction = DMA_FROM_DEVICE; | |
556 | else | |
557 | direction = DMA_TO_DEVICE; | |
558 | ||
559 | dma_unmap_single(mmc_dev(host->mmc), host->adma_addr, | |
560 | (128 * 2 + 1) * 4, DMA_TO_DEVICE); | |
561 | ||
562 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
563 | 128 * 4, direction); | |
564 | ||
565 | if (data->flags & MMC_DATA_READ) { | |
566 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, | |
567 | data->sg_len, direction); | |
568 | ||
569 | align = host->align_buffer; | |
570 | ||
571 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
572 | if (sg_dma_address(sg) & 0x3) { | |
573 | size = 4 - (sg_dma_address(sg) & 0x3); | |
574 | ||
575 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 576 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
577 | memcpy(buffer, align, size); |
578 | sdhci_kunmap_atomic(buffer, &flags); | |
579 | ||
580 | align += 4; | |
581 | } | |
582 | } | |
583 | } | |
584 | ||
585 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
586 | data->sg_len, direction); | |
587 | } | |
588 | ||
ee53ab5d | 589 | static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data) |
d129bceb | 590 | { |
1c8cde92 PO |
591 | u8 count; |
592 | unsigned target_timeout, current_timeout; | |
d129bceb | 593 | |
ee53ab5d PO |
594 | /* |
595 | * If the host controller provides us with an incorrect timeout | |
596 | * value, just skip the check and use 0xE. The hardware may take | |
597 | * longer to time out, but that's much better than having a too-short | |
598 | * timeout value. | |
599 | */ | |
11a2f1b7 | 600 | if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) |
ee53ab5d | 601 | return 0xE; |
e538fbe8 | 602 | |
1c8cde92 PO |
603 | /* timeout in us */ |
604 | target_timeout = data->timeout_ns / 1000 + | |
605 | data->timeout_clks / host->clock; | |
d129bceb | 606 | |
81b39802 AV |
607 | if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) |
608 | host->timeout_clk = host->clock / 1000; | |
609 | ||
1c8cde92 PO |
610 | /* |
611 | * Figure out needed cycles. | |
612 | * We do this in steps in order to fit inside a 32 bit int. | |
613 | * The first step is the minimum timeout, which will have a | |
614 | * minimum resolution of 6 bits: | |
615 | * (1) 2^13*1000 > 2^22, | |
616 | * (2) host->timeout_clk < 2^16 | |
617 | * => | |
618 | * (1) / (2) > 2^6 | |
619 | */ | |
620 | count = 0; | |
621 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; | |
622 | while (current_timeout < target_timeout) { | |
623 | count++; | |
624 | current_timeout <<= 1; | |
625 | if (count >= 0xF) | |
626 | break; | |
627 | } | |
628 | ||
629 | if (count >= 0xF) { | |
630 | printk(KERN_WARNING "%s: Too large timeout requested!\n", | |
631 | mmc_hostname(host->mmc)); | |
632 | count = 0xE; | |
633 | } | |
634 | ||
ee53ab5d PO |
635 | return count; |
636 | } | |
637 | ||
6aa943ab AV |
638 | static void sdhci_set_transfer_irqs(struct sdhci_host *host) |
639 | { | |
640 | u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; | |
641 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; | |
642 | ||
643 | if (host->flags & SDHCI_REQ_USE_DMA) | |
644 | sdhci_clear_set_irqs(host, pio_irqs, dma_irqs); | |
645 | else | |
646 | sdhci_clear_set_irqs(host, dma_irqs, pio_irqs); | |
647 | } | |
648 | ||
ee53ab5d PO |
649 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) |
650 | { | |
651 | u8 count; | |
2134a922 | 652 | u8 ctrl; |
8f1934ce | 653 | int ret; |
ee53ab5d PO |
654 | |
655 | WARN_ON(host->data); | |
656 | ||
657 | if (data == NULL) | |
658 | return; | |
659 | ||
660 | /* Sanity checks */ | |
661 | BUG_ON(data->blksz * data->blocks > 524288); | |
662 | BUG_ON(data->blksz > host->mmc->max_blk_size); | |
663 | BUG_ON(data->blocks > 65535); | |
664 | ||
665 | host->data = data; | |
666 | host->data_early = 0; | |
667 | ||
668 | count = sdhci_calc_timeout(host, data); | |
4e4141a5 | 669 | sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); |
d129bceb | 670 | |
a13abc7b | 671 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) |
c9fddbc4 PO |
672 | host->flags |= SDHCI_REQ_USE_DMA; |
673 | ||
2134a922 PO |
674 | /* |
675 | * FIXME: This doesn't account for merging when mapping the | |
676 | * scatterlist. | |
677 | */ | |
678 | if (host->flags & SDHCI_REQ_USE_DMA) { | |
679 | int broken, i; | |
680 | struct scatterlist *sg; | |
681 | ||
682 | broken = 0; | |
683 | if (host->flags & SDHCI_USE_ADMA) { | |
684 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
685 | broken = 1; | |
686 | } else { | |
687 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) | |
688 | broken = 1; | |
689 | } | |
690 | ||
691 | if (unlikely(broken)) { | |
692 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
693 | if (sg->length & 0x3) { | |
694 | DBG("Reverting to PIO because of " | |
695 | "transfer size (%d)\n", | |
696 | sg->length); | |
697 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
698 | break; | |
699 | } | |
700 | } | |
701 | } | |
c9fddbc4 PO |
702 | } |
703 | ||
704 | /* | |
705 | * The assumption here being that alignment is the same after | |
706 | * translation to device address space. | |
707 | */ | |
2134a922 PO |
708 | if (host->flags & SDHCI_REQ_USE_DMA) { |
709 | int broken, i; | |
710 | struct scatterlist *sg; | |
711 | ||
712 | broken = 0; | |
713 | if (host->flags & SDHCI_USE_ADMA) { | |
714 | /* | |
715 | * As we use 3 byte chunks to work around | |
716 | * alignment problems, we need to check this | |
717 | * quirk. | |
718 | */ | |
719 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
720 | broken = 1; | |
721 | } else { | |
722 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) | |
723 | broken = 1; | |
724 | } | |
725 | ||
726 | if (unlikely(broken)) { | |
727 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
728 | if (sg->offset & 0x3) { | |
729 | DBG("Reverting to PIO because of " | |
730 | "bad alignment\n"); | |
731 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
732 | break; | |
733 | } | |
734 | } | |
735 | } | |
736 | } | |
737 | ||
8f1934ce PO |
738 | if (host->flags & SDHCI_REQ_USE_DMA) { |
739 | if (host->flags & SDHCI_USE_ADMA) { | |
740 | ret = sdhci_adma_table_pre(host, data); | |
741 | if (ret) { | |
742 | /* | |
743 | * This only happens when someone fed | |
744 | * us an invalid request. | |
745 | */ | |
746 | WARN_ON(1); | |
ebd6d357 | 747 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 748 | } else { |
4e4141a5 AV |
749 | sdhci_writel(host, host->adma_addr, |
750 | SDHCI_ADMA_ADDRESS); | |
8f1934ce PO |
751 | } |
752 | } else { | |
c8b3e02e | 753 | int sg_cnt; |
8f1934ce | 754 | |
c8b3e02e | 755 | sg_cnt = dma_map_sg(mmc_dev(host->mmc), |
8f1934ce PO |
756 | data->sg, data->sg_len, |
757 | (data->flags & MMC_DATA_READ) ? | |
758 | DMA_FROM_DEVICE : | |
759 | DMA_TO_DEVICE); | |
c8b3e02e | 760 | if (sg_cnt == 0) { |
8f1934ce PO |
761 | /* |
762 | * This only happens when someone fed | |
763 | * us an invalid request. | |
764 | */ | |
765 | WARN_ON(1); | |
ebd6d357 | 766 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 767 | } else { |
719a61b4 | 768 | WARN_ON(sg_cnt != 1); |
4e4141a5 AV |
769 | sdhci_writel(host, sg_dma_address(data->sg), |
770 | SDHCI_DMA_ADDRESS); | |
8f1934ce PO |
771 | } |
772 | } | |
773 | } | |
774 | ||
2134a922 PO |
775 | /* |
776 | * Always adjust the DMA selection as some controllers | |
777 | * (e.g. JMicron) can't do PIO properly when the selection | |
778 | * is ADMA. | |
779 | */ | |
780 | if (host->version >= SDHCI_SPEC_200) { | |
4e4141a5 | 781 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
2134a922 PO |
782 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
783 | if ((host->flags & SDHCI_REQ_USE_DMA) && | |
784 | (host->flags & SDHCI_USE_ADMA)) | |
785 | ctrl |= SDHCI_CTRL_ADMA32; | |
786 | else | |
787 | ctrl |= SDHCI_CTRL_SDMA; | |
4e4141a5 | 788 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
c9fddbc4 PO |
789 | } |
790 | ||
8f1934ce | 791 | if (!(host->flags & SDHCI_REQ_USE_DMA)) { |
da60a91d SAS |
792 | int flags; |
793 | ||
794 | flags = SG_MITER_ATOMIC; | |
795 | if (host->data->flags & MMC_DATA_READ) | |
796 | flags |= SG_MITER_TO_SG; | |
797 | else | |
798 | flags |= SG_MITER_FROM_SG; | |
799 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
7659150c | 800 | host->blocks = data->blocks; |
d129bceb | 801 | } |
c7fa9963 | 802 | |
6aa943ab AV |
803 | sdhci_set_transfer_irqs(host); |
804 | ||
bab76961 | 805 | /* We do not handle DMA boundaries, so set it to max (512 KiB) */ |
4e4141a5 AV |
806 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE); |
807 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); | |
c7fa9963 PO |
808 | } |
809 | ||
810 | static void sdhci_set_transfer_mode(struct sdhci_host *host, | |
811 | struct mmc_data *data) | |
812 | { | |
813 | u16 mode; | |
814 | ||
c7fa9963 PO |
815 | if (data == NULL) |
816 | return; | |
817 | ||
e538fbe8 PO |
818 | WARN_ON(!host->data); |
819 | ||
c7fa9963 | 820 | mode = SDHCI_TRNS_BLK_CNT_EN; |
c4512f79 JH |
821 | if (data->blocks > 1) { |
822 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) | |
823 | mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12; | |
824 | else | |
825 | mode |= SDHCI_TRNS_MULTI; | |
826 | } | |
c7fa9963 PO |
827 | if (data->flags & MMC_DATA_READ) |
828 | mode |= SDHCI_TRNS_READ; | |
c9fddbc4 | 829 | if (host->flags & SDHCI_REQ_USE_DMA) |
c7fa9963 PO |
830 | mode |= SDHCI_TRNS_DMA; |
831 | ||
4e4141a5 | 832 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
d129bceb PO |
833 | } |
834 | ||
835 | static void sdhci_finish_data(struct sdhci_host *host) | |
836 | { | |
837 | struct mmc_data *data; | |
d129bceb PO |
838 | |
839 | BUG_ON(!host->data); | |
840 | ||
841 | data = host->data; | |
842 | host->data = NULL; | |
843 | ||
c9fddbc4 | 844 | if (host->flags & SDHCI_REQ_USE_DMA) { |
2134a922 PO |
845 | if (host->flags & SDHCI_USE_ADMA) |
846 | sdhci_adma_table_post(host, data); | |
847 | else { | |
848 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
849 | data->sg_len, (data->flags & MMC_DATA_READ) ? | |
850 | DMA_FROM_DEVICE : DMA_TO_DEVICE); | |
851 | } | |
d129bceb PO |
852 | } |
853 | ||
854 | /* | |
c9b74c5b PO |
855 | * The specification states that the block count register must |
856 | * be updated, but it does not specify at what point in the | |
857 | * data flow. That makes the register entirely useless to read | |
858 | * back so we have to assume that nothing made it to the card | |
859 | * in the event of an error. | |
d129bceb | 860 | */ |
c9b74c5b PO |
861 | if (data->error) |
862 | data->bytes_xfered = 0; | |
d129bceb | 863 | else |
c9b74c5b | 864 | data->bytes_xfered = data->blksz * data->blocks; |
d129bceb | 865 | |
d129bceb PO |
866 | if (data->stop) { |
867 | /* | |
868 | * The controller needs a reset of internal state machines | |
869 | * upon error conditions. | |
870 | */ | |
17b0429d | 871 | if (data->error) { |
d129bceb PO |
872 | sdhci_reset(host, SDHCI_RESET_CMD); |
873 | sdhci_reset(host, SDHCI_RESET_DATA); | |
874 | } | |
875 | ||
876 | sdhci_send_command(host, data->stop); | |
877 | } else | |
878 | tasklet_schedule(&host->finish_tasklet); | |
879 | } | |
880 | ||
881 | static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) | |
882 | { | |
883 | int flags; | |
fd2208d7 | 884 | u32 mask; |
7cb2c76f | 885 | unsigned long timeout; |
d129bceb PO |
886 | |
887 | WARN_ON(host->cmd); | |
888 | ||
d129bceb | 889 | /* Wait max 10 ms */ |
7cb2c76f | 890 | timeout = 10; |
fd2208d7 PO |
891 | |
892 | mask = SDHCI_CMD_INHIBIT; | |
893 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) | |
894 | mask |= SDHCI_DATA_INHIBIT; | |
895 | ||
896 | /* We shouldn't wait for data inihibit for stop commands, even | |
897 | though they might use busy signaling */ | |
898 | if (host->mrq->data && (cmd == host->mrq->data->stop)) | |
899 | mask &= ~SDHCI_DATA_INHIBIT; | |
900 | ||
4e4141a5 | 901 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
7cb2c76f | 902 | if (timeout == 0) { |
d129bceb | 903 | printk(KERN_ERR "%s: Controller never released " |
acf1da45 | 904 | "inhibit bit(s).\n", mmc_hostname(host->mmc)); |
d129bceb | 905 | sdhci_dumpregs(host); |
17b0429d | 906 | cmd->error = -EIO; |
d129bceb PO |
907 | tasklet_schedule(&host->finish_tasklet); |
908 | return; | |
909 | } | |
7cb2c76f PO |
910 | timeout--; |
911 | mdelay(1); | |
912 | } | |
d129bceb PO |
913 | |
914 | mod_timer(&host->timer, jiffies + 10 * HZ); | |
915 | ||
916 | host->cmd = cmd; | |
917 | ||
918 | sdhci_prepare_data(host, cmd->data); | |
919 | ||
4e4141a5 | 920 | sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); |
d129bceb | 921 | |
c7fa9963 PO |
922 | sdhci_set_transfer_mode(host, cmd->data); |
923 | ||
d129bceb | 924 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
acf1da45 | 925 | printk(KERN_ERR "%s: Unsupported response type!\n", |
d129bceb | 926 | mmc_hostname(host->mmc)); |
17b0429d | 927 | cmd->error = -EINVAL; |
d129bceb PO |
928 | tasklet_schedule(&host->finish_tasklet); |
929 | return; | |
930 | } | |
931 | ||
932 | if (!(cmd->flags & MMC_RSP_PRESENT)) | |
933 | flags = SDHCI_CMD_RESP_NONE; | |
934 | else if (cmd->flags & MMC_RSP_136) | |
935 | flags = SDHCI_CMD_RESP_LONG; | |
936 | else if (cmd->flags & MMC_RSP_BUSY) | |
937 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
938 | else | |
939 | flags = SDHCI_CMD_RESP_SHORT; | |
940 | ||
941 | if (cmd->flags & MMC_RSP_CRC) | |
942 | flags |= SDHCI_CMD_CRC; | |
943 | if (cmd->flags & MMC_RSP_OPCODE) | |
944 | flags |= SDHCI_CMD_INDEX; | |
945 | if (cmd->data) | |
946 | flags |= SDHCI_CMD_DATA; | |
947 | ||
4e4141a5 | 948 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); |
d129bceb PO |
949 | } |
950 | ||
951 | static void sdhci_finish_command(struct sdhci_host *host) | |
952 | { | |
953 | int i; | |
954 | ||
955 | BUG_ON(host->cmd == NULL); | |
956 | ||
957 | if (host->cmd->flags & MMC_RSP_PRESENT) { | |
958 | if (host->cmd->flags & MMC_RSP_136) { | |
959 | /* CRC is stripped so we need to do some shifting. */ | |
960 | for (i = 0;i < 4;i++) { | |
4e4141a5 | 961 | host->cmd->resp[i] = sdhci_readl(host, |
d129bceb PO |
962 | SDHCI_RESPONSE + (3-i)*4) << 8; |
963 | if (i != 3) | |
964 | host->cmd->resp[i] |= | |
4e4141a5 | 965 | sdhci_readb(host, |
d129bceb PO |
966 | SDHCI_RESPONSE + (3-i)*4-1); |
967 | } | |
968 | } else { | |
4e4141a5 | 969 | host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); |
d129bceb PO |
970 | } |
971 | } | |
972 | ||
17b0429d | 973 | host->cmd->error = 0; |
d129bceb | 974 | |
e538fbe8 PO |
975 | if (host->data && host->data_early) |
976 | sdhci_finish_data(host); | |
977 | ||
978 | if (!host->cmd->data) | |
d129bceb PO |
979 | tasklet_schedule(&host->finish_tasklet); |
980 | ||
981 | host->cmd = NULL; | |
982 | } | |
983 | ||
984 | static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) | |
985 | { | |
986 | int div; | |
987 | u16 clk; | |
7cb2c76f | 988 | unsigned long timeout; |
d129bceb PO |
989 | |
990 | if (clock == host->clock) | |
991 | return; | |
992 | ||
8114634c AV |
993 | if (host->ops->set_clock) { |
994 | host->ops->set_clock(host, clock); | |
995 | if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) | |
996 | return; | |
997 | } | |
998 | ||
4e4141a5 | 999 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
1000 | |
1001 | if (clock == 0) | |
1002 | goto out; | |
1003 | ||
85105c53 ZG |
1004 | if (host->version >= SDHCI_SPEC_300) { |
1005 | /* Version 3.00 divisors must be a multiple of 2. */ | |
1006 | if (host->max_clk <= clock) | |
1007 | div = 1; | |
1008 | else { | |
1009 | for (div = 2; div < 2046; div += 2) { | |
1010 | if ((host->max_clk / div) <= clock) | |
1011 | break; | |
1012 | } | |
1013 | } | |
1014 | } else { | |
1015 | /* Version 2.00 divisors must be a power of 2. */ | |
1016 | for (div = 1; div < 256; div *= 2) { | |
1017 | if ((host->max_clk / div) <= clock) | |
1018 | break; | |
1019 | } | |
d129bceb PO |
1020 | } |
1021 | div >>= 1; | |
1022 | ||
85105c53 ZG |
1023 | clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; |
1024 | clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) | |
1025 | << SDHCI_DIVIDER_HI_SHIFT; | |
d129bceb | 1026 | clk |= SDHCI_CLOCK_INT_EN; |
4e4141a5 | 1027 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb | 1028 | |
27f6cb16 CB |
1029 | /* Wait max 20 ms */ |
1030 | timeout = 20; | |
4e4141a5 | 1031 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
7cb2c76f PO |
1032 | & SDHCI_CLOCK_INT_STABLE)) { |
1033 | if (timeout == 0) { | |
acf1da45 PO |
1034 | printk(KERN_ERR "%s: Internal clock never " |
1035 | "stabilised.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
1036 | sdhci_dumpregs(host); |
1037 | return; | |
1038 | } | |
7cb2c76f PO |
1039 | timeout--; |
1040 | mdelay(1); | |
1041 | } | |
d129bceb PO |
1042 | |
1043 | clk |= SDHCI_CLOCK_CARD_EN; | |
4e4141a5 | 1044 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
1045 | |
1046 | out: | |
1047 | host->clock = clock; | |
1048 | } | |
1049 | ||
146ad66e PO |
1050 | static void sdhci_set_power(struct sdhci_host *host, unsigned short power) |
1051 | { | |
1052 | u8 pwr; | |
1053 | ||
ae628903 PO |
1054 | if (power == (unsigned short)-1) |
1055 | pwr = 0; | |
1056 | else { | |
1057 | switch (1 << power) { | |
1058 | case MMC_VDD_165_195: | |
1059 | pwr = SDHCI_POWER_180; | |
1060 | break; | |
1061 | case MMC_VDD_29_30: | |
1062 | case MMC_VDD_30_31: | |
1063 | pwr = SDHCI_POWER_300; | |
1064 | break; | |
1065 | case MMC_VDD_32_33: | |
1066 | case MMC_VDD_33_34: | |
1067 | pwr = SDHCI_POWER_330; | |
1068 | break; | |
1069 | default: | |
1070 | BUG(); | |
1071 | } | |
1072 | } | |
1073 | ||
1074 | if (host->pwr == pwr) | |
146ad66e PO |
1075 | return; |
1076 | ||
ae628903 PO |
1077 | host->pwr = pwr; |
1078 | ||
1079 | if (pwr == 0) { | |
4e4141a5 | 1080 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
ae628903 | 1081 | return; |
9e9dc5f2 DS |
1082 | } |
1083 | ||
1084 | /* | |
1085 | * Spec says that we should clear the power reg before setting | |
1086 | * a new value. Some controllers don't seem to like this though. | |
1087 | */ | |
b8c86fc5 | 1088 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) |
4e4141a5 | 1089 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
146ad66e | 1090 | |
e08c1694 | 1091 | /* |
c71f6512 | 1092 | * At least the Marvell CaFe chip gets confused if we set the voltage |
e08c1694 AS |
1093 | * and set turn on power at the same time, so set the voltage first. |
1094 | */ | |
11a2f1b7 | 1095 | if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) |
ae628903 | 1096 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
e08c1694 | 1097 | |
ae628903 | 1098 | pwr |= SDHCI_POWER_ON; |
146ad66e | 1099 | |
ae628903 | 1100 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
557b0697 HW |
1101 | |
1102 | /* | |
1103 | * Some controllers need an extra 10ms delay of 10ms before they | |
1104 | * can apply clock after applying power | |
1105 | */ | |
11a2f1b7 | 1106 | if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) |
557b0697 | 1107 | mdelay(10); |
146ad66e PO |
1108 | } |
1109 | ||
d129bceb PO |
1110 | /*****************************************************************************\ |
1111 | * * | |
1112 | * MMC callbacks * | |
1113 | * * | |
1114 | \*****************************************************************************/ | |
1115 | ||
1116 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1117 | { | |
1118 | struct sdhci_host *host; | |
68d1fb7e | 1119 | bool present; |
d129bceb PO |
1120 | unsigned long flags; |
1121 | ||
1122 | host = mmc_priv(mmc); | |
1123 | ||
1124 | spin_lock_irqsave(&host->lock, flags); | |
1125 | ||
1126 | WARN_ON(host->mrq != NULL); | |
1127 | ||
f9134319 | 1128 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1129 | sdhci_activate_led(host); |
2f730fec | 1130 | #endif |
c4512f79 JH |
1131 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) { |
1132 | if (mrq->stop) { | |
1133 | mrq->data->stop = NULL; | |
1134 | mrq->stop = NULL; | |
1135 | } | |
1136 | } | |
d129bceb PO |
1137 | |
1138 | host->mrq = mrq; | |
1139 | ||
68d1fb7e AV |
1140 | /* If polling, assume that the card is always present. */ |
1141 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) | |
1142 | present = true; | |
1143 | else | |
1144 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
1145 | SDHCI_CARD_PRESENT; | |
1146 | ||
1147 | if (!present || host->flags & SDHCI_DEVICE_DEAD) { | |
17b0429d | 1148 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb PO |
1149 | tasklet_schedule(&host->finish_tasklet); |
1150 | } else | |
1151 | sdhci_send_command(host, mrq->cmd); | |
1152 | ||
5f25a66f | 1153 | mmiowb(); |
d129bceb PO |
1154 | spin_unlock_irqrestore(&host->lock, flags); |
1155 | } | |
1156 | ||
1157 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1158 | { | |
1159 | struct sdhci_host *host; | |
1160 | unsigned long flags; | |
1161 | u8 ctrl; | |
1162 | ||
1163 | host = mmc_priv(mmc); | |
1164 | ||
1165 | spin_lock_irqsave(&host->lock, flags); | |
1166 | ||
1e72859e PO |
1167 | if (host->flags & SDHCI_DEVICE_DEAD) |
1168 | goto out; | |
1169 | ||
d129bceb PO |
1170 | /* |
1171 | * Reset the chip on each power off. | |
1172 | * Should clear out any weird states. | |
1173 | */ | |
1174 | if (ios->power_mode == MMC_POWER_OFF) { | |
4e4141a5 | 1175 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
7260cf5e | 1176 | sdhci_reinit(host); |
d129bceb PO |
1177 | } |
1178 | ||
1179 | sdhci_set_clock(host, ios->clock); | |
1180 | ||
1181 | if (ios->power_mode == MMC_POWER_OFF) | |
146ad66e | 1182 | sdhci_set_power(host, -1); |
d129bceb | 1183 | else |
146ad66e | 1184 | sdhci_set_power(host, ios->vdd); |
d129bceb | 1185 | |
4e4141a5 | 1186 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
cd9277c0 | 1187 | |
ae6d6c92 KP |
1188 | if (ios->bus_width == MMC_BUS_WIDTH_8) |
1189 | ctrl |= SDHCI_CTRL_8BITBUS; | |
1190 | else | |
1191 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
1192 | ||
d129bceb PO |
1193 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
1194 | ctrl |= SDHCI_CTRL_4BITBUS; | |
1195 | else | |
1196 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
cd9277c0 | 1197 | |
51932501 KP |
1198 | if (ios->timing == MMC_TIMING_SD_HS && |
1199 | !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) | |
cd9277c0 PO |
1200 | ctrl |= SDHCI_CTRL_HISPD; |
1201 | else | |
1202 | ctrl &= ~SDHCI_CTRL_HISPD; | |
1203 | ||
4e4141a5 | 1204 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb | 1205 | |
b8352260 LD |
1206 | /* |
1207 | * Some (ENE) controllers go apeshit on some ios operation, | |
1208 | * signalling timeout and CRC errors even on CMD0. Resetting | |
1209 | * it on each ios seems to solve the problem. | |
1210 | */ | |
b8c86fc5 | 1211 | if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
b8352260 LD |
1212 | sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
1213 | ||
1e72859e | 1214 | out: |
5f25a66f | 1215 | mmiowb(); |
d129bceb PO |
1216 | spin_unlock_irqrestore(&host->lock, flags); |
1217 | } | |
1218 | ||
1219 | static int sdhci_get_ro(struct mmc_host *mmc) | |
1220 | { | |
1221 | struct sdhci_host *host; | |
1222 | unsigned long flags; | |
1223 | int present; | |
1224 | ||
1225 | host = mmc_priv(mmc); | |
1226 | ||
1227 | spin_lock_irqsave(&host->lock, flags); | |
1228 | ||
1e72859e PO |
1229 | if (host->flags & SDHCI_DEVICE_DEAD) |
1230 | present = 0; | |
1231 | else | |
4e4141a5 | 1232 | present = sdhci_readl(host, SDHCI_PRESENT_STATE); |
d129bceb PO |
1233 | |
1234 | spin_unlock_irqrestore(&host->lock, flags); | |
1235 | ||
c5075a10 AV |
1236 | if (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT) |
1237 | return !!(present & SDHCI_WRITE_PROTECT); | |
d129bceb PO |
1238 | return !(present & SDHCI_WRITE_PROTECT); |
1239 | } | |
1240 | ||
f75979b7 PO |
1241 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
1242 | { | |
1243 | struct sdhci_host *host; | |
1244 | unsigned long flags; | |
f75979b7 PO |
1245 | |
1246 | host = mmc_priv(mmc); | |
1247 | ||
1248 | spin_lock_irqsave(&host->lock, flags); | |
1249 | ||
1e72859e PO |
1250 | if (host->flags & SDHCI_DEVICE_DEAD) |
1251 | goto out; | |
1252 | ||
f75979b7 | 1253 | if (enable) |
7260cf5e AV |
1254 | sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT); |
1255 | else | |
1256 | sdhci_mask_irqs(host, SDHCI_INT_CARD_INT); | |
1e72859e | 1257 | out: |
f75979b7 PO |
1258 | mmiowb(); |
1259 | ||
1260 | spin_unlock_irqrestore(&host->lock, flags); | |
1261 | } | |
1262 | ||
ab7aefd0 | 1263 | static const struct mmc_host_ops sdhci_ops = { |
d129bceb PO |
1264 | .request = sdhci_request, |
1265 | .set_ios = sdhci_set_ios, | |
1266 | .get_ro = sdhci_get_ro, | |
f75979b7 | 1267 | .enable_sdio_irq = sdhci_enable_sdio_irq, |
d129bceb PO |
1268 | }; |
1269 | ||
1270 | /*****************************************************************************\ | |
1271 | * * | |
1272 | * Tasklets * | |
1273 | * * | |
1274 | \*****************************************************************************/ | |
1275 | ||
1276 | static void sdhci_tasklet_card(unsigned long param) | |
1277 | { | |
1278 | struct sdhci_host *host; | |
1279 | unsigned long flags; | |
1280 | ||
1281 | host = (struct sdhci_host*)param; | |
1282 | ||
1283 | spin_lock_irqsave(&host->lock, flags); | |
1284 | ||
4e4141a5 | 1285 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { |
d129bceb PO |
1286 | if (host->mrq) { |
1287 | printk(KERN_ERR "%s: Card removed during transfer!\n", | |
1288 | mmc_hostname(host->mmc)); | |
1289 | printk(KERN_ERR "%s: Resetting controller.\n", | |
1290 | mmc_hostname(host->mmc)); | |
1291 | ||
1292 | sdhci_reset(host, SDHCI_RESET_CMD); | |
1293 | sdhci_reset(host, SDHCI_RESET_DATA); | |
1294 | ||
17b0429d | 1295 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb PO |
1296 | tasklet_schedule(&host->finish_tasklet); |
1297 | } | |
1298 | } | |
1299 | ||
1300 | spin_unlock_irqrestore(&host->lock, flags); | |
1301 | ||
04cf585d | 1302 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); |
d129bceb PO |
1303 | } |
1304 | ||
1305 | static void sdhci_tasklet_finish(unsigned long param) | |
1306 | { | |
1307 | struct sdhci_host *host; | |
1308 | unsigned long flags; | |
1309 | struct mmc_request *mrq; | |
1310 | ||
1311 | host = (struct sdhci_host*)param; | |
1312 | ||
1313 | spin_lock_irqsave(&host->lock, flags); | |
1314 | ||
1315 | del_timer(&host->timer); | |
1316 | ||
1317 | mrq = host->mrq; | |
1318 | ||
d129bceb PO |
1319 | /* |
1320 | * The controller needs a reset of internal state machines | |
1321 | * upon error conditions. | |
1322 | */ | |
1e72859e PO |
1323 | if (!(host->flags & SDHCI_DEVICE_DEAD) && |
1324 | (mrq->cmd->error || | |
1325 | (mrq->data && (mrq->data->error || | |
1326 | (mrq->data->stop && mrq->data->stop->error))) || | |
1327 | (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { | |
645289dc PO |
1328 | |
1329 | /* Some controllers need this kick or reset won't work here */ | |
b8c86fc5 | 1330 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { |
645289dc PO |
1331 | unsigned int clock; |
1332 | ||
1333 | /* This is to force an update */ | |
1334 | clock = host->clock; | |
1335 | host->clock = 0; | |
1336 | sdhci_set_clock(host, clock); | |
1337 | } | |
1338 | ||
1339 | /* Spec says we should do both at the same time, but Ricoh | |
1340 | controllers do not like that. */ | |
d129bceb PO |
1341 | sdhci_reset(host, SDHCI_RESET_CMD); |
1342 | sdhci_reset(host, SDHCI_RESET_DATA); | |
1343 | } | |
1344 | ||
1345 | host->mrq = NULL; | |
1346 | host->cmd = NULL; | |
1347 | host->data = NULL; | |
1348 | ||
f9134319 | 1349 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1350 | sdhci_deactivate_led(host); |
2f730fec | 1351 | #endif |
d129bceb | 1352 | |
5f25a66f | 1353 | mmiowb(); |
d129bceb PO |
1354 | spin_unlock_irqrestore(&host->lock, flags); |
1355 | ||
1356 | mmc_request_done(host->mmc, mrq); | |
1357 | } | |
1358 | ||
1359 | static void sdhci_timeout_timer(unsigned long data) | |
1360 | { | |
1361 | struct sdhci_host *host; | |
1362 | unsigned long flags; | |
1363 | ||
1364 | host = (struct sdhci_host*)data; | |
1365 | ||
1366 | spin_lock_irqsave(&host->lock, flags); | |
1367 | ||
1368 | if (host->mrq) { | |
acf1da45 PO |
1369 | printk(KERN_ERR "%s: Timeout waiting for hardware " |
1370 | "interrupt.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
1371 | sdhci_dumpregs(host); |
1372 | ||
1373 | if (host->data) { | |
17b0429d | 1374 | host->data->error = -ETIMEDOUT; |
d129bceb PO |
1375 | sdhci_finish_data(host); |
1376 | } else { | |
1377 | if (host->cmd) | |
17b0429d | 1378 | host->cmd->error = -ETIMEDOUT; |
d129bceb | 1379 | else |
17b0429d | 1380 | host->mrq->cmd->error = -ETIMEDOUT; |
d129bceb PO |
1381 | |
1382 | tasklet_schedule(&host->finish_tasklet); | |
1383 | } | |
1384 | } | |
1385 | ||
5f25a66f | 1386 | mmiowb(); |
d129bceb PO |
1387 | spin_unlock_irqrestore(&host->lock, flags); |
1388 | } | |
1389 | ||
1390 | /*****************************************************************************\ | |
1391 | * * | |
1392 | * Interrupt handling * | |
1393 | * * | |
1394 | \*****************************************************************************/ | |
1395 | ||
1396 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) | |
1397 | { | |
1398 | BUG_ON(intmask == 0); | |
1399 | ||
1400 | if (!host->cmd) { | |
b67ac3f3 PO |
1401 | printk(KERN_ERR "%s: Got command interrupt 0x%08x even " |
1402 | "though no command operation was in progress.\n", | |
1403 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
1404 | sdhci_dumpregs(host); |
1405 | return; | |
1406 | } | |
1407 | ||
43b58b36 | 1408 | if (intmask & SDHCI_INT_TIMEOUT) |
17b0429d PO |
1409 | host->cmd->error = -ETIMEDOUT; |
1410 | else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | | |
1411 | SDHCI_INT_INDEX)) | |
1412 | host->cmd->error = -EILSEQ; | |
43b58b36 | 1413 | |
e809517f | 1414 | if (host->cmd->error) { |
d129bceb | 1415 | tasklet_schedule(&host->finish_tasklet); |
e809517f PO |
1416 | return; |
1417 | } | |
1418 | ||
1419 | /* | |
1420 | * The host can send and interrupt when the busy state has | |
1421 | * ended, allowing us to wait without wasting CPU cycles. | |
1422 | * Unfortunately this is overloaded on the "data complete" | |
1423 | * interrupt, so we need to take some care when handling | |
1424 | * it. | |
1425 | * | |
1426 | * Note: The 1.0 specification is a bit ambiguous about this | |
1427 | * feature so there might be some problems with older | |
1428 | * controllers. | |
1429 | */ | |
1430 | if (host->cmd->flags & MMC_RSP_BUSY) { | |
1431 | if (host->cmd->data) | |
1432 | DBG("Cannot wait for busy signal when also " | |
1433 | "doing a data transfer"); | |
f945405c | 1434 | else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) |
e809517f | 1435 | return; |
f945405c BD |
1436 | |
1437 | /* The controller does not support the end-of-busy IRQ, | |
1438 | * fall through and take the SDHCI_INT_RESPONSE */ | |
e809517f PO |
1439 | } |
1440 | ||
1441 | if (intmask & SDHCI_INT_RESPONSE) | |
43b58b36 | 1442 | sdhci_finish_command(host); |
d129bceb PO |
1443 | } |
1444 | ||
0957c333 | 1445 | #ifdef CONFIG_MMC_DEBUG |
6882a8c0 BD |
1446 | static void sdhci_show_adma_error(struct sdhci_host *host) |
1447 | { | |
1448 | const char *name = mmc_hostname(host->mmc); | |
1449 | u8 *desc = host->adma_desc; | |
1450 | __le32 *dma; | |
1451 | __le16 *len; | |
1452 | u8 attr; | |
1453 | ||
1454 | sdhci_dumpregs(host); | |
1455 | ||
1456 | while (true) { | |
1457 | dma = (__le32 *)(desc + 4); | |
1458 | len = (__le16 *)(desc + 2); | |
1459 | attr = *desc; | |
1460 | ||
1461 | DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", | |
1462 | name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); | |
1463 | ||
1464 | desc += 8; | |
1465 | ||
1466 | if (attr & 2) | |
1467 | break; | |
1468 | } | |
1469 | } | |
1470 | #else | |
1471 | static void sdhci_show_adma_error(struct sdhci_host *host) { } | |
1472 | #endif | |
1473 | ||
d129bceb PO |
1474 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) |
1475 | { | |
1476 | BUG_ON(intmask == 0); | |
1477 | ||
1478 | if (!host->data) { | |
1479 | /* | |
e809517f PO |
1480 | * The "data complete" interrupt is also used to |
1481 | * indicate that a busy state has ended. See comment | |
1482 | * above in sdhci_cmd_irq(). | |
d129bceb | 1483 | */ |
e809517f PO |
1484 | if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { |
1485 | if (intmask & SDHCI_INT_DATA_END) { | |
1486 | sdhci_finish_command(host); | |
1487 | return; | |
1488 | } | |
1489 | } | |
d129bceb | 1490 | |
b67ac3f3 PO |
1491 | printk(KERN_ERR "%s: Got data interrupt 0x%08x even " |
1492 | "though no data operation was in progress.\n", | |
1493 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
1494 | sdhci_dumpregs(host); |
1495 | ||
1496 | return; | |
1497 | } | |
1498 | ||
1499 | if (intmask & SDHCI_INT_DATA_TIMEOUT) | |
17b0429d PO |
1500 | host->data->error = -ETIMEDOUT; |
1501 | else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) | |
1502 | host->data->error = -EILSEQ; | |
6882a8c0 BD |
1503 | else if (intmask & SDHCI_INT_ADMA_ERROR) { |
1504 | printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc)); | |
1505 | sdhci_show_adma_error(host); | |
2134a922 | 1506 | host->data->error = -EIO; |
6882a8c0 | 1507 | } |
d129bceb | 1508 | |
17b0429d | 1509 | if (host->data->error) |
d129bceb PO |
1510 | sdhci_finish_data(host); |
1511 | else { | |
a406f5a3 | 1512 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
d129bceb PO |
1513 | sdhci_transfer_pio(host); |
1514 | ||
6ba736a1 PO |
1515 | /* |
1516 | * We currently don't do anything fancy with DMA | |
1517 | * boundaries, but as we can't disable the feature | |
1518 | * we need to at least restart the transfer. | |
1519 | */ | |
1520 | if (intmask & SDHCI_INT_DMA_END) | |
4e4141a5 AV |
1521 | sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS), |
1522 | SDHCI_DMA_ADDRESS); | |
6ba736a1 | 1523 | |
e538fbe8 PO |
1524 | if (intmask & SDHCI_INT_DATA_END) { |
1525 | if (host->cmd) { | |
1526 | /* | |
1527 | * Data managed to finish before the | |
1528 | * command completed. Make sure we do | |
1529 | * things in the proper order. | |
1530 | */ | |
1531 | host->data_early = 1; | |
1532 | } else { | |
1533 | sdhci_finish_data(host); | |
1534 | } | |
1535 | } | |
d129bceb PO |
1536 | } |
1537 | } | |
1538 | ||
7d12e780 | 1539 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
d129bceb PO |
1540 | { |
1541 | irqreturn_t result; | |
1542 | struct sdhci_host* host = dev_id; | |
1543 | u32 intmask; | |
f75979b7 | 1544 | int cardint = 0; |
d129bceb PO |
1545 | |
1546 | spin_lock(&host->lock); | |
1547 | ||
4e4141a5 | 1548 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
d129bceb | 1549 | |
62df67a5 | 1550 | if (!intmask || intmask == 0xffffffff) { |
d129bceb PO |
1551 | result = IRQ_NONE; |
1552 | goto out; | |
1553 | } | |
1554 | ||
b69c9058 PO |
1555 | DBG("*** %s got interrupt: 0x%08x\n", |
1556 | mmc_hostname(host->mmc), intmask); | |
d129bceb | 1557 | |
3192a28f | 1558 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
4e4141a5 AV |
1559 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | |
1560 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); | |
d129bceb | 1561 | tasklet_schedule(&host->card_tasklet); |
3192a28f | 1562 | } |
d129bceb | 1563 | |
3192a28f | 1564 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); |
d129bceb | 1565 | |
3192a28f | 1566 | if (intmask & SDHCI_INT_CMD_MASK) { |
4e4141a5 AV |
1567 | sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, |
1568 | SDHCI_INT_STATUS); | |
3192a28f | 1569 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); |
d129bceb PO |
1570 | } |
1571 | ||
1572 | if (intmask & SDHCI_INT_DATA_MASK) { | |
4e4141a5 AV |
1573 | sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK, |
1574 | SDHCI_INT_STATUS); | |
3192a28f | 1575 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); |
d129bceb PO |
1576 | } |
1577 | ||
1578 | intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); | |
1579 | ||
964f9ce2 PO |
1580 | intmask &= ~SDHCI_INT_ERROR; |
1581 | ||
d129bceb | 1582 | if (intmask & SDHCI_INT_BUS_POWER) { |
3192a28f | 1583 | printk(KERN_ERR "%s: Card is consuming too much power!\n", |
d129bceb | 1584 | mmc_hostname(host->mmc)); |
4e4141a5 | 1585 | sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS); |
d129bceb PO |
1586 | } |
1587 | ||
9d26a5d3 | 1588 | intmask &= ~SDHCI_INT_BUS_POWER; |
3192a28f | 1589 | |
f75979b7 PO |
1590 | if (intmask & SDHCI_INT_CARD_INT) |
1591 | cardint = 1; | |
1592 | ||
1593 | intmask &= ~SDHCI_INT_CARD_INT; | |
1594 | ||
3192a28f | 1595 | if (intmask) { |
acf1da45 | 1596 | printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n", |
3192a28f | 1597 | mmc_hostname(host->mmc), intmask); |
d129bceb PO |
1598 | sdhci_dumpregs(host); |
1599 | ||
4e4141a5 | 1600 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); |
3192a28f | 1601 | } |
d129bceb PO |
1602 | |
1603 | result = IRQ_HANDLED; | |
1604 | ||
5f25a66f | 1605 | mmiowb(); |
d129bceb PO |
1606 | out: |
1607 | spin_unlock(&host->lock); | |
1608 | ||
f75979b7 PO |
1609 | /* |
1610 | * We have to delay this as it calls back into the driver. | |
1611 | */ | |
1612 | if (cardint) | |
1613 | mmc_signal_sdio_irq(host->mmc); | |
1614 | ||
d129bceb PO |
1615 | return result; |
1616 | } | |
1617 | ||
1618 | /*****************************************************************************\ | |
1619 | * * | |
1620 | * Suspend/resume * | |
1621 | * * | |
1622 | \*****************************************************************************/ | |
1623 | ||
1624 | #ifdef CONFIG_PM | |
1625 | ||
b8c86fc5 | 1626 | int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state) |
d129bceb | 1627 | { |
b8c86fc5 | 1628 | int ret; |
a715dfc7 | 1629 | |
7260cf5e AV |
1630 | sdhci_disable_card_detection(host); |
1631 | ||
1a13f8fa | 1632 | ret = mmc_suspend_host(host->mmc); |
b8c86fc5 PO |
1633 | if (ret) |
1634 | return ret; | |
a715dfc7 | 1635 | |
b8c86fc5 | 1636 | free_irq(host->irq, host); |
d129bceb | 1637 | |
9bea3c85 MS |
1638 | if (host->vmmc) |
1639 | ret = regulator_disable(host->vmmc); | |
1640 | ||
1641 | return ret; | |
d129bceb PO |
1642 | } |
1643 | ||
b8c86fc5 | 1644 | EXPORT_SYMBOL_GPL(sdhci_suspend_host); |
d129bceb | 1645 | |
b8c86fc5 PO |
1646 | int sdhci_resume_host(struct sdhci_host *host) |
1647 | { | |
1648 | int ret; | |
d129bceb | 1649 | |
9bea3c85 MS |
1650 | if (host->vmmc) { |
1651 | int ret = regulator_enable(host->vmmc); | |
1652 | if (ret) | |
1653 | return ret; | |
1654 | } | |
1655 | ||
1656 | ||
a13abc7b | 1657 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
1658 | if (host->ops->enable_dma) |
1659 | host->ops->enable_dma(host); | |
1660 | } | |
d129bceb | 1661 | |
b8c86fc5 PO |
1662 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
1663 | mmc_hostname(host->mmc), host); | |
df1c4b7b PO |
1664 | if (ret) |
1665 | return ret; | |
d129bceb | 1666 | |
2f4cbb3d | 1667 | sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); |
b8c86fc5 PO |
1668 | mmiowb(); |
1669 | ||
1670 | ret = mmc_resume_host(host->mmc); | |
7260cf5e AV |
1671 | sdhci_enable_card_detection(host); |
1672 | ||
2f4cbb3d | 1673 | return ret; |
d129bceb PO |
1674 | } |
1675 | ||
b8c86fc5 | 1676 | EXPORT_SYMBOL_GPL(sdhci_resume_host); |
d129bceb PO |
1677 | |
1678 | #endif /* CONFIG_PM */ | |
1679 | ||
1680 | /*****************************************************************************\ | |
1681 | * * | |
b8c86fc5 | 1682 | * Device allocation/registration * |
d129bceb PO |
1683 | * * |
1684 | \*****************************************************************************/ | |
1685 | ||
b8c86fc5 PO |
1686 | struct sdhci_host *sdhci_alloc_host(struct device *dev, |
1687 | size_t priv_size) | |
d129bceb | 1688 | { |
d129bceb PO |
1689 | struct mmc_host *mmc; |
1690 | struct sdhci_host *host; | |
1691 | ||
b8c86fc5 | 1692 | WARN_ON(dev == NULL); |
d129bceb | 1693 | |
b8c86fc5 | 1694 | mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); |
d129bceb | 1695 | if (!mmc) |
b8c86fc5 | 1696 | return ERR_PTR(-ENOMEM); |
d129bceb PO |
1697 | |
1698 | host = mmc_priv(mmc); | |
1699 | host->mmc = mmc; | |
1700 | ||
b8c86fc5 PO |
1701 | return host; |
1702 | } | |
8a4da143 | 1703 | |
b8c86fc5 | 1704 | EXPORT_SYMBOL_GPL(sdhci_alloc_host); |
d129bceb | 1705 | |
b8c86fc5 PO |
1706 | int sdhci_add_host(struct sdhci_host *host) |
1707 | { | |
1708 | struct mmc_host *mmc; | |
1709 | unsigned int caps; | |
b8c86fc5 | 1710 | int ret; |
d129bceb | 1711 | |
b8c86fc5 PO |
1712 | WARN_ON(host == NULL); |
1713 | if (host == NULL) | |
1714 | return -EINVAL; | |
d129bceb | 1715 | |
b8c86fc5 | 1716 | mmc = host->mmc; |
d129bceb | 1717 | |
b8c86fc5 PO |
1718 | if (debug_quirks) |
1719 | host->quirks = debug_quirks; | |
d129bceb | 1720 | |
d96649ed PO |
1721 | sdhci_reset(host, SDHCI_RESET_ALL); |
1722 | ||
4e4141a5 | 1723 | host->version = sdhci_readw(host, SDHCI_HOST_VERSION); |
2134a922 PO |
1724 | host->version = (host->version & SDHCI_SPEC_VER_MASK) |
1725 | >> SDHCI_SPEC_VER_SHIFT; | |
85105c53 | 1726 | if (host->version > SDHCI_SPEC_300) { |
4a965505 | 1727 | printk(KERN_ERR "%s: Unknown controller version (%d). " |
b69c9058 | 1728 | "You may experience problems.\n", mmc_hostname(mmc), |
2134a922 | 1729 | host->version); |
4a965505 PO |
1730 | } |
1731 | ||
ccc92c23 ML |
1732 | caps = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : |
1733 | sdhci_readl(host, SDHCI_CAPABILITIES); | |
d129bceb | 1734 | |
b8c86fc5 | 1735 | if (host->quirks & SDHCI_QUIRK_FORCE_DMA) |
a13abc7b RR |
1736 | host->flags |= SDHCI_USE_SDMA; |
1737 | else if (!(caps & SDHCI_CAN_DO_SDMA)) | |
1738 | DBG("Controller doesn't have SDMA capability\n"); | |
67435274 | 1739 | else |
a13abc7b | 1740 | host->flags |= SDHCI_USE_SDMA; |
d129bceb | 1741 | |
b8c86fc5 | 1742 | if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
a13abc7b | 1743 | (host->flags & SDHCI_USE_SDMA)) { |
cee687ce | 1744 | DBG("Disabling DMA as it is marked broken\n"); |
a13abc7b | 1745 | host->flags &= ~SDHCI_USE_SDMA; |
7c168e3d FT |
1746 | } |
1747 | ||
a13abc7b RR |
1748 | if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2)) |
1749 | host->flags |= SDHCI_USE_ADMA; | |
2134a922 PO |
1750 | |
1751 | if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && | |
1752 | (host->flags & SDHCI_USE_ADMA)) { | |
1753 | DBG("Disabling ADMA as it is marked broken\n"); | |
1754 | host->flags &= ~SDHCI_USE_ADMA; | |
1755 | } | |
1756 | ||
a13abc7b | 1757 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
1758 | if (host->ops->enable_dma) { |
1759 | if (host->ops->enable_dma(host)) { | |
1760 | printk(KERN_WARNING "%s: No suitable DMA " | |
1761 | "available. Falling back to PIO.\n", | |
1762 | mmc_hostname(mmc)); | |
a13abc7b RR |
1763 | host->flags &= |
1764 | ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); | |
b8c86fc5 | 1765 | } |
d129bceb PO |
1766 | } |
1767 | } | |
1768 | ||
2134a922 PO |
1769 | if (host->flags & SDHCI_USE_ADMA) { |
1770 | /* | |
1771 | * We need to allocate descriptors for all sg entries | |
1772 | * (128) and potentially one alignment transfer for | |
1773 | * each of those entries. | |
1774 | */ | |
1775 | host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL); | |
1776 | host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); | |
1777 | if (!host->adma_desc || !host->align_buffer) { | |
1778 | kfree(host->adma_desc); | |
1779 | kfree(host->align_buffer); | |
1780 | printk(KERN_WARNING "%s: Unable to allocate ADMA " | |
1781 | "buffers. Falling back to standard DMA.\n", | |
1782 | mmc_hostname(mmc)); | |
1783 | host->flags &= ~SDHCI_USE_ADMA; | |
1784 | } | |
1785 | } | |
1786 | ||
7659150c PO |
1787 | /* |
1788 | * If we use DMA, then it's up to the caller to set the DMA | |
1789 | * mask, but PIO does not need the hw shim so we set a new | |
1790 | * mask here in that case. | |
1791 | */ | |
a13abc7b | 1792 | if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { |
7659150c PO |
1793 | host->dma_mask = DMA_BIT_MASK(64); |
1794 | mmc_dev(host->mmc)->dma_mask = &host->dma_mask; | |
1795 | } | |
d129bceb | 1796 | |
c4687d5f ZG |
1797 | if (host->version >= SDHCI_SPEC_300) |
1798 | host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) | |
1799 | >> SDHCI_CLOCK_BASE_SHIFT; | |
1800 | else | |
1801 | host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) | |
1802 | >> SDHCI_CLOCK_BASE_SHIFT; | |
1803 | ||
4240ff0a | 1804 | host->max_clk *= 1000000; |
f27f47ef AV |
1805 | if (host->max_clk == 0 || host->quirks & |
1806 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { | |
4240ff0a BD |
1807 | if (!host->ops->get_max_clock) { |
1808 | printk(KERN_ERR | |
1809 | "%s: Hardware doesn't specify base clock " | |
1810 | "frequency.\n", mmc_hostname(mmc)); | |
1811 | return -ENODEV; | |
1812 | } | |
1813 | host->max_clk = host->ops->get_max_clock(host); | |
8ef1a143 | 1814 | } |
d129bceb | 1815 | |
1c8cde92 PO |
1816 | host->timeout_clk = |
1817 | (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; | |
1818 | if (host->timeout_clk == 0) { | |
81b39802 AV |
1819 | if (host->ops->get_timeout_clock) { |
1820 | host->timeout_clk = host->ops->get_timeout_clock(host); | |
1821 | } else if (!(host->quirks & | |
1822 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { | |
4240ff0a BD |
1823 | printk(KERN_ERR |
1824 | "%s: Hardware doesn't specify timeout clock " | |
1825 | "frequency.\n", mmc_hostname(mmc)); | |
1826 | return -ENODEV; | |
1827 | } | |
1c8cde92 PO |
1828 | } |
1829 | if (caps & SDHCI_TIMEOUT_CLK_UNIT) | |
1830 | host->timeout_clk *= 1000; | |
d129bceb PO |
1831 | |
1832 | /* | |
1833 | * Set host parameters. | |
1834 | */ | |
1835 | mmc->ops = &sdhci_ops; | |
ce5f036b | 1836 | if (host->ops->get_min_clock) |
a9e58f25 AV |
1837 | mmc->f_min = host->ops->get_min_clock(host); |
1838 | else | |
1839 | mmc->f_min = host->max_clk / 256; | |
d129bceb | 1840 | mmc->f_max = host->max_clk; |
c1f5977c | 1841 | mmc->caps |= MMC_CAP_SDIO_IRQ; |
5fe23c7f AV |
1842 | |
1843 | if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) | |
1844 | mmc->caps |= MMC_CAP_4_BIT_DATA; | |
d129bceb | 1845 | |
86a6a874 | 1846 | if (caps & SDHCI_CAN_DO_HISPD) |
cd9277c0 PO |
1847 | mmc->caps |= MMC_CAP_SD_HIGHSPEED; |
1848 | ||
68d1fb7e AV |
1849 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) |
1850 | mmc->caps |= MMC_CAP_NEEDS_POLL; | |
1851 | ||
146ad66e PO |
1852 | mmc->ocr_avail = 0; |
1853 | if (caps & SDHCI_CAN_VDD_330) | |
1854 | mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34; | |
c70840e8 | 1855 | if (caps & SDHCI_CAN_VDD_300) |
146ad66e | 1856 | mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31; |
c70840e8 | 1857 | if (caps & SDHCI_CAN_VDD_180) |
55556da0 | 1858 | mmc->ocr_avail |= MMC_VDD_165_195; |
146ad66e PO |
1859 | |
1860 | if (mmc->ocr_avail == 0) { | |
1861 | printk(KERN_ERR "%s: Hardware doesn't report any " | |
b69c9058 | 1862 | "support voltages.\n", mmc_hostname(mmc)); |
b8c86fc5 | 1863 | return -ENODEV; |
146ad66e PO |
1864 | } |
1865 | ||
d129bceb PO |
1866 | spin_lock_init(&host->lock); |
1867 | ||
1868 | /* | |
2134a922 PO |
1869 | * Maximum number of segments. Depends on if the hardware |
1870 | * can do scatter/gather or not. | |
d129bceb | 1871 | */ |
2134a922 | 1872 | if (host->flags & SDHCI_USE_ADMA) |
a36274e0 | 1873 | mmc->max_segs = 128; |
a13abc7b | 1874 | else if (host->flags & SDHCI_USE_SDMA) |
a36274e0 | 1875 | mmc->max_segs = 1; |
2134a922 | 1876 | else /* PIO */ |
a36274e0 | 1877 | mmc->max_segs = 128; |
d129bceb PO |
1878 | |
1879 | /* | |
bab76961 | 1880 | * Maximum number of sectors in one transfer. Limited by DMA boundary |
55db890a | 1881 | * size (512KiB). |
d129bceb | 1882 | */ |
55db890a | 1883 | mmc->max_req_size = 524288; |
d129bceb PO |
1884 | |
1885 | /* | |
1886 | * Maximum segment size. Could be one segment with the maximum number | |
2134a922 PO |
1887 | * of bytes. When doing hardware scatter/gather, each entry cannot |
1888 | * be larger than 64 KiB though. | |
d129bceb | 1889 | */ |
2134a922 PO |
1890 | if (host->flags & SDHCI_USE_ADMA) |
1891 | mmc->max_seg_size = 65536; | |
1892 | else | |
1893 | mmc->max_seg_size = mmc->max_req_size; | |
d129bceb | 1894 | |
fe4a3c7a PO |
1895 | /* |
1896 | * Maximum block size. This varies from controller to controller and | |
1897 | * is specified in the capabilities register. | |
1898 | */ | |
0633f654 AV |
1899 | if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { |
1900 | mmc->max_blk_size = 2; | |
1901 | } else { | |
1902 | mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> | |
1903 | SDHCI_MAX_BLOCK_SHIFT; | |
1904 | if (mmc->max_blk_size >= 3) { | |
1905 | printk(KERN_WARNING "%s: Invalid maximum block size, " | |
1906 | "assuming 512 bytes\n", mmc_hostname(mmc)); | |
1907 | mmc->max_blk_size = 0; | |
1908 | } | |
1909 | } | |
1910 | ||
1911 | mmc->max_blk_size = 512 << mmc->max_blk_size; | |
fe4a3c7a | 1912 | |
55db890a PO |
1913 | /* |
1914 | * Maximum block count. | |
1915 | */ | |
1388eefd | 1916 | mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; |
55db890a | 1917 | |
d129bceb PO |
1918 | /* |
1919 | * Init tasklets. | |
1920 | */ | |
1921 | tasklet_init(&host->card_tasklet, | |
1922 | sdhci_tasklet_card, (unsigned long)host); | |
1923 | tasklet_init(&host->finish_tasklet, | |
1924 | sdhci_tasklet_finish, (unsigned long)host); | |
1925 | ||
e4cad1b5 | 1926 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
d129bceb | 1927 | |
dace1453 | 1928 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
b69c9058 | 1929 | mmc_hostname(mmc), host); |
d129bceb | 1930 | if (ret) |
8ef1a143 | 1931 | goto untasklet; |
d129bceb | 1932 | |
9bea3c85 MS |
1933 | host->vmmc = regulator_get(mmc_dev(mmc), "vmmc"); |
1934 | if (IS_ERR(host->vmmc)) { | |
1935 | printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc)); | |
1936 | host->vmmc = NULL; | |
1937 | } else { | |
1938 | regulator_enable(host->vmmc); | |
1939 | } | |
1940 | ||
2f4cbb3d | 1941 | sdhci_init(host, 0); |
d129bceb PO |
1942 | |
1943 | #ifdef CONFIG_MMC_DEBUG | |
1944 | sdhci_dumpregs(host); | |
1945 | #endif | |
1946 | ||
f9134319 | 1947 | #ifdef SDHCI_USE_LEDS_CLASS |
5dbace0c HS |
1948 | snprintf(host->led_name, sizeof(host->led_name), |
1949 | "%s::", mmc_hostname(mmc)); | |
1950 | host->led.name = host->led_name; | |
2f730fec PO |
1951 | host->led.brightness = LED_OFF; |
1952 | host->led.default_trigger = mmc_hostname(mmc); | |
1953 | host->led.brightness_set = sdhci_led_control; | |
1954 | ||
b8c86fc5 | 1955 | ret = led_classdev_register(mmc_dev(mmc), &host->led); |
2f730fec PO |
1956 | if (ret) |
1957 | goto reset; | |
1958 | #endif | |
1959 | ||
5f25a66f PO |
1960 | mmiowb(); |
1961 | ||
d129bceb PO |
1962 | mmc_add_host(mmc); |
1963 | ||
a13abc7b | 1964 | printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n", |
d1b26863 | 1965 | mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), |
a13abc7b RR |
1966 | (host->flags & SDHCI_USE_ADMA) ? "ADMA" : |
1967 | (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); | |
d129bceb | 1968 | |
7260cf5e AV |
1969 | sdhci_enable_card_detection(host); |
1970 | ||
d129bceb PO |
1971 | return 0; |
1972 | ||
f9134319 | 1973 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
1974 | reset: |
1975 | sdhci_reset(host, SDHCI_RESET_ALL); | |
1976 | free_irq(host->irq, host); | |
1977 | #endif | |
8ef1a143 | 1978 | untasklet: |
d129bceb PO |
1979 | tasklet_kill(&host->card_tasklet); |
1980 | tasklet_kill(&host->finish_tasklet); | |
d129bceb PO |
1981 | |
1982 | return ret; | |
1983 | } | |
1984 | ||
b8c86fc5 | 1985 | EXPORT_SYMBOL_GPL(sdhci_add_host); |
d129bceb | 1986 | |
1e72859e | 1987 | void sdhci_remove_host(struct sdhci_host *host, int dead) |
b8c86fc5 | 1988 | { |
1e72859e PO |
1989 | unsigned long flags; |
1990 | ||
1991 | if (dead) { | |
1992 | spin_lock_irqsave(&host->lock, flags); | |
1993 | ||
1994 | host->flags |= SDHCI_DEVICE_DEAD; | |
1995 | ||
1996 | if (host->mrq) { | |
1997 | printk(KERN_ERR "%s: Controller removed during " | |
1998 | " transfer!\n", mmc_hostname(host->mmc)); | |
1999 | ||
2000 | host->mrq->cmd->error = -ENOMEDIUM; | |
2001 | tasklet_schedule(&host->finish_tasklet); | |
2002 | } | |
2003 | ||
2004 | spin_unlock_irqrestore(&host->lock, flags); | |
2005 | } | |
2006 | ||
7260cf5e AV |
2007 | sdhci_disable_card_detection(host); |
2008 | ||
b8c86fc5 | 2009 | mmc_remove_host(host->mmc); |
d129bceb | 2010 | |
f9134319 | 2011 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
2012 | led_classdev_unregister(&host->led); |
2013 | #endif | |
2014 | ||
1e72859e PO |
2015 | if (!dead) |
2016 | sdhci_reset(host, SDHCI_RESET_ALL); | |
d129bceb PO |
2017 | |
2018 | free_irq(host->irq, host); | |
2019 | ||
2020 | del_timer_sync(&host->timer); | |
2021 | ||
2022 | tasklet_kill(&host->card_tasklet); | |
2023 | tasklet_kill(&host->finish_tasklet); | |
2134a922 | 2024 | |
9bea3c85 MS |
2025 | if (host->vmmc) { |
2026 | regulator_disable(host->vmmc); | |
2027 | regulator_put(host->vmmc); | |
2028 | } | |
2029 | ||
2134a922 PO |
2030 | kfree(host->adma_desc); |
2031 | kfree(host->align_buffer); | |
2032 | ||
2033 | host->adma_desc = NULL; | |
2034 | host->align_buffer = NULL; | |
d129bceb PO |
2035 | } |
2036 | ||
b8c86fc5 | 2037 | EXPORT_SYMBOL_GPL(sdhci_remove_host); |
d129bceb | 2038 | |
b8c86fc5 | 2039 | void sdhci_free_host(struct sdhci_host *host) |
d129bceb | 2040 | { |
b8c86fc5 | 2041 | mmc_free_host(host->mmc); |
d129bceb PO |
2042 | } |
2043 | ||
b8c86fc5 | 2044 | EXPORT_SYMBOL_GPL(sdhci_free_host); |
d129bceb PO |
2045 | |
2046 | /*****************************************************************************\ | |
2047 | * * | |
2048 | * Driver init/exit * | |
2049 | * * | |
2050 | \*****************************************************************************/ | |
2051 | ||
2052 | static int __init sdhci_drv_init(void) | |
2053 | { | |
2054 | printk(KERN_INFO DRIVER_NAME | |
52fbf9c9 | 2055 | ": Secure Digital Host Controller Interface driver\n"); |
d129bceb PO |
2056 | printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
2057 | ||
b8c86fc5 | 2058 | return 0; |
d129bceb PO |
2059 | } |
2060 | ||
2061 | static void __exit sdhci_drv_exit(void) | |
2062 | { | |
d129bceb PO |
2063 | } |
2064 | ||
2065 | module_init(sdhci_drv_init); | |
2066 | module_exit(sdhci_drv_exit); | |
2067 | ||
df673b22 | 2068 | module_param(debug_quirks, uint, 0444); |
67435274 | 2069 | |
32710e8f | 2070 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 | 2071 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); |
d129bceb | 2072 | MODULE_LICENSE("GPL"); |
67435274 | 2073 | |
df673b22 | 2074 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |