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Commit | Line | Data |
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d129bceb | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
d129bceb | 3 | * |
b69c9058 | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
d129bceb PO |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
84c46a53 PO |
10 | * |
11 | * Thanks to the following companies for their support: | |
12 | * | |
13 | * - JMicron (hardware and technical support) | |
d129bceb PO |
14 | */ |
15 | ||
d129bceb PO |
16 | #include <linux/delay.h> |
17 | #include <linux/highmem.h> | |
b8c86fc5 | 18 | #include <linux/io.h> |
d129bceb | 19 | #include <linux/dma-mapping.h> |
11763609 | 20 | #include <linux/scatterlist.h> |
d129bceb | 21 | |
2f730fec PO |
22 | #include <linux/leds.h> |
23 | ||
d129bceb | 24 | #include <linux/mmc/host.h> |
d129bceb | 25 | |
d129bceb PO |
26 | #include "sdhci.h" |
27 | ||
28 | #define DRIVER_NAME "sdhci" | |
d129bceb | 29 | |
d129bceb | 30 | #define DBG(f, x...) \ |
c6563178 | 31 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
d129bceb | 32 | |
f9134319 PO |
33 | #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ |
34 | defined(CONFIG_MMC_SDHCI_MODULE)) | |
35 | #define SDHCI_USE_LEDS_CLASS | |
36 | #endif | |
37 | ||
df673b22 | 38 | static unsigned int debug_quirks = 0; |
67435274 | 39 | |
d129bceb PO |
40 | static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *); |
41 | static void sdhci_finish_data(struct sdhci_host *); | |
42 | ||
43 | static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); | |
44 | static void sdhci_finish_command(struct sdhci_host *); | |
45 | ||
46 | static void sdhci_dumpregs(struct sdhci_host *host) | |
47 | { | |
48 | printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n"); | |
49 | ||
50 | printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", | |
4e4141a5 AV |
51 | sdhci_readl(host, SDHCI_DMA_ADDRESS), |
52 | sdhci_readw(host, SDHCI_HOST_VERSION)); | |
d129bceb | 53 | printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", |
4e4141a5 AV |
54 | sdhci_readw(host, SDHCI_BLOCK_SIZE), |
55 | sdhci_readw(host, SDHCI_BLOCK_COUNT)); | |
d129bceb | 56 | printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", |
4e4141a5 AV |
57 | sdhci_readl(host, SDHCI_ARGUMENT), |
58 | sdhci_readw(host, SDHCI_TRANSFER_MODE)); | |
d129bceb | 59 | printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", |
4e4141a5 AV |
60 | sdhci_readl(host, SDHCI_PRESENT_STATE), |
61 | sdhci_readb(host, SDHCI_HOST_CONTROL)); | |
d129bceb | 62 | printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", |
4e4141a5 AV |
63 | sdhci_readb(host, SDHCI_POWER_CONTROL), |
64 | sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); | |
d129bceb | 65 | printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", |
4e4141a5 AV |
66 | sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), |
67 | sdhci_readw(host, SDHCI_CLOCK_CONTROL)); | |
d129bceb | 68 | printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", |
4e4141a5 AV |
69 | sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), |
70 | sdhci_readl(host, SDHCI_INT_STATUS)); | |
d129bceb | 71 | printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", |
4e4141a5 AV |
72 | sdhci_readl(host, SDHCI_INT_ENABLE), |
73 | sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); | |
d129bceb | 74 | printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", |
4e4141a5 AV |
75 | sdhci_readw(host, SDHCI_ACMD12_ERR), |
76 | sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); | |
d129bceb | 77 | printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n", |
4e4141a5 AV |
78 | sdhci_readl(host, SDHCI_CAPABILITIES), |
79 | sdhci_readl(host, SDHCI_MAX_CURRENT)); | |
d129bceb PO |
80 | |
81 | printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n"); | |
82 | } | |
83 | ||
84 | /*****************************************************************************\ | |
85 | * * | |
86 | * Low level functions * | |
87 | * * | |
88 | \*****************************************************************************/ | |
89 | ||
7260cf5e AV |
90 | static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) |
91 | { | |
92 | u32 ier; | |
93 | ||
94 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); | |
95 | ier &= ~clear; | |
96 | ier |= set; | |
97 | sdhci_writel(host, ier, SDHCI_INT_ENABLE); | |
98 | sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); | |
99 | } | |
100 | ||
101 | static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs) | |
102 | { | |
103 | sdhci_clear_set_irqs(host, 0, irqs); | |
104 | } | |
105 | ||
106 | static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs) | |
107 | { | |
108 | sdhci_clear_set_irqs(host, irqs, 0); | |
109 | } | |
110 | ||
111 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) | |
112 | { | |
113 | u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; | |
114 | ||
68d1fb7e AV |
115 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) |
116 | return; | |
117 | ||
7260cf5e AV |
118 | if (enable) |
119 | sdhci_unmask_irqs(host, irqs); | |
120 | else | |
121 | sdhci_mask_irqs(host, irqs); | |
122 | } | |
123 | ||
124 | static void sdhci_enable_card_detection(struct sdhci_host *host) | |
125 | { | |
126 | sdhci_set_card_detection(host, true); | |
127 | } | |
128 | ||
129 | static void sdhci_disable_card_detection(struct sdhci_host *host) | |
130 | { | |
131 | sdhci_set_card_detection(host, false); | |
132 | } | |
133 | ||
d129bceb PO |
134 | static void sdhci_reset(struct sdhci_host *host, u8 mask) |
135 | { | |
e16514d8 | 136 | unsigned long timeout; |
063a9dbb | 137 | u32 uninitialized_var(ier); |
e16514d8 | 138 | |
b8c86fc5 | 139 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { |
4e4141a5 | 140 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & |
8a4da143 PO |
141 | SDHCI_CARD_PRESENT)) |
142 | return; | |
143 | } | |
144 | ||
063a9dbb AV |
145 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) |
146 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); | |
147 | ||
4e4141a5 | 148 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
d129bceb | 149 | |
e16514d8 | 150 | if (mask & SDHCI_RESET_ALL) |
d129bceb PO |
151 | host->clock = 0; |
152 | ||
e16514d8 PO |
153 | /* Wait max 100 ms */ |
154 | timeout = 100; | |
155 | ||
156 | /* hw clears the bit when it's done */ | |
4e4141a5 | 157 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { |
e16514d8 | 158 | if (timeout == 0) { |
acf1da45 | 159 | printk(KERN_ERR "%s: Reset 0x%x never completed.\n", |
e16514d8 PO |
160 | mmc_hostname(host->mmc), (int)mask); |
161 | sdhci_dumpregs(host); | |
162 | return; | |
163 | } | |
164 | timeout--; | |
165 | mdelay(1); | |
d129bceb | 166 | } |
063a9dbb AV |
167 | |
168 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) | |
169 | sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier); | |
d129bceb PO |
170 | } |
171 | ||
172 | static void sdhci_init(struct sdhci_host *host) | |
173 | { | |
d129bceb PO |
174 | sdhci_reset(host, SDHCI_RESET_ALL); |
175 | ||
7260cf5e AV |
176 | sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, |
177 | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | | |
3192a28f PO |
178 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | |
179 | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | | |
6aa943ab | 180 | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); |
7260cf5e | 181 | } |
d129bceb | 182 | |
7260cf5e AV |
183 | static void sdhci_reinit(struct sdhci_host *host) |
184 | { | |
185 | sdhci_init(host); | |
186 | sdhci_enable_card_detection(host); | |
d129bceb PO |
187 | } |
188 | ||
189 | static void sdhci_activate_led(struct sdhci_host *host) | |
190 | { | |
191 | u8 ctrl; | |
192 | ||
4e4141a5 | 193 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 194 | ctrl |= SDHCI_CTRL_LED; |
4e4141a5 | 195 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
196 | } |
197 | ||
198 | static void sdhci_deactivate_led(struct sdhci_host *host) | |
199 | { | |
200 | u8 ctrl; | |
201 | ||
4e4141a5 | 202 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 203 | ctrl &= ~SDHCI_CTRL_LED; |
4e4141a5 | 204 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
205 | } |
206 | ||
f9134319 | 207 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
208 | static void sdhci_led_control(struct led_classdev *led, |
209 | enum led_brightness brightness) | |
210 | { | |
211 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); | |
212 | unsigned long flags; | |
213 | ||
214 | spin_lock_irqsave(&host->lock, flags); | |
215 | ||
216 | if (brightness == LED_OFF) | |
217 | sdhci_deactivate_led(host); | |
218 | else | |
219 | sdhci_activate_led(host); | |
220 | ||
221 | spin_unlock_irqrestore(&host->lock, flags); | |
222 | } | |
223 | #endif | |
224 | ||
d129bceb PO |
225 | /*****************************************************************************\ |
226 | * * | |
227 | * Core functions * | |
228 | * * | |
229 | \*****************************************************************************/ | |
230 | ||
a406f5a3 | 231 | static void sdhci_read_block_pio(struct sdhci_host *host) |
d129bceb | 232 | { |
7659150c PO |
233 | unsigned long flags; |
234 | size_t blksize, len, chunk; | |
7244b85b | 235 | u32 uninitialized_var(scratch); |
7659150c | 236 | u8 *buf; |
d129bceb | 237 | |
a406f5a3 | 238 | DBG("PIO reading\n"); |
d129bceb | 239 | |
a406f5a3 | 240 | blksize = host->data->blksz; |
7659150c | 241 | chunk = 0; |
d129bceb | 242 | |
7659150c | 243 | local_irq_save(flags); |
d129bceb | 244 | |
a406f5a3 | 245 | while (blksize) { |
7659150c PO |
246 | if (!sg_miter_next(&host->sg_miter)) |
247 | BUG(); | |
d129bceb | 248 | |
7659150c | 249 | len = min(host->sg_miter.length, blksize); |
d129bceb | 250 | |
7659150c PO |
251 | blksize -= len; |
252 | host->sg_miter.consumed = len; | |
14d836e7 | 253 | |
7659150c | 254 | buf = host->sg_miter.addr; |
d129bceb | 255 | |
7659150c PO |
256 | while (len) { |
257 | if (chunk == 0) { | |
4e4141a5 | 258 | scratch = sdhci_readl(host, SDHCI_BUFFER); |
7659150c | 259 | chunk = 4; |
a406f5a3 | 260 | } |
7659150c PO |
261 | |
262 | *buf = scratch & 0xFF; | |
263 | ||
264 | buf++; | |
265 | scratch >>= 8; | |
266 | chunk--; | |
267 | len--; | |
d129bceb | 268 | } |
a406f5a3 | 269 | } |
7659150c PO |
270 | |
271 | sg_miter_stop(&host->sg_miter); | |
272 | ||
273 | local_irq_restore(flags); | |
a406f5a3 | 274 | } |
d129bceb | 275 | |
a406f5a3 PO |
276 | static void sdhci_write_block_pio(struct sdhci_host *host) |
277 | { | |
7659150c PO |
278 | unsigned long flags; |
279 | size_t blksize, len, chunk; | |
280 | u32 scratch; | |
281 | u8 *buf; | |
d129bceb | 282 | |
a406f5a3 PO |
283 | DBG("PIO writing\n"); |
284 | ||
285 | blksize = host->data->blksz; | |
7659150c PO |
286 | chunk = 0; |
287 | scratch = 0; | |
d129bceb | 288 | |
7659150c | 289 | local_irq_save(flags); |
d129bceb | 290 | |
a406f5a3 | 291 | while (blksize) { |
7659150c PO |
292 | if (!sg_miter_next(&host->sg_miter)) |
293 | BUG(); | |
a406f5a3 | 294 | |
7659150c PO |
295 | len = min(host->sg_miter.length, blksize); |
296 | ||
297 | blksize -= len; | |
298 | host->sg_miter.consumed = len; | |
299 | ||
300 | buf = host->sg_miter.addr; | |
d129bceb | 301 | |
7659150c PO |
302 | while (len) { |
303 | scratch |= (u32)*buf << (chunk * 8); | |
304 | ||
305 | buf++; | |
306 | chunk++; | |
307 | len--; | |
308 | ||
309 | if ((chunk == 4) || ((len == 0) && (blksize == 0))) { | |
4e4141a5 | 310 | sdhci_writel(host, scratch, SDHCI_BUFFER); |
7659150c PO |
311 | chunk = 0; |
312 | scratch = 0; | |
d129bceb | 313 | } |
d129bceb PO |
314 | } |
315 | } | |
7659150c PO |
316 | |
317 | sg_miter_stop(&host->sg_miter); | |
318 | ||
319 | local_irq_restore(flags); | |
a406f5a3 PO |
320 | } |
321 | ||
322 | static void sdhci_transfer_pio(struct sdhci_host *host) | |
323 | { | |
324 | u32 mask; | |
325 | ||
326 | BUG_ON(!host->data); | |
327 | ||
7659150c | 328 | if (host->blocks == 0) |
a406f5a3 PO |
329 | return; |
330 | ||
331 | if (host->data->flags & MMC_DATA_READ) | |
332 | mask = SDHCI_DATA_AVAILABLE; | |
333 | else | |
334 | mask = SDHCI_SPACE_AVAILABLE; | |
335 | ||
4a3cba32 PO |
336 | /* |
337 | * Some controllers (JMicron JMB38x) mess up the buffer bits | |
338 | * for transfers < 4 bytes. As long as it is just one block, | |
339 | * we can ignore the bits. | |
340 | */ | |
341 | if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && | |
342 | (host->data->blocks == 1)) | |
343 | mask = ~0; | |
344 | ||
4e4141a5 | 345 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
3e3bf207 AV |
346 | if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) |
347 | udelay(100); | |
348 | ||
a406f5a3 PO |
349 | if (host->data->flags & MMC_DATA_READ) |
350 | sdhci_read_block_pio(host); | |
351 | else | |
352 | sdhci_write_block_pio(host); | |
d129bceb | 353 | |
7659150c PO |
354 | host->blocks--; |
355 | if (host->blocks == 0) | |
a406f5a3 | 356 | break; |
a406f5a3 | 357 | } |
d129bceb | 358 | |
a406f5a3 | 359 | DBG("PIO transfer complete.\n"); |
d129bceb PO |
360 | } |
361 | ||
2134a922 PO |
362 | static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) |
363 | { | |
364 | local_irq_save(*flags); | |
365 | return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; | |
366 | } | |
367 | ||
368 | static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) | |
369 | { | |
370 | kunmap_atomic(buffer, KM_BIO_SRC_IRQ); | |
371 | local_irq_restore(*flags); | |
372 | } | |
373 | ||
8f1934ce | 374 | static int sdhci_adma_table_pre(struct sdhci_host *host, |
2134a922 PO |
375 | struct mmc_data *data) |
376 | { | |
377 | int direction; | |
378 | ||
379 | u8 *desc; | |
380 | u8 *align; | |
381 | dma_addr_t addr; | |
382 | dma_addr_t align_addr; | |
383 | int len, offset; | |
384 | ||
385 | struct scatterlist *sg; | |
386 | int i; | |
387 | char *buffer; | |
388 | unsigned long flags; | |
389 | ||
390 | /* | |
391 | * The spec does not specify endianness of descriptor table. | |
392 | * We currently guess that it is LE. | |
393 | */ | |
394 | ||
395 | if (data->flags & MMC_DATA_READ) | |
396 | direction = DMA_FROM_DEVICE; | |
397 | else | |
398 | direction = DMA_TO_DEVICE; | |
399 | ||
400 | /* | |
401 | * The ADMA descriptor table is mapped further down as we | |
402 | * need to fill it with data first. | |
403 | */ | |
404 | ||
405 | host->align_addr = dma_map_single(mmc_dev(host->mmc), | |
406 | host->align_buffer, 128 * 4, direction); | |
8d8bb39b | 407 | if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) |
8f1934ce | 408 | goto fail; |
2134a922 PO |
409 | BUG_ON(host->align_addr & 0x3); |
410 | ||
411 | host->sg_count = dma_map_sg(mmc_dev(host->mmc), | |
412 | data->sg, data->sg_len, direction); | |
8f1934ce PO |
413 | if (host->sg_count == 0) |
414 | goto unmap_align; | |
2134a922 PO |
415 | |
416 | desc = host->adma_desc; | |
417 | align = host->align_buffer; | |
418 | ||
419 | align_addr = host->align_addr; | |
420 | ||
421 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
422 | addr = sg_dma_address(sg); | |
423 | len = sg_dma_len(sg); | |
424 | ||
425 | /* | |
426 | * The SDHCI specification states that ADMA | |
427 | * addresses must be 32-bit aligned. If they | |
428 | * aren't, then we use a bounce buffer for | |
429 | * the (up to three) bytes that screw up the | |
430 | * alignment. | |
431 | */ | |
432 | offset = (4 - (addr & 0x3)) & 0x3; | |
433 | if (offset) { | |
434 | if (data->flags & MMC_DATA_WRITE) { | |
435 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 436 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
437 | memcpy(align, buffer, offset); |
438 | sdhci_kunmap_atomic(buffer, &flags); | |
439 | } | |
440 | ||
441 | desc[7] = (align_addr >> 24) & 0xff; | |
442 | desc[6] = (align_addr >> 16) & 0xff; | |
443 | desc[5] = (align_addr >> 8) & 0xff; | |
444 | desc[4] = (align_addr >> 0) & 0xff; | |
445 | ||
446 | BUG_ON(offset > 65536); | |
447 | ||
448 | desc[3] = (offset >> 8) & 0xff; | |
449 | desc[2] = (offset >> 0) & 0xff; | |
450 | ||
451 | desc[1] = 0x00; | |
452 | desc[0] = 0x21; /* tran, valid */ | |
453 | ||
454 | align += 4; | |
455 | align_addr += 4; | |
456 | ||
457 | desc += 8; | |
458 | ||
459 | addr += offset; | |
460 | len -= offset; | |
461 | } | |
462 | ||
463 | desc[7] = (addr >> 24) & 0xff; | |
464 | desc[6] = (addr >> 16) & 0xff; | |
465 | desc[5] = (addr >> 8) & 0xff; | |
466 | desc[4] = (addr >> 0) & 0xff; | |
467 | ||
468 | BUG_ON(len > 65536); | |
469 | ||
470 | desc[3] = (len >> 8) & 0xff; | |
471 | desc[2] = (len >> 0) & 0xff; | |
472 | ||
473 | desc[1] = 0x00; | |
474 | desc[0] = 0x21; /* tran, valid */ | |
475 | ||
476 | desc += 8; | |
477 | ||
478 | /* | |
479 | * If this triggers then we have a calculation bug | |
480 | * somewhere. :/ | |
481 | */ | |
482 | WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); | |
483 | } | |
484 | ||
485 | /* | |
486 | * Add a terminating entry. | |
487 | */ | |
488 | desc[7] = 0; | |
489 | desc[6] = 0; | |
490 | desc[5] = 0; | |
491 | desc[4] = 0; | |
492 | ||
493 | desc[3] = 0; | |
494 | desc[2] = 0; | |
495 | ||
496 | desc[1] = 0x00; | |
497 | desc[0] = 0x03; /* nop, end, valid */ | |
498 | ||
499 | /* | |
500 | * Resync align buffer as we might have changed it. | |
501 | */ | |
502 | if (data->flags & MMC_DATA_WRITE) { | |
503 | dma_sync_single_for_device(mmc_dev(host->mmc), | |
504 | host->align_addr, 128 * 4, direction); | |
505 | } | |
506 | ||
507 | host->adma_addr = dma_map_single(mmc_dev(host->mmc), | |
508 | host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE); | |
980167b7 | 509 | if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr)) |
8f1934ce | 510 | goto unmap_entries; |
2134a922 | 511 | BUG_ON(host->adma_addr & 0x3); |
8f1934ce PO |
512 | |
513 | return 0; | |
514 | ||
515 | unmap_entries: | |
516 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
517 | data->sg_len, direction); | |
518 | unmap_align: | |
519 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
520 | 128 * 4, direction); | |
521 | fail: | |
522 | return -EINVAL; | |
2134a922 PO |
523 | } |
524 | ||
525 | static void sdhci_adma_table_post(struct sdhci_host *host, | |
526 | struct mmc_data *data) | |
527 | { | |
528 | int direction; | |
529 | ||
530 | struct scatterlist *sg; | |
531 | int i, size; | |
532 | u8 *align; | |
533 | char *buffer; | |
534 | unsigned long flags; | |
535 | ||
536 | if (data->flags & MMC_DATA_READ) | |
537 | direction = DMA_FROM_DEVICE; | |
538 | else | |
539 | direction = DMA_TO_DEVICE; | |
540 | ||
541 | dma_unmap_single(mmc_dev(host->mmc), host->adma_addr, | |
542 | (128 * 2 + 1) * 4, DMA_TO_DEVICE); | |
543 | ||
544 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
545 | 128 * 4, direction); | |
546 | ||
547 | if (data->flags & MMC_DATA_READ) { | |
548 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, | |
549 | data->sg_len, direction); | |
550 | ||
551 | align = host->align_buffer; | |
552 | ||
553 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
554 | if (sg_dma_address(sg) & 0x3) { | |
555 | size = 4 - (sg_dma_address(sg) & 0x3); | |
556 | ||
557 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 558 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
559 | memcpy(buffer, align, size); |
560 | sdhci_kunmap_atomic(buffer, &flags); | |
561 | ||
562 | align += 4; | |
563 | } | |
564 | } | |
565 | } | |
566 | ||
567 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
568 | data->sg_len, direction); | |
569 | } | |
570 | ||
ee53ab5d | 571 | static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data) |
d129bceb | 572 | { |
1c8cde92 PO |
573 | u8 count; |
574 | unsigned target_timeout, current_timeout; | |
d129bceb | 575 | |
ee53ab5d PO |
576 | /* |
577 | * If the host controller provides us with an incorrect timeout | |
578 | * value, just skip the check and use 0xE. The hardware may take | |
579 | * longer to time out, but that's much better than having a too-short | |
580 | * timeout value. | |
581 | */ | |
582 | if ((host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)) | |
583 | return 0xE; | |
e538fbe8 | 584 | |
1c8cde92 PO |
585 | /* timeout in us */ |
586 | target_timeout = data->timeout_ns / 1000 + | |
587 | data->timeout_clks / host->clock; | |
d129bceb | 588 | |
1c8cde92 PO |
589 | /* |
590 | * Figure out needed cycles. | |
591 | * We do this in steps in order to fit inside a 32 bit int. | |
592 | * The first step is the minimum timeout, which will have a | |
593 | * minimum resolution of 6 bits: | |
594 | * (1) 2^13*1000 > 2^22, | |
595 | * (2) host->timeout_clk < 2^16 | |
596 | * => | |
597 | * (1) / (2) > 2^6 | |
598 | */ | |
599 | count = 0; | |
600 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; | |
601 | while (current_timeout < target_timeout) { | |
602 | count++; | |
603 | current_timeout <<= 1; | |
604 | if (count >= 0xF) | |
605 | break; | |
606 | } | |
607 | ||
608 | if (count >= 0xF) { | |
609 | printk(KERN_WARNING "%s: Too large timeout requested!\n", | |
610 | mmc_hostname(host->mmc)); | |
611 | count = 0xE; | |
612 | } | |
613 | ||
ee53ab5d PO |
614 | return count; |
615 | } | |
616 | ||
6aa943ab AV |
617 | static void sdhci_set_transfer_irqs(struct sdhci_host *host) |
618 | { | |
619 | u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; | |
620 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; | |
621 | ||
622 | if (host->flags & SDHCI_REQ_USE_DMA) | |
623 | sdhci_clear_set_irqs(host, pio_irqs, dma_irqs); | |
624 | else | |
625 | sdhci_clear_set_irqs(host, dma_irqs, pio_irqs); | |
626 | } | |
627 | ||
ee53ab5d PO |
628 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) |
629 | { | |
630 | u8 count; | |
2134a922 | 631 | u8 ctrl; |
8f1934ce | 632 | int ret; |
ee53ab5d PO |
633 | |
634 | WARN_ON(host->data); | |
635 | ||
636 | if (data == NULL) | |
637 | return; | |
638 | ||
639 | /* Sanity checks */ | |
640 | BUG_ON(data->blksz * data->blocks > 524288); | |
641 | BUG_ON(data->blksz > host->mmc->max_blk_size); | |
642 | BUG_ON(data->blocks > 65535); | |
643 | ||
644 | host->data = data; | |
645 | host->data_early = 0; | |
646 | ||
647 | count = sdhci_calc_timeout(host, data); | |
4e4141a5 | 648 | sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); |
d129bceb | 649 | |
c9fddbc4 PO |
650 | if (host->flags & SDHCI_USE_DMA) |
651 | host->flags |= SDHCI_REQ_USE_DMA; | |
652 | ||
2134a922 PO |
653 | /* |
654 | * FIXME: This doesn't account for merging when mapping the | |
655 | * scatterlist. | |
656 | */ | |
657 | if (host->flags & SDHCI_REQ_USE_DMA) { | |
658 | int broken, i; | |
659 | struct scatterlist *sg; | |
660 | ||
661 | broken = 0; | |
662 | if (host->flags & SDHCI_USE_ADMA) { | |
663 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
664 | broken = 1; | |
665 | } else { | |
666 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) | |
667 | broken = 1; | |
668 | } | |
669 | ||
670 | if (unlikely(broken)) { | |
671 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
672 | if (sg->length & 0x3) { | |
673 | DBG("Reverting to PIO because of " | |
674 | "transfer size (%d)\n", | |
675 | sg->length); | |
676 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
677 | break; | |
678 | } | |
679 | } | |
680 | } | |
c9fddbc4 PO |
681 | } |
682 | ||
683 | /* | |
684 | * The assumption here being that alignment is the same after | |
685 | * translation to device address space. | |
686 | */ | |
2134a922 PO |
687 | if (host->flags & SDHCI_REQ_USE_DMA) { |
688 | int broken, i; | |
689 | struct scatterlist *sg; | |
690 | ||
691 | broken = 0; | |
692 | if (host->flags & SDHCI_USE_ADMA) { | |
693 | /* | |
694 | * As we use 3 byte chunks to work around | |
695 | * alignment problems, we need to check this | |
696 | * quirk. | |
697 | */ | |
698 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
699 | broken = 1; | |
700 | } else { | |
701 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) | |
702 | broken = 1; | |
703 | } | |
704 | ||
705 | if (unlikely(broken)) { | |
706 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
707 | if (sg->offset & 0x3) { | |
708 | DBG("Reverting to PIO because of " | |
709 | "bad alignment\n"); | |
710 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
711 | break; | |
712 | } | |
713 | } | |
714 | } | |
715 | } | |
716 | ||
8f1934ce PO |
717 | if (host->flags & SDHCI_REQ_USE_DMA) { |
718 | if (host->flags & SDHCI_USE_ADMA) { | |
719 | ret = sdhci_adma_table_pre(host, data); | |
720 | if (ret) { | |
721 | /* | |
722 | * This only happens when someone fed | |
723 | * us an invalid request. | |
724 | */ | |
725 | WARN_ON(1); | |
ebd6d357 | 726 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 727 | } else { |
4e4141a5 AV |
728 | sdhci_writel(host, host->adma_addr, |
729 | SDHCI_ADMA_ADDRESS); | |
8f1934ce PO |
730 | } |
731 | } else { | |
c8b3e02e | 732 | int sg_cnt; |
8f1934ce | 733 | |
c8b3e02e | 734 | sg_cnt = dma_map_sg(mmc_dev(host->mmc), |
8f1934ce PO |
735 | data->sg, data->sg_len, |
736 | (data->flags & MMC_DATA_READ) ? | |
737 | DMA_FROM_DEVICE : | |
738 | DMA_TO_DEVICE); | |
c8b3e02e | 739 | if (sg_cnt == 0) { |
8f1934ce PO |
740 | /* |
741 | * This only happens when someone fed | |
742 | * us an invalid request. | |
743 | */ | |
744 | WARN_ON(1); | |
ebd6d357 | 745 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 746 | } else { |
719a61b4 | 747 | WARN_ON(sg_cnt != 1); |
4e4141a5 AV |
748 | sdhci_writel(host, sg_dma_address(data->sg), |
749 | SDHCI_DMA_ADDRESS); | |
8f1934ce PO |
750 | } |
751 | } | |
752 | } | |
753 | ||
2134a922 PO |
754 | /* |
755 | * Always adjust the DMA selection as some controllers | |
756 | * (e.g. JMicron) can't do PIO properly when the selection | |
757 | * is ADMA. | |
758 | */ | |
759 | if (host->version >= SDHCI_SPEC_200) { | |
4e4141a5 | 760 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
2134a922 PO |
761 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
762 | if ((host->flags & SDHCI_REQ_USE_DMA) && | |
763 | (host->flags & SDHCI_USE_ADMA)) | |
764 | ctrl |= SDHCI_CTRL_ADMA32; | |
765 | else | |
766 | ctrl |= SDHCI_CTRL_SDMA; | |
4e4141a5 | 767 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
c9fddbc4 PO |
768 | } |
769 | ||
8f1934ce | 770 | if (!(host->flags & SDHCI_REQ_USE_DMA)) { |
7659150c PO |
771 | sg_miter_start(&host->sg_miter, |
772 | data->sg, data->sg_len, SG_MITER_ATOMIC); | |
773 | host->blocks = data->blocks; | |
d129bceb | 774 | } |
c7fa9963 | 775 | |
6aa943ab AV |
776 | sdhci_set_transfer_irqs(host); |
777 | ||
bab76961 | 778 | /* We do not handle DMA boundaries, so set it to max (512 KiB) */ |
4e4141a5 AV |
779 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE); |
780 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); | |
c7fa9963 PO |
781 | } |
782 | ||
783 | static void sdhci_set_transfer_mode(struct sdhci_host *host, | |
784 | struct mmc_data *data) | |
785 | { | |
786 | u16 mode; | |
787 | ||
c7fa9963 PO |
788 | if (data == NULL) |
789 | return; | |
790 | ||
e538fbe8 PO |
791 | WARN_ON(!host->data); |
792 | ||
c7fa9963 PO |
793 | mode = SDHCI_TRNS_BLK_CNT_EN; |
794 | if (data->blocks > 1) | |
795 | mode |= SDHCI_TRNS_MULTI; | |
796 | if (data->flags & MMC_DATA_READ) | |
797 | mode |= SDHCI_TRNS_READ; | |
c9fddbc4 | 798 | if (host->flags & SDHCI_REQ_USE_DMA) |
c7fa9963 PO |
799 | mode |= SDHCI_TRNS_DMA; |
800 | ||
4e4141a5 | 801 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
d129bceb PO |
802 | } |
803 | ||
804 | static void sdhci_finish_data(struct sdhci_host *host) | |
805 | { | |
806 | struct mmc_data *data; | |
d129bceb PO |
807 | |
808 | BUG_ON(!host->data); | |
809 | ||
810 | data = host->data; | |
811 | host->data = NULL; | |
812 | ||
c9fddbc4 | 813 | if (host->flags & SDHCI_REQ_USE_DMA) { |
2134a922 PO |
814 | if (host->flags & SDHCI_USE_ADMA) |
815 | sdhci_adma_table_post(host, data); | |
816 | else { | |
817 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
818 | data->sg_len, (data->flags & MMC_DATA_READ) ? | |
819 | DMA_FROM_DEVICE : DMA_TO_DEVICE); | |
820 | } | |
d129bceb PO |
821 | } |
822 | ||
823 | /* | |
c9b74c5b PO |
824 | * The specification states that the block count register must |
825 | * be updated, but it does not specify at what point in the | |
826 | * data flow. That makes the register entirely useless to read | |
827 | * back so we have to assume that nothing made it to the card | |
828 | * in the event of an error. | |
d129bceb | 829 | */ |
c9b74c5b PO |
830 | if (data->error) |
831 | data->bytes_xfered = 0; | |
d129bceb | 832 | else |
c9b74c5b | 833 | data->bytes_xfered = data->blksz * data->blocks; |
d129bceb | 834 | |
d129bceb PO |
835 | if (data->stop) { |
836 | /* | |
837 | * The controller needs a reset of internal state machines | |
838 | * upon error conditions. | |
839 | */ | |
17b0429d | 840 | if (data->error) { |
d129bceb PO |
841 | sdhci_reset(host, SDHCI_RESET_CMD); |
842 | sdhci_reset(host, SDHCI_RESET_DATA); | |
843 | } | |
844 | ||
845 | sdhci_send_command(host, data->stop); | |
846 | } else | |
847 | tasklet_schedule(&host->finish_tasklet); | |
848 | } | |
849 | ||
850 | static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) | |
851 | { | |
852 | int flags; | |
fd2208d7 | 853 | u32 mask; |
7cb2c76f | 854 | unsigned long timeout; |
d129bceb PO |
855 | |
856 | WARN_ON(host->cmd); | |
857 | ||
d129bceb | 858 | /* Wait max 10 ms */ |
7cb2c76f | 859 | timeout = 10; |
fd2208d7 PO |
860 | |
861 | mask = SDHCI_CMD_INHIBIT; | |
862 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) | |
863 | mask |= SDHCI_DATA_INHIBIT; | |
864 | ||
865 | /* We shouldn't wait for data inihibit for stop commands, even | |
866 | though they might use busy signaling */ | |
867 | if (host->mrq->data && (cmd == host->mrq->data->stop)) | |
868 | mask &= ~SDHCI_DATA_INHIBIT; | |
869 | ||
4e4141a5 | 870 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
7cb2c76f | 871 | if (timeout == 0) { |
d129bceb | 872 | printk(KERN_ERR "%s: Controller never released " |
acf1da45 | 873 | "inhibit bit(s).\n", mmc_hostname(host->mmc)); |
d129bceb | 874 | sdhci_dumpregs(host); |
17b0429d | 875 | cmd->error = -EIO; |
d129bceb PO |
876 | tasklet_schedule(&host->finish_tasklet); |
877 | return; | |
878 | } | |
7cb2c76f PO |
879 | timeout--; |
880 | mdelay(1); | |
881 | } | |
d129bceb PO |
882 | |
883 | mod_timer(&host->timer, jiffies + 10 * HZ); | |
884 | ||
885 | host->cmd = cmd; | |
886 | ||
887 | sdhci_prepare_data(host, cmd->data); | |
888 | ||
4e4141a5 | 889 | sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); |
d129bceb | 890 | |
c7fa9963 PO |
891 | sdhci_set_transfer_mode(host, cmd->data); |
892 | ||
d129bceb | 893 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
acf1da45 | 894 | printk(KERN_ERR "%s: Unsupported response type!\n", |
d129bceb | 895 | mmc_hostname(host->mmc)); |
17b0429d | 896 | cmd->error = -EINVAL; |
d129bceb PO |
897 | tasklet_schedule(&host->finish_tasklet); |
898 | return; | |
899 | } | |
900 | ||
901 | if (!(cmd->flags & MMC_RSP_PRESENT)) | |
902 | flags = SDHCI_CMD_RESP_NONE; | |
903 | else if (cmd->flags & MMC_RSP_136) | |
904 | flags = SDHCI_CMD_RESP_LONG; | |
905 | else if (cmd->flags & MMC_RSP_BUSY) | |
906 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
907 | else | |
908 | flags = SDHCI_CMD_RESP_SHORT; | |
909 | ||
910 | if (cmd->flags & MMC_RSP_CRC) | |
911 | flags |= SDHCI_CMD_CRC; | |
912 | if (cmd->flags & MMC_RSP_OPCODE) | |
913 | flags |= SDHCI_CMD_INDEX; | |
914 | if (cmd->data) | |
915 | flags |= SDHCI_CMD_DATA; | |
916 | ||
4e4141a5 | 917 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); |
d129bceb PO |
918 | } |
919 | ||
920 | static void sdhci_finish_command(struct sdhci_host *host) | |
921 | { | |
922 | int i; | |
923 | ||
924 | BUG_ON(host->cmd == NULL); | |
925 | ||
926 | if (host->cmd->flags & MMC_RSP_PRESENT) { | |
927 | if (host->cmd->flags & MMC_RSP_136) { | |
928 | /* CRC is stripped so we need to do some shifting. */ | |
929 | for (i = 0;i < 4;i++) { | |
4e4141a5 | 930 | host->cmd->resp[i] = sdhci_readl(host, |
d129bceb PO |
931 | SDHCI_RESPONSE + (3-i)*4) << 8; |
932 | if (i != 3) | |
933 | host->cmd->resp[i] |= | |
4e4141a5 | 934 | sdhci_readb(host, |
d129bceb PO |
935 | SDHCI_RESPONSE + (3-i)*4-1); |
936 | } | |
937 | } else { | |
4e4141a5 | 938 | host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); |
d129bceb PO |
939 | } |
940 | } | |
941 | ||
17b0429d | 942 | host->cmd->error = 0; |
d129bceb | 943 | |
e538fbe8 PO |
944 | if (host->data && host->data_early) |
945 | sdhci_finish_data(host); | |
946 | ||
947 | if (!host->cmd->data) | |
d129bceb PO |
948 | tasklet_schedule(&host->finish_tasklet); |
949 | ||
950 | host->cmd = NULL; | |
951 | } | |
952 | ||
953 | static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) | |
954 | { | |
955 | int div; | |
956 | u16 clk; | |
7cb2c76f | 957 | unsigned long timeout; |
d129bceb PO |
958 | |
959 | if (clock == host->clock) | |
960 | return; | |
961 | ||
8114634c AV |
962 | if (host->ops->set_clock) { |
963 | host->ops->set_clock(host, clock); | |
964 | if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) | |
965 | return; | |
966 | } | |
967 | ||
4e4141a5 | 968 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
969 | |
970 | if (clock == 0) | |
971 | goto out; | |
972 | ||
973 | for (div = 1;div < 256;div *= 2) { | |
974 | if ((host->max_clk / div) <= clock) | |
975 | break; | |
976 | } | |
977 | div >>= 1; | |
978 | ||
979 | clk = div << SDHCI_DIVIDER_SHIFT; | |
980 | clk |= SDHCI_CLOCK_INT_EN; | |
4e4141a5 | 981 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
982 | |
983 | /* Wait max 10 ms */ | |
7cb2c76f | 984 | timeout = 10; |
4e4141a5 | 985 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
7cb2c76f PO |
986 | & SDHCI_CLOCK_INT_STABLE)) { |
987 | if (timeout == 0) { | |
acf1da45 PO |
988 | printk(KERN_ERR "%s: Internal clock never " |
989 | "stabilised.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
990 | sdhci_dumpregs(host); |
991 | return; | |
992 | } | |
7cb2c76f PO |
993 | timeout--; |
994 | mdelay(1); | |
995 | } | |
d129bceb PO |
996 | |
997 | clk |= SDHCI_CLOCK_CARD_EN; | |
4e4141a5 | 998 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
999 | |
1000 | out: | |
1001 | host->clock = clock; | |
1002 | } | |
1003 | ||
146ad66e PO |
1004 | static void sdhci_set_power(struct sdhci_host *host, unsigned short power) |
1005 | { | |
1006 | u8 pwr; | |
1007 | ||
ae628903 PO |
1008 | if (power == (unsigned short)-1) |
1009 | pwr = 0; | |
1010 | else { | |
1011 | switch (1 << power) { | |
1012 | case MMC_VDD_165_195: | |
1013 | pwr = SDHCI_POWER_180; | |
1014 | break; | |
1015 | case MMC_VDD_29_30: | |
1016 | case MMC_VDD_30_31: | |
1017 | pwr = SDHCI_POWER_300; | |
1018 | break; | |
1019 | case MMC_VDD_32_33: | |
1020 | case MMC_VDD_33_34: | |
1021 | pwr = SDHCI_POWER_330; | |
1022 | break; | |
1023 | default: | |
1024 | BUG(); | |
1025 | } | |
1026 | } | |
1027 | ||
1028 | if (host->pwr == pwr) | |
146ad66e PO |
1029 | return; |
1030 | ||
ae628903 PO |
1031 | host->pwr = pwr; |
1032 | ||
1033 | if (pwr == 0) { | |
4e4141a5 | 1034 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
ae628903 | 1035 | return; |
9e9dc5f2 DS |
1036 | } |
1037 | ||
1038 | /* | |
1039 | * Spec says that we should clear the power reg before setting | |
1040 | * a new value. Some controllers don't seem to like this though. | |
1041 | */ | |
b8c86fc5 | 1042 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) |
4e4141a5 | 1043 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
146ad66e | 1044 | |
e08c1694 | 1045 | /* |
c71f6512 | 1046 | * At least the Marvell CaFe chip gets confused if we set the voltage |
e08c1694 AS |
1047 | * and set turn on power at the same time, so set the voltage first. |
1048 | */ | |
b8c86fc5 | 1049 | if ((host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)) |
ae628903 | 1050 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
e08c1694 | 1051 | |
ae628903 | 1052 | pwr |= SDHCI_POWER_ON; |
146ad66e | 1053 | |
ae628903 | 1054 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
146ad66e PO |
1055 | } |
1056 | ||
d129bceb PO |
1057 | /*****************************************************************************\ |
1058 | * * | |
1059 | * MMC callbacks * | |
1060 | * * | |
1061 | \*****************************************************************************/ | |
1062 | ||
1063 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1064 | { | |
1065 | struct sdhci_host *host; | |
68d1fb7e | 1066 | bool present; |
d129bceb PO |
1067 | unsigned long flags; |
1068 | ||
1069 | host = mmc_priv(mmc); | |
1070 | ||
1071 | spin_lock_irqsave(&host->lock, flags); | |
1072 | ||
1073 | WARN_ON(host->mrq != NULL); | |
1074 | ||
f9134319 | 1075 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1076 | sdhci_activate_led(host); |
2f730fec | 1077 | #endif |
d129bceb PO |
1078 | |
1079 | host->mrq = mrq; | |
1080 | ||
68d1fb7e AV |
1081 | /* If polling, assume that the card is always present. */ |
1082 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) | |
1083 | present = true; | |
1084 | else | |
1085 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
1086 | SDHCI_CARD_PRESENT; | |
1087 | ||
1088 | if (!present || host->flags & SDHCI_DEVICE_DEAD) { | |
17b0429d | 1089 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb PO |
1090 | tasklet_schedule(&host->finish_tasklet); |
1091 | } else | |
1092 | sdhci_send_command(host, mrq->cmd); | |
1093 | ||
5f25a66f | 1094 | mmiowb(); |
d129bceb PO |
1095 | spin_unlock_irqrestore(&host->lock, flags); |
1096 | } | |
1097 | ||
1098 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1099 | { | |
1100 | struct sdhci_host *host; | |
1101 | unsigned long flags; | |
1102 | u8 ctrl; | |
1103 | ||
1104 | host = mmc_priv(mmc); | |
1105 | ||
1106 | spin_lock_irqsave(&host->lock, flags); | |
1107 | ||
1e72859e PO |
1108 | if (host->flags & SDHCI_DEVICE_DEAD) |
1109 | goto out; | |
1110 | ||
d129bceb PO |
1111 | /* |
1112 | * Reset the chip on each power off. | |
1113 | * Should clear out any weird states. | |
1114 | */ | |
1115 | if (ios->power_mode == MMC_POWER_OFF) { | |
4e4141a5 | 1116 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
7260cf5e | 1117 | sdhci_reinit(host); |
d129bceb PO |
1118 | } |
1119 | ||
1120 | sdhci_set_clock(host, ios->clock); | |
1121 | ||
1122 | if (ios->power_mode == MMC_POWER_OFF) | |
146ad66e | 1123 | sdhci_set_power(host, -1); |
d129bceb | 1124 | else |
146ad66e | 1125 | sdhci_set_power(host, ios->vdd); |
d129bceb | 1126 | |
4e4141a5 | 1127 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
cd9277c0 | 1128 | |
d129bceb PO |
1129 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
1130 | ctrl |= SDHCI_CTRL_4BITBUS; | |
1131 | else | |
1132 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
cd9277c0 PO |
1133 | |
1134 | if (ios->timing == MMC_TIMING_SD_HS) | |
1135 | ctrl |= SDHCI_CTRL_HISPD; | |
1136 | else | |
1137 | ctrl &= ~SDHCI_CTRL_HISPD; | |
1138 | ||
4e4141a5 | 1139 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb | 1140 | |
b8352260 LD |
1141 | /* |
1142 | * Some (ENE) controllers go apeshit on some ios operation, | |
1143 | * signalling timeout and CRC errors even on CMD0. Resetting | |
1144 | * it on each ios seems to solve the problem. | |
1145 | */ | |
b8c86fc5 | 1146 | if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
b8352260 LD |
1147 | sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
1148 | ||
1e72859e | 1149 | out: |
5f25a66f | 1150 | mmiowb(); |
d129bceb PO |
1151 | spin_unlock_irqrestore(&host->lock, flags); |
1152 | } | |
1153 | ||
1154 | static int sdhci_get_ro(struct mmc_host *mmc) | |
1155 | { | |
1156 | struct sdhci_host *host; | |
1157 | unsigned long flags; | |
1158 | int present; | |
1159 | ||
1160 | host = mmc_priv(mmc); | |
1161 | ||
1162 | spin_lock_irqsave(&host->lock, flags); | |
1163 | ||
1e72859e PO |
1164 | if (host->flags & SDHCI_DEVICE_DEAD) |
1165 | present = 0; | |
1166 | else | |
4e4141a5 | 1167 | present = sdhci_readl(host, SDHCI_PRESENT_STATE); |
d129bceb PO |
1168 | |
1169 | spin_unlock_irqrestore(&host->lock, flags); | |
1170 | ||
c5075a10 AV |
1171 | if (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT) |
1172 | return !!(present & SDHCI_WRITE_PROTECT); | |
d129bceb PO |
1173 | return !(present & SDHCI_WRITE_PROTECT); |
1174 | } | |
1175 | ||
f75979b7 PO |
1176 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
1177 | { | |
1178 | struct sdhci_host *host; | |
1179 | unsigned long flags; | |
f75979b7 PO |
1180 | |
1181 | host = mmc_priv(mmc); | |
1182 | ||
1183 | spin_lock_irqsave(&host->lock, flags); | |
1184 | ||
1e72859e PO |
1185 | if (host->flags & SDHCI_DEVICE_DEAD) |
1186 | goto out; | |
1187 | ||
f75979b7 | 1188 | if (enable) |
7260cf5e AV |
1189 | sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT); |
1190 | else | |
1191 | sdhci_mask_irqs(host, SDHCI_INT_CARD_INT); | |
1e72859e | 1192 | out: |
f75979b7 PO |
1193 | mmiowb(); |
1194 | ||
1195 | spin_unlock_irqrestore(&host->lock, flags); | |
1196 | } | |
1197 | ||
ab7aefd0 | 1198 | static const struct mmc_host_ops sdhci_ops = { |
d129bceb PO |
1199 | .request = sdhci_request, |
1200 | .set_ios = sdhci_set_ios, | |
1201 | .get_ro = sdhci_get_ro, | |
f75979b7 | 1202 | .enable_sdio_irq = sdhci_enable_sdio_irq, |
d129bceb PO |
1203 | }; |
1204 | ||
1205 | /*****************************************************************************\ | |
1206 | * * | |
1207 | * Tasklets * | |
1208 | * * | |
1209 | \*****************************************************************************/ | |
1210 | ||
1211 | static void sdhci_tasklet_card(unsigned long param) | |
1212 | { | |
1213 | struct sdhci_host *host; | |
1214 | unsigned long flags; | |
1215 | ||
1216 | host = (struct sdhci_host*)param; | |
1217 | ||
1218 | spin_lock_irqsave(&host->lock, flags); | |
1219 | ||
4e4141a5 | 1220 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { |
d129bceb PO |
1221 | if (host->mrq) { |
1222 | printk(KERN_ERR "%s: Card removed during transfer!\n", | |
1223 | mmc_hostname(host->mmc)); | |
1224 | printk(KERN_ERR "%s: Resetting controller.\n", | |
1225 | mmc_hostname(host->mmc)); | |
1226 | ||
1227 | sdhci_reset(host, SDHCI_RESET_CMD); | |
1228 | sdhci_reset(host, SDHCI_RESET_DATA); | |
1229 | ||
17b0429d | 1230 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb PO |
1231 | tasklet_schedule(&host->finish_tasklet); |
1232 | } | |
1233 | } | |
1234 | ||
1235 | spin_unlock_irqrestore(&host->lock, flags); | |
1236 | ||
04cf585d | 1237 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); |
d129bceb PO |
1238 | } |
1239 | ||
1240 | static void sdhci_tasklet_finish(unsigned long param) | |
1241 | { | |
1242 | struct sdhci_host *host; | |
1243 | unsigned long flags; | |
1244 | struct mmc_request *mrq; | |
1245 | ||
1246 | host = (struct sdhci_host*)param; | |
1247 | ||
1248 | spin_lock_irqsave(&host->lock, flags); | |
1249 | ||
1250 | del_timer(&host->timer); | |
1251 | ||
1252 | mrq = host->mrq; | |
1253 | ||
d129bceb PO |
1254 | /* |
1255 | * The controller needs a reset of internal state machines | |
1256 | * upon error conditions. | |
1257 | */ | |
1e72859e PO |
1258 | if (!(host->flags & SDHCI_DEVICE_DEAD) && |
1259 | (mrq->cmd->error || | |
1260 | (mrq->data && (mrq->data->error || | |
1261 | (mrq->data->stop && mrq->data->stop->error))) || | |
1262 | (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { | |
645289dc PO |
1263 | |
1264 | /* Some controllers need this kick or reset won't work here */ | |
b8c86fc5 | 1265 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { |
645289dc PO |
1266 | unsigned int clock; |
1267 | ||
1268 | /* This is to force an update */ | |
1269 | clock = host->clock; | |
1270 | host->clock = 0; | |
1271 | sdhci_set_clock(host, clock); | |
1272 | } | |
1273 | ||
1274 | /* Spec says we should do both at the same time, but Ricoh | |
1275 | controllers do not like that. */ | |
d129bceb PO |
1276 | sdhci_reset(host, SDHCI_RESET_CMD); |
1277 | sdhci_reset(host, SDHCI_RESET_DATA); | |
1278 | } | |
1279 | ||
1280 | host->mrq = NULL; | |
1281 | host->cmd = NULL; | |
1282 | host->data = NULL; | |
1283 | ||
f9134319 | 1284 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1285 | sdhci_deactivate_led(host); |
2f730fec | 1286 | #endif |
d129bceb | 1287 | |
5f25a66f | 1288 | mmiowb(); |
d129bceb PO |
1289 | spin_unlock_irqrestore(&host->lock, flags); |
1290 | ||
1291 | mmc_request_done(host->mmc, mrq); | |
1292 | } | |
1293 | ||
1294 | static void sdhci_timeout_timer(unsigned long data) | |
1295 | { | |
1296 | struct sdhci_host *host; | |
1297 | unsigned long flags; | |
1298 | ||
1299 | host = (struct sdhci_host*)data; | |
1300 | ||
1301 | spin_lock_irqsave(&host->lock, flags); | |
1302 | ||
1303 | if (host->mrq) { | |
acf1da45 PO |
1304 | printk(KERN_ERR "%s: Timeout waiting for hardware " |
1305 | "interrupt.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
1306 | sdhci_dumpregs(host); |
1307 | ||
1308 | if (host->data) { | |
17b0429d | 1309 | host->data->error = -ETIMEDOUT; |
d129bceb PO |
1310 | sdhci_finish_data(host); |
1311 | } else { | |
1312 | if (host->cmd) | |
17b0429d | 1313 | host->cmd->error = -ETIMEDOUT; |
d129bceb | 1314 | else |
17b0429d | 1315 | host->mrq->cmd->error = -ETIMEDOUT; |
d129bceb PO |
1316 | |
1317 | tasklet_schedule(&host->finish_tasklet); | |
1318 | } | |
1319 | } | |
1320 | ||
5f25a66f | 1321 | mmiowb(); |
d129bceb PO |
1322 | spin_unlock_irqrestore(&host->lock, flags); |
1323 | } | |
1324 | ||
1325 | /*****************************************************************************\ | |
1326 | * * | |
1327 | * Interrupt handling * | |
1328 | * * | |
1329 | \*****************************************************************************/ | |
1330 | ||
1331 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) | |
1332 | { | |
1333 | BUG_ON(intmask == 0); | |
1334 | ||
1335 | if (!host->cmd) { | |
b67ac3f3 PO |
1336 | printk(KERN_ERR "%s: Got command interrupt 0x%08x even " |
1337 | "though no command operation was in progress.\n", | |
1338 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
1339 | sdhci_dumpregs(host); |
1340 | return; | |
1341 | } | |
1342 | ||
43b58b36 | 1343 | if (intmask & SDHCI_INT_TIMEOUT) |
17b0429d PO |
1344 | host->cmd->error = -ETIMEDOUT; |
1345 | else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | | |
1346 | SDHCI_INT_INDEX)) | |
1347 | host->cmd->error = -EILSEQ; | |
43b58b36 | 1348 | |
e809517f | 1349 | if (host->cmd->error) { |
d129bceb | 1350 | tasklet_schedule(&host->finish_tasklet); |
e809517f PO |
1351 | return; |
1352 | } | |
1353 | ||
1354 | /* | |
1355 | * The host can send and interrupt when the busy state has | |
1356 | * ended, allowing us to wait without wasting CPU cycles. | |
1357 | * Unfortunately this is overloaded on the "data complete" | |
1358 | * interrupt, so we need to take some care when handling | |
1359 | * it. | |
1360 | * | |
1361 | * Note: The 1.0 specification is a bit ambiguous about this | |
1362 | * feature so there might be some problems with older | |
1363 | * controllers. | |
1364 | */ | |
1365 | if (host->cmd->flags & MMC_RSP_BUSY) { | |
1366 | if (host->cmd->data) | |
1367 | DBG("Cannot wait for busy signal when also " | |
1368 | "doing a data transfer"); | |
f945405c | 1369 | else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) |
e809517f | 1370 | return; |
f945405c BD |
1371 | |
1372 | /* The controller does not support the end-of-busy IRQ, | |
1373 | * fall through and take the SDHCI_INT_RESPONSE */ | |
e809517f PO |
1374 | } |
1375 | ||
1376 | if (intmask & SDHCI_INT_RESPONSE) | |
43b58b36 | 1377 | sdhci_finish_command(host); |
d129bceb PO |
1378 | } |
1379 | ||
1380 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) | |
1381 | { | |
1382 | BUG_ON(intmask == 0); | |
1383 | ||
1384 | if (!host->data) { | |
1385 | /* | |
e809517f PO |
1386 | * The "data complete" interrupt is also used to |
1387 | * indicate that a busy state has ended. See comment | |
1388 | * above in sdhci_cmd_irq(). | |
d129bceb | 1389 | */ |
e809517f PO |
1390 | if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { |
1391 | if (intmask & SDHCI_INT_DATA_END) { | |
1392 | sdhci_finish_command(host); | |
1393 | return; | |
1394 | } | |
1395 | } | |
d129bceb | 1396 | |
b67ac3f3 PO |
1397 | printk(KERN_ERR "%s: Got data interrupt 0x%08x even " |
1398 | "though no data operation was in progress.\n", | |
1399 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
1400 | sdhci_dumpregs(host); |
1401 | ||
1402 | return; | |
1403 | } | |
1404 | ||
1405 | if (intmask & SDHCI_INT_DATA_TIMEOUT) | |
17b0429d PO |
1406 | host->data->error = -ETIMEDOUT; |
1407 | else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) | |
1408 | host->data->error = -EILSEQ; | |
2134a922 PO |
1409 | else if (intmask & SDHCI_INT_ADMA_ERROR) |
1410 | host->data->error = -EIO; | |
d129bceb | 1411 | |
17b0429d | 1412 | if (host->data->error) |
d129bceb PO |
1413 | sdhci_finish_data(host); |
1414 | else { | |
a406f5a3 | 1415 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
d129bceb PO |
1416 | sdhci_transfer_pio(host); |
1417 | ||
6ba736a1 PO |
1418 | /* |
1419 | * We currently don't do anything fancy with DMA | |
1420 | * boundaries, but as we can't disable the feature | |
1421 | * we need to at least restart the transfer. | |
1422 | */ | |
1423 | if (intmask & SDHCI_INT_DMA_END) | |
4e4141a5 AV |
1424 | sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS), |
1425 | SDHCI_DMA_ADDRESS); | |
6ba736a1 | 1426 | |
e538fbe8 PO |
1427 | if (intmask & SDHCI_INT_DATA_END) { |
1428 | if (host->cmd) { | |
1429 | /* | |
1430 | * Data managed to finish before the | |
1431 | * command completed. Make sure we do | |
1432 | * things in the proper order. | |
1433 | */ | |
1434 | host->data_early = 1; | |
1435 | } else { | |
1436 | sdhci_finish_data(host); | |
1437 | } | |
1438 | } | |
d129bceb PO |
1439 | } |
1440 | } | |
1441 | ||
7d12e780 | 1442 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
d129bceb PO |
1443 | { |
1444 | irqreturn_t result; | |
1445 | struct sdhci_host* host = dev_id; | |
1446 | u32 intmask; | |
f75979b7 | 1447 | int cardint = 0; |
d129bceb PO |
1448 | |
1449 | spin_lock(&host->lock); | |
1450 | ||
4e4141a5 | 1451 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
d129bceb | 1452 | |
62df67a5 | 1453 | if (!intmask || intmask == 0xffffffff) { |
d129bceb PO |
1454 | result = IRQ_NONE; |
1455 | goto out; | |
1456 | } | |
1457 | ||
b69c9058 PO |
1458 | DBG("*** %s got interrupt: 0x%08x\n", |
1459 | mmc_hostname(host->mmc), intmask); | |
d129bceb | 1460 | |
3192a28f | 1461 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
4e4141a5 AV |
1462 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | |
1463 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); | |
d129bceb | 1464 | tasklet_schedule(&host->card_tasklet); |
3192a28f | 1465 | } |
d129bceb | 1466 | |
3192a28f | 1467 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); |
d129bceb | 1468 | |
3192a28f | 1469 | if (intmask & SDHCI_INT_CMD_MASK) { |
4e4141a5 AV |
1470 | sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, |
1471 | SDHCI_INT_STATUS); | |
3192a28f | 1472 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); |
d129bceb PO |
1473 | } |
1474 | ||
1475 | if (intmask & SDHCI_INT_DATA_MASK) { | |
4e4141a5 AV |
1476 | sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK, |
1477 | SDHCI_INT_STATUS); | |
3192a28f | 1478 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); |
d129bceb PO |
1479 | } |
1480 | ||
1481 | intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); | |
1482 | ||
964f9ce2 PO |
1483 | intmask &= ~SDHCI_INT_ERROR; |
1484 | ||
d129bceb | 1485 | if (intmask & SDHCI_INT_BUS_POWER) { |
3192a28f | 1486 | printk(KERN_ERR "%s: Card is consuming too much power!\n", |
d129bceb | 1487 | mmc_hostname(host->mmc)); |
4e4141a5 | 1488 | sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS); |
d129bceb PO |
1489 | } |
1490 | ||
9d26a5d3 | 1491 | intmask &= ~SDHCI_INT_BUS_POWER; |
3192a28f | 1492 | |
f75979b7 PO |
1493 | if (intmask & SDHCI_INT_CARD_INT) |
1494 | cardint = 1; | |
1495 | ||
1496 | intmask &= ~SDHCI_INT_CARD_INT; | |
1497 | ||
3192a28f | 1498 | if (intmask) { |
acf1da45 | 1499 | printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n", |
3192a28f | 1500 | mmc_hostname(host->mmc), intmask); |
d129bceb PO |
1501 | sdhci_dumpregs(host); |
1502 | ||
4e4141a5 | 1503 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); |
3192a28f | 1504 | } |
d129bceb PO |
1505 | |
1506 | result = IRQ_HANDLED; | |
1507 | ||
5f25a66f | 1508 | mmiowb(); |
d129bceb PO |
1509 | out: |
1510 | spin_unlock(&host->lock); | |
1511 | ||
f75979b7 PO |
1512 | /* |
1513 | * We have to delay this as it calls back into the driver. | |
1514 | */ | |
1515 | if (cardint) | |
1516 | mmc_signal_sdio_irq(host->mmc); | |
1517 | ||
d129bceb PO |
1518 | return result; |
1519 | } | |
1520 | ||
1521 | /*****************************************************************************\ | |
1522 | * * | |
1523 | * Suspend/resume * | |
1524 | * * | |
1525 | \*****************************************************************************/ | |
1526 | ||
1527 | #ifdef CONFIG_PM | |
1528 | ||
b8c86fc5 | 1529 | int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state) |
d129bceb | 1530 | { |
b8c86fc5 | 1531 | int ret; |
a715dfc7 | 1532 | |
7260cf5e AV |
1533 | sdhci_disable_card_detection(host); |
1534 | ||
b8c86fc5 PO |
1535 | ret = mmc_suspend_host(host->mmc, state); |
1536 | if (ret) | |
1537 | return ret; | |
a715dfc7 | 1538 | |
b8c86fc5 | 1539 | free_irq(host->irq, host); |
d129bceb PO |
1540 | |
1541 | return 0; | |
1542 | } | |
1543 | ||
b8c86fc5 | 1544 | EXPORT_SYMBOL_GPL(sdhci_suspend_host); |
d129bceb | 1545 | |
b8c86fc5 PO |
1546 | int sdhci_resume_host(struct sdhci_host *host) |
1547 | { | |
1548 | int ret; | |
d129bceb | 1549 | |
b8c86fc5 PO |
1550 | if (host->flags & SDHCI_USE_DMA) { |
1551 | if (host->ops->enable_dma) | |
1552 | host->ops->enable_dma(host); | |
1553 | } | |
d129bceb | 1554 | |
b8c86fc5 PO |
1555 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
1556 | mmc_hostname(host->mmc), host); | |
df1c4b7b PO |
1557 | if (ret) |
1558 | return ret; | |
d129bceb | 1559 | |
b8c86fc5 PO |
1560 | sdhci_init(host); |
1561 | mmiowb(); | |
1562 | ||
1563 | ret = mmc_resume_host(host->mmc); | |
1564 | if (ret) | |
1565 | return ret; | |
d129bceb | 1566 | |
7260cf5e AV |
1567 | sdhci_enable_card_detection(host); |
1568 | ||
d129bceb PO |
1569 | return 0; |
1570 | } | |
1571 | ||
b8c86fc5 | 1572 | EXPORT_SYMBOL_GPL(sdhci_resume_host); |
d129bceb PO |
1573 | |
1574 | #endif /* CONFIG_PM */ | |
1575 | ||
1576 | /*****************************************************************************\ | |
1577 | * * | |
b8c86fc5 | 1578 | * Device allocation/registration * |
d129bceb PO |
1579 | * * |
1580 | \*****************************************************************************/ | |
1581 | ||
b8c86fc5 PO |
1582 | struct sdhci_host *sdhci_alloc_host(struct device *dev, |
1583 | size_t priv_size) | |
d129bceb | 1584 | { |
d129bceb PO |
1585 | struct mmc_host *mmc; |
1586 | struct sdhci_host *host; | |
1587 | ||
b8c86fc5 | 1588 | WARN_ON(dev == NULL); |
d129bceb | 1589 | |
b8c86fc5 | 1590 | mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); |
d129bceb | 1591 | if (!mmc) |
b8c86fc5 | 1592 | return ERR_PTR(-ENOMEM); |
d129bceb PO |
1593 | |
1594 | host = mmc_priv(mmc); | |
1595 | host->mmc = mmc; | |
1596 | ||
b8c86fc5 PO |
1597 | return host; |
1598 | } | |
8a4da143 | 1599 | |
b8c86fc5 | 1600 | EXPORT_SYMBOL_GPL(sdhci_alloc_host); |
d129bceb | 1601 | |
b8c86fc5 PO |
1602 | int sdhci_add_host(struct sdhci_host *host) |
1603 | { | |
1604 | struct mmc_host *mmc; | |
1605 | unsigned int caps; | |
b8c86fc5 | 1606 | int ret; |
d129bceb | 1607 | |
b8c86fc5 PO |
1608 | WARN_ON(host == NULL); |
1609 | if (host == NULL) | |
1610 | return -EINVAL; | |
d129bceb | 1611 | |
b8c86fc5 | 1612 | mmc = host->mmc; |
d129bceb | 1613 | |
b8c86fc5 PO |
1614 | if (debug_quirks) |
1615 | host->quirks = debug_quirks; | |
d129bceb | 1616 | |
d96649ed PO |
1617 | sdhci_reset(host, SDHCI_RESET_ALL); |
1618 | ||
4e4141a5 | 1619 | host->version = sdhci_readw(host, SDHCI_HOST_VERSION); |
2134a922 PO |
1620 | host->version = (host->version & SDHCI_SPEC_VER_MASK) |
1621 | >> SDHCI_SPEC_VER_SHIFT; | |
1622 | if (host->version > SDHCI_SPEC_200) { | |
4a965505 | 1623 | printk(KERN_ERR "%s: Unknown controller version (%d). " |
b69c9058 | 1624 | "You may experience problems.\n", mmc_hostname(mmc), |
2134a922 | 1625 | host->version); |
4a965505 PO |
1626 | } |
1627 | ||
4e4141a5 | 1628 | caps = sdhci_readl(host, SDHCI_CAPABILITIES); |
d129bceb | 1629 | |
b8c86fc5 | 1630 | if (host->quirks & SDHCI_QUIRK_FORCE_DMA) |
98608076 | 1631 | host->flags |= SDHCI_USE_DMA; |
67435274 PO |
1632 | else if (!(caps & SDHCI_CAN_DO_DMA)) |
1633 | DBG("Controller doesn't have DMA capability\n"); | |
1634 | else | |
d129bceb PO |
1635 | host->flags |= SDHCI_USE_DMA; |
1636 | ||
b8c86fc5 | 1637 | if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
7c168e3d | 1638 | (host->flags & SDHCI_USE_DMA)) { |
cee687ce | 1639 | DBG("Disabling DMA as it is marked broken\n"); |
7c168e3d FT |
1640 | host->flags &= ~SDHCI_USE_DMA; |
1641 | } | |
1642 | ||
2134a922 PO |
1643 | if (host->flags & SDHCI_USE_DMA) { |
1644 | if ((host->version >= SDHCI_SPEC_200) && | |
1645 | (caps & SDHCI_CAN_DO_ADMA2)) | |
1646 | host->flags |= SDHCI_USE_ADMA; | |
1647 | } | |
1648 | ||
1649 | if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && | |
1650 | (host->flags & SDHCI_USE_ADMA)) { | |
1651 | DBG("Disabling ADMA as it is marked broken\n"); | |
1652 | host->flags &= ~SDHCI_USE_ADMA; | |
1653 | } | |
1654 | ||
d129bceb | 1655 | if (host->flags & SDHCI_USE_DMA) { |
b8c86fc5 PO |
1656 | if (host->ops->enable_dma) { |
1657 | if (host->ops->enable_dma(host)) { | |
1658 | printk(KERN_WARNING "%s: No suitable DMA " | |
1659 | "available. Falling back to PIO.\n", | |
1660 | mmc_hostname(mmc)); | |
2134a922 | 1661 | host->flags &= ~(SDHCI_USE_DMA | SDHCI_USE_ADMA); |
b8c86fc5 | 1662 | } |
d129bceb PO |
1663 | } |
1664 | } | |
1665 | ||
2134a922 PO |
1666 | if (host->flags & SDHCI_USE_ADMA) { |
1667 | /* | |
1668 | * We need to allocate descriptors for all sg entries | |
1669 | * (128) and potentially one alignment transfer for | |
1670 | * each of those entries. | |
1671 | */ | |
1672 | host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL); | |
1673 | host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); | |
1674 | if (!host->adma_desc || !host->align_buffer) { | |
1675 | kfree(host->adma_desc); | |
1676 | kfree(host->align_buffer); | |
1677 | printk(KERN_WARNING "%s: Unable to allocate ADMA " | |
1678 | "buffers. Falling back to standard DMA.\n", | |
1679 | mmc_hostname(mmc)); | |
1680 | host->flags &= ~SDHCI_USE_ADMA; | |
1681 | } | |
1682 | } | |
1683 | ||
7659150c PO |
1684 | /* |
1685 | * If we use DMA, then it's up to the caller to set the DMA | |
1686 | * mask, but PIO does not need the hw shim so we set a new | |
1687 | * mask here in that case. | |
1688 | */ | |
1689 | if (!(host->flags & SDHCI_USE_DMA)) { | |
1690 | host->dma_mask = DMA_BIT_MASK(64); | |
1691 | mmc_dev(host->mmc)->dma_mask = &host->dma_mask; | |
1692 | } | |
d129bceb | 1693 | |
8ef1a143 PO |
1694 | host->max_clk = |
1695 | (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; | |
4240ff0a | 1696 | host->max_clk *= 1000000; |
8ef1a143 | 1697 | if (host->max_clk == 0) { |
4240ff0a BD |
1698 | if (!host->ops->get_max_clock) { |
1699 | printk(KERN_ERR | |
1700 | "%s: Hardware doesn't specify base clock " | |
1701 | "frequency.\n", mmc_hostname(mmc)); | |
1702 | return -ENODEV; | |
1703 | } | |
1704 | host->max_clk = host->ops->get_max_clock(host); | |
8ef1a143 | 1705 | } |
d129bceb | 1706 | |
1c8cde92 PO |
1707 | host->timeout_clk = |
1708 | (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; | |
1709 | if (host->timeout_clk == 0) { | |
4240ff0a BD |
1710 | if (!host->ops->get_timeout_clock) { |
1711 | printk(KERN_ERR | |
1712 | "%s: Hardware doesn't specify timeout clock " | |
1713 | "frequency.\n", mmc_hostname(mmc)); | |
1714 | return -ENODEV; | |
1715 | } | |
1716 | host->timeout_clk = host->ops->get_timeout_clock(host); | |
1c8cde92 PO |
1717 | } |
1718 | if (caps & SDHCI_TIMEOUT_CLK_UNIT) | |
1719 | host->timeout_clk *= 1000; | |
d129bceb PO |
1720 | |
1721 | /* | |
1722 | * Set host parameters. | |
1723 | */ | |
1724 | mmc->ops = &sdhci_ops; | |
1725 | mmc->f_min = host->max_clk / 256; | |
1726 | mmc->f_max = host->max_clk; | |
c9b74c5b | 1727 | mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; |
d129bceb | 1728 | |
86a6a874 | 1729 | if (caps & SDHCI_CAN_DO_HISPD) |
cd9277c0 PO |
1730 | mmc->caps |= MMC_CAP_SD_HIGHSPEED; |
1731 | ||
68d1fb7e AV |
1732 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) |
1733 | mmc->caps |= MMC_CAP_NEEDS_POLL; | |
1734 | ||
146ad66e PO |
1735 | mmc->ocr_avail = 0; |
1736 | if (caps & SDHCI_CAN_VDD_330) | |
1737 | mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34; | |
c70840e8 | 1738 | if (caps & SDHCI_CAN_VDD_300) |
146ad66e | 1739 | mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31; |
c70840e8 | 1740 | if (caps & SDHCI_CAN_VDD_180) |
55556da0 | 1741 | mmc->ocr_avail |= MMC_VDD_165_195; |
146ad66e PO |
1742 | |
1743 | if (mmc->ocr_avail == 0) { | |
1744 | printk(KERN_ERR "%s: Hardware doesn't report any " | |
b69c9058 | 1745 | "support voltages.\n", mmc_hostname(mmc)); |
b8c86fc5 | 1746 | return -ENODEV; |
146ad66e PO |
1747 | } |
1748 | ||
d129bceb PO |
1749 | spin_lock_init(&host->lock); |
1750 | ||
1751 | /* | |
2134a922 PO |
1752 | * Maximum number of segments. Depends on if the hardware |
1753 | * can do scatter/gather or not. | |
d129bceb | 1754 | */ |
2134a922 PO |
1755 | if (host->flags & SDHCI_USE_ADMA) |
1756 | mmc->max_hw_segs = 128; | |
1757 | else if (host->flags & SDHCI_USE_DMA) | |
d129bceb | 1758 | mmc->max_hw_segs = 1; |
2134a922 PO |
1759 | else /* PIO */ |
1760 | mmc->max_hw_segs = 128; | |
1761 | mmc->max_phys_segs = 128; | |
d129bceb PO |
1762 | |
1763 | /* | |
bab76961 | 1764 | * Maximum number of sectors in one transfer. Limited by DMA boundary |
55db890a | 1765 | * size (512KiB). |
d129bceb | 1766 | */ |
55db890a | 1767 | mmc->max_req_size = 524288; |
d129bceb PO |
1768 | |
1769 | /* | |
1770 | * Maximum segment size. Could be one segment with the maximum number | |
2134a922 PO |
1771 | * of bytes. When doing hardware scatter/gather, each entry cannot |
1772 | * be larger than 64 KiB though. | |
d129bceb | 1773 | */ |
2134a922 PO |
1774 | if (host->flags & SDHCI_USE_ADMA) |
1775 | mmc->max_seg_size = 65536; | |
1776 | else | |
1777 | mmc->max_seg_size = mmc->max_req_size; | |
d129bceb | 1778 | |
fe4a3c7a PO |
1779 | /* |
1780 | * Maximum block size. This varies from controller to controller and | |
1781 | * is specified in the capabilities register. | |
1782 | */ | |
0633f654 AV |
1783 | if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { |
1784 | mmc->max_blk_size = 2; | |
1785 | } else { | |
1786 | mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> | |
1787 | SDHCI_MAX_BLOCK_SHIFT; | |
1788 | if (mmc->max_blk_size >= 3) { | |
1789 | printk(KERN_WARNING "%s: Invalid maximum block size, " | |
1790 | "assuming 512 bytes\n", mmc_hostname(mmc)); | |
1791 | mmc->max_blk_size = 0; | |
1792 | } | |
1793 | } | |
1794 | ||
1795 | mmc->max_blk_size = 512 << mmc->max_blk_size; | |
fe4a3c7a | 1796 | |
55db890a PO |
1797 | /* |
1798 | * Maximum block count. | |
1799 | */ | |
1800 | mmc->max_blk_count = 65535; | |
1801 | ||
d129bceb PO |
1802 | /* |
1803 | * Init tasklets. | |
1804 | */ | |
1805 | tasklet_init(&host->card_tasklet, | |
1806 | sdhci_tasklet_card, (unsigned long)host); | |
1807 | tasklet_init(&host->finish_tasklet, | |
1808 | sdhci_tasklet_finish, (unsigned long)host); | |
1809 | ||
e4cad1b5 | 1810 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
d129bceb | 1811 | |
dace1453 | 1812 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
b69c9058 | 1813 | mmc_hostname(mmc), host); |
d129bceb | 1814 | if (ret) |
8ef1a143 | 1815 | goto untasklet; |
d129bceb PO |
1816 | |
1817 | sdhci_init(host); | |
1818 | ||
1819 | #ifdef CONFIG_MMC_DEBUG | |
1820 | sdhci_dumpregs(host); | |
1821 | #endif | |
1822 | ||
f9134319 | 1823 | #ifdef SDHCI_USE_LEDS_CLASS |
5dbace0c HS |
1824 | snprintf(host->led_name, sizeof(host->led_name), |
1825 | "%s::", mmc_hostname(mmc)); | |
1826 | host->led.name = host->led_name; | |
2f730fec PO |
1827 | host->led.brightness = LED_OFF; |
1828 | host->led.default_trigger = mmc_hostname(mmc); | |
1829 | host->led.brightness_set = sdhci_led_control; | |
1830 | ||
b8c86fc5 | 1831 | ret = led_classdev_register(mmc_dev(mmc), &host->led); |
2f730fec PO |
1832 | if (ret) |
1833 | goto reset; | |
1834 | #endif | |
1835 | ||
5f25a66f PO |
1836 | mmiowb(); |
1837 | ||
d129bceb PO |
1838 | mmc_add_host(mmc); |
1839 | ||
2134a922 | 1840 | printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s%s\n", |
d1b26863 | 1841 | mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), |
2134a922 | 1842 | (host->flags & SDHCI_USE_ADMA)?"A":"", |
d129bceb PO |
1843 | (host->flags & SDHCI_USE_DMA)?"DMA":"PIO"); |
1844 | ||
7260cf5e AV |
1845 | sdhci_enable_card_detection(host); |
1846 | ||
d129bceb PO |
1847 | return 0; |
1848 | ||
f9134319 | 1849 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
1850 | reset: |
1851 | sdhci_reset(host, SDHCI_RESET_ALL); | |
1852 | free_irq(host->irq, host); | |
1853 | #endif | |
8ef1a143 | 1854 | untasklet: |
d129bceb PO |
1855 | tasklet_kill(&host->card_tasklet); |
1856 | tasklet_kill(&host->finish_tasklet); | |
d129bceb PO |
1857 | |
1858 | return ret; | |
1859 | } | |
1860 | ||
b8c86fc5 | 1861 | EXPORT_SYMBOL_GPL(sdhci_add_host); |
d129bceb | 1862 | |
1e72859e | 1863 | void sdhci_remove_host(struct sdhci_host *host, int dead) |
b8c86fc5 | 1864 | { |
1e72859e PO |
1865 | unsigned long flags; |
1866 | ||
1867 | if (dead) { | |
1868 | spin_lock_irqsave(&host->lock, flags); | |
1869 | ||
1870 | host->flags |= SDHCI_DEVICE_DEAD; | |
1871 | ||
1872 | if (host->mrq) { | |
1873 | printk(KERN_ERR "%s: Controller removed during " | |
1874 | " transfer!\n", mmc_hostname(host->mmc)); | |
1875 | ||
1876 | host->mrq->cmd->error = -ENOMEDIUM; | |
1877 | tasklet_schedule(&host->finish_tasklet); | |
1878 | } | |
1879 | ||
1880 | spin_unlock_irqrestore(&host->lock, flags); | |
1881 | } | |
1882 | ||
7260cf5e AV |
1883 | sdhci_disable_card_detection(host); |
1884 | ||
b8c86fc5 | 1885 | mmc_remove_host(host->mmc); |
d129bceb | 1886 | |
f9134319 | 1887 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
1888 | led_classdev_unregister(&host->led); |
1889 | #endif | |
1890 | ||
1e72859e PO |
1891 | if (!dead) |
1892 | sdhci_reset(host, SDHCI_RESET_ALL); | |
d129bceb PO |
1893 | |
1894 | free_irq(host->irq, host); | |
1895 | ||
1896 | del_timer_sync(&host->timer); | |
1897 | ||
1898 | tasklet_kill(&host->card_tasklet); | |
1899 | tasklet_kill(&host->finish_tasklet); | |
2134a922 PO |
1900 | |
1901 | kfree(host->adma_desc); | |
1902 | kfree(host->align_buffer); | |
1903 | ||
1904 | host->adma_desc = NULL; | |
1905 | host->align_buffer = NULL; | |
d129bceb PO |
1906 | } |
1907 | ||
b8c86fc5 | 1908 | EXPORT_SYMBOL_GPL(sdhci_remove_host); |
d129bceb | 1909 | |
b8c86fc5 | 1910 | void sdhci_free_host(struct sdhci_host *host) |
d129bceb | 1911 | { |
b8c86fc5 | 1912 | mmc_free_host(host->mmc); |
d129bceb PO |
1913 | } |
1914 | ||
b8c86fc5 | 1915 | EXPORT_SYMBOL_GPL(sdhci_free_host); |
d129bceb PO |
1916 | |
1917 | /*****************************************************************************\ | |
1918 | * * | |
1919 | * Driver init/exit * | |
1920 | * * | |
1921 | \*****************************************************************************/ | |
1922 | ||
1923 | static int __init sdhci_drv_init(void) | |
1924 | { | |
1925 | printk(KERN_INFO DRIVER_NAME | |
52fbf9c9 | 1926 | ": Secure Digital Host Controller Interface driver\n"); |
d129bceb PO |
1927 | printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
1928 | ||
b8c86fc5 | 1929 | return 0; |
d129bceb PO |
1930 | } |
1931 | ||
1932 | static void __exit sdhci_drv_exit(void) | |
1933 | { | |
d129bceb PO |
1934 | } |
1935 | ||
1936 | module_init(sdhci_drv_init); | |
1937 | module_exit(sdhci_drv_exit); | |
1938 | ||
df673b22 | 1939 | module_param(debug_quirks, uint, 0444); |
67435274 | 1940 | |
32710e8f | 1941 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 | 1942 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); |
d129bceb | 1943 | MODULE_LICENSE("GPL"); |
67435274 | 1944 | |
df673b22 | 1945 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |