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mmc: sdhci-pic32: remove owner assignment
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
f9134319
PO		 41#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43#define SDHCI_USE_LEDS_CLASS
44#endif
45
b513ea25
AN		 46#define MAX_TUNING_LOOP 40
47
df673b22 48static unsigned int debug_quirks = 0;
66fd8ad5 49static unsigned int debug_quirks2;
67435274 50
d129bceb
PO		 51static void sdhci_finish_data(struct sdhci_host *);
52
d129bceb 53static void sdhci_finish_command(struct sdhci_host *);
069c9f14 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
04e079cf 56static int sdhci_do_get_cd(struct sdhci_host *host);
d129bceb 57
162d6f98 58#ifdef CONFIG_PM
f0710a55
AH		 59static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
60static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5 61#else
f0710a55
AH		 62static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
63{
64}
65static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
66{
67}
66fd8ad5
AH		 68#endif
69
d129bceb
PO		 70static void sdhci_dumpregs(struct sdhci_host *host)
71{
a3c76eb9 72 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 73 mmc_hostname(host->mmc));
d129bceb 74
a3c76eb9 75 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 76 sdhci_readl(host, SDHCI_DMA_ADDRESS),
77 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 78 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 79 sdhci_readw(host, SDHCI_BLOCK_SIZE),
80 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 81 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 82 sdhci_readl(host, SDHCI_ARGUMENT),
83 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 84 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 85 sdhci_readl(host, SDHCI_PRESENT_STATE),
86 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 87 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 88 sdhci_readb(host, SDHCI_POWER_CONTROL),
89 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 90 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 91 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
92 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 93 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 94 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
95 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 96 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 97 sdhci_readl(host, SDHCI_INT_ENABLE),
98 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 99 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 100 sdhci_readw(host, SDHCI_ACMD12_ERR),
101 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 102 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 103 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 104 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 105 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 106 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 107 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 108 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 109 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 110
e57a5f61
AH		 111 if (host->flags & SDHCI_USE_ADMA) {
112 if (host->flags & SDHCI_USE_64_BIT_DMA)
113 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
114 readl(host->ioaddr + SDHCI_ADMA_ERROR),
115 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
116 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
117 else
118 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
119 readl(host->ioaddr + SDHCI_ADMA_ERROR),
120 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
121 }
be3f4ae0 122
a3c76eb9 123 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 124}
125
126/*****************************************************************************\
127 * *
128 * Low level functions *
129 * *
130\*****************************************************************************/
131
7260cf5e
AV		 132static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
133{
5b4f1f6c 134 u32 present;
7260cf5e 135
c79396c1 136 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 137 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 138 return;
139
5b4f1f6c
RK		 140 if (enable) {
141 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
142 SDHCI_CARD_PRESENT;
d25928d1 143
5b4f1f6c
RK		 144 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
145 SDHCI_INT_CARD_INSERT;
146 } else {
147 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
148 }
b537f94c
RK		 149
150 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
151 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 152}
153
154static void sdhci_enable_card_detection(struct sdhci_host *host)
155{
156 sdhci_set_card_detection(host, true);
157}
158
159static void sdhci_disable_card_detection(struct sdhci_host *host)
160{
161 sdhci_set_card_detection(host, false);
162}
163
03231f9b 164void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 165{
e16514d8 166 unsigned long timeout;
393c1a34 167
4e4141a5 168 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 169
f0710a55 170 if (mask & SDHCI_RESET_ALL) {
d129bceb 171 host->clock = 0;
f0710a55
AH		 172 /* Reset-all turns off SD Bus Power */
173 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
174 sdhci_runtime_pm_bus_off(host);
175 }
d129bceb 176
e16514d8
PO		 177 /* Wait max 100 ms */
178 timeout = 100;
179
180 /* hw clears the bit when it's done */
4e4141a5 181 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 182 if (timeout == 0) {
a3c76eb9 183 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 184 mmc_hostname(host->mmc), (int)mask);
185 sdhci_dumpregs(host);
186 return;
187 }
188 timeout--;
189 mdelay(1);
d129bceb 190 }
03231f9b
RK		 191}
192EXPORT_SYMBOL_GPL(sdhci_reset);
193
194static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
195{
196 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
135b0a28 197 if (!sdhci_do_get_cd(host))
03231f9b
RK		 198 return;
199 }
063a9dbb 200
03231f9b 201 host->ops->reset(host, mask);
393c1a34 202
da91a8f9
RK		 203 if (mask & SDHCI_RESET_ALL) {
204 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
205 if (host->ops->enable_dma)
206 host->ops->enable_dma(host);
207 }
208
209 /* Resetting the controller clears many */
210 host->preset_enabled = false;
3abc1e80 211 }
d129bceb
PO		 212}
213
2f4cbb3d
NP		 214static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
215
216static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 217{
2f4cbb3d 218 if (soft)
03231f9b 219 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 220 else
03231f9b 221 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 222
b537f94c
RK		 223 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
224 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
225 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
226 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
227 SDHCI_INT_RESPONSE;
228
229 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
230 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 231
232 if (soft) {
233 /* force clock reconfiguration */
234 host->clock = 0;
235 sdhci_set_ios(host->mmc, &host->mmc->ios);
236 }
7260cf5e 237}
d129bceb 238
7260cf5e
AV		 239static void sdhci_reinit(struct sdhci_host *host)
240{
2f4cbb3d 241 sdhci_init(host, 0);
7260cf5e 242 sdhci_enable_card_detection(host);
d129bceb
PO		 243}
244
245static void sdhci_activate_led(struct sdhci_host *host)
246{
247 u8 ctrl;
248
4e4141a5 249 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 250 ctrl |= SDHCI_CTRL_LED;
4e4141a5 251 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 252}
253
254static void sdhci_deactivate_led(struct sdhci_host *host)
255{
256 u8 ctrl;
257
4e4141a5 258 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 259 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 260 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 261}
262
f9134319 263#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 264static void sdhci_led_control(struct led_classdev *led,
265 enum led_brightness brightness)
266{
267 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
268 unsigned long flags;
269
270 spin_lock_irqsave(&host->lock, flags);
271
66fd8ad5
AH		 272 if (host->runtime_suspended)
273 goto out;
274
2f730fec
PO		 275 if (brightness == LED_OFF)
276 sdhci_deactivate_led(host);
277 else
278 sdhci_activate_led(host);
66fd8ad5 279out:
2f730fec
PO		 280 spin_unlock_irqrestore(&host->lock, flags);
281}
282#endif
283
d129bceb
PO		 284/*****************************************************************************\
285 * *
286 * Core functions *
287 * *
288\*****************************************************************************/
289
a406f5a3 290static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 291{
7659150c
PO		 292 unsigned long flags;
293 size_t blksize, len, chunk;
7244b85b 294 u32 uninitialized_var(scratch);
7659150c 295 u8 *buf;
d129bceb 296
a406f5a3 297 DBG("PIO reading\n");
d129bceb 298
a406f5a3 299 blksize = host->data->blksz;
7659150c 300 chunk = 0;
d129bceb 301
7659150c 302 local_irq_save(flags);
d129bceb 303
a406f5a3 304 while (blksize) {
bf3a35ac 305 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 306
7659150c 307 len = min(host->sg_miter.length, blksize);
d129bceb 308
7659150c
PO		 309 blksize -= len;
310 host->sg_miter.consumed = len;
14d836e7 311
7659150c 312 buf = host->sg_miter.addr;
d129bceb 313
7659150c
PO		 314 while (len) {
315 if (chunk == 0) {
4e4141a5 316 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 317 chunk = 4;
a406f5a3 318 }
7659150c
PO		 319
320 *buf = scratch & 0xFF;
321
322 buf++;
323 scratch >>= 8;
324 chunk--;
325 len--;
d129bceb 326 }
a406f5a3 327 }
7659150c
PO		 328
329 sg_miter_stop(&host->sg_miter);
330
331 local_irq_restore(flags);
a406f5a3 332}
d129bceb 333
a406f5a3
PO		 334static void sdhci_write_block_pio(struct sdhci_host *host)
335{
7659150c
PO		 336 unsigned long flags;
337 size_t blksize, len, chunk;
338 u32 scratch;
339 u8 *buf;
d129bceb 340
a406f5a3
PO		 341 DBG("PIO writing\n");
342
343 blksize = host->data->blksz;
7659150c
PO		 344 chunk = 0;
345 scratch = 0;
d129bceb 346
7659150c 347 local_irq_save(flags);
d129bceb 348
a406f5a3 349 while (blksize) {
bf3a35ac 350 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 351
7659150c
PO		 352 len = min(host->sg_miter.length, blksize);
353
354 blksize -= len;
355 host->sg_miter.consumed = len;
356
357 buf = host->sg_miter.addr;
d129bceb 358
7659150c
PO		 359 while (len) {
360 scratch |= (u32)*buf << (chunk * 8);
361
362 buf++;
363 chunk++;
364 len--;
365
366 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 367 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 368 chunk = 0;
369 scratch = 0;
d129bceb 370 }
d129bceb
PO		 371 }
372 }
7659150c
PO		 373
374 sg_miter_stop(&host->sg_miter);
375
376 local_irq_restore(flags);
a406f5a3
PO		 377}
378
379static void sdhci_transfer_pio(struct sdhci_host *host)
380{
381 u32 mask;
382
383 BUG_ON(!host->data);
384
7659150c 385 if (host->blocks == 0)
a406f5a3
PO		 386 return;
387
388 if (host->data->flags & MMC_DATA_READ)
389 mask = SDHCI_DATA_AVAILABLE;
390 else
391 mask = SDHCI_SPACE_AVAILABLE;
392
4a3cba32
PO		 393 /*
394 * Some controllers (JMicron JMB38x) mess up the buffer bits
395 * for transfers < 4 bytes. As long as it is just one block,
396 * we can ignore the bits.
397 */
398 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
399 (host->data->blocks == 1))
400 mask = ~0;
401
4e4141a5 402 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 403 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
404 udelay(100);
405
a406f5a3
PO		 406 if (host->data->flags & MMC_DATA_READ)
407 sdhci_read_block_pio(host);
408 else
409 sdhci_write_block_pio(host);
d129bceb 410
7659150c
PO		 411 host->blocks--;
412 if (host->blocks == 0)
a406f5a3 413 break;
a406f5a3 414 }
d129bceb 415
a406f5a3 416 DBG("PIO transfer complete.\n");
d129bceb
PO		 417}
418
48857d9b 419static int sdhci_pre_dma_transfer(struct sdhci_host *host,
c0999b72 420 struct mmc_data *data, int cookie)
48857d9b
RK		 421{
422 int sg_count;
423
94538e51
RK		 424 /*
425 * If the data buffers are already mapped, return the previous
426 * dma_map_sg() result.
427 */
428 if (data->host_cookie == COOKIE_PRE_MAPPED)
48857d9b 429 return data->sg_count;
48857d9b
RK		 430
431 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
432 data->flags & MMC_DATA_WRITE ?
433 DMA_TO_DEVICE : DMA_FROM_DEVICE);
434
435 if (sg_count == 0)
436 return -ENOSPC;
437
438 data->sg_count = sg_count;
c0999b72 439 data->host_cookie = cookie;
48857d9b
RK		 440
441 return sg_count;
442}
443
2134a922
PO		 444static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
445{
446 local_irq_save(*flags);
482fce99 447 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 448}
449
450static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
451{
482fce99 452 kunmap_atomic(buffer);
2134a922
PO		 453 local_irq_restore(*flags);
454}
455
e57a5f61
AH		 456static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
457 dma_addr_t addr, int len, unsigned cmd)
118cd17d 458{
e57a5f61 459 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 460
e57a5f61 461 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 462 dma_desc->cmd = cpu_to_le16(cmd);
463 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 464 dma_desc->addr_lo = cpu_to_le32((u32)addr);
465
466 if (host->flags & SDHCI_USE_64_BIT_DMA)
467 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 468}
469
b5ffa674
AH		 470static void sdhci_adma_mark_end(void *desc)
471{
e57a5f61 472 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 473
e57a5f61 474 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 475 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 476}
477
60c64762
RK		 478static void sdhci_adma_table_pre(struct sdhci_host *host,
479 struct mmc_data *data, int sg_count)
2134a922 480{
2134a922 481 struct scatterlist *sg;
2134a922 482 unsigned long flags;
acc3ad13
RK		 483 dma_addr_t addr, align_addr;
484 void *desc, *align;
485 char *buffer;
486 int len, offset, i;
2134a922
PO		 487
488 /*
489 * The spec does not specify endianness of descriptor table.
490 * We currently guess that it is LE.
491 */
492
60c64762 493 host->sg_count = sg_count;
2134a922 494
4efaa6fb 495 desc = host->adma_table;
2134a922
PO		 496 align = host->align_buffer;
497
498 align_addr = host->align_addr;
499
500 for_each_sg(data->sg, sg, host->sg_count, i) {
501 addr = sg_dma_address(sg);
502 len = sg_dma_len(sg);
503
504 /*
acc3ad13
RK		 505 * The SDHCI specification states that ADMA addresses must
506 * be 32-bit aligned. If they aren't, then we use a bounce
507 * buffer for the (up to three) bytes that screw up the
2134a922
PO		 508 * alignment.
509 */
04a5ae6f
AH		 510 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
511 SDHCI_ADMA2_MASK;
2134a922
PO		 512 if (offset) {
513 if (data->flags & MMC_DATA_WRITE) {
514 buffer = sdhci_kmap_atomic(sg, &flags);
515 memcpy(align, buffer, offset);
516 sdhci_kunmap_atomic(buffer, &flags);
517 }
518
118cd17d 519 /* tran, valid */
e57a5f61 520 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 521 ADMA2_TRAN_VALID);
2134a922
PO		 522
523 BUG_ON(offset > 65536);
524
04a5ae6f
AH		 525 align += SDHCI_ADMA2_ALIGN;
526 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 527
76fe379a 528 desc += host->desc_sz;
2134a922
PO		 529
530 addr += offset;
531 len -= offset;
532 }
533
2134a922
PO		 534 BUG_ON(len > 65536);
535
347ea32d
AH		 536 if (len) {
537 /* tran, valid */
538 sdhci_adma_write_desc(host, desc, addr, len,
539 ADMA2_TRAN_VALID);
540 desc += host->desc_sz;
541 }
2134a922
PO		 542
543 /*
544 * If this triggers then we have a calculation bug
545 * somewhere. :/
546 */
76fe379a 547 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 548 }
549
70764a90 550 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
acc3ad13 551 /* Mark the last descriptor as the terminating descriptor */
4efaa6fb 552 if (desc != host->adma_table) {
76fe379a 553 desc -= host->desc_sz;
b5ffa674 554 sdhci_adma_mark_end(desc);
70764a90
TA		 555 }
556 } else {
acc3ad13 557 /* Add a terminating entry - nop, end, valid */
e57a5f61 558 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 559 }
2134a922
PO		 560}
561
562static void sdhci_adma_table_post(struct sdhci_host *host,
563 struct mmc_data *data)
564{
2134a922
PO		 565 struct scatterlist *sg;
566 int i, size;
1c3d5f6d 567 void *align;
2134a922
PO		 568 char *buffer;
569 unsigned long flags;
570
47fa9613
RK		 571 if (data->flags & MMC_DATA_READ) {
572 bool has_unaligned = false;
de0b65a7 573
47fa9613
RK		 574 /* Do a quick scan of the SG list for any unaligned mappings */
575 for_each_sg(data->sg, sg, host->sg_count, i)
576 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
577 has_unaligned = true;
578 break;
579 }
2134a922 580
47fa9613
RK		 581 if (has_unaligned) {
582 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
f55c98f7 583 data->sg_len, DMA_FROM_DEVICE);
2134a922 584
47fa9613 585 align = host->align_buffer;
2134a922 586
47fa9613
RK		 587 for_each_sg(data->sg, sg, host->sg_count, i) {
588 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
589 size = SDHCI_ADMA2_ALIGN -
590 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
591
592 buffer = sdhci_kmap_atomic(sg, &flags);
593 memcpy(buffer, align, size);
594 sdhci_kunmap_atomic(buffer, &flags);
2134a922 595
47fa9613
RK		 596 align += SDHCI_ADMA2_ALIGN;
597 }
2134a922
PO		 598 }
599 }
600 }
2134a922
PO		 601}
602
a3c7778f 603static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 604{
1c8cde92 605 u8 count;
a3c7778f 606 struct mmc_data *data = cmd->data;
1c8cde92 607 unsigned target_timeout, current_timeout;
d129bceb 608
ee53ab5d
PO		 609 /*
610 * If the host controller provides us with an incorrect timeout
611 * value, just skip the check and use 0xE. The hardware may take
612 * longer to time out, but that's much better than having a too-short
613 * timeout value.
614 */
11a2f1b7 615 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 616 return 0xE;
e538fbe8 617
a3c7778f 618 /* Unspecified timeout, assume max */
1d4d7744 619 if (!data && !cmd->busy_timeout)
a3c7778f 620 return 0xE;
d129bceb 621
a3c7778f
AW		 622 /* timeout in us */
623 if (!data)
1d4d7744 624 target_timeout = cmd->busy_timeout * 1000;
78a2ca27 625 else {
fafcfda9 626 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
7f05538a
RK		 627 if (host->clock && data->timeout_clks) {
628 unsigned long long val;
629
630 /*
631 * data->timeout_clks is in units of clock cycles.
632 * host->clock is in Hz. target_timeout is in us.
633 * Hence, us = 1000000 * cycles / Hz. Round up.
634 */
635 val = 1000000 * data->timeout_clks;
636 if (do_div(val, host->clock))
637 target_timeout++;
638 target_timeout += val;
639 }
78a2ca27 640 }
81b39802 641
1c8cde92
PO		 642 /*
643 * Figure out needed cycles.
644 * We do this in steps in order to fit inside a 32 bit int.
645 * The first step is the minimum timeout, which will have a
646 * minimum resolution of 6 bits:
647 * (1) 2^13*1000 > 2^22,
648 * (2) host->timeout_clk < 2^16
649 * =>
650 * (1) / (2) > 2^6
651 */
652 count = 0;
653 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
654 while (current_timeout < target_timeout) {
655 count++;
656 current_timeout <<= 1;
657 if (count >= 0xF)
658 break;
659 }
660
661 if (count >= 0xF) {
09eeff52
CB		 662 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
663 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 664 count = 0xE;
665 }
666
ee53ab5d
PO		 667 return count;
668}
669
6aa943ab
AV		 670static void sdhci_set_transfer_irqs(struct sdhci_host *host)
671{
672 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
673 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
674
675 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 676 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 677 else
b537f94c
RK		 678 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
679
680 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
681 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 682}
683
b45e668a 684static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 685{
686 u8 count;
b45e668a
AD		 687
688 if (host->ops->set_timeout) {
689 host->ops->set_timeout(host, cmd);
690 } else {
691 count = sdhci_calc_timeout(host, cmd);
692 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
693 }
694}
695
696static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
697{
2134a922 698 u8 ctrl;
a3c7778f 699 struct mmc_data *data = cmd->data;
ee53ab5d
PO		 700
701 WARN_ON(host->data);
702
b45e668a
AD		 703 if (data || (cmd->flags & MMC_RSP_BUSY))
704 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 705
706 if (!data)
ee53ab5d
PO		 707 return;
708
709 /* Sanity checks */
710 BUG_ON(data->blksz * data->blocks > 524288);
711 BUG_ON(data->blksz > host->mmc->max_blk_size);
712 BUG_ON(data->blocks > 65535);
713
714 host->data = data;
715 host->data_early = 0;
f6a03cbf 716 host->data->bytes_xfered = 0;
ee53ab5d 717
fce14421 718 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2134a922 719 struct scatterlist *sg;
df953925 720 unsigned int length_mask, offset_mask;
a0eaf0f9 721 int i;
2134a922 722
fce14421
RK		 723 host->flags |= SDHCI_REQ_USE_DMA;
724
725 /*
726 * FIXME: This doesn't account for merging when mapping the
727 * scatterlist.
728 *
729 * The assumption here being that alignment and lengths are
730 * the same after DMA mapping to device address space.
731 */
a0eaf0f9 732 length_mask = 0;
df953925 733 offset_mask = 0;
2134a922 734 if (host->flags & SDHCI_USE_ADMA) {
df953925 735 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
a0eaf0f9 736 length_mask = 3;
df953925
RK		 737 /*
738 * As we use up to 3 byte chunks to work
739 * around alignment problems, we need to
740 * check the offset as well.
741 */
742 offset_mask = 3;
743 }
2134a922
PO		 744 } else {
745 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
a0eaf0f9 746 length_mask = 3;
df953925
RK		 747 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
748 offset_mask = 3;
2134a922
PO		 749 }
750
df953925 751 if (unlikely(length_mask | offset_mask)) {
2134a922 752 for_each_sg(data->sg, sg, data->sg_len, i) {
a0eaf0f9 753 if (sg->length & length_mask) {
2e4456f0 754 DBG("Reverting to PIO because of transfer size (%d)\n",
a0eaf0f9 755 sg->length);
2134a922
PO		 756 host->flags &= ~SDHCI_REQ_USE_DMA;
757 break;
758 }
a0eaf0f9 759 if (sg->offset & offset_mask) {
2e4456f0 760 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 761 host->flags &= ~SDHCI_REQ_USE_DMA;
762 break;
763 }
764 }
765 }
766 }
767
8f1934ce 768 if (host->flags & SDHCI_REQ_USE_DMA) {
c0999b72 769 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
60c64762
RK		 770
771 if (sg_cnt <= 0) {
772 /*
773 * This only happens when someone fed
774 * us an invalid request.
775 */
776 WARN_ON(1);
777 host->flags &= ~SDHCI_REQ_USE_DMA;
778 } else if (host->flags & SDHCI_USE_ADMA) {
779 sdhci_adma_table_pre(host, data, sg_cnt);
780
781 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
782 if (host->flags & SDHCI_USE_64_BIT_DMA)
783 sdhci_writel(host,
784 (u64)host->adma_addr >> 32,
785 SDHCI_ADMA_ADDRESS_HI);
8f1934ce 786 } else {
60c64762
RK		 787 WARN_ON(sg_cnt != 1);
788 sdhci_writel(host, sg_dma_address(data->sg),
789 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 790 }
791 }
792
2134a922
PO		 793 /*
794 * Always adjust the DMA selection as some controllers
795 * (e.g. JMicron) can't do PIO properly when the selection
796 * is ADMA.
797 */
798 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 799 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 800 ctrl &= ~SDHCI_CTRL_DMA_MASK;
801 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 802 (host->flags & SDHCI_USE_ADMA)) {
803 if (host->flags & SDHCI_USE_64_BIT_DMA)
804 ctrl |= SDHCI_CTRL_ADMA64;
805 else
806 ctrl |= SDHCI_CTRL_ADMA32;
807 } else {
2134a922 808 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 809 }
4e4141a5 810 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 811 }
812
8f1934ce 813 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 814 int flags;
815
816 flags = SG_MITER_ATOMIC;
817 if (host->data->flags & MMC_DATA_READ)
818 flags |= SG_MITER_TO_SG;
819 else
820 flags |= SG_MITER_FROM_SG;
821 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 822 host->blocks = data->blocks;
d129bceb 823 }
c7fa9963 824
6aa943ab
AV		 825 sdhci_set_transfer_irqs(host);
826
f6a03cbf
MV		 827 /* Set the DMA boundary value and block size */
828 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
829 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 830 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 831}
832
833static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 834 struct mmc_command *cmd)
c7fa9963 835{
d3fc5d71 836 u16 mode = 0;
e89d456f 837 struct mmc_data *data = cmd->data;
c7fa9963 838
2b558c13 839 if (data == NULL) {
9b8ffea6
VW		 840 if (host->quirks2 &
841 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
842 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
843 } else {
2b558c13 844 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 845 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
846 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 847 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 848 }
c7fa9963 849 return;
2b558c13 850 }
c7fa9963 851
e538fbe8
PO		 852 WARN_ON(!host->data);
853
d3fc5d71
VY		 854 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
855 mode = SDHCI_TRNS_BLK_CNT_EN;
856
e89d456f 857 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 858 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 859 /*
860 * If we are sending CMD23, CMD12 never gets sent
861 * on successful completion (so no Auto-CMD12).
862 */
85cc1c33
CD		 863 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
864 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 865 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 866 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
867 mode |= SDHCI_TRNS_AUTO_CMD23;
868 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
869 }
c4512f79 870 }
8edf6371 871
c7fa9963
PO		 872 if (data->flags & MMC_DATA_READ)
873 mode |= SDHCI_TRNS_READ;
c9fddbc4 874 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 875 mode |= SDHCI_TRNS_DMA;
876
4e4141a5 877 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 878}
879
880static void sdhci_finish_data(struct sdhci_host *host)
881{
882 struct mmc_data *data;
d129bceb
PO		 883
884 BUG_ON(!host->data);
885
886 data = host->data;
887 host->data = NULL;
888
add8913d
RK		 889 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
890 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
891 sdhci_adma_table_post(host, data);
d129bceb
PO		 892
893 /*
c9b74c5b
PO		 894 * The specification states that the block count register must
895 * be updated, but it does not specify at what point in the
896 * data flow. That makes the register entirely useless to read
897 * back so we have to assume that nothing made it to the card
898 * in the event of an error.
d129bceb 899 */
c9b74c5b
PO		 900 if (data->error)
901 data->bytes_xfered = 0;
d129bceb 902 else
c9b74c5b 903 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 904
e89d456f
AW		 905 /*
906 * Need to send CMD12 if -
907 * a) open-ended multiblock transfer (no CMD23)
908 * b) error in multiblock transfer
909 */
910 if (data->stop &&
911 (data->error ||
912 !host->mrq->sbc)) {
913
d129bceb
PO		 914 /*
915 * The controller needs a reset of internal state machines
916 * upon error conditions.
917 */
17b0429d 918 if (data->error) {
03231f9b
RK		 919 sdhci_do_reset(host, SDHCI_RESET_CMD);
920 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 921 }
922
923 sdhci_send_command(host, data->stop);
924 } else
925 tasklet_schedule(&host->finish_tasklet);
926}
927
c0e55129 928void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 929{
930 int flags;
fd2208d7 931 u32 mask;
7cb2c76f 932 unsigned long timeout;
d129bceb
PO		 933
934 WARN_ON(host->cmd);
935
96776200
RK		 936 /* Initially, a command has no error */
937 cmd->error = 0;
938
d129bceb 939 /* Wait max 10 ms */
7cb2c76f 940 timeout = 10;
fd2208d7
PO		 941
942 mask = SDHCI_CMD_INHIBIT;
943 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
944 mask |= SDHCI_DATA_INHIBIT;
945
946 /* We shouldn't wait for data inihibit for stop commands, even
947 though they might use busy signaling */
948 if (host->mrq->data && (cmd == host->mrq->data->stop))
949 mask &= ~SDHCI_DATA_INHIBIT;
950
4e4141a5 951 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 952 if (timeout == 0) {
2e4456f0
MV		 953 pr_err("%s: Controller never released inhibit bit(s).\n",
954 mmc_hostname(host->mmc));
d129bceb 955 sdhci_dumpregs(host);
17b0429d 956 cmd->error = -EIO;
d129bceb
PO		 957 tasklet_schedule(&host->finish_tasklet);
958 return;
959 }
7cb2c76f
PO		 960 timeout--;
961 mdelay(1);
962 }
d129bceb 963
3e1a6892 964 timeout = jiffies;
1d4d7744
UH		 965 if (!cmd->data && cmd->busy_timeout > 9000)
966 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 967 else
968 timeout += 10 * HZ;
969 mod_timer(&host->timer, timeout);
d129bceb
PO		 970
971 host->cmd = cmd;
e99783a4 972 host->busy_handle = 0;
d129bceb 973
a3c7778f 974 sdhci_prepare_data(host, cmd);
d129bceb 975
4e4141a5 976 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 977
e89d456f 978 sdhci_set_transfer_mode(host, cmd);
c7fa9963 979
d129bceb 980 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 981 pr_err("%s: Unsupported response type!\n",
d129bceb 982 mmc_hostname(host->mmc));
17b0429d 983 cmd->error = -EINVAL;
d129bceb
PO		 984 tasklet_schedule(&host->finish_tasklet);
985 return;
986 }
987
988 if (!(cmd->flags & MMC_RSP_PRESENT))
989 flags = SDHCI_CMD_RESP_NONE;
990 else if (cmd->flags & MMC_RSP_136)
991 flags = SDHCI_CMD_RESP_LONG;
992 else if (cmd->flags & MMC_RSP_BUSY)
993 flags = SDHCI_CMD_RESP_SHORT_BUSY;
994 else
995 flags = SDHCI_CMD_RESP_SHORT;
996
997 if (cmd->flags & MMC_RSP_CRC)
998 flags |= SDHCI_CMD_CRC;
999 if (cmd->flags & MMC_RSP_OPCODE)
1000 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1001
1002 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1003 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1004 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1005 flags |= SDHCI_CMD_DATA;
1006
4e4141a5 1007 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1008}
c0e55129 1009EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1010
1011static void sdhci_finish_command(struct sdhci_host *host)
1012{
1013 int i;
1014
1015 BUG_ON(host->cmd == NULL);
1016
1017 if (host->cmd->flags & MMC_RSP_PRESENT) {
1018 if (host->cmd->flags & MMC_RSP_136) {
1019 /* CRC is stripped so we need to do some shifting. */
1020 for (i = 0;i < 4;i++) {
4e4141a5 1021 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1022 SDHCI_RESPONSE + (3-i)*4) << 8;
1023 if (i != 3)
1024 host->cmd->resp[i] |=
4e4141a5 1025 sdhci_readb(host,
d129bceb
PO		 1026 SDHCI_RESPONSE + (3-i)*4-1);
1027 }
1028 } else {
4e4141a5 1029 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1030 }
1031 }
1032
e89d456f
AW		 1033 /* Finished CMD23, now send actual command. */
1034 if (host->cmd == host->mrq->sbc) {
1035 host->cmd = NULL;
1036 sdhci_send_command(host, host->mrq->cmd);
1037 } else {
e538fbe8 1038
e89d456f
AW		 1039 /* Processed actual command. */
1040 if (host->data && host->data_early)
1041 sdhci_finish_data(host);
d129bceb 1042
e89d456f
AW		 1043 if (!host->cmd->data)
1044 tasklet_schedule(&host->finish_tasklet);
1045
1046 host->cmd = NULL;
1047 }
d129bceb
PO		 1048}
1049
52983382
KL		 1050static u16 sdhci_get_preset_value(struct sdhci_host *host)
1051{
d975f121 1052 u16 preset = 0;
52983382 1053
d975f121
RK		 1054 switch (host->timing) {
1055 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1056 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1057 break;
d975f121 1058 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1059 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1060 break;
d975f121 1061 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1062 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1063 break;
d975f121
RK		 1064 case MMC_TIMING_UHS_SDR104:
1065 case MMC_TIMING_MMC_HS200:
52983382
KL		 1066 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1067 break;
d975f121 1068 case MMC_TIMING_UHS_DDR50:
0dafa60e 1069 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1070 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1071 break;
e9fb05d5
AH		 1072 case MMC_TIMING_MMC_HS400:
1073 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1074 break;
52983382
KL		 1075 default:
1076 pr_warn("%s: Invalid UHS-I mode selected\n",
1077 mmc_hostname(host->mmc));
1078 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1079 break;
1080 }
1081 return preset;
1082}
1083
1771059c 1084void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1085{
c3ed3877 1086 int div = 0; /* Initialized for compiler warning */
df16219f 1087 int real_div = div, clk_mul = 1;
c3ed3877 1088 u16 clk = 0;
7cb2c76f 1089 unsigned long timeout;
5497159c 1090 bool switch_base_clk = false;
d129bceb 1091
1650d0c7
RK		 1092 host->mmc->actual_clock = 0;
1093
4e4141a5 1094 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
af951761 1095 if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1096 mdelay(1);
d129bceb
PO		 1097
1098 if (clock == 0)
373073ef 1099 return;
d129bceb 1100
85105c53 1101 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1102 if (host->preset_enabled) {
52983382
KL		 1103 u16 pre_val;
1104
1105 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1106 pre_val = sdhci_get_preset_value(host);
1107 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1108 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1109 if (host->clk_mul &&
1110 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1111 clk = SDHCI_PROG_CLOCK_MODE;
1112 real_div = div + 1;
1113 clk_mul = host->clk_mul;
1114 } else {
1115 real_div = max_t(int, 1, div << 1);
1116 }
1117 goto clock_set;
1118 }
1119
c3ed3877
AN		 1120 /*
1121 * Check if the Host Controller supports Programmable Clock
1122 * Mode.
1123 */
1124 if (host->clk_mul) {
52983382
KL		 1125 for (div = 1; div <= 1024; div++) {
1126 if ((host->max_clk * host->clk_mul / div)
1127 <= clock)
1128 break;
1129 }
5497159c 1130 if ((host->max_clk * host->clk_mul / div) <= clock) {
1131 /*
1132 * Set Programmable Clock Mode in the Clock
1133 * Control register.
1134 */
1135 clk = SDHCI_PROG_CLOCK_MODE;
1136 real_div = div;
1137 clk_mul = host->clk_mul;
1138 div--;
1139 } else {
1140 /*
1141 * Divisor can be too small to reach clock
1142 * speed requirement. Then use the base clock.
1143 */
1144 switch_base_clk = true;
1145 }
1146 }
1147
1148 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1149 /* Version 3.00 divisors must be a multiple of 2. */
1150 if (host->max_clk <= clock)
1151 div = 1;
1152 else {
1153 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1154 div += 2) {
1155 if ((host->max_clk / div) <= clock)
1156 break;
1157 }
85105c53 1158 }
df16219f 1159 real_div = div;
c3ed3877 1160 div >>= 1;
d1955c3a
SG		 1161 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1162 && !div && host->max_clk <= 25000000)
1163 div = 1;
85105c53
ZG		 1164 }
1165 } else {
1166 /* Version 2.00 divisors must be a power of 2. */
0397526d 1167 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1168 if ((host->max_clk / div) <= clock)
1169 break;
1170 }
df16219f 1171 real_div = div;
c3ed3877 1172 div >>= 1;
d129bceb 1173 }
d129bceb 1174
52983382 1175clock_set:
03d6f5ff 1176 if (real_div)
df16219f 1177 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1178 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1179 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1180 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1181 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1182 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1183
27f6cb16
CB		 1184 /* Wait max 20 ms */
1185 timeout = 20;
4e4141a5 1186 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1187 & SDHCI_CLOCK_INT_STABLE)) {
1188 if (timeout == 0) {
2e4456f0
MV		 1189 pr_err("%s: Internal clock never stabilised.\n",
1190 mmc_hostname(host->mmc));
d129bceb
PO		 1191 sdhci_dumpregs(host);
1192 return;
1193 }
7cb2c76f
PO		 1194 timeout--;
1195 mdelay(1);
1196 }
d129bceb
PO		 1197
1198 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1199 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1200}
1771059c 1201EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1202
1dceb041
AH		 1203static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1204 unsigned short vdd)
146ad66e 1205{
3a48edc4 1206 struct mmc_host *mmc = host->mmc;
1dceb041
AH		 1207
1208 spin_unlock_irq(&host->lock);
1209 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1210 spin_lock_irq(&host->lock);
1211
1212 if (mode != MMC_POWER_OFF)
1213 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1214 else
1215 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1216}
1217
1218void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1219 unsigned short vdd)
1220{
8364248a 1221 u8 pwr = 0;
146ad66e 1222
24fbb3ca
RK		 1223 if (mode != MMC_POWER_OFF) {
1224 switch (1 << vdd) {
ae628903
PO		 1225 case MMC_VDD_165_195:
1226 pwr = SDHCI_POWER_180;
1227 break;
1228 case MMC_VDD_29_30:
1229 case MMC_VDD_30_31:
1230 pwr = SDHCI_POWER_300;
1231 break;
1232 case MMC_VDD_32_33:
1233 case MMC_VDD_33_34:
1234 pwr = SDHCI_POWER_330;
1235 break;
1236 default:
9d5de93f
AH		 1237 WARN(1, "%s: Invalid vdd %#x\n",
1238 mmc_hostname(host->mmc), vdd);
1239 break;
ae628903
PO		 1240 }
1241 }
1242
1243 if (host->pwr == pwr)
e921a8b6 1244 return;
146ad66e 1245
ae628903
PO		 1246 host->pwr = pwr;
1247
1248 if (pwr == 0) {
4e4141a5 1249 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1250 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1251 sdhci_runtime_pm_bus_off(host);
e921a8b6
RK		 1252 } else {
1253 /*
1254 * Spec says that we should clear the power reg before setting
1255 * a new value. Some controllers don't seem to like this though.
1256 */
1257 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1258 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1259
e921a8b6
RK		 1260 /*
1261 * At least the Marvell CaFe chip gets confused if we set the
1262 * voltage and set turn on power at the same time, so set the
1263 * voltage first.
1264 */
1265 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1266 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1267
e921a8b6 1268 pwr |= SDHCI_POWER_ON;
146ad66e 1269
e921a8b6 1270 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1271
e921a8b6
RK		 1272 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1273 sdhci_runtime_pm_bus_on(host);
f0710a55 1274
e921a8b6
RK		 1275 /*
1276 * Some controllers need an extra 10ms delay of 10ms before
1277 * they can apply clock after applying power
1278 */
1279 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1280 mdelay(10);
1281 }
1dceb041
AH		 1282}
1283EXPORT_SYMBOL_GPL(sdhci_set_power);
918f4cbd 1284
1dceb041
AH		 1285static void __sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1286 unsigned short vdd)
1287{
1288 struct mmc_host *mmc = host->mmc;
1289
1290 if (host->ops->set_power)
1291 host->ops->set_power(host, mode, vdd);
1292 else if (!IS_ERR(mmc->supply.vmmc))
1293 sdhci_set_power_reg(host, mode, vdd);
1294 else
1295 sdhci_set_power(host, mode, vdd);
146ad66e
PO		 1296}
1297
d129bceb
PO		 1298/*****************************************************************************\
1299 * *
1300 * MMC callbacks *
1301 * *
1302\*****************************************************************************/
1303
1304static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1305{
1306 struct sdhci_host *host;
505a8680 1307 int present;
d129bceb
PO		 1308 unsigned long flags;
1309
1310 host = mmc_priv(mmc);
1311
04e079cf 1312 /* Firstly check card presence */
8d28b7a7 1313 present = mmc->ops->get_cd(mmc);
2836766a 1314
d129bceb
PO		 1315 spin_lock_irqsave(&host->lock, flags);
1316
1317 WARN_ON(host->mrq != NULL);
1318
f9134319 1319#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1320 sdhci_activate_led(host);
2f730fec 1321#endif
e89d456f
AW		 1322
1323 /*
1324 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1325 * requests if Auto-CMD12 is enabled.
1326 */
1327 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1328 if (mrq->stop) {
1329 mrq->data->stop = NULL;
1330 mrq->stop = NULL;
1331 }
1332 }
d129bceb
PO		 1333
1334 host->mrq = mrq;
1335
68d1fb7e 1336 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1337 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1338 tasklet_schedule(&host->finish_tasklet);
cf2b5eea 1339 } else {
8edf6371 1340 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1341 sdhci_send_command(host, mrq->sbc);
1342 else
1343 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1344 }
d129bceb 1345
5f25a66f 1346 mmiowb();
d129bceb
PO		 1347 spin_unlock_irqrestore(&host->lock, flags);
1348}
1349
2317f56c
RK		 1350void sdhci_set_bus_width(struct sdhci_host *host, int width)
1351{
1352 u8 ctrl;
1353
1354 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1355 if (width == MMC_BUS_WIDTH_8) {
1356 ctrl &= ~SDHCI_CTRL_4BITBUS;
1357 if (host->version >= SDHCI_SPEC_300)
1358 ctrl |= SDHCI_CTRL_8BITBUS;
1359 } else {
1360 if (host->version >= SDHCI_SPEC_300)
1361 ctrl &= ~SDHCI_CTRL_8BITBUS;
1362 if (width == MMC_BUS_WIDTH_4)
1363 ctrl |= SDHCI_CTRL_4BITBUS;
1364 else
1365 ctrl &= ~SDHCI_CTRL_4BITBUS;
1366 }
1367 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1368}
1369EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1370
96d7b78c
RK		 1371void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1372{
1373 u16 ctrl_2;
1374
1375 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1376 /* Select Bus Speed Mode for host */
1377 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1378 if ((timing == MMC_TIMING_MMC_HS200) ||
1379 (timing == MMC_TIMING_UHS_SDR104))
1380 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1381 else if (timing == MMC_TIMING_UHS_SDR12)
1382 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1383 else if (timing == MMC_TIMING_UHS_SDR25)
1384 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1385 else if (timing == MMC_TIMING_UHS_SDR50)
1386 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1387 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1388 (timing == MMC_TIMING_MMC_DDR52))
1389 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1390 else if (timing == MMC_TIMING_MMC_HS400)
1391 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1392 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1393}
1394EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1395
66fd8ad5 1396static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1397{
d129bceb
PO		 1398 unsigned long flags;
1399 u8 ctrl;
3a48edc4 1400 struct mmc_host *mmc = host->mmc;
d129bceb 1401
d129bceb
PO		 1402 spin_lock_irqsave(&host->lock, flags);
1403
ceb6143b
AH		 1404 if (host->flags & SDHCI_DEVICE_DEAD) {
1405 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1406 if (!IS_ERR(mmc->supply.vmmc) &&
1407 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1408 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1409 return;
1410 }
1e72859e 1411
d129bceb
PO		 1412 /*
1413 * Reset the chip on each power off.
1414 * Should clear out any weird states.
1415 */
1416 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1417 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1418 sdhci_reinit(host);
d129bceb
PO		 1419 }
1420
52983382 1421 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1422 (ios->power_mode == MMC_POWER_UP) &&
1423 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1424 sdhci_enable_preset_value(host, false);
1425
373073ef 1426 if (!ios->clock || ios->clock != host->clock) {
1771059c 1427 host->ops->set_clock(host, ios->clock);
373073ef 1428 host->clock = ios->clock;
03d6f5ff
AD		 1429
1430 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1431 host->clock) {
1432 host->timeout_clk = host->mmc->actual_clock ?
1433 host->mmc->actual_clock / 1000 :
1434 host->clock / 1000;
1435 host->mmc->max_busy_timeout =
1436 host->ops->get_max_timeout_count ?
1437 host->ops->get_max_timeout_count(host) :
1438 1 << 27;
1439 host->mmc->max_busy_timeout /= host->timeout_clk;
1440 }
373073ef 1441 }
d129bceb 1442
1dceb041 1443 __sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1444
643a81ff
PR		 1445 if (host->ops->platform_send_init_74_clocks)
1446 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1447
2317f56c 1448 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1449
15ec4461 1450 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1451
3ab9c8da
PR		 1452 if ((ios->timing == MMC_TIMING_SD_HS ||
1453 ios->timing == MMC_TIMING_MMC_HS)
1454 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1455 ctrl |= SDHCI_CTRL_HISPD;
1456 else
1457 ctrl &= ~SDHCI_CTRL_HISPD;
1458
d6d50a15 1459 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1460 u16 clk, ctrl_2;
49c468fc
AN		 1461
1462 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1463 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1464 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1465 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1466 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1467 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1468 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1469 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1470 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1471
da91a8f9 1472 if (!host->preset_enabled) {
758535c4 1473 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1474 /*
1475 * We only need to set Driver Strength if the
1476 * preset value enable is not set.
1477 */
da91a8f9 1478 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1479 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1480 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1481 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1482 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1483 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1484 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1485 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1486 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1487 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1488 else {
2e4456f0
MV		 1489 pr_warn("%s: invalid driver type, default to driver type B\n",
1490 mmc_hostname(mmc));
43e943a0
PG		 1491 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1492 }
d6d50a15
AN		 1493
1494 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1495 } else {
1496 /*
1497 * According to SDHC Spec v3.00, if the Preset Value
1498 * Enable in the Host Control 2 register is set, we
1499 * need to reset SD Clock Enable before changing High
1500 * Speed Enable to avoid generating clock gliches.
1501 */
758535c4
AN		 1502
1503 /* Reset SD Clock Enable */
1504 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1505 clk &= ~SDHCI_CLOCK_CARD_EN;
1506 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1507
1508 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1509
1510 /* Re-enable SD Clock */
1771059c 1511 host->ops->set_clock(host, host->clock);
d6d50a15 1512 }
49c468fc 1513
49c468fc
AN		 1514 /* Reset SD Clock Enable */
1515 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1516 clk &= ~SDHCI_CLOCK_CARD_EN;
1517 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1518
96d7b78c 1519 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1520 host->timing = ios->timing;
49c468fc 1521
52983382
KL		 1522 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1523 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1524 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1525 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1526 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 1527 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1528 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 1529 u16 preset;
1530
1531 sdhci_enable_preset_value(host, true);
1532 preset = sdhci_get_preset_value(host);
1533 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1534 >> SDHCI_PRESET_DRV_SHIFT;
1535 }
1536
49c468fc 1537 /* Re-enable SD Clock */
1771059c 1538 host->ops->set_clock(host, host->clock);
758535c4
AN		 1539 } else
1540 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1541
b8352260
LD		 1542 /*
1543 * Some (ENE) controllers go apeshit on some ios operation,
1544 * signalling timeout and CRC errors even on CMD0. Resetting
1545 * it on each ios seems to solve the problem.
1546 */
c63705e1 1547 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1548 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1549
5f25a66f 1550 mmiowb();
d129bceb
PO		 1551 spin_unlock_irqrestore(&host->lock, flags);
1552}
1553
66fd8ad5
AH		 1554static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1555{
1556 struct sdhci_host *host = mmc_priv(mmc);
1557
66fd8ad5 1558 sdhci_do_set_ios(host, ios);
66fd8ad5
AH		 1559}
1560
94144a46
KL		 1561static int sdhci_do_get_cd(struct sdhci_host *host)
1562{
1563 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1564
1565 if (host->flags & SDHCI_DEVICE_DEAD)
1566 return 0;
1567
88af5655
II		 1568 /* If nonremovable, assume that the card is always present. */
1569 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
94144a46
KL		 1570 return 1;
1571
88af5655
II		 1572 /*
1573 * Try slot gpio detect, if defined it take precedence
1574 * over build in controller functionality
1575 */
94144a46
KL		 1576 if (!IS_ERR_VALUE(gpio_cd))
1577 return !!gpio_cd;
1578
88af5655
II		 1579 /* If polling, assume that the card is always present. */
1580 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1581 return 1;
1582
94144a46
KL		 1583 /* Host native card detect */
1584 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1585}
1586
1587static int sdhci_get_cd(struct mmc_host *mmc)
1588{
1589 struct sdhci_host *host = mmc_priv(mmc);
94144a46 1590
15e82076 1591 return sdhci_do_get_cd(host);
94144a46
KL		 1592}
1593
66fd8ad5 1594static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1595{
d129bceb 1596 unsigned long flags;
2dfb579c 1597 int is_readonly;
d129bceb 1598
d129bceb
PO		 1599 spin_lock_irqsave(&host->lock, flags);
1600
1e72859e 1601 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1602 is_readonly = 0;
1603 else if (host->ops->get_ro)
1604 is_readonly = host->ops->get_ro(host);
1e72859e 1605 else
2dfb579c
WS		 1606 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1607 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1608
1609 spin_unlock_irqrestore(&host->lock, flags);
1610
2dfb579c
WS		 1611 /* This quirk needs to be replaced by a callback-function later */
1612 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1613 !is_readonly : is_readonly;
d129bceb
PO		 1614}
1615
82b0e23a
TI		 1616#define SAMPLE_COUNT 5
1617
66fd8ad5 1618static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1619{
82b0e23a
TI		 1620 int i, ro_count;
1621
82b0e23a 1622 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1623 return sdhci_check_ro(host);
82b0e23a
TI		 1624
1625 ro_count = 0;
1626 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1627 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1628 if (++ro_count > SAMPLE_COUNT / 2)
1629 return 1;
1630 }
1631 msleep(30);
1632 }
1633 return 0;
1634}
1635
20758b66
AH		 1636static void sdhci_hw_reset(struct mmc_host *mmc)
1637{
1638 struct sdhci_host *host = mmc_priv(mmc);
1639
1640 if (host->ops && host->ops->hw_reset)
1641 host->ops->hw_reset(host);
1642}
1643
66fd8ad5 1644static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1645{
66fd8ad5 1646 struct sdhci_host *host = mmc_priv(mmc);
f75979b7 1647
15e82076 1648 return sdhci_do_get_ro(host);
66fd8ad5 1649}
f75979b7 1650
66fd8ad5
AH		 1651static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1652{
be138554 1653 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1654 if (enable)
b537f94c 1655 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1656 else
b537f94c
RK		 1657 host->ier &= ~SDHCI_INT_CARD_INT;
1658
1659 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1660 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1661 mmiowb();
1662 }
66fd8ad5
AH		 1663}
1664
1665static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1666{
1667 struct sdhci_host *host = mmc_priv(mmc);
1668 unsigned long flags;
f75979b7 1669
66fd8ad5 1670 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1671 if (enable)
1672 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1673 else
1674 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1675
66fd8ad5 1676 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1677 spin_unlock_irqrestore(&host->lock, flags);
1678}
1679
20b92a30 1680static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1681 struct mmc_ios *ios)
f2119df6 1682{
3a48edc4 1683 struct mmc_host *mmc = host->mmc;
20b92a30 1684 u16 ctrl;
6231f3de 1685 int ret;
f2119df6 1686
20b92a30
KL		 1687 /*
1688 * Signal Voltage Switching is only applicable for Host Controllers
1689 * v3.00 and above.
1690 */
1691 if (host->version < SDHCI_SPEC_300)
1692 return 0;
6231f3de 1693
f2119df6 1694 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1695
21f5998f 1696 switch (ios->signal_voltage) {
20b92a30
KL		 1697 case MMC_SIGNAL_VOLTAGE_330:
1698 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1699 ctrl &= ~SDHCI_CTRL_VDD_180;
1700 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1701
3a48edc4
TK		 1702 if (!IS_ERR(mmc->supply.vqmmc)) {
1703 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1704 3600000);
20b92a30 1705 if (ret) {
6606110d
JP		 1706 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1707 mmc_hostname(mmc));
20b92a30
KL		 1708 return -EIO;
1709 }
1710 }
1711 /* Wait for 5ms */
1712 usleep_range(5000, 5500);
f2119df6 1713
20b92a30
KL		 1714 /* 3.3V regulator output should be stable within 5 ms */
1715 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1716 if (!(ctrl & SDHCI_CTRL_VDD_180))
1717 return 0;
6231f3de 1718
6606110d
JP		 1719 pr_warn("%s: 3.3V regulator output did not became stable\n",
1720 mmc_hostname(mmc));
20b92a30
KL		 1721
1722 return -EAGAIN;
1723 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1724 if (!IS_ERR(mmc->supply.vqmmc)) {
1725 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1726 1700000, 1950000);
1727 if (ret) {
6606110d
JP		 1728 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1729 mmc_hostname(mmc));
20b92a30
KL		 1730 return -EIO;
1731 }
1732 }
6231f3de 1733
6231f3de
PR		 1734 /*
1735 * Enable 1.8V Signal Enable in the Host Control2
1736 * register
1737 */
20b92a30
KL		 1738 ctrl |= SDHCI_CTRL_VDD_180;
1739 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1740
9d967a61
VY		 1741 /* Some controller need to do more when switching */
1742 if (host->ops->voltage_switch)
1743 host->ops->voltage_switch(host);
1744
20b92a30
KL		 1745 /* 1.8V regulator output should be stable within 5 ms */
1746 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1747 if (ctrl & SDHCI_CTRL_VDD_180)
1748 return 0;
f2119df6 1749
6606110d
JP		 1750 pr_warn("%s: 1.8V regulator output did not became stable\n",
1751 mmc_hostname(mmc));
f2119df6 1752
20b92a30
KL		 1753 return -EAGAIN;
1754 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1755 if (!IS_ERR(mmc->supply.vqmmc)) {
1756 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1757 1300000);
20b92a30 1758 if (ret) {
6606110d
JP		 1759 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1760 mmc_hostname(mmc));
20b92a30 1761 return -EIO;
f2119df6
AN		 1762 }
1763 }
6231f3de 1764 return 0;
20b92a30 1765 default:
f2119df6
AN		 1766 /* No signal voltage switch required */
1767 return 0;
20b92a30 1768 }
f2119df6
AN		 1769}
1770
66fd8ad5 1771static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1772 struct mmc_ios *ios)
66fd8ad5
AH		 1773{
1774 struct sdhci_host *host = mmc_priv(mmc);
66fd8ad5
AH		 1775
1776 if (host->version < SDHCI_SPEC_300)
1777 return 0;
15e82076
UH		 1778
1779 return sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1780}
1781
20b92a30
KL		 1782static int sdhci_card_busy(struct mmc_host *mmc)
1783{
1784 struct sdhci_host *host = mmc_priv(mmc);
1785 u32 present_state;
1786
20b92a30
KL		 1787 /* Check whether DAT[3:0] is 0000 */
1788 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
20b92a30
KL		 1789
1790 return !(present_state & SDHCI_DATA_LVL_MASK);
1791}
1792
b5540ce1
AH		 1793static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1794{
1795 struct sdhci_host *host = mmc_priv(mmc);
1796 unsigned long flags;
1797
1798 spin_lock_irqsave(&host->lock, flags);
1799 host->flags |= SDHCI_HS400_TUNING;
1800 spin_unlock_irqrestore(&host->lock, flags);
1801
1802 return 0;
1803}
1804
069c9f14 1805static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1806{
4b6f37d3 1807 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1808 u16 ctrl;
b513ea25 1809 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1810 int err = 0;
2b35bd83 1811 unsigned long flags;
38e40bf5 1812 unsigned int tuning_count = 0;
b5540ce1 1813 bool hs400_tuning;
b513ea25 1814
2b35bd83 1815 spin_lock_irqsave(&host->lock, flags);
b513ea25 1816
b5540ce1
AH		 1817 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1818 host->flags &= ~SDHCI_HS400_TUNING;
1819
38e40bf5
AH		 1820 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1821 tuning_count = host->tuning_count;
1822
b513ea25 1823 /*
9faac7b9
WY		 1824 * The Host Controller needs tuning in case of SDR104 and DDR50
1825 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1826 * the Capabilities register.
069c9f14
G		 1827 * If the Host Controller supports the HS200 mode then the
1828 * tuning function has to be executed.
b513ea25 1829 */
4b6f37d3 1830 switch (host->timing) {
b5540ce1 1831 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1832 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1833 err = -EINVAL;
1834 goto out_unlock;
1835
4b6f37d3 1836 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1837 /*
1838 * Periodic re-tuning for HS400 is not expected to be needed, so
1839 * disable it here.
1840 */
1841 if (hs400_tuning)
1842 tuning_count = 0;
1843 break;
1844
4b6f37d3 1845 case MMC_TIMING_UHS_SDR104:
9faac7b9 1846 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 1847 break;
1848
1849 case MMC_TIMING_UHS_SDR50:
1850 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1851 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1852 break;
1853 /* FALLTHROUGH */
1854
1855 default:
d519c863 1856 goto out_unlock;
b513ea25
AN		 1857 }
1858
45251812 1859 if (host->ops->platform_execute_tuning) {
2b35bd83 1860 spin_unlock_irqrestore(&host->lock, flags);
45251812 1861 err = host->ops->platform_execute_tuning(host, opcode);
45251812
DA		 1862 return err;
1863 }
1864
4b6f37d3
RK		 1865 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1866 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 1867 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1868 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 1869 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1870
1871 /*
1872 * As per the Host Controller spec v3.00, tuning command
1873 * generates Buffer Read Ready interrupt, so enable that.
1874 *
1875 * Note: The spec clearly says that when tuning sequence
1876 * is being performed, the controller does not generate
1877 * interrupts other than Buffer Read Ready interrupt. But
1878 * to make sure we don't hit a controller bug, we _only_
1879 * enable Buffer Read Ready interrupt here.
1880 */
b537f94c
RK		 1881 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1882 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1883
1884 /*
1885 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1886 * of loops reaches 40 times or a timeout of 150ms occurs.
1887 */
b513ea25
AN		 1888 do {
1889 struct mmc_command cmd = {0};
66fd8ad5 1890 struct mmc_request mrq = {NULL};
b513ea25 1891
069c9f14 1892 cmd.opcode = opcode;
b513ea25
AN		 1893 cmd.arg = 0;
1894 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1895 cmd.retries = 0;
1896 cmd.data = NULL;
1897 cmd.error = 0;
1898
7ce45e95
AC		 1899 if (tuning_loop_counter-- == 0)
1900 break;
1901
b513ea25
AN		 1902 mrq.cmd = &cmd;
1903 host->mrq = &mrq;
1904
1905 /*
1906 * In response to CMD19, the card sends 64 bytes of tuning
1907 * block to the Host Controller. So we set the block size
1908 * to 64 here.
1909 */
069c9f14
G		 1910 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1911 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1912 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1913 SDHCI_BLOCK_SIZE);
1914 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1915 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1916 SDHCI_BLOCK_SIZE);
1917 } else {
1918 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1919 SDHCI_BLOCK_SIZE);
1920 }
b513ea25
AN		 1921
1922 /*
1923 * The tuning block is sent by the card to the host controller.
1924 * So we set the TRNS_READ bit in the Transfer Mode register.
1925 * This also takes care of setting DMA Enable and Multi Block
1926 * Select in the same register to 0.
1927 */
1928 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1929
1930 sdhci_send_command(host, &cmd);
1931
1932 host->cmd = NULL;
1933 host->mrq = NULL;
1934
2b35bd83 1935 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1936 /* Wait for Buffer Read Ready interrupt */
1937 wait_event_interruptible_timeout(host->buf_ready_int,
1938 (host->tuning_done == 1),
1939 msecs_to_jiffies(50));
2b35bd83 1940 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1941
1942 if (!host->tuning_done) {
2e4456f0 1943 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
b513ea25
AN		 1944 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1945 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1946 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1947 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1948
1949 err = -EIO;
1950 goto out;
1951 }
1952
1953 host->tuning_done = 0;
1954
1955 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 1956
1957 /* eMMC spec does not require a delay between tuning cycles */
1958 if (opcode == MMC_SEND_TUNING_BLOCK)
1959 mdelay(1);
b513ea25
AN		 1960 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1961
1962 /*
1963 * The Host Driver has exhausted the maximum number of loops allowed,
1964 * so use fixed sampling frequency.
1965 */
7ce45e95 1966 if (tuning_loop_counter < 0) {
b513ea25
AN		 1967 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1968 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 1969 }
1970 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2e4456f0 1971 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
114f2bf6 1972 err = -EIO;
b513ea25
AN		 1973 }
1974
1975out:
38e40bf5 1976 if (tuning_count) {
66c39dfc
AH		 1977 /*
1978 * In case tuning fails, host controllers which support
1979 * re-tuning can try tuning again at a later time, when the
1980 * re-tuning timer expires. So for these controllers, we
1981 * return 0. Since there might be other controllers who do not
1982 * have this capability, we return error for them.
1983 */
1984 err = 0;
cf2b5eea
AN		 1985 }
1986
66c39dfc 1987 host->mmc->retune_period = err ? 0 : tuning_count;
cf2b5eea 1988
b537f94c
RK		 1989 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1990 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 1991out_unlock:
2b35bd83 1992 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1993 return err;
1994}
1995
cb849648
AH		 1996static int sdhci_select_drive_strength(struct mmc_card *card,
1997 unsigned int max_dtr, int host_drv,
1998 int card_drv, int *drv_type)
1999{
2000 struct sdhci_host *host = mmc_priv(card->host);
2001
2002 if (!host->ops->select_drive_strength)
2003 return 0;
2004
2005 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2006 card_drv, drv_type);
2007}
52983382
KL		 2008
2009static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2010{
4d55c5a1
AN		 2011 /* Host Controller v3.00 defines preset value registers */
2012 if (host->version < SDHCI_SPEC_300)
2013 return;
2014
4d55c5a1
AN		 2015 /*
2016 * We only enable or disable Preset Value if they are not already
2017 * enabled or disabled respectively. Otherwise, we bail out.
2018 */
da91a8f9
RK		 2019 if (host->preset_enabled != enable) {
2020 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2021
2022 if (enable)
2023 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2024 else
2025 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2026
4d55c5a1 2027 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2028
2029 if (enable)
2030 host->flags |= SDHCI_PV_ENABLED;
2031 else
2032 host->flags &= ~SDHCI_PV_ENABLED;
2033
2034 host->preset_enabled = enable;
4d55c5a1 2035 }
66fd8ad5
AH		 2036}
2037
348487cb
HC		 2038static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2039 int err)
2040{
2041 struct sdhci_host *host = mmc_priv(mmc);
2042 struct mmc_data *data = mrq->data;
2043
f48f039c 2044 if (data->host_cookie != COOKIE_UNMAPPED)
771a3dc2
RK		 2045 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2046 data->flags & MMC_DATA_WRITE ?
2047 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2048
2049 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2050}
2051
348487cb
HC		 2052static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2053 bool is_first_req)
2054{
2055 struct sdhci_host *host = mmc_priv(mmc);
2056
d31911b9 2057 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2058
2059 if (host->flags & SDHCI_REQ_USE_DMA)
94538e51 2060 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
348487cb
HC		 2061}
2062
71e69211 2063static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2064{
71e69211 2065 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2066 unsigned long flags;
2836766a 2067 int present;
d129bceb 2068
722e1280
CD		 2069 /* First check if client has provided their own card event */
2070 if (host->ops->card_event)
2071 host->ops->card_event(host);
2072
2836766a
KK		 2073 present = sdhci_do_get_cd(host);
2074
d129bceb
PO		 2075 spin_lock_irqsave(&host->lock, flags);
2076
66fd8ad5 2077 /* Check host->mrq first in case we are runtime suspended */
2836766a 2078 if (host->mrq && !present) {
a3c76eb9 2079 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2080 mmc_hostname(host->mmc));
a3c76eb9 2081 pr_err("%s: Resetting controller.\n",
66fd8ad5 2082 mmc_hostname(host->mmc));
d129bceb 2083
03231f9b
RK		 2084 sdhci_do_reset(host, SDHCI_RESET_CMD);
2085 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2086
66fd8ad5
AH		 2087 host->mrq->cmd->error = -ENOMEDIUM;
2088 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2089 }
2090
2091 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2092}
2093
2094static const struct mmc_host_ops sdhci_ops = {
2095 .request = sdhci_request,
348487cb
HC		 2096 .post_req = sdhci_post_req,
2097 .pre_req = sdhci_pre_req,
71e69211 2098 .set_ios = sdhci_set_ios,
94144a46 2099 .get_cd = sdhci_get_cd,
71e69211
GL		 2100 .get_ro = sdhci_get_ro,
2101 .hw_reset = sdhci_hw_reset,
2102 .enable_sdio_irq = sdhci_enable_sdio_irq,
2103 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2104 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2105 .execute_tuning = sdhci_execute_tuning,
cb849648 2106 .select_drive_strength = sdhci_select_drive_strength,
71e69211 2107 .card_event = sdhci_card_event,
20b92a30 2108 .card_busy = sdhci_card_busy,
71e69211
GL		 2109};
2110
2111/*****************************************************************************\
2112 * *
2113 * Tasklets *
2114 * *
2115\*****************************************************************************/
2116
d129bceb
PO		 2117static void sdhci_tasklet_finish(unsigned long param)
2118{
2119 struct sdhci_host *host;
2120 unsigned long flags;
2121 struct mmc_request *mrq;
2122
2123 host = (struct sdhci_host*)param;
2124
66fd8ad5
AH		 2125 spin_lock_irqsave(&host->lock, flags);
2126
0c9c99a7
CB		 2127 /*
2128 * If this tasklet gets rescheduled while running, it will
2129 * be run again afterwards but without any active request.
2130 */
66fd8ad5
AH		 2131 if (!host->mrq) {
2132 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2133 return;
66fd8ad5 2134 }
d129bceb
PO		 2135
2136 del_timer(&host->timer);
2137
2138 mrq = host->mrq;
2139
054cedff
RK		 2140 /*
2141 * Always unmap the data buffers if they were mapped by
2142 * sdhci_prepare_data() whenever we finish with a request.
2143 * This avoids leaking DMA mappings on error.
2144 */
2145 if (host->flags & SDHCI_REQ_USE_DMA) {
2146 struct mmc_data *data = mrq->data;
2147
2148 if (data && data->host_cookie == COOKIE_MAPPED) {
2149 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2150 (data->flags & MMC_DATA_READ) ?
2151 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2152 data->host_cookie = COOKIE_UNMAPPED;
2153 }
2154 }
2155
d129bceb
PO		 2156 /*
2157 * The controller needs a reset of internal state machines
2158 * upon error conditions.
2159 */
1e72859e 2160 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2161 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2162 (mrq->sbc && mrq->sbc->error) ||
2163 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2164 (mrq->data->stop && mrq->data->stop->error))) ||
2165 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2166
2167 /* Some controllers need this kick or reset won't work here */
8213af3b 2168 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2169 /* This is to force an update */
1771059c 2170 host->ops->set_clock(host, host->clock);
645289dc
PO		 2171
2172 /* Spec says we should do both at the same time, but Ricoh
2173 controllers do not like that. */
03231f9b
RK		 2174 sdhci_do_reset(host, SDHCI_RESET_CMD);
2175 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2176 }
2177
2178 host->mrq = NULL;
2179 host->cmd = NULL;
2180 host->data = NULL;
2181
f9134319 2182#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2183 sdhci_deactivate_led(host);
2f730fec 2184#endif
d129bceb 2185
5f25a66f 2186 mmiowb();
d129bceb
PO		 2187 spin_unlock_irqrestore(&host->lock, flags);
2188
2189 mmc_request_done(host->mmc, mrq);
2190}
2191
2192static void sdhci_timeout_timer(unsigned long data)
2193{
2194 struct sdhci_host *host;
2195 unsigned long flags;
2196
2197 host = (struct sdhci_host*)data;
2198
2199 spin_lock_irqsave(&host->lock, flags);
2200
2201 if (host->mrq) {
2e4456f0
MV		 2202 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2203 mmc_hostname(host->mmc));
d129bceb
PO		 2204 sdhci_dumpregs(host);
2205
2206 if (host->data) {
17b0429d 2207 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2208 sdhci_finish_data(host);
2209 } else {
2210 if (host->cmd)
17b0429d 2211 host->cmd->error = -ETIMEDOUT;
d129bceb 2212 else
17b0429d 2213 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2214
2215 tasklet_schedule(&host->finish_tasklet);
2216 }
2217 }
2218
5f25a66f 2219 mmiowb();
d129bceb
PO		 2220 spin_unlock_irqrestore(&host->lock, flags);
2221}
2222
2223/*****************************************************************************\
2224 * *
2225 * Interrupt handling *
2226 * *
2227\*****************************************************************************/
2228
61541397 2229static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb
PO		 2230{
2231 BUG_ON(intmask == 0);
2232
2233 if (!host->cmd) {
2e4456f0
MV		 2234 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2235 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2236 sdhci_dumpregs(host);
2237 return;
2238 }
2239
ec014cba
RK		 2240 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2241 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2242 if (intmask & SDHCI_INT_TIMEOUT)
2243 host->cmd->error = -ETIMEDOUT;
2244 else
2245 host->cmd->error = -EILSEQ;
43b58b36 2246
71fcbda0
RK		 2247 /*
2248 * If this command initiates a data phase and a response
2249 * CRC error is signalled, the card can start transferring
2250 * data - the card may have received the command without
2251 * error. We must not terminate the mmc_request early.
2252 *
2253 * If the card did not receive the command or returned an
2254 * error which prevented it sending data, the data phase
2255 * will time out.
2256 */
2257 if (host->cmd->data &&
2258 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2259 SDHCI_INT_CRC) {
2260 host->cmd = NULL;
2261 return;
2262 }
2263
d129bceb 2264 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2265 return;
2266 }
2267
2268 /*
2269 * The host can send and interrupt when the busy state has
2270 * ended, allowing us to wait without wasting CPU cycles.
2271 * Unfortunately this is overloaded on the "data complete"
2272 * interrupt, so we need to take some care when handling
2273 * it.
2274 *
2275 * Note: The 1.0 specification is a bit ambiguous about this
2276 * feature so there might be some problems with older
2277 * controllers.
2278 */
2279 if (host->cmd->flags & MMC_RSP_BUSY) {
2280 if (host->cmd->data)
2e4456f0 2281 DBG("Cannot wait for busy signal when also doing a data transfer");
e99783a4
CM		 2282 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2283 && !host->busy_handle) {
2284 /* Mark that command complete before busy is ended */
2285 host->busy_handle = 1;
e809517f 2286 return;
e99783a4 2287 }
f945405c
BD		 2288
2289 /* The controller does not support the end-of-busy IRQ,
2290 * fall through and take the SDHCI_INT_RESPONSE */
61541397
AH		 2291 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2292 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2293 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2294 }
2295
2296 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2297 sdhci_finish_command(host);
d129bceb
PO		 2298}
2299
0957c333 2300#ifdef CONFIG_MMC_DEBUG
08621b18 2301static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2302{
2303 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2304 void *desc = host->adma_table;
6882a8c0
BD		 2305
2306 sdhci_dumpregs(host);
2307
2308 while (true) {
e57a5f61
AH		 2309 struct sdhci_adma2_64_desc *dma_desc = desc;
2310
2311 if (host->flags & SDHCI_USE_64_BIT_DMA)
2312 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2313 name, desc, le32_to_cpu(dma_desc->addr_hi),
2314 le32_to_cpu(dma_desc->addr_lo),
2315 le16_to_cpu(dma_desc->len),
2316 le16_to_cpu(dma_desc->cmd));
2317 else
2318 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2319 name, desc, le32_to_cpu(dma_desc->addr_lo),
2320 le16_to_cpu(dma_desc->len),
2321 le16_to_cpu(dma_desc->cmd));
6882a8c0 2322
76fe379a 2323 desc += host->desc_sz;
6882a8c0 2324
0545230f 2325 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2326 break;
2327 }
2328}
2329#else
08621b18 2330static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2331#endif
2332
d129bceb
PO		 2333static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2334{
069c9f14 2335 u32 command;
d129bceb
PO		 2336 BUG_ON(intmask == 0);
2337
b513ea25
AN		 2338 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2339 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2340 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2341 if (command == MMC_SEND_TUNING_BLOCK ||
2342 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2343 host->tuning_done = 1;
2344 wake_up(&host->buf_ready_int);
2345 return;
2346 }
2347 }
2348
d129bceb
PO		 2349 if (!host->data) {
2350 /*
e809517f
PO		 2351 * The "data complete" interrupt is also used to
2352 * indicate that a busy state has ended. See comment
2353 * above in sdhci_cmd_irq().
d129bceb 2354 */
e809517f 2355 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2356 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2357 host->cmd->error = -ETIMEDOUT;
2358 tasklet_schedule(&host->finish_tasklet);
2359 return;
2360 }
e809517f 2361 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2362 /*
2363 * Some cards handle busy-end interrupt
2364 * before the command completed, so make
2365 * sure we do things in the proper order.
2366 */
2367 if (host->busy_handle)
2368 sdhci_finish_command(host);
2369 else
2370 host->busy_handle = 1;
e809517f
PO		 2371 return;
2372 }
2373 }
d129bceb 2374
2e4456f0
MV		 2375 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2376 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2377 sdhci_dumpregs(host);
2378
2379 return;
2380 }
2381
2382 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2383 host->data->error = -ETIMEDOUT;
22113efd
AL		 2384 else if (intmask & SDHCI_INT_DATA_END_BIT)
2385 host->data->error = -EILSEQ;
2386 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2387 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2388 != MMC_BUS_TEST_R)
17b0429d 2389 host->data->error = -EILSEQ;
6882a8c0 2390 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2391 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2392 sdhci_adma_show_error(host);
2134a922 2393 host->data->error = -EIO;
a4071fbb
HZ		 2394 if (host->ops->adma_workaround)
2395 host->ops->adma_workaround(host, intmask);
6882a8c0 2396 }
d129bceb 2397
17b0429d 2398 if (host->data->error)
d129bceb
PO		 2399 sdhci_finish_data(host);
2400 else {
a406f5a3 2401 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2402 sdhci_transfer_pio(host);
2403
6ba736a1
PO		 2404 /*
2405 * We currently don't do anything fancy with DMA
2406 * boundaries, but as we can't disable the feature
2407 * we need to at least restart the transfer.
f6a03cbf
MV		 2408 *
2409 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2410 * should return a valid address to continue from, but as
2411 * some controllers are faulty, don't trust them.
6ba736a1 2412 */
f6a03cbf
MV		 2413 if (intmask & SDHCI_INT_DMA_END) {
2414 u32 dmastart, dmanow;
2415 dmastart = sg_dma_address(host->data->sg);
2416 dmanow = dmastart + host->data->bytes_xfered;
2417 /*
2418 * Force update to the next DMA block boundary.
2419 */
2420 dmanow = (dmanow &
2421 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2422 SDHCI_DEFAULT_BOUNDARY_SIZE;
2423 host->data->bytes_xfered = dmanow - dmastart;
2424 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2425 " next 0x%08x\n",
2426 mmc_hostname(host->mmc), dmastart,
2427 host->data->bytes_xfered, dmanow);
2428 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2429 }
6ba736a1 2430
e538fbe8
PO		 2431 if (intmask & SDHCI_INT_DATA_END) {
2432 if (host->cmd) {
2433 /*
2434 * Data managed to finish before the
2435 * command completed. Make sure we do
2436 * things in the proper order.
2437 */
2438 host->data_early = 1;
2439 } else {
2440 sdhci_finish_data(host);
2441 }
2442 }
d129bceb
PO		 2443 }
2444}
2445
7d12e780 2446static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2447{
781e989c 2448 irqreturn_t result = IRQ_NONE;
66fd8ad5 2449 struct sdhci_host *host = dev_id;
41005003 2450 u32 intmask, mask, unexpected = 0;
781e989c 2451 int max_loops = 16;
d129bceb
PO		 2452
2453 spin_lock(&host->lock);
2454
be138554 2455 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2456 spin_unlock(&host->lock);
655bca76 2457 return IRQ_NONE;
66fd8ad5
AH		 2458 }
2459
4e4141a5 2460 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2461 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2462 result = IRQ_NONE;
2463 goto out;
2464 }
2465
41005003
RK		 2466 do {
2467 /* Clear selected interrupts. */
2468 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2469 SDHCI_INT_BUS_POWER);
2470 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2471
41005003
RK		 2472 DBG("*** %s got interrupt: 0x%08x\n",
2473 mmc_hostname(host->mmc), intmask);
d129bceb 2474
41005003
RK		 2475 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2476 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2477 SDHCI_CARD_PRESENT;
d129bceb 2478
41005003
RK		 2479 /*
2480 * There is a observation on i.mx esdhc. INSERT
2481 * bit will be immediately set again when it gets
2482 * cleared, if a card is inserted. We have to mask
2483 * the irq to prevent interrupt storm which will
2484 * freeze the system. And the REMOVE gets the
2485 * same situation.
2486 *
2487 * More testing are needed here to ensure it works
2488 * for other platforms though.
2489 */
b537f94c
RK		 2490 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2491 SDHCI_INT_CARD_REMOVE);
2492 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2493 SDHCI_INT_CARD_INSERT;
2494 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2495 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2496
2497 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2498 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2499
2500 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2501 SDHCI_INT_CARD_REMOVE);
2502 result = IRQ_WAKE_THREAD;
41005003 2503 }
d129bceb 2504
41005003 2505 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2506 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2507 &intmask);
964f9ce2 2508
41005003
RK		 2509 if (intmask & SDHCI_INT_DATA_MASK)
2510 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2511
41005003
RK		 2512 if (intmask & SDHCI_INT_BUS_POWER)
2513 pr_err("%s: Card is consuming too much power!\n",
2514 mmc_hostname(host->mmc));
3192a28f 2515
781e989c
RK		 2516 if (intmask & SDHCI_INT_CARD_INT) {
2517 sdhci_enable_sdio_irq_nolock(host, false);
2518 host->thread_isr |= SDHCI_INT_CARD_INT;
2519 result = IRQ_WAKE_THREAD;
2520 }
f75979b7 2521
41005003
RK		 2522 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2523 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2524 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2525 SDHCI_INT_CARD_INT);
f75979b7 2526
41005003
RK		 2527 if (intmask) {
2528 unexpected |= intmask;
2529 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2530 }
d129bceb 2531
781e989c
RK		 2532 if (result == IRQ_NONE)
2533 result = IRQ_HANDLED;
d129bceb 2534
41005003 2535 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2536 } while (intmask && --max_loops);
d129bceb
PO		 2537out:
2538 spin_unlock(&host->lock);
2539
6379b237
AS		 2540 if (unexpected) {
2541 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2542 mmc_hostname(host->mmc), unexpected);
2543 sdhci_dumpregs(host);
2544 }
f75979b7 2545
d129bceb
PO		 2546 return result;
2547}
2548
781e989c
RK		 2549static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2550{
2551 struct sdhci_host *host = dev_id;
2552 unsigned long flags;
2553 u32 isr;
2554
2555 spin_lock_irqsave(&host->lock, flags);
2556 isr = host->thread_isr;
2557 host->thread_isr = 0;
2558 spin_unlock_irqrestore(&host->lock, flags);
2559
3560db8e
RK		 2560 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2561 sdhci_card_event(host->mmc);
2562 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2563 }
2564
781e989c
RK		 2565 if (isr & SDHCI_INT_CARD_INT) {
2566 sdio_run_irqs(host->mmc);
2567
2568 spin_lock_irqsave(&host->lock, flags);
2569 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2570 sdhci_enable_sdio_irq_nolock(host, true);
2571 spin_unlock_irqrestore(&host->lock, flags);
2572 }
2573
2574 return isr ? IRQ_HANDLED : IRQ_NONE;
2575}
2576
d129bceb
PO		 2577/*****************************************************************************\
2578 * *
2579 * Suspend/resume *
2580 * *
2581\*****************************************************************************/
2582
2583#ifdef CONFIG_PM
ad080d79
KL		 2584void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2585{
2586 u8 val;
2587 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2588 | SDHCI_WAKE_ON_INT;
2589
2590 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2591 val |= mask ;
2592 /* Avoid fake wake up */
2593 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2594 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2595 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2596}
2597EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2598
0b10f478 2599static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2600{
2601 u8 val;
2602 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2603 | SDHCI_WAKE_ON_INT;
2604
2605 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2606 val &= ~mask;
2607 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2608}
d129bceb 2609
29495aa0 2610int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2611{
7260cf5e
AV		 2612 sdhci_disable_card_detection(host);
2613
66c39dfc
AH		 2614 mmc_retune_timer_stop(host->mmc);
2615 mmc_retune_needed(host->mmc);
cf2b5eea 2616
ad080d79 2617 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2618 host->ier = 0;
2619 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2620 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2621 free_irq(host->irq, host);
2622 } else {
2623 sdhci_enable_irq_wakeups(host);
2624 enable_irq_wake(host->irq);
2625 }
4ee14ec6 2626 return 0;
d129bceb
PO		 2627}
2628
b8c86fc5 2629EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2630
b8c86fc5
PO		 2631int sdhci_resume_host(struct sdhci_host *host)
2632{
4ee14ec6 2633 int ret = 0;
d129bceb 2634
a13abc7b 2635 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2636 if (host->ops->enable_dma)
2637 host->ops->enable_dma(host);
2638 }
d129bceb 2639
6308d290
AH		 2640 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2641 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2642 /* Card keeps power but host controller does not */
2643 sdhci_init(host, 0);
2644 host->pwr = 0;
2645 host->clock = 0;
2646 sdhci_do_set_ios(host, &host->mmc->ios);
2647 } else {
2648 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2649 mmiowb();
2650 }
b8c86fc5 2651
14a7b416
HC		 2652 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2653 ret = request_threaded_irq(host->irq, sdhci_irq,
2654 sdhci_thread_irq, IRQF_SHARED,
2655 mmc_hostname(host->mmc), host);
2656 if (ret)
2657 return ret;
2658 } else {
2659 sdhci_disable_irq_wakeups(host);
2660 disable_irq_wake(host->irq);
2661 }
2662
7260cf5e
AV		 2663 sdhci_enable_card_detection(host);
2664
2f4cbb3d 2665 return ret;
d129bceb
PO		 2666}
2667
b8c86fc5 2668EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5 2669
f0710a55
AH		 2670static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2671{
5c671c41 2672 if (host->bus_on)
f0710a55
AH		 2673 return;
2674 host->bus_on = true;
2675 pm_runtime_get_noresume(host->mmc->parent);
2676}
2677
2678static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2679{
5c671c41 2680 if (!host->bus_on)
f0710a55
AH		 2681 return;
2682 host->bus_on = false;
2683 pm_runtime_put_noidle(host->mmc->parent);
2684}
2685
66fd8ad5
AH		 2686int sdhci_runtime_suspend_host(struct sdhci_host *host)
2687{
2688 unsigned long flags;
66fd8ad5 2689
66c39dfc
AH		 2690 mmc_retune_timer_stop(host->mmc);
2691 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2692
2693 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2694 host->ier &= SDHCI_INT_CARD_INT;
2695 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2696 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2697 spin_unlock_irqrestore(&host->lock, flags);
2698
781e989c 2699 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2700
2701 spin_lock_irqsave(&host->lock, flags);
2702 host->runtime_suspended = true;
2703 spin_unlock_irqrestore(&host->lock, flags);
2704
8a125bad 2705 return 0;
66fd8ad5
AH		 2706}
2707EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2708
2709int sdhci_runtime_resume_host(struct sdhci_host *host)
2710{
2711 unsigned long flags;
8a125bad 2712 int host_flags = host->flags;
66fd8ad5
AH		 2713
2714 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2715 if (host->ops->enable_dma)
2716 host->ops->enable_dma(host);
2717 }
2718
2719 sdhci_init(host, 0);
2720
2721 /* Force clock and power re-program */
2722 host->pwr = 0;
2723 host->clock = 0;
3396e736 2724 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
66fd8ad5
AH		 2725 sdhci_do_set_ios(host, &host->mmc->ios);
2726
52983382
KL		 2727 if ((host_flags & SDHCI_PV_ENABLED) &&
2728 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2729 spin_lock_irqsave(&host->lock, flags);
2730 sdhci_enable_preset_value(host, true);
2731 spin_unlock_irqrestore(&host->lock, flags);
2732 }
66fd8ad5 2733
66fd8ad5
AH		 2734 spin_lock_irqsave(&host->lock, flags);
2735
2736 host->runtime_suspended = false;
2737
2738 /* Enable SDIO IRQ */
ef104333 2739 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2740 sdhci_enable_sdio_irq_nolock(host, true);
2741
2742 /* Enable Card Detection */
2743 sdhci_enable_card_detection(host);
2744
2745 spin_unlock_irqrestore(&host->lock, flags);
2746
8a125bad 2747 return 0;
66fd8ad5
AH		 2748}
2749EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2750
162d6f98 2751#endif /* CONFIG_PM */
66fd8ad5 2752
d129bceb
PO		 2753/*****************************************************************************\
2754 * *
b8c86fc5 2755 * Device allocation/registration *
d129bceb
PO		 2756 * *
2757\*****************************************************************************/
2758
b8c86fc5
PO		 2759struct sdhci_host *sdhci_alloc_host(struct device *dev,
2760 size_t priv_size)
d129bceb 2761{
d129bceb
PO		 2762 struct mmc_host *mmc;
2763 struct sdhci_host *host;
2764
b8c86fc5 2765 WARN_ON(dev == NULL);
d129bceb 2766
b8c86fc5 2767 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2768 if (!mmc)
b8c86fc5 2769 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2770
2771 host = mmc_priv(mmc);
2772 host->mmc = mmc;
bf60e592
AH		 2773 host->mmc_host_ops = sdhci_ops;
2774 mmc->ops = &host->mmc_host_ops;
d129bceb 2775
b8c86fc5
PO		 2776 return host;
2777}
8a4da143 2778
b8c86fc5 2779EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2780
7b91369b
AC		 2781static int sdhci_set_dma_mask(struct sdhci_host *host)
2782{
2783 struct mmc_host *mmc = host->mmc;
2784 struct device *dev = mmc_dev(mmc);
2785 int ret = -EINVAL;
2786
2787 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
2788 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2789
2790 /* Try 64-bit mask if hardware is capable of it */
2791 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2792 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
2793 if (ret) {
2794 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
2795 mmc_hostname(mmc));
2796 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2797 }
2798 }
2799
2800 /* 32-bit mask as default & fallback */
2801 if (ret) {
2802 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2803 if (ret)
2804 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
2805 mmc_hostname(mmc));
2806 }
2807
2808 return ret;
2809}
2810
b8c86fc5
PO		 2811int sdhci_add_host(struct sdhci_host *host)
2812{
2813 struct mmc_host *mmc;
bd6a8c30 2814 u32 caps[2] = {0, 0};
f2119df6
AN		 2815 u32 max_current_caps;
2816 unsigned int ocr_avail;
f5fa92e5 2817 unsigned int override_timeout_clk;
59241757 2818 u32 max_clk;
b8c86fc5 2819 int ret;
d129bceb 2820
b8c86fc5
PO		 2821 WARN_ON(host == NULL);
2822 if (host == NULL)
2823 return -EINVAL;
d129bceb 2824
b8c86fc5 2825 mmc = host->mmc;
d129bceb 2826
b8c86fc5
PO		 2827 if (debug_quirks)
2828 host->quirks = debug_quirks;
66fd8ad5
AH		 2829 if (debug_quirks2)
2830 host->quirks2 = debug_quirks2;
d129bceb 2831
f5fa92e5
AH		 2832 override_timeout_clk = host->timeout_clk;
2833
03231f9b 2834 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2835
4e4141a5 2836 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2837 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2838 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2839 if (host->version > SDHCI_SPEC_300) {
2e4456f0
MV		 2840 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2841 mmc_hostname(mmc), host->version);
4a965505
PO		 2842 }
2843
f2119df6 2844 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2845 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2846
bd6a8c30
PR		 2847 if (host->version >= SDHCI_SPEC_300)
2848 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2849 host->caps1 :
2850 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2851
b8c86fc5 2852 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2853 host->flags |= SDHCI_USE_SDMA;
f2119df6 2854 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2855 DBG("Controller doesn't have SDMA capability\n");
67435274 2856 else
a13abc7b 2857 host->flags |= SDHCI_USE_SDMA;
d129bceb 2858
b8c86fc5 2859 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2860 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2861 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2862 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2863 }
2864
f2119df6
AN		 2865 if ((host->version >= SDHCI_SPEC_200) &&
2866 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2867 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2868
2869 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2870 (host->flags & SDHCI_USE_ADMA)) {
2871 DBG("Disabling ADMA as it is marked broken\n");
2872 host->flags &= ~SDHCI_USE_ADMA;
2873 }
2874
e57a5f61
AH		 2875 /*
2876 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2877 * and *must* do 64-bit DMA. A driver has the opportunity to change
2878 * that during the first call to ->enable_dma(). Similarly
2879 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2880 * implement.
2881 */
5eaa7476 2882 if (caps[0] & SDHCI_CAN_64BIT)
e57a5f61
AH		 2883 host->flags |= SDHCI_USE_64_BIT_DMA;
2884
a13abc7b 2885 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
7b91369b
AC		 2886 ret = sdhci_set_dma_mask(host);
2887
2888 if (!ret && host->ops->enable_dma)
2889 ret = host->ops->enable_dma(host);
2890
2891 if (ret) {
2892 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2893 mmc_hostname(mmc));
2894 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2895
2896 ret = 0;
d129bceb
PO		 2897 }
2898 }
2899
e57a5f61
AH		 2900 /* SDMA does not support 64-bit DMA */
2901 if (host->flags & SDHCI_USE_64_BIT_DMA)
2902 host->flags &= ~SDHCI_USE_SDMA;
2903
2134a922 2904 if (host->flags & SDHCI_USE_ADMA) {
e66e61cb
RK		 2905 dma_addr_t dma;
2906 void *buf;
2907
2134a922 2908 /*
76fe379a
AH		 2909 * The DMA descriptor table size is calculated as the maximum
2910 * number of segments times 2, to allow for an alignment
2911 * descriptor for each segment, plus 1 for a nop end descriptor,
2912 * all multipled by the descriptor size.
2134a922 2913 */
e57a5f61
AH		 2914 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2915 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2916 SDHCI_ADMA2_64_DESC_SZ;
e57a5f61 2917 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
e57a5f61
AH		 2918 } else {
2919 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2920 SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2921 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2922 }
e66e61cb 2923
04a5ae6f 2924 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
e66e61cb
RK		 2925 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
2926 host->adma_table_sz, &dma, GFP_KERNEL);
2927 if (!buf) {
6606110d 2928 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 2929 mmc_hostname(mmc));
2930 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 2931 } else if ((dma + host->align_buffer_sz) &
2932 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 2933 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2934 mmc_hostname(mmc));
d1e49f77 2935 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 2936 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
2937 host->adma_table_sz, buf, dma);
2938 } else {
2939 host->align_buffer = buf;
2940 host->align_addr = dma;
edd63fcc 2941
e66e61cb
RK		 2942 host->adma_table = buf + host->align_buffer_sz;
2943 host->adma_addr = dma + host->align_buffer_sz;
2944 }
2134a922
PO		 2945 }
2946
7659150c
PO		 2947 /*
2948 * If we use DMA, then it's up to the caller to set the DMA
2949 * mask, but PIO does not need the hw shim so we set a new
2950 * mask here in that case.
2951 */
a13abc7b 2952 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 2953 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 2954 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 2955 }
d129bceb 2956
c4687d5f 2957 if (host->version >= SDHCI_SPEC_300)
f2119df6 2958 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2959 >> SDHCI_CLOCK_BASE_SHIFT;
2960 else
f2119df6 2961 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2962 >> SDHCI_CLOCK_BASE_SHIFT;
2963
4240ff0a 2964 host->max_clk *= 1000000;
f27f47ef
AV		 2965 if (host->max_clk == 0 || host->quirks &
2966 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2967 if (!host->ops->get_max_clock) {
2e4456f0
MV		 2968 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
2969 mmc_hostname(mmc));
4240ff0a
BD		 2970 return -ENODEV;
2971 }
2972 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2973 }
d129bceb 2974
c3ed3877
AN		 2975 /*
2976 * In case of Host Controller v3.00, find out whether clock
2977 * multiplier is supported.
2978 */
2979 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2980 SDHCI_CLOCK_MUL_SHIFT;
2981
2982 /*
2983 * In case the value in Clock Multiplier is 0, then programmable
2984 * clock mode is not supported, otherwise the actual clock
2985 * multiplier is one more than the value of Clock Multiplier
2986 * in the Capabilities Register.
2987 */
2988 if (host->clk_mul)
2989 host->clk_mul += 1;
2990
d129bceb
PO		 2991 /*
2992 * Set host parameters.
2993 */
59241757
DA		 2994 max_clk = host->max_clk;
2995
ce5f036b 2996 if (host->ops->get_min_clock)
a9e58f25 2997 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2998 else if (host->version >= SDHCI_SPEC_300) {
2999 if (host->clk_mul) {
3000 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3001 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3002 } else
3003 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3004 } else
0397526d 3005 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3006
59241757
DA		 3007 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3008 mmc->f_max = max_clk;
3009
28aab053
AD		 3010 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3011 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3012 SDHCI_TIMEOUT_CLK_SHIFT;
3013 if (host->timeout_clk == 0) {
3014 if (host->ops->get_timeout_clock) {
3015 host->timeout_clk =
3016 host->ops->get_timeout_clock(host);
3017 } else {
3018 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3019 mmc_hostname(mmc));
3020 return -ENODEV;
3021 }
272308ca 3022 }
272308ca 3023
28aab053
AD		 3024 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3025 host->timeout_clk *= 1000;
272308ca 3026
99513624
AH		 3027 if (override_timeout_clk)
3028 host->timeout_clk = override_timeout_clk;
3029
28aab053 3030 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3031 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3032 mmc->max_busy_timeout /= host->timeout_clk;
3033 }
58d1246d 3034
e89d456f 3035 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3036 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3037
3038 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3039 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3040
8edf6371 3041 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3042 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3043 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3044 !(host->flags & SDHCI_USE_SDMA)) &&
3045 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3046 host->flags |= SDHCI_AUTO_CMD23;
3047 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3048 } else {
3049 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3050 }
3051
15ec4461
PR		 3052 /*
3053 * A controller may support 8-bit width, but the board itself
3054 * might not have the pins brought out. Boards that support
3055 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3056 * their platform code before calling sdhci_add_host(), and we
3057 * won't assume 8-bit width for hosts without that CAP.
3058 */
5fe23c7f 3059 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3060 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3061
63ef5d8c
JH		 3062 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3063 mmc->caps &= ~MMC_CAP_CMD23;
3064
f2119df6 3065 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 3066 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3067
176d1ed4 3068 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
c31d22eb
II		 3069 !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3070 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
68d1fb7e
AV		 3071 mmc->caps |= MMC_CAP_NEEDS_POLL;
3072
3a48edc4
TK		 3073 /* If there are external regulators, get them */
3074 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3075 return -EPROBE_DEFER;
3076
6231f3de 3077 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3078 if (!IS_ERR(mmc->supply.vqmmc)) {
3079 ret = regulator_enable(mmc->supply.vqmmc);
3080 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3081 1950000))
8363c374
KL		 3082 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3083 SDHCI_SUPPORT_SDR50 |
3084 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3085 if (ret) {
3086 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3087 mmc_hostname(mmc), ret);
4bb74313 3088 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3089 }
8363c374 3090 }
6231f3de 3091
6a66180a
DD		 3092 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3093 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3094 SDHCI_SUPPORT_DDR50);
3095
4188bba0
AC		 3096 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3097 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3098 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3099 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3100
3101 /* SDR104 supports also implies SDR50 support */
156e14b1 3102 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3103 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3104 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3105 * field can be promoted to support HS200.
3106 */
549c0b18 3107 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3108 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3109 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3110 mmc->caps |= MMC_CAP_UHS_SDR50;
3111
e9fb05d5
AH		 3112 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3113 (caps[1] & SDHCI_SUPPORT_HS400))
3114 mmc->caps2 |= MMC_CAP2_HS400;
3115
549c0b18
AH		 3116 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3117 (IS_ERR(mmc->supply.vqmmc) ||
3118 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3119 1300000)))
3120 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3121
9107ebbf
MC		 3122 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3123 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3124 mmc->caps |= MMC_CAP_UHS_DDR50;
3125
069c9f14 3126 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3127 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3128 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3129
156e14b1 3130 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3131 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3132 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3133
d6d50a15
AN		 3134 /* Driver Type(s) (A, C, D) supported by the host */
3135 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3136 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3137 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3138 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3139 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3140 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3141
cf2b5eea
AN		 3142 /* Initial value for re-tuning timer count */
3143 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3144 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3145
3146 /*
3147 * In case Re-tuning Timer is not disabled, the actual value of
3148 * re-tuning timer will be 2 ^ (n - 1).
3149 */
3150 if (host->tuning_count)
3151 host->tuning_count = 1 << (host->tuning_count - 1);
3152
3153 /* Re-tuning mode supported by the Host Controller */
3154 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3155 SDHCI_RETUNING_MODE_SHIFT;
3156
8f230f45 3157 ocr_avail = 0;
bad37e1a 3158
f2119df6
AN		 3159 /*
3160 * According to SD Host Controller spec v3.00, if the Host System
3161 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3162 * the value is meaningful only if Voltage Support in the Capabilities
3163 * register is set. The actual current value is 4 times the register
3164 * value.
3165 */
3166 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3167 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3168 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3169 if (curr > 0) {
3170
3171 /* convert to SDHCI_MAX_CURRENT format */
3172 curr = curr/1000; /* convert to mA */
3173 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3174
3175 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3176 max_current_caps =
3177 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3178 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3179 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3180 }
3181 }
f2119df6
AN		 3182
3183 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3184 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3185
55c4665e 3186 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3187 SDHCI_MAX_CURRENT_330_MASK) >>
3188 SDHCI_MAX_CURRENT_330_SHIFT) *
3189 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3190 }
3191 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3192 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3193
55c4665e 3194 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3195 SDHCI_MAX_CURRENT_300_MASK) >>
3196 SDHCI_MAX_CURRENT_300_SHIFT) *
3197 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3198 }
3199 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3200 ocr_avail |= MMC_VDD_165_195;
3201
55c4665e 3202 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3203 SDHCI_MAX_CURRENT_180_MASK) >>
3204 SDHCI_MAX_CURRENT_180_SHIFT) *
3205 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3206 }
3207
5fd26c7e
UH		 3208 /* If OCR set by host, use it instead. */
3209 if (host->ocr_mask)
3210 ocr_avail = host->ocr_mask;
3211
3212 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3213 if (mmc->ocr_avail)
52221610 3214 ocr_avail = mmc->ocr_avail;
3a48edc4 3215
8f230f45
TI		 3216 mmc->ocr_avail = ocr_avail;
3217 mmc->ocr_avail_sdio = ocr_avail;
3218 if (host->ocr_avail_sdio)
3219 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3220 mmc->ocr_avail_sd = ocr_avail;
3221 if (host->ocr_avail_sd)
3222 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3223 else /* normal SD controllers don't support 1.8V */
3224 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3225 mmc->ocr_avail_mmc = ocr_avail;
3226 if (host->ocr_avail_mmc)
3227 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3228
3229 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 3230 pr_err("%s: Hardware doesn't report any support voltages.\n",
3231 mmc_hostname(mmc));
b8c86fc5 3232 return -ENODEV;
146ad66e
PO		 3233 }
3234
d129bceb
PO		 3235 spin_lock_init(&host->lock);
3236
3237 /*
2134a922
PO		 3238 * Maximum number of segments. Depends on if the hardware
3239 * can do scatter/gather or not.
d129bceb 3240 */
2134a922 3241 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3242 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3243 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3244 mmc->max_segs = 1;
2134a922 3245 else /* PIO */
4fb213f8 3246 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3247
3248 /*
ac00531d
AH		 3249 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3250 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3251 * is less anyway.
d129bceb 3252 */
55db890a 3253 mmc->max_req_size = 524288;
d129bceb
PO		 3254
3255 /*
3256 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3257 * of bytes. When doing hardware scatter/gather, each entry cannot
3258 * be larger than 64 KiB though.
d129bceb 3259 */
30652aa3
OJ		 3260 if (host->flags & SDHCI_USE_ADMA) {
3261 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3262 mmc->max_seg_size = 65535;
3263 else
3264 mmc->max_seg_size = 65536;
3265 } else {
2134a922 3266 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3267 }
d129bceb 3268
fe4a3c7a
PO		 3269 /*
3270 * Maximum block size. This varies from controller to controller and
3271 * is specified in the capabilities register.
3272 */
0633f654
AV		 3273 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3274 mmc->max_blk_size = 2;
3275 } else {
f2119df6 3276 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3277 SDHCI_MAX_BLOCK_SHIFT;
3278 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3279 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3280 mmc_hostname(mmc));
0633f654
AV		 3281 mmc->max_blk_size = 0;
3282 }
3283 }
3284
3285 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3286
55db890a
PO		 3287 /*
3288 * Maximum block count.
3289 */
1388eefd 3290 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3291
d129bceb
PO		 3292 /*
3293 * Init tasklets.
3294 */
d129bceb
PO		 3295 tasklet_init(&host->finish_tasklet,
3296 sdhci_tasklet_finish, (unsigned long)host);
3297
e4cad1b5 3298 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3299
250fb7b4 3300 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3301
2af502ca
SG		 3302 sdhci_init(host, 0);
3303
781e989c
RK		 3304 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3305 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3306 if (ret) {
3307 pr_err("%s: Failed to request IRQ %d: %d\n",
3308 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3309 goto untasklet;
0fc81ee3 3310 }
d129bceb 3311
d129bceb
PO		 3312#ifdef CONFIG_MMC_DEBUG
3313 sdhci_dumpregs(host);
3314#endif
3315
f9134319 3316#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3317 snprintf(host->led_name, sizeof(host->led_name),
3318 "%s::", mmc_hostname(mmc));
3319 host->led.name = host->led_name;
2f730fec
PO		 3320 host->led.brightness = LED_OFF;
3321 host->led.default_trigger = mmc_hostname(mmc);
3322 host->led.brightness_set = sdhci_led_control;
3323
b8c86fc5 3324 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3325 if (ret) {
3326 pr_err("%s: Failed to register LED device: %d\n",
3327 mmc_hostname(mmc), ret);
2f730fec 3328 goto reset;
0fc81ee3 3329 }
2f730fec
PO		 3330#endif
3331
5f25a66f
PO		 3332 mmiowb();
3333
d129bceb
PO		 3334 mmc_add_host(mmc);
3335
a3c76eb9 3336 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3337 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3338 (host->flags & SDHCI_USE_ADMA) ?
3339 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3340 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3341
7260cf5e
AV		 3342 sdhci_enable_card_detection(host);
3343
d129bceb
PO		 3344 return 0;
3345
f9134319 3346#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3347reset:
03231f9b 3348 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3349 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3350 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3351 free_irq(host->irq, host);
3352#endif
8ef1a143 3353untasklet:
d129bceb 3354 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3355
3356 return ret;
3357}
3358
b8c86fc5 3359EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3360
1e72859e 3361void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3362{
3a48edc4 3363 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3364 unsigned long flags;
3365
3366 if (dead) {
3367 spin_lock_irqsave(&host->lock, flags);
3368
3369 host->flags |= SDHCI_DEVICE_DEAD;
3370
3371 if (host->mrq) {
a3c76eb9 3372 pr_err("%s: Controller removed during "
4e743f1f 3373 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3374
3375 host->mrq->cmd->error = -ENOMEDIUM;
3376 tasklet_schedule(&host->finish_tasklet);
3377 }
3378
3379 spin_unlock_irqrestore(&host->lock, flags);
3380 }
3381
7260cf5e
AV		 3382 sdhci_disable_card_detection(host);
3383
4e743f1f 3384 mmc_remove_host(mmc);
d129bceb 3385
f9134319 3386#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3387 led_classdev_unregister(&host->led);
3388#endif
3389
1e72859e 3390 if (!dead)
03231f9b 3391 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3392
b537f94c
RK		 3393 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3394 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3395 free_irq(host->irq, host);
3396
3397 del_timer_sync(&host->timer);
3398
d129bceb 3399 tasklet_kill(&host->finish_tasklet);
2134a922 3400
3a48edc4
TK		 3401 if (!IS_ERR(mmc->supply.vqmmc))
3402 regulator_disable(mmc->supply.vqmmc);
6231f3de 3403
edd63fcc 3404 if (host->align_buffer)
e66e61cb
RK		 3405 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3406 host->adma_table_sz, host->align_buffer,
3407 host->align_addr);
2134a922 3408
4efaa6fb 3409 host->adma_table = NULL;
2134a922 3410 host->align_buffer = NULL;
d129bceb
PO		 3411}
3412
b8c86fc5 3413EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3414
b8c86fc5 3415void sdhci_free_host(struct sdhci_host *host)
d129bceb 3416{
b8c86fc5 3417 mmc_free_host(host->mmc);
d129bceb
PO		 3418}
3419
b8c86fc5 3420EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3421
3422/*****************************************************************************\
3423 * *
3424 * Driver init/exit *
3425 * *
3426\*****************************************************************************/
3427
3428static int __init sdhci_drv_init(void)
3429{
a3c76eb9 3430 pr_info(DRIVER_NAME
52fbf9c9 3431 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3432 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3433
b8c86fc5 3434 return 0;
d129bceb
PO		 3435}
3436
3437static void __exit sdhci_drv_exit(void)
3438{
d129bceb
PO		 3439}
3440
3441module_init(sdhci_drv_init);
3442module_exit(sdhci_drv_exit);
3443
df673b22 3444module_param(debug_quirks, uint, 0444);
66fd8ad5 3445module_param(debug_quirks2, uint, 0444);
67435274 3446
32710e8f 3447MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3448MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3449MODULE_LICENSE("GPL");
67435274 3450
df673b22 3451MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3452MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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