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mmc: sdhci: consolidate the DMA/ADMA size/address quicks
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
f9134319
PO		 41#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43#define SDHCI_USE_LEDS_CLASS
44#endif
45
b513ea25
AN		 46#define MAX_TUNING_LOOP 40
47
df673b22 48static unsigned int debug_quirks = 0;
66fd8ad5 49static unsigned int debug_quirks2;
67435274 50
d129bceb
PO		 51static void sdhci_finish_data(struct sdhci_host *);
52
d129bceb 53static void sdhci_finish_command(struct sdhci_host *);
069c9f14 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
04e079cf 56static int sdhci_do_get_cd(struct sdhci_host *host);
d129bceb 57
162d6f98 58#ifdef CONFIG_PM
66fd8ad5
AH		 59static int sdhci_runtime_pm_get(struct sdhci_host *host);
60static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 61static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
62static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 63#else
64static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
65{
66 return 0;
67}
68static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
69{
70 return 0;
71}
f0710a55
AH		 72static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
73{
74}
75static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
76{
77}
66fd8ad5
AH		 78#endif
79
d129bceb
PO		 80static void sdhci_dumpregs(struct sdhci_host *host)
81{
a3c76eb9 82 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 83 mmc_hostname(host->mmc));
d129bceb 84
a3c76eb9 85 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 86 sdhci_readl(host, SDHCI_DMA_ADDRESS),
87 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 88 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 89 sdhci_readw(host, SDHCI_BLOCK_SIZE),
90 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 91 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 92 sdhci_readl(host, SDHCI_ARGUMENT),
93 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 94 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 95 sdhci_readl(host, SDHCI_PRESENT_STATE),
96 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 97 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 98 sdhci_readb(host, SDHCI_POWER_CONTROL),
99 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 100 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 101 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
102 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 103 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 104 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
105 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 106 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 107 sdhci_readl(host, SDHCI_INT_ENABLE),
108 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 109 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 110 sdhci_readw(host, SDHCI_ACMD12_ERR),
111 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 112 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 113 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 114 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 115 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 116 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 117 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 118 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 119 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 120
e57a5f61
AH		 121 if (host->flags & SDHCI_USE_ADMA) {
122 if (host->flags & SDHCI_USE_64_BIT_DMA)
123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
124 readl(host->ioaddr + SDHCI_ADMA_ERROR),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
126 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
127 else
128 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
129 readl(host->ioaddr + SDHCI_ADMA_ERROR),
130 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
131 }
be3f4ae0 132
a3c76eb9 133 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 134}
135
136/*****************************************************************************\
137 * *
138 * Low level functions *
139 * *
140\*****************************************************************************/
141
7260cf5e
AV		 142static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
143{
5b4f1f6c 144 u32 present;
7260cf5e 145
c79396c1 146 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 147 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 148 return;
149
5b4f1f6c
RK		 150 if (enable) {
151 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
152 SDHCI_CARD_PRESENT;
d25928d1 153
5b4f1f6c
RK		 154 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
155 SDHCI_INT_CARD_INSERT;
156 } else {
157 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
158 }
b537f94c
RK		 159
160 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
161 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 162}
163
164static void sdhci_enable_card_detection(struct sdhci_host *host)
165{
166 sdhci_set_card_detection(host, true);
167}
168
169static void sdhci_disable_card_detection(struct sdhci_host *host)
170{
171 sdhci_set_card_detection(host, false);
172}
173
03231f9b 174void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 175{
e16514d8 176 unsigned long timeout;
393c1a34 177
4e4141a5 178 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 179
f0710a55 180 if (mask & SDHCI_RESET_ALL) {
d129bceb 181 host->clock = 0;
f0710a55
AH		 182 /* Reset-all turns off SD Bus Power */
183 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
184 sdhci_runtime_pm_bus_off(host);
185 }
d129bceb 186
e16514d8
PO		 187 /* Wait max 100 ms */
188 timeout = 100;
189
190 /* hw clears the bit when it's done */
4e4141a5 191 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 192 if (timeout == 0) {
a3c76eb9 193 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 194 mmc_hostname(host->mmc), (int)mask);
195 sdhci_dumpregs(host);
196 return;
197 }
198 timeout--;
199 mdelay(1);
d129bceb 200 }
03231f9b
RK		 201}
202EXPORT_SYMBOL_GPL(sdhci_reset);
203
204static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
205{
206 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
135b0a28 207 if (!sdhci_do_get_cd(host))
03231f9b
RK		 208 return;
209 }
063a9dbb 210
03231f9b 211 host->ops->reset(host, mask);
393c1a34 212
da91a8f9
RK		 213 if (mask & SDHCI_RESET_ALL) {
214 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
215 if (host->ops->enable_dma)
216 host->ops->enable_dma(host);
217 }
218
219 /* Resetting the controller clears many */
220 host->preset_enabled = false;
3abc1e80 221 }
d129bceb
PO		 222}
223
2f4cbb3d
NP		 224static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
225
226static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 227{
2f4cbb3d 228 if (soft)
03231f9b 229 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 230 else
03231f9b 231 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 232
b537f94c
RK		 233 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
235 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
236 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
237 SDHCI_INT_RESPONSE;
238
239 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
240 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 241
242 if (soft) {
243 /* force clock reconfiguration */
244 host->clock = 0;
245 sdhci_set_ios(host->mmc, &host->mmc->ios);
246 }
7260cf5e 247}
d129bceb 248
7260cf5e
AV		 249static void sdhci_reinit(struct sdhci_host *host)
250{
2f4cbb3d 251 sdhci_init(host, 0);
7260cf5e 252 sdhci_enable_card_detection(host);
d129bceb
PO		 253}
254
255static void sdhci_activate_led(struct sdhci_host *host)
256{
257 u8 ctrl;
258
4e4141a5 259 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 260 ctrl |= SDHCI_CTRL_LED;
4e4141a5 261 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 262}
263
264static void sdhci_deactivate_led(struct sdhci_host *host)
265{
266 u8 ctrl;
267
4e4141a5 268 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 269 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 270 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 271}
272
f9134319 273#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 274static void sdhci_led_control(struct led_classdev *led,
275 enum led_brightness brightness)
276{
277 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
278 unsigned long flags;
279
280 spin_lock_irqsave(&host->lock, flags);
281
66fd8ad5
AH		 282 if (host->runtime_suspended)
283 goto out;
284
2f730fec
PO		 285 if (brightness == LED_OFF)
286 sdhci_deactivate_led(host);
287 else
288 sdhci_activate_led(host);
66fd8ad5 289out:
2f730fec
PO		 290 spin_unlock_irqrestore(&host->lock, flags);
291}
292#endif
293
d129bceb
PO		 294/*****************************************************************************\
295 * *
296 * Core functions *
297 * *
298\*****************************************************************************/
299
a406f5a3 300static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 301{
7659150c
PO		 302 unsigned long flags;
303 size_t blksize, len, chunk;
7244b85b 304 u32 uninitialized_var(scratch);
7659150c 305 u8 *buf;
d129bceb 306
a406f5a3 307 DBG("PIO reading\n");
d129bceb 308
a406f5a3 309 blksize = host->data->blksz;
7659150c 310 chunk = 0;
d129bceb 311
7659150c 312 local_irq_save(flags);
d129bceb 313
a406f5a3 314 while (blksize) {
bf3a35ac 315 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 316
7659150c 317 len = min(host->sg_miter.length, blksize);
d129bceb 318
7659150c
PO		 319 blksize -= len;
320 host->sg_miter.consumed = len;
14d836e7 321
7659150c 322 buf = host->sg_miter.addr;
d129bceb 323
7659150c
PO		 324 while (len) {
325 if (chunk == 0) {
4e4141a5 326 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 327 chunk = 4;
a406f5a3 328 }
7659150c
PO		 329
330 *buf = scratch & 0xFF;
331
332 buf++;
333 scratch >>= 8;
334 chunk--;
335 len--;
d129bceb 336 }
a406f5a3 337 }
7659150c
PO		 338
339 sg_miter_stop(&host->sg_miter);
340
341 local_irq_restore(flags);
a406f5a3 342}
d129bceb 343
a406f5a3
PO		 344static void sdhci_write_block_pio(struct sdhci_host *host)
345{
7659150c
PO		 346 unsigned long flags;
347 size_t blksize, len, chunk;
348 u32 scratch;
349 u8 *buf;
d129bceb 350
a406f5a3
PO		 351 DBG("PIO writing\n");
352
353 blksize = host->data->blksz;
7659150c
PO		 354 chunk = 0;
355 scratch = 0;
d129bceb 356
7659150c 357 local_irq_save(flags);
d129bceb 358
a406f5a3 359 while (blksize) {
bf3a35ac 360 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 361
7659150c
PO		 362 len = min(host->sg_miter.length, blksize);
363
364 blksize -= len;
365 host->sg_miter.consumed = len;
366
367 buf = host->sg_miter.addr;
d129bceb 368
7659150c
PO		 369 while (len) {
370 scratch |= (u32)*buf << (chunk * 8);
371
372 buf++;
373 chunk++;
374 len--;
375
376 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 377 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 378 chunk = 0;
379 scratch = 0;
d129bceb 380 }
d129bceb
PO		 381 }
382 }
7659150c
PO		 383
384 sg_miter_stop(&host->sg_miter);
385
386 local_irq_restore(flags);
a406f5a3
PO		 387}
388
389static void sdhci_transfer_pio(struct sdhci_host *host)
390{
391 u32 mask;
392
393 BUG_ON(!host->data);
394
7659150c 395 if (host->blocks == 0)
a406f5a3
PO		 396 return;
397
398 if (host->data->flags & MMC_DATA_READ)
399 mask = SDHCI_DATA_AVAILABLE;
400 else
401 mask = SDHCI_SPACE_AVAILABLE;
402
4a3cba32
PO		 403 /*
404 * Some controllers (JMicron JMB38x) mess up the buffer bits
405 * for transfers < 4 bytes. As long as it is just one block,
406 * we can ignore the bits.
407 */
408 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
409 (host->data->blocks == 1))
410 mask = ~0;
411
4e4141a5 412 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 413 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
414 udelay(100);
415
a406f5a3
PO		 416 if (host->data->flags & MMC_DATA_READ)
417 sdhci_read_block_pio(host);
418 else
419 sdhci_write_block_pio(host);
d129bceb 420
7659150c
PO		 421 host->blocks--;
422 if (host->blocks == 0)
a406f5a3 423 break;
a406f5a3 424 }
d129bceb 425
a406f5a3 426 DBG("PIO transfer complete.\n");
d129bceb
PO		 427}
428
48857d9b 429static int sdhci_pre_dma_transfer(struct sdhci_host *host,
c0999b72 430 struct mmc_data *data, int cookie)
48857d9b
RK		 431{
432 int sg_count;
433
94538e51
RK		 434 /*
435 * If the data buffers are already mapped, return the previous
436 * dma_map_sg() result.
437 */
438 if (data->host_cookie == COOKIE_PRE_MAPPED)
48857d9b 439 return data->sg_count;
48857d9b
RK		 440
441 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
442 data->flags & MMC_DATA_WRITE ?
443 DMA_TO_DEVICE : DMA_FROM_DEVICE);
444
445 if (sg_count == 0)
446 return -ENOSPC;
447
448 data->sg_count = sg_count;
c0999b72 449 data->host_cookie = cookie;
48857d9b
RK		 450
451 return sg_count;
452}
453
2134a922
PO		 454static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
455{
456 local_irq_save(*flags);
482fce99 457 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 458}
459
460static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
461{
482fce99 462 kunmap_atomic(buffer);
2134a922
PO		 463 local_irq_restore(*flags);
464}
465
e57a5f61
AH		 466static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
467 dma_addr_t addr, int len, unsigned cmd)
118cd17d 468{
e57a5f61 469 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 470
e57a5f61 471 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 472 dma_desc->cmd = cpu_to_le16(cmd);
473 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 474 dma_desc->addr_lo = cpu_to_le32((u32)addr);
475
476 if (host->flags & SDHCI_USE_64_BIT_DMA)
477 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 478}
479
b5ffa674
AH		 480static void sdhci_adma_mark_end(void *desc)
481{
e57a5f61 482 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 483
e57a5f61 484 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 485 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 486}
487
60c64762
RK		 488static void sdhci_adma_table_pre(struct sdhci_host *host,
489 struct mmc_data *data, int sg_count)
2134a922 490{
2134a922 491 struct scatterlist *sg;
2134a922 492 unsigned long flags;
acc3ad13
RK		 493 dma_addr_t addr, align_addr;
494 void *desc, *align;
495 char *buffer;
496 int len, offset, i;
2134a922
PO		 497
498 /*
499 * The spec does not specify endianness of descriptor table.
500 * We currently guess that it is LE.
501 */
502
60c64762 503 host->sg_count = sg_count;
2134a922 504
4efaa6fb 505 desc = host->adma_table;
2134a922
PO		 506 align = host->align_buffer;
507
508 align_addr = host->align_addr;
509
510 for_each_sg(data->sg, sg, host->sg_count, i) {
511 addr = sg_dma_address(sg);
512 len = sg_dma_len(sg);
513
514 /*
acc3ad13
RK		 515 * The SDHCI specification states that ADMA addresses must
516 * be 32-bit aligned. If they aren't, then we use a bounce
517 * buffer for the (up to three) bytes that screw up the
2134a922
PO		 518 * alignment.
519 */
04a5ae6f
AH		 520 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
521 SDHCI_ADMA2_MASK;
2134a922
PO		 522 if (offset) {
523 if (data->flags & MMC_DATA_WRITE) {
524 buffer = sdhci_kmap_atomic(sg, &flags);
525 memcpy(align, buffer, offset);
526 sdhci_kunmap_atomic(buffer, &flags);
527 }
528
118cd17d 529 /* tran, valid */
e57a5f61 530 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 531 ADMA2_TRAN_VALID);
2134a922
PO		 532
533 BUG_ON(offset > 65536);
534
04a5ae6f
AH		 535 align += SDHCI_ADMA2_ALIGN;
536 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 537
76fe379a 538 desc += host->desc_sz;
2134a922
PO		 539
540 addr += offset;
541 len -= offset;
542 }
543
2134a922
PO		 544 BUG_ON(len > 65536);
545
347ea32d
AH		 546 if (len) {
547 /* tran, valid */
548 sdhci_adma_write_desc(host, desc, addr, len,
549 ADMA2_TRAN_VALID);
550 desc += host->desc_sz;
551 }
2134a922
PO		 552
553 /*
554 * If this triggers then we have a calculation bug
555 * somewhere. :/
556 */
76fe379a 557 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 558 }
559
70764a90 560 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
acc3ad13 561 /* Mark the last descriptor as the terminating descriptor */
4efaa6fb 562 if (desc != host->adma_table) {
76fe379a 563 desc -= host->desc_sz;
b5ffa674 564 sdhci_adma_mark_end(desc);
70764a90
TA		 565 }
566 } else {
acc3ad13 567 /* Add a terminating entry - nop, end, valid */
e57a5f61 568 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 569 }
2134a922
PO		 570}
571
572static void sdhci_adma_table_post(struct sdhci_host *host,
573 struct mmc_data *data)
574{
2134a922
PO		 575 struct scatterlist *sg;
576 int i, size;
1c3d5f6d 577 void *align;
2134a922
PO		 578 char *buffer;
579 unsigned long flags;
580
47fa9613
RK		 581 if (data->flags & MMC_DATA_READ) {
582 bool has_unaligned = false;
de0b65a7 583
47fa9613
RK		 584 /* Do a quick scan of the SG list for any unaligned mappings */
585 for_each_sg(data->sg, sg, host->sg_count, i)
586 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
587 has_unaligned = true;
588 break;
589 }
2134a922 590
47fa9613
RK		 591 if (has_unaligned) {
592 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
f55c98f7 593 data->sg_len, DMA_FROM_DEVICE);
2134a922 594
47fa9613 595 align = host->align_buffer;
2134a922 596
47fa9613
RK		 597 for_each_sg(data->sg, sg, host->sg_count, i) {
598 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
599 size = SDHCI_ADMA2_ALIGN -
600 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
601
602 buffer = sdhci_kmap_atomic(sg, &flags);
603 memcpy(buffer, align, size);
604 sdhci_kunmap_atomic(buffer, &flags);
2134a922 605
47fa9613
RK		 606 align += SDHCI_ADMA2_ALIGN;
607 }
2134a922
PO		 608 }
609 }
610 }
2134a922
PO		 611}
612
a3c7778f 613static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 614{
1c8cde92 615 u8 count;
a3c7778f 616 struct mmc_data *data = cmd->data;
1c8cde92 617 unsigned target_timeout, current_timeout;
d129bceb 618
ee53ab5d
PO		 619 /*
620 * If the host controller provides us with an incorrect timeout
621 * value, just skip the check and use 0xE. The hardware may take
622 * longer to time out, but that's much better than having a too-short
623 * timeout value.
624 */
11a2f1b7 625 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 626 return 0xE;
e538fbe8 627
a3c7778f 628 /* Unspecified timeout, assume max */
1d4d7744 629 if (!data && !cmd->busy_timeout)
a3c7778f 630 return 0xE;
d129bceb 631
a3c7778f
AW		 632 /* timeout in us */
633 if (!data)
1d4d7744 634 target_timeout = cmd->busy_timeout * 1000;
78a2ca27 635 else {
fafcfda9 636 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
7f05538a
RK		 637 if (host->clock && data->timeout_clks) {
638 unsigned long long val;
639
640 /*
641 * data->timeout_clks is in units of clock cycles.
642 * host->clock is in Hz. target_timeout is in us.
643 * Hence, us = 1000000 * cycles / Hz. Round up.
644 */
645 val = 1000000 * data->timeout_clks;
646 if (do_div(val, host->clock))
647 target_timeout++;
648 target_timeout += val;
649 }
78a2ca27 650 }
81b39802 651
1c8cde92
PO		 652 /*
653 * Figure out needed cycles.
654 * We do this in steps in order to fit inside a 32 bit int.
655 * The first step is the minimum timeout, which will have a
656 * minimum resolution of 6 bits:
657 * (1) 2^13*1000 > 2^22,
658 * (2) host->timeout_clk < 2^16
659 * =>
660 * (1) / (2) > 2^6
661 */
662 count = 0;
663 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
664 while (current_timeout < target_timeout) {
665 count++;
666 current_timeout <<= 1;
667 if (count >= 0xF)
668 break;
669 }
670
671 if (count >= 0xF) {
09eeff52
CB		 672 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
673 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 674 count = 0xE;
675 }
676
ee53ab5d
PO		 677 return count;
678}
679
6aa943ab
AV		 680static void sdhci_set_transfer_irqs(struct sdhci_host *host)
681{
682 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
683 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
684
685 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 686 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 687 else
b537f94c
RK		 688 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
689
690 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
691 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 692}
693
b45e668a 694static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 695{
696 u8 count;
b45e668a
AD		 697
698 if (host->ops->set_timeout) {
699 host->ops->set_timeout(host, cmd);
700 } else {
701 count = sdhci_calc_timeout(host, cmd);
702 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
703 }
704}
705
706static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
707{
2134a922 708 u8 ctrl;
a3c7778f 709 struct mmc_data *data = cmd->data;
ee53ab5d
PO		 710
711 WARN_ON(host->data);
712
b45e668a
AD		 713 if (data || (cmd->flags & MMC_RSP_BUSY))
714 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 715
716 if (!data)
ee53ab5d
PO		 717 return;
718
719 /* Sanity checks */
720 BUG_ON(data->blksz * data->blocks > 524288);
721 BUG_ON(data->blksz > host->mmc->max_blk_size);
722 BUG_ON(data->blocks > 65535);
723
724 host->data = data;
725 host->data_early = 0;
f6a03cbf 726 host->data->bytes_xfered = 0;
ee53ab5d 727
a13abc7b 728 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 729 host->flags |= SDHCI_REQ_USE_DMA;
730
2134a922
PO		 731 /*
732 * FIXME: This doesn't account for merging when mapping the
733 * scatterlist.
df953925
RK		 734 *
735 * The assumption here being that alignment and lengths are
736 * the same after DMA mapping to device address space.
2134a922
PO		 737 */
738 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922 739 struct scatterlist *sg;
df953925 740 unsigned int length_mask, offset_mask;
a0eaf0f9 741 int i;
2134a922 742
a0eaf0f9 743 length_mask = 0;
df953925 744 offset_mask = 0;
2134a922 745 if (host->flags & SDHCI_USE_ADMA) {
df953925 746 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
a0eaf0f9 747 length_mask = 3;
df953925
RK		 748 /*
749 * As we use up to 3 byte chunks to work
750 * around alignment problems, we need to
751 * check the offset as well.
752 */
753 offset_mask = 3;
754 }
2134a922
PO		 755 } else {
756 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
a0eaf0f9 757 length_mask = 3;
df953925
RK		 758 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
759 offset_mask = 3;
2134a922
PO		 760 }
761
df953925 762 if (unlikely(length_mask | offset_mask)) {
2134a922 763 for_each_sg(data->sg, sg, data->sg_len, i) {
a0eaf0f9 764 if (sg->length & length_mask) {
2e4456f0 765 DBG("Reverting to PIO because of transfer size (%d)\n",
a0eaf0f9 766 sg->length);
2134a922
PO		 767 host->flags &= ~SDHCI_REQ_USE_DMA;
768 break;
769 }
a0eaf0f9 770 if (sg->offset & offset_mask) {
2e4456f0 771 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 772 host->flags &= ~SDHCI_REQ_USE_DMA;
773 break;
774 }
775 }
776 }
777 }
778
8f1934ce 779 if (host->flags & SDHCI_REQ_USE_DMA) {
c0999b72 780 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
60c64762
RK		 781
782 if (sg_cnt <= 0) {
783 /*
784 * This only happens when someone fed
785 * us an invalid request.
786 */
787 WARN_ON(1);
788 host->flags &= ~SDHCI_REQ_USE_DMA;
789 } else if (host->flags & SDHCI_USE_ADMA) {
790 sdhci_adma_table_pre(host, data, sg_cnt);
791
792 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
793 if (host->flags & SDHCI_USE_64_BIT_DMA)
794 sdhci_writel(host,
795 (u64)host->adma_addr >> 32,
796 SDHCI_ADMA_ADDRESS_HI);
8f1934ce 797 } else {
60c64762
RK		 798 WARN_ON(sg_cnt != 1);
799 sdhci_writel(host, sg_dma_address(data->sg),
800 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 801 }
802 }
803
2134a922
PO		 804 /*
805 * Always adjust the DMA selection as some controllers
806 * (e.g. JMicron) can't do PIO properly when the selection
807 * is ADMA.
808 */
809 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 810 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 811 ctrl &= ~SDHCI_CTRL_DMA_MASK;
812 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 813 (host->flags & SDHCI_USE_ADMA)) {
814 if (host->flags & SDHCI_USE_64_BIT_DMA)
815 ctrl |= SDHCI_CTRL_ADMA64;
816 else
817 ctrl |= SDHCI_CTRL_ADMA32;
818 } else {
2134a922 819 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 820 }
4e4141a5 821 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 822 }
823
8f1934ce 824 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 825 int flags;
826
827 flags = SG_MITER_ATOMIC;
828 if (host->data->flags & MMC_DATA_READ)
829 flags |= SG_MITER_TO_SG;
830 else
831 flags |= SG_MITER_FROM_SG;
832 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 833 host->blocks = data->blocks;
d129bceb 834 }
c7fa9963 835
6aa943ab
AV		 836 sdhci_set_transfer_irqs(host);
837
f6a03cbf
MV		 838 /* Set the DMA boundary value and block size */
839 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
840 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 841 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 842}
843
844static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 845 struct mmc_command *cmd)
c7fa9963 846{
d3fc5d71 847 u16 mode = 0;
e89d456f 848 struct mmc_data *data = cmd->data;
c7fa9963 849
2b558c13 850 if (data == NULL) {
9b8ffea6
VW		 851 if (host->quirks2 &
852 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
853 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
854 } else {
2b558c13 855 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 856 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
857 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 858 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 859 }
c7fa9963 860 return;
2b558c13 861 }
c7fa9963 862
e538fbe8
PO		 863 WARN_ON(!host->data);
864
d3fc5d71
VY		 865 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
866 mode = SDHCI_TRNS_BLK_CNT_EN;
867
e89d456f 868 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 869 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 870 /*
871 * If we are sending CMD23, CMD12 never gets sent
872 * on successful completion (so no Auto-CMD12).
873 */
85cc1c33
CD		 874 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
875 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 876 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 877 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
878 mode |= SDHCI_TRNS_AUTO_CMD23;
879 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
880 }
c4512f79 881 }
8edf6371 882
c7fa9963
PO		 883 if (data->flags & MMC_DATA_READ)
884 mode |= SDHCI_TRNS_READ;
c9fddbc4 885 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 886 mode |= SDHCI_TRNS_DMA;
887
4e4141a5 888 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 889}
890
891static void sdhci_finish_data(struct sdhci_host *host)
892{
893 struct mmc_data *data;
d129bceb
PO		 894
895 BUG_ON(!host->data);
896
897 data = host->data;
898 host->data = NULL;
899
add8913d
RK		 900 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
901 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
902 sdhci_adma_table_post(host, data);
d129bceb
PO		 903
904 /*
c9b74c5b
PO		 905 * The specification states that the block count register must
906 * be updated, but it does not specify at what point in the
907 * data flow. That makes the register entirely useless to read
908 * back so we have to assume that nothing made it to the card
909 * in the event of an error.
d129bceb 910 */
c9b74c5b
PO		 911 if (data->error)
912 data->bytes_xfered = 0;
d129bceb 913 else
c9b74c5b 914 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 915
e89d456f
AW		 916 /*
917 * Need to send CMD12 if -
918 * a) open-ended multiblock transfer (no CMD23)
919 * b) error in multiblock transfer
920 */
921 if (data->stop &&
922 (data->error ||
923 !host->mrq->sbc)) {
924
d129bceb
PO		 925 /*
926 * The controller needs a reset of internal state machines
927 * upon error conditions.
928 */
17b0429d 929 if (data->error) {
03231f9b
RK		 930 sdhci_do_reset(host, SDHCI_RESET_CMD);
931 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 932 }
933
934 sdhci_send_command(host, data->stop);
935 } else
936 tasklet_schedule(&host->finish_tasklet);
937}
938
c0e55129 939void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 940{
941 int flags;
fd2208d7 942 u32 mask;
7cb2c76f 943 unsigned long timeout;
d129bceb
PO		 944
945 WARN_ON(host->cmd);
946
96776200
RK		 947 /* Initially, a command has no error */
948 cmd->error = 0;
949
d129bceb 950 /* Wait max 10 ms */
7cb2c76f 951 timeout = 10;
fd2208d7
PO		 952
953 mask = SDHCI_CMD_INHIBIT;
954 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
955 mask |= SDHCI_DATA_INHIBIT;
956
957 /* We shouldn't wait for data inihibit for stop commands, even
958 though they might use busy signaling */
959 if (host->mrq->data && (cmd == host->mrq->data->stop))
960 mask &= ~SDHCI_DATA_INHIBIT;
961
4e4141a5 962 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 963 if (timeout == 0) {
2e4456f0
MV		 964 pr_err("%s: Controller never released inhibit bit(s).\n",
965 mmc_hostname(host->mmc));
d129bceb 966 sdhci_dumpregs(host);
17b0429d 967 cmd->error = -EIO;
d129bceb
PO		 968 tasklet_schedule(&host->finish_tasklet);
969 return;
970 }
7cb2c76f
PO		 971 timeout--;
972 mdelay(1);
973 }
d129bceb 974
3e1a6892 975 timeout = jiffies;
1d4d7744
UH		 976 if (!cmd->data && cmd->busy_timeout > 9000)
977 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 978 else
979 timeout += 10 * HZ;
980 mod_timer(&host->timer, timeout);
d129bceb
PO		 981
982 host->cmd = cmd;
e99783a4 983 host->busy_handle = 0;
d129bceb 984
a3c7778f 985 sdhci_prepare_data(host, cmd);
d129bceb 986
4e4141a5 987 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 988
e89d456f 989 sdhci_set_transfer_mode(host, cmd);
c7fa9963 990
d129bceb 991 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 992 pr_err("%s: Unsupported response type!\n",
d129bceb 993 mmc_hostname(host->mmc));
17b0429d 994 cmd->error = -EINVAL;
d129bceb
PO		 995 tasklet_schedule(&host->finish_tasklet);
996 return;
997 }
998
999 if (!(cmd->flags & MMC_RSP_PRESENT))
1000 flags = SDHCI_CMD_RESP_NONE;
1001 else if (cmd->flags & MMC_RSP_136)
1002 flags = SDHCI_CMD_RESP_LONG;
1003 else if (cmd->flags & MMC_RSP_BUSY)
1004 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1005 else
1006 flags = SDHCI_CMD_RESP_SHORT;
1007
1008 if (cmd->flags & MMC_RSP_CRC)
1009 flags |= SDHCI_CMD_CRC;
1010 if (cmd->flags & MMC_RSP_OPCODE)
1011 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1012
1013 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1014 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1015 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1016 flags |= SDHCI_CMD_DATA;
1017
4e4141a5 1018 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1019}
c0e55129 1020EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1021
1022static void sdhci_finish_command(struct sdhci_host *host)
1023{
1024 int i;
1025
1026 BUG_ON(host->cmd == NULL);
1027
1028 if (host->cmd->flags & MMC_RSP_PRESENT) {
1029 if (host->cmd->flags & MMC_RSP_136) {
1030 /* CRC is stripped so we need to do some shifting. */
1031 for (i = 0;i < 4;i++) {
4e4141a5 1032 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1033 SDHCI_RESPONSE + (3-i)*4) << 8;
1034 if (i != 3)
1035 host->cmd->resp[i] |=
4e4141a5 1036 sdhci_readb(host,
d129bceb
PO		 1037 SDHCI_RESPONSE + (3-i)*4-1);
1038 }
1039 } else {
4e4141a5 1040 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1041 }
1042 }
1043
e89d456f
AW		 1044 /* Finished CMD23, now send actual command. */
1045 if (host->cmd == host->mrq->sbc) {
1046 host->cmd = NULL;
1047 sdhci_send_command(host, host->mrq->cmd);
1048 } else {
e538fbe8 1049
e89d456f
AW		 1050 /* Processed actual command. */
1051 if (host->data && host->data_early)
1052 sdhci_finish_data(host);
d129bceb 1053
e89d456f
AW		 1054 if (!host->cmd->data)
1055 tasklet_schedule(&host->finish_tasklet);
1056
1057 host->cmd = NULL;
1058 }
d129bceb
PO		 1059}
1060
52983382
KL		 1061static u16 sdhci_get_preset_value(struct sdhci_host *host)
1062{
d975f121 1063 u16 preset = 0;
52983382 1064
d975f121
RK		 1065 switch (host->timing) {
1066 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1067 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1068 break;
d975f121 1069 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1070 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1071 break;
d975f121 1072 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1073 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1074 break;
d975f121
RK		 1075 case MMC_TIMING_UHS_SDR104:
1076 case MMC_TIMING_MMC_HS200:
52983382
KL		 1077 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1078 break;
d975f121 1079 case MMC_TIMING_UHS_DDR50:
0dafa60e 1080 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1081 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1082 break;
e9fb05d5
AH		 1083 case MMC_TIMING_MMC_HS400:
1084 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1085 break;
52983382
KL		 1086 default:
1087 pr_warn("%s: Invalid UHS-I mode selected\n",
1088 mmc_hostname(host->mmc));
1089 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1090 break;
1091 }
1092 return preset;
1093}
1094
1771059c 1095void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1096{
c3ed3877 1097 int div = 0; /* Initialized for compiler warning */
df16219f 1098 int real_div = div, clk_mul = 1;
c3ed3877 1099 u16 clk = 0;
7cb2c76f 1100 unsigned long timeout;
5497159c 1101 bool switch_base_clk = false;
d129bceb 1102
1650d0c7
RK		 1103 host->mmc->actual_clock = 0;
1104
4e4141a5 1105 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
af951761 1106 if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1107 mdelay(1);
d129bceb
PO		 1108
1109 if (clock == 0)
373073ef 1110 return;
d129bceb 1111
85105c53 1112 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1113 if (host->preset_enabled) {
52983382
KL		 1114 u16 pre_val;
1115
1116 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1117 pre_val = sdhci_get_preset_value(host);
1118 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1119 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1120 if (host->clk_mul &&
1121 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1122 clk = SDHCI_PROG_CLOCK_MODE;
1123 real_div = div + 1;
1124 clk_mul = host->clk_mul;
1125 } else {
1126 real_div = max_t(int, 1, div << 1);
1127 }
1128 goto clock_set;
1129 }
1130
c3ed3877
AN		 1131 /*
1132 * Check if the Host Controller supports Programmable Clock
1133 * Mode.
1134 */
1135 if (host->clk_mul) {
52983382
KL		 1136 for (div = 1; div <= 1024; div++) {
1137 if ((host->max_clk * host->clk_mul / div)
1138 <= clock)
1139 break;
1140 }
5497159c 1141 if ((host->max_clk * host->clk_mul / div) <= clock) {
1142 /*
1143 * Set Programmable Clock Mode in the Clock
1144 * Control register.
1145 */
1146 clk = SDHCI_PROG_CLOCK_MODE;
1147 real_div = div;
1148 clk_mul = host->clk_mul;
1149 div--;
1150 } else {
1151 /*
1152 * Divisor can be too small to reach clock
1153 * speed requirement. Then use the base clock.
1154 */
1155 switch_base_clk = true;
1156 }
1157 }
1158
1159 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1160 /* Version 3.00 divisors must be a multiple of 2. */
1161 if (host->max_clk <= clock)
1162 div = 1;
1163 else {
1164 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1165 div += 2) {
1166 if ((host->max_clk / div) <= clock)
1167 break;
1168 }
85105c53 1169 }
df16219f 1170 real_div = div;
c3ed3877 1171 div >>= 1;
d1955c3a
SG		 1172 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1173 && !div && host->max_clk <= 25000000)
1174 div = 1;
85105c53
ZG		 1175 }
1176 } else {
1177 /* Version 2.00 divisors must be a power of 2. */
0397526d 1178 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1179 if ((host->max_clk / div) <= clock)
1180 break;
1181 }
df16219f 1182 real_div = div;
c3ed3877 1183 div >>= 1;
d129bceb 1184 }
d129bceb 1185
52983382 1186clock_set:
03d6f5ff 1187 if (real_div)
df16219f 1188 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1189 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1190 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1191 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1192 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1193 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1194
27f6cb16
CB		 1195 /* Wait max 20 ms */
1196 timeout = 20;
4e4141a5 1197 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1198 & SDHCI_CLOCK_INT_STABLE)) {
1199 if (timeout == 0) {
2e4456f0
MV		 1200 pr_err("%s: Internal clock never stabilised.\n",
1201 mmc_hostname(host->mmc));
d129bceb
PO		 1202 sdhci_dumpregs(host);
1203 return;
1204 }
7cb2c76f
PO		 1205 timeout--;
1206 mdelay(1);
1207 }
d129bceb
PO		 1208
1209 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1210 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1211}
1771059c 1212EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1213
24fbb3ca
RK		 1214static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1215 unsigned short vdd)
146ad66e 1216{
3a48edc4 1217 struct mmc_host *mmc = host->mmc;
8364248a 1218 u8 pwr = 0;
146ad66e 1219
24fbb3ca
RK		 1220 if (mode != MMC_POWER_OFF) {
1221 switch (1 << vdd) {
ae628903
PO		 1222 case MMC_VDD_165_195:
1223 pwr = SDHCI_POWER_180;
1224 break;
1225 case MMC_VDD_29_30:
1226 case MMC_VDD_30_31:
1227 pwr = SDHCI_POWER_300;
1228 break;
1229 case MMC_VDD_32_33:
1230 case MMC_VDD_33_34:
1231 pwr = SDHCI_POWER_330;
1232 break;
1233 default:
9d5de93f
AH		 1234 WARN(1, "%s: Invalid vdd %#x\n",
1235 mmc_hostname(host->mmc), vdd);
1236 break;
ae628903
PO		 1237 }
1238 }
1239
1240 if (host->pwr == pwr)
e921a8b6 1241 return;
146ad66e 1242
ae628903
PO		 1243 host->pwr = pwr;
1244
1245 if (pwr == 0) {
4e4141a5 1246 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1247 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1248 sdhci_runtime_pm_bus_off(host);
24fbb3ca 1249 vdd = 0;
e921a8b6
RK		 1250 } else {
1251 /*
1252 * Spec says that we should clear the power reg before setting
1253 * a new value. Some controllers don't seem to like this though.
1254 */
1255 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1256 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1257
e921a8b6
RK		 1258 /*
1259 * At least the Marvell CaFe chip gets confused if we set the
1260 * voltage and set turn on power at the same time, so set the
1261 * voltage first.
1262 */
1263 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1264 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1265
e921a8b6 1266 pwr |= SDHCI_POWER_ON;
146ad66e 1267
e921a8b6 1268 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1269
e921a8b6
RK		 1270 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1271 sdhci_runtime_pm_bus_on(host);
f0710a55 1272
e921a8b6
RK		 1273 /*
1274 * Some controllers need an extra 10ms delay of 10ms before
1275 * they can apply clock after applying power
1276 */
1277 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1278 mdelay(10);
1279 }
918f4cbd
JZ		 1280
1281 if (!IS_ERR(mmc->supply.vmmc)) {
1282 spin_unlock_irq(&host->lock);
1283 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1284 spin_lock_irq(&host->lock);
1285 }
146ad66e
PO		 1286}
1287
d129bceb
PO		 1288/*****************************************************************************\
1289 * *
1290 * MMC callbacks *
1291 * *
1292\*****************************************************************************/
1293
1294static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1295{
1296 struct sdhci_host *host;
505a8680 1297 int present;
d129bceb
PO		 1298 unsigned long flags;
1299
1300 host = mmc_priv(mmc);
1301
66fd8ad5
AH		 1302 sdhci_runtime_pm_get(host);
1303
04e079cf 1304 /* Firstly check card presence */
8d28b7a7 1305 present = mmc->ops->get_cd(mmc);
2836766a 1306
d129bceb
PO		 1307 spin_lock_irqsave(&host->lock, flags);
1308
1309 WARN_ON(host->mrq != NULL);
1310
f9134319 1311#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1312 sdhci_activate_led(host);
2f730fec 1313#endif
e89d456f
AW		 1314
1315 /*
1316 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1317 * requests if Auto-CMD12 is enabled.
1318 */
1319 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1320 if (mrq->stop) {
1321 mrq->data->stop = NULL;
1322 mrq->stop = NULL;
1323 }
1324 }
d129bceb
PO		 1325
1326 host->mrq = mrq;
1327
68d1fb7e 1328 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1329 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1330 tasklet_schedule(&host->finish_tasklet);
cf2b5eea 1331 } else {
8edf6371 1332 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1333 sdhci_send_command(host, mrq->sbc);
1334 else
1335 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1336 }
d129bceb 1337
5f25a66f 1338 mmiowb();
d129bceb
PO		 1339 spin_unlock_irqrestore(&host->lock, flags);
1340}
1341
2317f56c
RK		 1342void sdhci_set_bus_width(struct sdhci_host *host, int width)
1343{
1344 u8 ctrl;
1345
1346 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1347 if (width == MMC_BUS_WIDTH_8) {
1348 ctrl &= ~SDHCI_CTRL_4BITBUS;
1349 if (host->version >= SDHCI_SPEC_300)
1350 ctrl |= SDHCI_CTRL_8BITBUS;
1351 } else {
1352 if (host->version >= SDHCI_SPEC_300)
1353 ctrl &= ~SDHCI_CTRL_8BITBUS;
1354 if (width == MMC_BUS_WIDTH_4)
1355 ctrl |= SDHCI_CTRL_4BITBUS;
1356 else
1357 ctrl &= ~SDHCI_CTRL_4BITBUS;
1358 }
1359 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1360}
1361EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1362
96d7b78c
RK		 1363void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1364{
1365 u16 ctrl_2;
1366
1367 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1368 /* Select Bus Speed Mode for host */
1369 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1370 if ((timing == MMC_TIMING_MMC_HS200) ||
1371 (timing == MMC_TIMING_UHS_SDR104))
1372 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1373 else if (timing == MMC_TIMING_UHS_SDR12)
1374 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1375 else if (timing == MMC_TIMING_UHS_SDR25)
1376 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1377 else if (timing == MMC_TIMING_UHS_SDR50)
1378 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1379 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1380 (timing == MMC_TIMING_MMC_DDR52))
1381 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1382 else if (timing == MMC_TIMING_MMC_HS400)
1383 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1384 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1385}
1386EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1387
66fd8ad5 1388static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1389{
d129bceb
PO		 1390 unsigned long flags;
1391 u8 ctrl;
3a48edc4 1392 struct mmc_host *mmc = host->mmc;
d129bceb 1393
d129bceb
PO		 1394 spin_lock_irqsave(&host->lock, flags);
1395
ceb6143b
AH		 1396 if (host->flags & SDHCI_DEVICE_DEAD) {
1397 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1398 if (!IS_ERR(mmc->supply.vmmc) &&
1399 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1400 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1401 return;
1402 }
1e72859e 1403
d129bceb
PO		 1404 /*
1405 * Reset the chip on each power off.
1406 * Should clear out any weird states.
1407 */
1408 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1409 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1410 sdhci_reinit(host);
d129bceb
PO		 1411 }
1412
52983382 1413 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1414 (ios->power_mode == MMC_POWER_UP) &&
1415 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1416 sdhci_enable_preset_value(host, false);
1417
373073ef 1418 if (!ios->clock || ios->clock != host->clock) {
1771059c 1419 host->ops->set_clock(host, ios->clock);
373073ef 1420 host->clock = ios->clock;
03d6f5ff
AD		 1421
1422 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1423 host->clock) {
1424 host->timeout_clk = host->mmc->actual_clock ?
1425 host->mmc->actual_clock / 1000 :
1426 host->clock / 1000;
1427 host->mmc->max_busy_timeout =
1428 host->ops->get_max_timeout_count ?
1429 host->ops->get_max_timeout_count(host) :
1430 1 << 27;
1431 host->mmc->max_busy_timeout /= host->timeout_clk;
1432 }
373073ef 1433 }
d129bceb 1434
24fbb3ca 1435 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1436
643a81ff
PR		 1437 if (host->ops->platform_send_init_74_clocks)
1438 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1439
2317f56c 1440 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1441
15ec4461 1442 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1443
3ab9c8da
PR		 1444 if ((ios->timing == MMC_TIMING_SD_HS ||
1445 ios->timing == MMC_TIMING_MMC_HS)
1446 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1447 ctrl |= SDHCI_CTRL_HISPD;
1448 else
1449 ctrl &= ~SDHCI_CTRL_HISPD;
1450
d6d50a15 1451 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1452 u16 clk, ctrl_2;
49c468fc
AN		 1453
1454 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1455 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1456 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1457 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1458 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1459 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1460 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1461 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1462 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1463
da91a8f9 1464 if (!host->preset_enabled) {
758535c4 1465 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1466 /*
1467 * We only need to set Driver Strength if the
1468 * preset value enable is not set.
1469 */
da91a8f9 1470 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1471 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1472 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1473 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1474 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1475 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1476 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1477 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1478 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1479 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1480 else {
2e4456f0
MV		 1481 pr_warn("%s: invalid driver type, default to driver type B\n",
1482 mmc_hostname(mmc));
43e943a0
PG		 1483 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1484 }
d6d50a15
AN		 1485
1486 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1487 } else {
1488 /*
1489 * According to SDHC Spec v3.00, if the Preset Value
1490 * Enable in the Host Control 2 register is set, we
1491 * need to reset SD Clock Enable before changing High
1492 * Speed Enable to avoid generating clock gliches.
1493 */
758535c4
AN		 1494
1495 /* Reset SD Clock Enable */
1496 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1497 clk &= ~SDHCI_CLOCK_CARD_EN;
1498 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1499
1500 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1501
1502 /* Re-enable SD Clock */
1771059c 1503 host->ops->set_clock(host, host->clock);
d6d50a15 1504 }
49c468fc 1505
49c468fc
AN		 1506 /* Reset SD Clock Enable */
1507 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1508 clk &= ~SDHCI_CLOCK_CARD_EN;
1509 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1510
96d7b78c 1511 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1512 host->timing = ios->timing;
49c468fc 1513
52983382
KL		 1514 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1515 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1516 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1517 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1518 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 1519 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1520 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 1521 u16 preset;
1522
1523 sdhci_enable_preset_value(host, true);
1524 preset = sdhci_get_preset_value(host);
1525 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1526 >> SDHCI_PRESET_DRV_SHIFT;
1527 }
1528
49c468fc 1529 /* Re-enable SD Clock */
1771059c 1530 host->ops->set_clock(host, host->clock);
758535c4
AN		 1531 } else
1532 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1533
b8352260
LD		 1534 /*
1535 * Some (ENE) controllers go apeshit on some ios operation,
1536 * signalling timeout and CRC errors even on CMD0. Resetting
1537 * it on each ios seems to solve the problem.
1538 */
c63705e1 1539 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1540 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1541
5f25a66f 1542 mmiowb();
d129bceb
PO		 1543 spin_unlock_irqrestore(&host->lock, flags);
1544}
1545
66fd8ad5
AH		 1546static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1547{
1548 struct sdhci_host *host = mmc_priv(mmc);
1549
1550 sdhci_runtime_pm_get(host);
1551 sdhci_do_set_ios(host, ios);
1552 sdhci_runtime_pm_put(host);
1553}
1554
94144a46
KL		 1555static int sdhci_do_get_cd(struct sdhci_host *host)
1556{
1557 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1558
1559 if (host->flags & SDHCI_DEVICE_DEAD)
1560 return 0;
1561
88af5655
II		 1562 /* If nonremovable, assume that the card is always present. */
1563 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
94144a46
KL		 1564 return 1;
1565
88af5655
II		 1566 /*
1567 * Try slot gpio detect, if defined it take precedence
1568 * over build in controller functionality
1569 */
94144a46
KL		 1570 if (!IS_ERR_VALUE(gpio_cd))
1571 return !!gpio_cd;
1572
88af5655
II		 1573 /* If polling, assume that the card is always present. */
1574 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1575 return 1;
1576
94144a46
KL		 1577 /* Host native card detect */
1578 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1579}
1580
1581static int sdhci_get_cd(struct mmc_host *mmc)
1582{
1583 struct sdhci_host *host = mmc_priv(mmc);
1584 int ret;
1585
1586 sdhci_runtime_pm_get(host);
1587 ret = sdhci_do_get_cd(host);
1588 sdhci_runtime_pm_put(host);
1589 return ret;
1590}
1591
66fd8ad5 1592static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1593{
d129bceb 1594 unsigned long flags;
2dfb579c 1595 int is_readonly;
d129bceb 1596
d129bceb
PO		 1597 spin_lock_irqsave(&host->lock, flags);
1598
1e72859e 1599 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1600 is_readonly = 0;
1601 else if (host->ops->get_ro)
1602 is_readonly = host->ops->get_ro(host);
1e72859e 1603 else
2dfb579c
WS		 1604 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1605 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1606
1607 spin_unlock_irqrestore(&host->lock, flags);
1608
2dfb579c
WS		 1609 /* This quirk needs to be replaced by a callback-function later */
1610 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1611 !is_readonly : is_readonly;
d129bceb
PO		 1612}
1613
82b0e23a
TI		 1614#define SAMPLE_COUNT 5
1615
66fd8ad5 1616static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1617{
82b0e23a
TI		 1618 int i, ro_count;
1619
82b0e23a 1620 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1621 return sdhci_check_ro(host);
82b0e23a
TI		 1622
1623 ro_count = 0;
1624 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1625 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1626 if (++ro_count > SAMPLE_COUNT / 2)
1627 return 1;
1628 }
1629 msleep(30);
1630 }
1631 return 0;
1632}
1633
20758b66
AH		 1634static void sdhci_hw_reset(struct mmc_host *mmc)
1635{
1636 struct sdhci_host *host = mmc_priv(mmc);
1637
1638 if (host->ops && host->ops->hw_reset)
1639 host->ops->hw_reset(host);
1640}
1641
66fd8ad5 1642static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1643{
66fd8ad5
AH		 1644 struct sdhci_host *host = mmc_priv(mmc);
1645 int ret;
f75979b7 1646
66fd8ad5
AH		 1647 sdhci_runtime_pm_get(host);
1648 ret = sdhci_do_get_ro(host);
1649 sdhci_runtime_pm_put(host);
1650 return ret;
1651}
f75979b7 1652
66fd8ad5
AH		 1653static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1654{
be138554 1655 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1656 if (enable)
b537f94c 1657 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1658 else
b537f94c
RK		 1659 host->ier &= ~SDHCI_INT_CARD_INT;
1660
1661 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1662 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1663 mmiowb();
1664 }
66fd8ad5
AH		 1665}
1666
1667static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1668{
1669 struct sdhci_host *host = mmc_priv(mmc);
1670 unsigned long flags;
f75979b7 1671
ef104333
RK		 1672 sdhci_runtime_pm_get(host);
1673
66fd8ad5 1674 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1675 if (enable)
1676 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1677 else
1678 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1679
66fd8ad5 1680 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1681 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1682
1683 sdhci_runtime_pm_put(host);
f75979b7
PO		 1684}
1685
20b92a30 1686static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1687 struct mmc_ios *ios)
f2119df6 1688{
3a48edc4 1689 struct mmc_host *mmc = host->mmc;
20b92a30 1690 u16 ctrl;
6231f3de 1691 int ret;
f2119df6 1692
20b92a30
KL		 1693 /*
1694 * Signal Voltage Switching is only applicable for Host Controllers
1695 * v3.00 and above.
1696 */
1697 if (host->version < SDHCI_SPEC_300)
1698 return 0;
6231f3de 1699
f2119df6 1700 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1701
21f5998f 1702 switch (ios->signal_voltage) {
20b92a30
KL		 1703 case MMC_SIGNAL_VOLTAGE_330:
1704 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1705 ctrl &= ~SDHCI_CTRL_VDD_180;
1706 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1707
3a48edc4
TK		 1708 if (!IS_ERR(mmc->supply.vqmmc)) {
1709 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1710 3600000);
20b92a30 1711 if (ret) {
6606110d
JP		 1712 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1713 mmc_hostname(mmc));
20b92a30
KL		 1714 return -EIO;
1715 }
1716 }
1717 /* Wait for 5ms */
1718 usleep_range(5000, 5500);
f2119df6 1719
20b92a30
KL		 1720 /* 3.3V regulator output should be stable within 5 ms */
1721 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1722 if (!(ctrl & SDHCI_CTRL_VDD_180))
1723 return 0;
6231f3de 1724
6606110d
JP		 1725 pr_warn("%s: 3.3V regulator output did not became stable\n",
1726 mmc_hostname(mmc));
20b92a30
KL		 1727
1728 return -EAGAIN;
1729 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1730 if (!IS_ERR(mmc->supply.vqmmc)) {
1731 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1732 1700000, 1950000);
1733 if (ret) {
6606110d
JP		 1734 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1735 mmc_hostname(mmc));
20b92a30
KL		 1736 return -EIO;
1737 }
1738 }
6231f3de 1739
6231f3de
PR		 1740 /*
1741 * Enable 1.8V Signal Enable in the Host Control2
1742 * register
1743 */
20b92a30
KL		 1744 ctrl |= SDHCI_CTRL_VDD_180;
1745 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1746
9d967a61
VY		 1747 /* Some controller need to do more when switching */
1748 if (host->ops->voltage_switch)
1749 host->ops->voltage_switch(host);
1750
20b92a30
KL		 1751 /* 1.8V regulator output should be stable within 5 ms */
1752 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1753 if (ctrl & SDHCI_CTRL_VDD_180)
1754 return 0;
f2119df6 1755
6606110d
JP		 1756 pr_warn("%s: 1.8V regulator output did not became stable\n",
1757 mmc_hostname(mmc));
f2119df6 1758
20b92a30
KL		 1759 return -EAGAIN;
1760 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1761 if (!IS_ERR(mmc->supply.vqmmc)) {
1762 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1763 1300000);
20b92a30 1764 if (ret) {
6606110d
JP		 1765 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1766 mmc_hostname(mmc));
20b92a30 1767 return -EIO;
f2119df6
AN		 1768 }
1769 }
6231f3de 1770 return 0;
20b92a30 1771 default:
f2119df6
AN		 1772 /* No signal voltage switch required */
1773 return 0;
20b92a30 1774 }
f2119df6
AN		 1775}
1776
66fd8ad5 1777static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1778 struct mmc_ios *ios)
66fd8ad5
AH		 1779{
1780 struct sdhci_host *host = mmc_priv(mmc);
1781 int err;
1782
1783 if (host->version < SDHCI_SPEC_300)
1784 return 0;
1785 sdhci_runtime_pm_get(host);
21f5998f 1786 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1787 sdhci_runtime_pm_put(host);
1788 return err;
1789}
1790
20b92a30
KL		 1791static int sdhci_card_busy(struct mmc_host *mmc)
1792{
1793 struct sdhci_host *host = mmc_priv(mmc);
1794 u32 present_state;
1795
1796 sdhci_runtime_pm_get(host);
1797 /* Check whether DAT[3:0] is 0000 */
1798 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1799 sdhci_runtime_pm_put(host);
1800
1801 return !(present_state & SDHCI_DATA_LVL_MASK);
1802}
1803
b5540ce1
AH		 1804static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1805{
1806 struct sdhci_host *host = mmc_priv(mmc);
1807 unsigned long flags;
1808
1809 spin_lock_irqsave(&host->lock, flags);
1810 host->flags |= SDHCI_HS400_TUNING;
1811 spin_unlock_irqrestore(&host->lock, flags);
1812
1813 return 0;
1814}
1815
069c9f14 1816static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1817{
4b6f37d3 1818 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1819 u16 ctrl;
b513ea25 1820 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1821 int err = 0;
2b35bd83 1822 unsigned long flags;
38e40bf5 1823 unsigned int tuning_count = 0;
b5540ce1 1824 bool hs400_tuning;
b513ea25 1825
66fd8ad5 1826 sdhci_runtime_pm_get(host);
2b35bd83 1827 spin_lock_irqsave(&host->lock, flags);
b513ea25 1828
b5540ce1
AH		 1829 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1830 host->flags &= ~SDHCI_HS400_TUNING;
1831
38e40bf5
AH		 1832 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1833 tuning_count = host->tuning_count;
1834
b513ea25 1835 /*
9faac7b9
WY		 1836 * The Host Controller needs tuning in case of SDR104 and DDR50
1837 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1838 * the Capabilities register.
069c9f14
G		 1839 * If the Host Controller supports the HS200 mode then the
1840 * tuning function has to be executed.
b513ea25 1841 */
4b6f37d3 1842 switch (host->timing) {
b5540ce1 1843 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1844 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1845 err = -EINVAL;
1846 goto out_unlock;
1847
4b6f37d3 1848 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1849 /*
1850 * Periodic re-tuning for HS400 is not expected to be needed, so
1851 * disable it here.
1852 */
1853 if (hs400_tuning)
1854 tuning_count = 0;
1855 break;
1856
4b6f37d3 1857 case MMC_TIMING_UHS_SDR104:
9faac7b9 1858 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 1859 break;
1860
1861 case MMC_TIMING_UHS_SDR50:
1862 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1863 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1864 break;
1865 /* FALLTHROUGH */
1866
1867 default:
d519c863 1868 goto out_unlock;
b513ea25
AN		 1869 }
1870
45251812 1871 if (host->ops->platform_execute_tuning) {
2b35bd83 1872 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1873 err = host->ops->platform_execute_tuning(host, opcode);
1874 sdhci_runtime_pm_put(host);
1875 return err;
1876 }
1877
4b6f37d3
RK		 1878 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1879 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 1880 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1881 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 1882 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1883
1884 /*
1885 * As per the Host Controller spec v3.00, tuning command
1886 * generates Buffer Read Ready interrupt, so enable that.
1887 *
1888 * Note: The spec clearly says that when tuning sequence
1889 * is being performed, the controller does not generate
1890 * interrupts other than Buffer Read Ready interrupt. But
1891 * to make sure we don't hit a controller bug, we _only_
1892 * enable Buffer Read Ready interrupt here.
1893 */
b537f94c
RK		 1894 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1895 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1896
1897 /*
1898 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1899 * of loops reaches 40 times or a timeout of 150ms occurs.
1900 */
b513ea25
AN		 1901 do {
1902 struct mmc_command cmd = {0};
66fd8ad5 1903 struct mmc_request mrq = {NULL};
b513ea25 1904
069c9f14 1905 cmd.opcode = opcode;
b513ea25
AN		 1906 cmd.arg = 0;
1907 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1908 cmd.retries = 0;
1909 cmd.data = NULL;
1910 cmd.error = 0;
1911
7ce45e95
AC		 1912 if (tuning_loop_counter-- == 0)
1913 break;
1914
b513ea25
AN		 1915 mrq.cmd = &cmd;
1916 host->mrq = &mrq;
1917
1918 /*
1919 * In response to CMD19, the card sends 64 bytes of tuning
1920 * block to the Host Controller. So we set the block size
1921 * to 64 here.
1922 */
069c9f14
G		 1923 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1924 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1925 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1926 SDHCI_BLOCK_SIZE);
1927 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1928 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1929 SDHCI_BLOCK_SIZE);
1930 } else {
1931 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1932 SDHCI_BLOCK_SIZE);
1933 }
b513ea25
AN		 1934
1935 /*
1936 * The tuning block is sent by the card to the host controller.
1937 * So we set the TRNS_READ bit in the Transfer Mode register.
1938 * This also takes care of setting DMA Enable and Multi Block
1939 * Select in the same register to 0.
1940 */
1941 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1942
1943 sdhci_send_command(host, &cmd);
1944
1945 host->cmd = NULL;
1946 host->mrq = NULL;
1947
2b35bd83 1948 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1949 /* Wait for Buffer Read Ready interrupt */
1950 wait_event_interruptible_timeout(host->buf_ready_int,
1951 (host->tuning_done == 1),
1952 msecs_to_jiffies(50));
2b35bd83 1953 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1954
1955 if (!host->tuning_done) {
2e4456f0 1956 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
b513ea25
AN		 1957 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1958 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1959 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1960 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1961
1962 err = -EIO;
1963 goto out;
1964 }
1965
1966 host->tuning_done = 0;
1967
1968 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 1969
1970 /* eMMC spec does not require a delay between tuning cycles */
1971 if (opcode == MMC_SEND_TUNING_BLOCK)
1972 mdelay(1);
b513ea25
AN		 1973 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1974
1975 /*
1976 * The Host Driver has exhausted the maximum number of loops allowed,
1977 * so use fixed sampling frequency.
1978 */
7ce45e95 1979 if (tuning_loop_counter < 0) {
b513ea25
AN		 1980 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1981 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 1982 }
1983 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2e4456f0 1984 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
114f2bf6 1985 err = -EIO;
b513ea25
AN		 1986 }
1987
1988out:
38e40bf5 1989 if (tuning_count) {
66c39dfc
AH		 1990 /*
1991 * In case tuning fails, host controllers which support
1992 * re-tuning can try tuning again at a later time, when the
1993 * re-tuning timer expires. So for these controllers, we
1994 * return 0. Since there might be other controllers who do not
1995 * have this capability, we return error for them.
1996 */
1997 err = 0;
cf2b5eea
AN		 1998 }
1999
66c39dfc 2000 host->mmc->retune_period = err ? 0 : tuning_count;
cf2b5eea 2001
b537f94c
RK		 2002 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2003 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2004out_unlock:
2b35bd83 2005 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2006 sdhci_runtime_pm_put(host);
b513ea25
AN		 2007
2008 return err;
2009}
2010
cb849648
AH		 2011static int sdhci_select_drive_strength(struct mmc_card *card,
2012 unsigned int max_dtr, int host_drv,
2013 int card_drv, int *drv_type)
2014{
2015 struct sdhci_host *host = mmc_priv(card->host);
2016
2017 if (!host->ops->select_drive_strength)
2018 return 0;
2019
2020 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2021 card_drv, drv_type);
2022}
52983382
KL		 2023
2024static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2025{
4d55c5a1
AN		 2026 /* Host Controller v3.00 defines preset value registers */
2027 if (host->version < SDHCI_SPEC_300)
2028 return;
2029
4d55c5a1
AN		 2030 /*
2031 * We only enable or disable Preset Value if they are not already
2032 * enabled or disabled respectively. Otherwise, we bail out.
2033 */
da91a8f9
RK		 2034 if (host->preset_enabled != enable) {
2035 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2036
2037 if (enable)
2038 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2039 else
2040 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2041
4d55c5a1 2042 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2043
2044 if (enable)
2045 host->flags |= SDHCI_PV_ENABLED;
2046 else
2047 host->flags &= ~SDHCI_PV_ENABLED;
2048
2049 host->preset_enabled = enable;
4d55c5a1 2050 }
66fd8ad5
AH		 2051}
2052
348487cb
HC		 2053static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2054 int err)
2055{
2056 struct sdhci_host *host = mmc_priv(mmc);
2057 struct mmc_data *data = mrq->data;
2058
f48f039c 2059 if (data->host_cookie != COOKIE_UNMAPPED)
771a3dc2
RK		 2060 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2061 data->flags & MMC_DATA_WRITE ?
2062 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2063
2064 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2065}
2066
348487cb
HC		 2067static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2068 bool is_first_req)
2069{
2070 struct sdhci_host *host = mmc_priv(mmc);
2071
d31911b9 2072 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2073
2074 if (host->flags & SDHCI_REQ_USE_DMA)
94538e51 2075 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
348487cb
HC		 2076}
2077
71e69211 2078static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2079{
71e69211 2080 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2081 unsigned long flags;
2836766a 2082 int present;
d129bceb 2083
722e1280
CD		 2084 /* First check if client has provided their own card event */
2085 if (host->ops->card_event)
2086 host->ops->card_event(host);
2087
2836766a
KK		 2088 present = sdhci_do_get_cd(host);
2089
d129bceb
PO		 2090 spin_lock_irqsave(&host->lock, flags);
2091
66fd8ad5 2092 /* Check host->mrq first in case we are runtime suspended */
2836766a 2093 if (host->mrq && !present) {
a3c76eb9 2094 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2095 mmc_hostname(host->mmc));
a3c76eb9 2096 pr_err("%s: Resetting controller.\n",
66fd8ad5 2097 mmc_hostname(host->mmc));
d129bceb 2098
03231f9b
RK		 2099 sdhci_do_reset(host, SDHCI_RESET_CMD);
2100 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2101
66fd8ad5
AH		 2102 host->mrq->cmd->error = -ENOMEDIUM;
2103 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2104 }
2105
2106 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2107}
2108
2109static const struct mmc_host_ops sdhci_ops = {
2110 .request = sdhci_request,
348487cb
HC		 2111 .post_req = sdhci_post_req,
2112 .pre_req = sdhci_pre_req,
71e69211 2113 .set_ios = sdhci_set_ios,
94144a46 2114 .get_cd = sdhci_get_cd,
71e69211
GL		 2115 .get_ro = sdhci_get_ro,
2116 .hw_reset = sdhci_hw_reset,
2117 .enable_sdio_irq = sdhci_enable_sdio_irq,
2118 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2119 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2120 .execute_tuning = sdhci_execute_tuning,
cb849648 2121 .select_drive_strength = sdhci_select_drive_strength,
71e69211 2122 .card_event = sdhci_card_event,
20b92a30 2123 .card_busy = sdhci_card_busy,
71e69211
GL		 2124};
2125
2126/*****************************************************************************\
2127 * *
2128 * Tasklets *
2129 * *
2130\*****************************************************************************/
2131
d129bceb
PO		 2132static void sdhci_tasklet_finish(unsigned long param)
2133{
2134 struct sdhci_host *host;
2135 unsigned long flags;
2136 struct mmc_request *mrq;
2137
2138 host = (struct sdhci_host*)param;
2139
66fd8ad5
AH		 2140 spin_lock_irqsave(&host->lock, flags);
2141
0c9c99a7
CB		 2142 /*
2143 * If this tasklet gets rescheduled while running, it will
2144 * be run again afterwards but without any active request.
2145 */
66fd8ad5
AH		 2146 if (!host->mrq) {
2147 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2148 return;
66fd8ad5 2149 }
d129bceb
PO		 2150
2151 del_timer(&host->timer);
2152
2153 mrq = host->mrq;
2154
054cedff
RK		 2155 /*
2156 * Always unmap the data buffers if they were mapped by
2157 * sdhci_prepare_data() whenever we finish with a request.
2158 * This avoids leaking DMA mappings on error.
2159 */
2160 if (host->flags & SDHCI_REQ_USE_DMA) {
2161 struct mmc_data *data = mrq->data;
2162
2163 if (data && data->host_cookie == COOKIE_MAPPED) {
2164 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2165 (data->flags & MMC_DATA_READ) ?
2166 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2167 data->host_cookie = COOKIE_UNMAPPED;
2168 }
2169 }
2170
d129bceb
PO		 2171 /*
2172 * The controller needs a reset of internal state machines
2173 * upon error conditions.
2174 */
1e72859e 2175 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2176 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2177 (mrq->sbc && mrq->sbc->error) ||
2178 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2179 (mrq->data->stop && mrq->data->stop->error))) ||
2180 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2181
2182 /* Some controllers need this kick or reset won't work here */
8213af3b 2183 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2184 /* This is to force an update */
1771059c 2185 host->ops->set_clock(host, host->clock);
645289dc
PO		 2186
2187 /* Spec says we should do both at the same time, but Ricoh
2188 controllers do not like that. */
03231f9b
RK		 2189 sdhci_do_reset(host, SDHCI_RESET_CMD);
2190 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2191 }
2192
2193 host->mrq = NULL;
2194 host->cmd = NULL;
2195 host->data = NULL;
2196
f9134319 2197#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2198 sdhci_deactivate_led(host);
2f730fec 2199#endif
d129bceb 2200
5f25a66f 2201 mmiowb();
d129bceb
PO		 2202 spin_unlock_irqrestore(&host->lock, flags);
2203
2204 mmc_request_done(host->mmc, mrq);
66fd8ad5 2205 sdhci_runtime_pm_put(host);
d129bceb
PO		 2206}
2207
2208static void sdhci_timeout_timer(unsigned long data)
2209{
2210 struct sdhci_host *host;
2211 unsigned long flags;
2212
2213 host = (struct sdhci_host*)data;
2214
2215 spin_lock_irqsave(&host->lock, flags);
2216
2217 if (host->mrq) {
2e4456f0
MV		 2218 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2219 mmc_hostname(host->mmc));
d129bceb
PO		 2220 sdhci_dumpregs(host);
2221
2222 if (host->data) {
17b0429d 2223 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2224 sdhci_finish_data(host);
2225 } else {
2226 if (host->cmd)
17b0429d 2227 host->cmd->error = -ETIMEDOUT;
d129bceb 2228 else
17b0429d 2229 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2230
2231 tasklet_schedule(&host->finish_tasklet);
2232 }
2233 }
2234
5f25a66f 2235 mmiowb();
d129bceb
PO		 2236 spin_unlock_irqrestore(&host->lock, flags);
2237}
2238
2239/*****************************************************************************\
2240 * *
2241 * Interrupt handling *
2242 * *
2243\*****************************************************************************/
2244
61541397 2245static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb
PO		 2246{
2247 BUG_ON(intmask == 0);
2248
2249 if (!host->cmd) {
2e4456f0
MV		 2250 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2251 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2252 sdhci_dumpregs(host);
2253 return;
2254 }
2255
ec014cba
RK		 2256 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2257 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2258 if (intmask & SDHCI_INT_TIMEOUT)
2259 host->cmd->error = -ETIMEDOUT;
2260 else
2261 host->cmd->error = -EILSEQ;
43b58b36 2262
71fcbda0
RK		 2263 /*
2264 * If this command initiates a data phase and a response
2265 * CRC error is signalled, the card can start transferring
2266 * data - the card may have received the command without
2267 * error. We must not terminate the mmc_request early.
2268 *
2269 * If the card did not receive the command or returned an
2270 * error which prevented it sending data, the data phase
2271 * will time out.
2272 */
2273 if (host->cmd->data &&
2274 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2275 SDHCI_INT_CRC) {
2276 host->cmd = NULL;
2277 return;
2278 }
2279
d129bceb 2280 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2281 return;
2282 }
2283
2284 /*
2285 * The host can send and interrupt when the busy state has
2286 * ended, allowing us to wait without wasting CPU cycles.
2287 * Unfortunately this is overloaded on the "data complete"
2288 * interrupt, so we need to take some care when handling
2289 * it.
2290 *
2291 * Note: The 1.0 specification is a bit ambiguous about this
2292 * feature so there might be some problems with older
2293 * controllers.
2294 */
2295 if (host->cmd->flags & MMC_RSP_BUSY) {
2296 if (host->cmd->data)
2e4456f0 2297 DBG("Cannot wait for busy signal when also doing a data transfer");
e99783a4
CM		 2298 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2299 && !host->busy_handle) {
2300 /* Mark that command complete before busy is ended */
2301 host->busy_handle = 1;
e809517f 2302 return;
e99783a4 2303 }
f945405c
BD		 2304
2305 /* The controller does not support the end-of-busy IRQ,
2306 * fall through and take the SDHCI_INT_RESPONSE */
61541397
AH		 2307 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2308 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2309 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2310 }
2311
2312 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2313 sdhci_finish_command(host);
d129bceb
PO		 2314}
2315
0957c333 2316#ifdef CONFIG_MMC_DEBUG
08621b18 2317static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2318{
2319 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2320 void *desc = host->adma_table;
6882a8c0
BD		 2321
2322 sdhci_dumpregs(host);
2323
2324 while (true) {
e57a5f61
AH		 2325 struct sdhci_adma2_64_desc *dma_desc = desc;
2326
2327 if (host->flags & SDHCI_USE_64_BIT_DMA)
2328 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2329 name, desc, le32_to_cpu(dma_desc->addr_hi),
2330 le32_to_cpu(dma_desc->addr_lo),
2331 le16_to_cpu(dma_desc->len),
2332 le16_to_cpu(dma_desc->cmd));
2333 else
2334 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2335 name, desc, le32_to_cpu(dma_desc->addr_lo),
2336 le16_to_cpu(dma_desc->len),
2337 le16_to_cpu(dma_desc->cmd));
6882a8c0 2338
76fe379a 2339 desc += host->desc_sz;
6882a8c0 2340
0545230f 2341 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2342 break;
2343 }
2344}
2345#else
08621b18 2346static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2347#endif
2348
d129bceb
PO		 2349static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2350{
069c9f14 2351 u32 command;
d129bceb
PO		 2352 BUG_ON(intmask == 0);
2353
b513ea25
AN		 2354 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2355 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2356 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2357 if (command == MMC_SEND_TUNING_BLOCK ||
2358 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2359 host->tuning_done = 1;
2360 wake_up(&host->buf_ready_int);
2361 return;
2362 }
2363 }
2364
d129bceb
PO		 2365 if (!host->data) {
2366 /*
e809517f
PO		 2367 * The "data complete" interrupt is also used to
2368 * indicate that a busy state has ended. See comment
2369 * above in sdhci_cmd_irq().
d129bceb 2370 */
e809517f 2371 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2372 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2373 host->cmd->error = -ETIMEDOUT;
2374 tasklet_schedule(&host->finish_tasklet);
2375 return;
2376 }
e809517f 2377 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2378 /*
2379 * Some cards handle busy-end interrupt
2380 * before the command completed, so make
2381 * sure we do things in the proper order.
2382 */
2383 if (host->busy_handle)
2384 sdhci_finish_command(host);
2385 else
2386 host->busy_handle = 1;
e809517f
PO		 2387 return;
2388 }
2389 }
d129bceb 2390
2e4456f0
MV		 2391 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2392 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2393 sdhci_dumpregs(host);
2394
2395 return;
2396 }
2397
2398 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2399 host->data->error = -ETIMEDOUT;
22113efd
AL		 2400 else if (intmask & SDHCI_INT_DATA_END_BIT)
2401 host->data->error = -EILSEQ;
2402 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2403 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2404 != MMC_BUS_TEST_R)
17b0429d 2405 host->data->error = -EILSEQ;
6882a8c0 2406 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2407 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2408 sdhci_adma_show_error(host);
2134a922 2409 host->data->error = -EIO;
a4071fbb
HZ		 2410 if (host->ops->adma_workaround)
2411 host->ops->adma_workaround(host, intmask);
6882a8c0 2412 }
d129bceb 2413
17b0429d 2414 if (host->data->error)
d129bceb
PO		 2415 sdhci_finish_data(host);
2416 else {
a406f5a3 2417 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2418 sdhci_transfer_pio(host);
2419
6ba736a1
PO		 2420 /*
2421 * We currently don't do anything fancy with DMA
2422 * boundaries, but as we can't disable the feature
2423 * we need to at least restart the transfer.
f6a03cbf
MV		 2424 *
2425 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2426 * should return a valid address to continue from, but as
2427 * some controllers are faulty, don't trust them.
6ba736a1 2428 */
f6a03cbf
MV		 2429 if (intmask & SDHCI_INT_DMA_END) {
2430 u32 dmastart, dmanow;
2431 dmastart = sg_dma_address(host->data->sg);
2432 dmanow = dmastart + host->data->bytes_xfered;
2433 /*
2434 * Force update to the next DMA block boundary.
2435 */
2436 dmanow = (dmanow &
2437 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2438 SDHCI_DEFAULT_BOUNDARY_SIZE;
2439 host->data->bytes_xfered = dmanow - dmastart;
2440 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2441 " next 0x%08x\n",
2442 mmc_hostname(host->mmc), dmastart,
2443 host->data->bytes_xfered, dmanow);
2444 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2445 }
6ba736a1 2446
e538fbe8
PO		 2447 if (intmask & SDHCI_INT_DATA_END) {
2448 if (host->cmd) {
2449 /*
2450 * Data managed to finish before the
2451 * command completed. Make sure we do
2452 * things in the proper order.
2453 */
2454 host->data_early = 1;
2455 } else {
2456 sdhci_finish_data(host);
2457 }
2458 }
d129bceb
PO		 2459 }
2460}
2461
7d12e780 2462static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2463{
781e989c 2464 irqreturn_t result = IRQ_NONE;
66fd8ad5 2465 struct sdhci_host *host = dev_id;
41005003 2466 u32 intmask, mask, unexpected = 0;
781e989c 2467 int max_loops = 16;
d129bceb
PO		 2468
2469 spin_lock(&host->lock);
2470
be138554 2471 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2472 spin_unlock(&host->lock);
655bca76 2473 return IRQ_NONE;
66fd8ad5
AH		 2474 }
2475
4e4141a5 2476 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2477 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2478 result = IRQ_NONE;
2479 goto out;
2480 }
2481
41005003
RK		 2482 do {
2483 /* Clear selected interrupts. */
2484 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2485 SDHCI_INT_BUS_POWER);
2486 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2487
41005003
RK		 2488 DBG("*** %s got interrupt: 0x%08x\n",
2489 mmc_hostname(host->mmc), intmask);
d129bceb 2490
41005003
RK		 2491 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2492 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2493 SDHCI_CARD_PRESENT;
d129bceb 2494
41005003
RK		 2495 /*
2496 * There is a observation on i.mx esdhc. INSERT
2497 * bit will be immediately set again when it gets
2498 * cleared, if a card is inserted. We have to mask
2499 * the irq to prevent interrupt storm which will
2500 * freeze the system. And the REMOVE gets the
2501 * same situation.
2502 *
2503 * More testing are needed here to ensure it works
2504 * for other platforms though.
2505 */
b537f94c
RK		 2506 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2507 SDHCI_INT_CARD_REMOVE);
2508 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2509 SDHCI_INT_CARD_INSERT;
2510 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2511 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2512
2513 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2514 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2515
2516 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2517 SDHCI_INT_CARD_REMOVE);
2518 result = IRQ_WAKE_THREAD;
41005003 2519 }
d129bceb 2520
41005003 2521 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2522 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2523 &intmask);
964f9ce2 2524
41005003
RK		 2525 if (intmask & SDHCI_INT_DATA_MASK)
2526 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2527
41005003
RK		 2528 if (intmask & SDHCI_INT_BUS_POWER)
2529 pr_err("%s: Card is consuming too much power!\n",
2530 mmc_hostname(host->mmc));
3192a28f 2531
781e989c
RK		 2532 if (intmask & SDHCI_INT_CARD_INT) {
2533 sdhci_enable_sdio_irq_nolock(host, false);
2534 host->thread_isr |= SDHCI_INT_CARD_INT;
2535 result = IRQ_WAKE_THREAD;
2536 }
f75979b7 2537
41005003
RK		 2538 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2539 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2540 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2541 SDHCI_INT_CARD_INT);
f75979b7 2542
41005003
RK		 2543 if (intmask) {
2544 unexpected |= intmask;
2545 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2546 }
d129bceb 2547
781e989c
RK		 2548 if (result == IRQ_NONE)
2549 result = IRQ_HANDLED;
d129bceb 2550
41005003 2551 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2552 } while (intmask && --max_loops);
d129bceb
PO		 2553out:
2554 spin_unlock(&host->lock);
2555
6379b237
AS		 2556 if (unexpected) {
2557 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2558 mmc_hostname(host->mmc), unexpected);
2559 sdhci_dumpregs(host);
2560 }
f75979b7 2561
d129bceb
PO		 2562 return result;
2563}
2564
781e989c
RK		 2565static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2566{
2567 struct sdhci_host *host = dev_id;
2568 unsigned long flags;
2569 u32 isr;
2570
2571 spin_lock_irqsave(&host->lock, flags);
2572 isr = host->thread_isr;
2573 host->thread_isr = 0;
2574 spin_unlock_irqrestore(&host->lock, flags);
2575
3560db8e
RK		 2576 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2577 sdhci_card_event(host->mmc);
2578 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2579 }
2580
781e989c
RK		 2581 if (isr & SDHCI_INT_CARD_INT) {
2582 sdio_run_irqs(host->mmc);
2583
2584 spin_lock_irqsave(&host->lock, flags);
2585 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2586 sdhci_enable_sdio_irq_nolock(host, true);
2587 spin_unlock_irqrestore(&host->lock, flags);
2588 }
2589
2590 return isr ? IRQ_HANDLED : IRQ_NONE;
2591}
2592
d129bceb
PO		 2593/*****************************************************************************\
2594 * *
2595 * Suspend/resume *
2596 * *
2597\*****************************************************************************/
2598
2599#ifdef CONFIG_PM
ad080d79
KL		 2600void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2601{
2602 u8 val;
2603 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2604 | SDHCI_WAKE_ON_INT;
2605
2606 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2607 val |= mask ;
2608 /* Avoid fake wake up */
2609 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2610 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2611 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2612}
2613EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2614
0b10f478 2615static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2616{
2617 u8 val;
2618 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2619 | SDHCI_WAKE_ON_INT;
2620
2621 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2622 val &= ~mask;
2623 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2624}
d129bceb 2625
29495aa0 2626int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2627{
7260cf5e
AV		 2628 sdhci_disable_card_detection(host);
2629
66c39dfc
AH		 2630 mmc_retune_timer_stop(host->mmc);
2631 mmc_retune_needed(host->mmc);
cf2b5eea 2632
ad080d79 2633 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2634 host->ier = 0;
2635 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2636 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2637 free_irq(host->irq, host);
2638 } else {
2639 sdhci_enable_irq_wakeups(host);
2640 enable_irq_wake(host->irq);
2641 }
4ee14ec6 2642 return 0;
d129bceb
PO		 2643}
2644
b8c86fc5 2645EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2646
b8c86fc5
PO		 2647int sdhci_resume_host(struct sdhci_host *host)
2648{
4ee14ec6 2649 int ret = 0;
d129bceb 2650
a13abc7b 2651 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2652 if (host->ops->enable_dma)
2653 host->ops->enable_dma(host);
2654 }
d129bceb 2655
6308d290
AH		 2656 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2657 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2658 /* Card keeps power but host controller does not */
2659 sdhci_init(host, 0);
2660 host->pwr = 0;
2661 host->clock = 0;
2662 sdhci_do_set_ios(host, &host->mmc->ios);
2663 } else {
2664 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2665 mmiowb();
2666 }
b8c86fc5 2667
14a7b416
HC		 2668 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2669 ret = request_threaded_irq(host->irq, sdhci_irq,
2670 sdhci_thread_irq, IRQF_SHARED,
2671 mmc_hostname(host->mmc), host);
2672 if (ret)
2673 return ret;
2674 } else {
2675 sdhci_disable_irq_wakeups(host);
2676 disable_irq_wake(host->irq);
2677 }
2678
7260cf5e
AV		 2679 sdhci_enable_card_detection(host);
2680
2f4cbb3d 2681 return ret;
d129bceb
PO		 2682}
2683
b8c86fc5 2684EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5
AH		 2685
2686static int sdhci_runtime_pm_get(struct sdhci_host *host)
2687{
2688 return pm_runtime_get_sync(host->mmc->parent);
2689}
2690
2691static int sdhci_runtime_pm_put(struct sdhci_host *host)
2692{
2693 pm_runtime_mark_last_busy(host->mmc->parent);
2694 return pm_runtime_put_autosuspend(host->mmc->parent);
2695}
2696
f0710a55
AH		 2697static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2698{
5c671c41 2699 if (host->bus_on)
f0710a55
AH		 2700 return;
2701 host->bus_on = true;
2702 pm_runtime_get_noresume(host->mmc->parent);
2703}
2704
2705static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2706{
5c671c41 2707 if (!host->bus_on)
f0710a55
AH		 2708 return;
2709 host->bus_on = false;
2710 pm_runtime_put_noidle(host->mmc->parent);
2711}
2712
66fd8ad5
AH		 2713int sdhci_runtime_suspend_host(struct sdhci_host *host)
2714{
2715 unsigned long flags;
66fd8ad5 2716
66c39dfc
AH		 2717 mmc_retune_timer_stop(host->mmc);
2718 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2719
2720 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2721 host->ier &= SDHCI_INT_CARD_INT;
2722 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2723 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2724 spin_unlock_irqrestore(&host->lock, flags);
2725
781e989c 2726 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2727
2728 spin_lock_irqsave(&host->lock, flags);
2729 host->runtime_suspended = true;
2730 spin_unlock_irqrestore(&host->lock, flags);
2731
8a125bad 2732 return 0;
66fd8ad5
AH		 2733}
2734EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2735
2736int sdhci_runtime_resume_host(struct sdhci_host *host)
2737{
2738 unsigned long flags;
8a125bad 2739 int host_flags = host->flags;
66fd8ad5
AH		 2740
2741 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2742 if (host->ops->enable_dma)
2743 host->ops->enable_dma(host);
2744 }
2745
2746 sdhci_init(host, 0);
2747
2748 /* Force clock and power re-program */
2749 host->pwr = 0;
2750 host->clock = 0;
3396e736 2751 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
66fd8ad5
AH		 2752 sdhci_do_set_ios(host, &host->mmc->ios);
2753
52983382
KL		 2754 if ((host_flags & SDHCI_PV_ENABLED) &&
2755 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2756 spin_lock_irqsave(&host->lock, flags);
2757 sdhci_enable_preset_value(host, true);
2758 spin_unlock_irqrestore(&host->lock, flags);
2759 }
66fd8ad5 2760
66fd8ad5
AH		 2761 spin_lock_irqsave(&host->lock, flags);
2762
2763 host->runtime_suspended = false;
2764
2765 /* Enable SDIO IRQ */
ef104333 2766 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2767 sdhci_enable_sdio_irq_nolock(host, true);
2768
2769 /* Enable Card Detection */
2770 sdhci_enable_card_detection(host);
2771
2772 spin_unlock_irqrestore(&host->lock, flags);
2773
8a125bad 2774 return 0;
66fd8ad5
AH		 2775}
2776EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2777
162d6f98 2778#endif /* CONFIG_PM */
66fd8ad5 2779
d129bceb
PO		 2780/*****************************************************************************\
2781 * *
b8c86fc5 2782 * Device allocation/registration *
d129bceb
PO		 2783 * *
2784\*****************************************************************************/
2785
b8c86fc5
PO		 2786struct sdhci_host *sdhci_alloc_host(struct device *dev,
2787 size_t priv_size)
d129bceb 2788{
d129bceb
PO		 2789 struct mmc_host *mmc;
2790 struct sdhci_host *host;
2791
b8c86fc5 2792 WARN_ON(dev == NULL);
d129bceb 2793
b8c86fc5 2794 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2795 if (!mmc)
b8c86fc5 2796 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2797
2798 host = mmc_priv(mmc);
2799 host->mmc = mmc;
bf60e592
AH		 2800 host->mmc_host_ops = sdhci_ops;
2801 mmc->ops = &host->mmc_host_ops;
d129bceb 2802
b8c86fc5
PO		 2803 return host;
2804}
8a4da143 2805
b8c86fc5 2806EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2807
b8c86fc5
PO		 2808int sdhci_add_host(struct sdhci_host *host)
2809{
2810 struct mmc_host *mmc;
bd6a8c30 2811 u32 caps[2] = {0, 0};
f2119df6
AN		 2812 u32 max_current_caps;
2813 unsigned int ocr_avail;
f5fa92e5 2814 unsigned int override_timeout_clk;
59241757 2815 u32 max_clk;
b8c86fc5 2816 int ret;
d129bceb 2817
b8c86fc5
PO		 2818 WARN_ON(host == NULL);
2819 if (host == NULL)
2820 return -EINVAL;
d129bceb 2821
b8c86fc5 2822 mmc = host->mmc;
d129bceb 2823
b8c86fc5
PO		 2824 if (debug_quirks)
2825 host->quirks = debug_quirks;
66fd8ad5
AH		 2826 if (debug_quirks2)
2827 host->quirks2 = debug_quirks2;
d129bceb 2828
f5fa92e5
AH		 2829 override_timeout_clk = host->timeout_clk;
2830
03231f9b 2831 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2832
4e4141a5 2833 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2834 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2835 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2836 if (host->version > SDHCI_SPEC_300) {
2e4456f0
MV		 2837 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2838 mmc_hostname(mmc), host->version);
4a965505
PO		 2839 }
2840
f2119df6 2841 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2842 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2843
bd6a8c30
PR		 2844 if (host->version >= SDHCI_SPEC_300)
2845 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2846 host->caps1 :
2847 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2848
b8c86fc5 2849 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2850 host->flags |= SDHCI_USE_SDMA;
f2119df6 2851 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2852 DBG("Controller doesn't have SDMA capability\n");
67435274 2853 else
a13abc7b 2854 host->flags |= SDHCI_USE_SDMA;
d129bceb 2855
b8c86fc5 2856 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2857 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2858 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2859 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2860 }
2861
f2119df6
AN		 2862 if ((host->version >= SDHCI_SPEC_200) &&
2863 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2864 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2865
2866 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2867 (host->flags & SDHCI_USE_ADMA)) {
2868 DBG("Disabling ADMA as it is marked broken\n");
2869 host->flags &= ~SDHCI_USE_ADMA;
2870 }
2871
e57a5f61
AH		 2872 /*
2873 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2874 * and *must* do 64-bit DMA. A driver has the opportunity to change
2875 * that during the first call to ->enable_dma(). Similarly
2876 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2877 * implement.
2878 */
5eaa7476 2879 if (caps[0] & SDHCI_CAN_64BIT)
e57a5f61
AH		 2880 host->flags |= SDHCI_USE_64_BIT_DMA;
2881
a13abc7b 2882 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2883 if (host->ops->enable_dma) {
2884 if (host->ops->enable_dma(host)) {
6606110d 2885 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
b8c86fc5 2886 mmc_hostname(mmc));
a13abc7b
RR		 2887 host->flags &=
2888 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2889 }
d129bceb
PO		 2890 }
2891 }
2892
e57a5f61
AH		 2893 /* SDMA does not support 64-bit DMA */
2894 if (host->flags & SDHCI_USE_64_BIT_DMA)
2895 host->flags &= ~SDHCI_USE_SDMA;
2896
2134a922 2897 if (host->flags & SDHCI_USE_ADMA) {
e66e61cb
RK		 2898 dma_addr_t dma;
2899 void *buf;
2900
2134a922 2901 /*
76fe379a
AH		 2902 * The DMA descriptor table size is calculated as the maximum
2903 * number of segments times 2, to allow for an alignment
2904 * descriptor for each segment, plus 1 for a nop end descriptor,
2905 * all multipled by the descriptor size.
2134a922 2906 */
e57a5f61
AH		 2907 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2908 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2909 SDHCI_ADMA2_64_DESC_SZ;
e57a5f61 2910 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
e57a5f61
AH		 2911 } else {
2912 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2913 SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2914 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2915 }
e66e61cb 2916
04a5ae6f 2917 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
e66e61cb
RK		 2918 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
2919 host->adma_table_sz, &dma, GFP_KERNEL);
2920 if (!buf) {
6606110d 2921 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 2922 mmc_hostname(mmc));
2923 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 2924 } else if ((dma + host->align_buffer_sz) &
2925 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 2926 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2927 mmc_hostname(mmc));
d1e49f77 2928 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 2929 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
2930 host->adma_table_sz, buf, dma);
2931 } else {
2932 host->align_buffer = buf;
2933 host->align_addr = dma;
edd63fcc 2934
e66e61cb
RK		 2935 host->adma_table = buf + host->align_buffer_sz;
2936 host->adma_addr = dma + host->align_buffer_sz;
2937 }
2134a922
PO		 2938 }
2939
7659150c
PO		 2940 /*
2941 * If we use DMA, then it's up to the caller to set the DMA
2942 * mask, but PIO does not need the hw shim so we set a new
2943 * mask here in that case.
2944 */
a13abc7b 2945 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 2946 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 2947 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 2948 }
d129bceb 2949
c4687d5f 2950 if (host->version >= SDHCI_SPEC_300)
f2119df6 2951 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2952 >> SDHCI_CLOCK_BASE_SHIFT;
2953 else
f2119df6 2954 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2955 >> SDHCI_CLOCK_BASE_SHIFT;
2956
4240ff0a 2957 host->max_clk *= 1000000;
f27f47ef
AV		 2958 if (host->max_clk == 0 || host->quirks &
2959 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2960 if (!host->ops->get_max_clock) {
2e4456f0
MV		 2961 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
2962 mmc_hostname(mmc));
4240ff0a
BD		 2963 return -ENODEV;
2964 }
2965 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2966 }
d129bceb 2967
c3ed3877
AN		 2968 /*
2969 * In case of Host Controller v3.00, find out whether clock
2970 * multiplier is supported.
2971 */
2972 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2973 SDHCI_CLOCK_MUL_SHIFT;
2974
2975 /*
2976 * In case the value in Clock Multiplier is 0, then programmable
2977 * clock mode is not supported, otherwise the actual clock
2978 * multiplier is one more than the value of Clock Multiplier
2979 * in the Capabilities Register.
2980 */
2981 if (host->clk_mul)
2982 host->clk_mul += 1;
2983
d129bceb
PO		 2984 /*
2985 * Set host parameters.
2986 */
59241757
DA		 2987 max_clk = host->max_clk;
2988
ce5f036b 2989 if (host->ops->get_min_clock)
a9e58f25 2990 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2991 else if (host->version >= SDHCI_SPEC_300) {
2992 if (host->clk_mul) {
2993 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 2994 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 2995 } else
2996 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2997 } else
0397526d 2998 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2999
59241757
DA		 3000 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3001 mmc->f_max = max_clk;
3002
28aab053
AD		 3003 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3004 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3005 SDHCI_TIMEOUT_CLK_SHIFT;
3006 if (host->timeout_clk == 0) {
3007 if (host->ops->get_timeout_clock) {
3008 host->timeout_clk =
3009 host->ops->get_timeout_clock(host);
3010 } else {
3011 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3012 mmc_hostname(mmc));
3013 return -ENODEV;
3014 }
272308ca 3015 }
272308ca 3016
28aab053
AD		 3017 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3018 host->timeout_clk *= 1000;
272308ca 3019
28aab053 3020 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3021 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3022 mmc->max_busy_timeout /= host->timeout_clk;
3023 }
58d1246d 3024
f5fa92e5
AH		 3025 if (override_timeout_clk)
3026 host->timeout_clk = override_timeout_clk;
3027
e89d456f 3028 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3029 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3030
3031 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3032 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3033
8edf6371 3034 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3035 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3036 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3037 !(host->flags & SDHCI_USE_SDMA)) &&
3038 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3039 host->flags |= SDHCI_AUTO_CMD23;
3040 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3041 } else {
3042 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3043 }
3044
15ec4461
PR		 3045 /*
3046 * A controller may support 8-bit width, but the board itself
3047 * might not have the pins brought out. Boards that support
3048 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3049 * their platform code before calling sdhci_add_host(), and we
3050 * won't assume 8-bit width for hosts without that CAP.
3051 */
5fe23c7f 3052 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3053 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3054
63ef5d8c
JH		 3055 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3056 mmc->caps &= ~MMC_CAP_CMD23;
3057
f2119df6 3058 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 3059 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3060
176d1ed4 3061 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
c31d22eb
II		 3062 !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3063 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
68d1fb7e
AV		 3064 mmc->caps |= MMC_CAP_NEEDS_POLL;
3065
3a48edc4
TK		 3066 /* If there are external regulators, get them */
3067 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3068 return -EPROBE_DEFER;
3069
6231f3de 3070 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3071 if (!IS_ERR(mmc->supply.vqmmc)) {
3072 ret = regulator_enable(mmc->supply.vqmmc);
3073 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3074 1950000))
8363c374
KL		 3075 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3076 SDHCI_SUPPORT_SDR50 |
3077 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3078 if (ret) {
3079 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3080 mmc_hostname(mmc), ret);
4bb74313 3081 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3082 }
8363c374 3083 }
6231f3de 3084
6a66180a
DD		 3085 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3086 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3087 SDHCI_SUPPORT_DDR50);
3088
4188bba0
AC		 3089 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3090 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3091 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3092 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3093
3094 /* SDR104 supports also implies SDR50 support */
156e14b1 3095 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3096 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3097 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3098 * field can be promoted to support HS200.
3099 */
549c0b18 3100 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3101 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3102 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3103 mmc->caps |= MMC_CAP_UHS_SDR50;
3104
e9fb05d5
AH		 3105 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3106 (caps[1] & SDHCI_SUPPORT_HS400))
3107 mmc->caps2 |= MMC_CAP2_HS400;
3108
549c0b18
AH		 3109 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3110 (IS_ERR(mmc->supply.vqmmc) ||
3111 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3112 1300000)))
3113 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3114
9107ebbf
MC		 3115 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3116 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3117 mmc->caps |= MMC_CAP_UHS_DDR50;
3118
069c9f14 3119 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3120 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3121 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3122
156e14b1 3123 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3124 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3125 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3126
d6d50a15
AN		 3127 /* Driver Type(s) (A, C, D) supported by the host */
3128 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3129 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3130 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3131 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3132 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3133 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3134
cf2b5eea
AN		 3135 /* Initial value for re-tuning timer count */
3136 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3137 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3138
3139 /*
3140 * In case Re-tuning Timer is not disabled, the actual value of
3141 * re-tuning timer will be 2 ^ (n - 1).
3142 */
3143 if (host->tuning_count)
3144 host->tuning_count = 1 << (host->tuning_count - 1);
3145
3146 /* Re-tuning mode supported by the Host Controller */
3147 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3148 SDHCI_RETUNING_MODE_SHIFT;
3149
8f230f45 3150 ocr_avail = 0;
bad37e1a 3151
f2119df6
AN		 3152 /*
3153 * According to SD Host Controller spec v3.00, if the Host System
3154 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3155 * the value is meaningful only if Voltage Support in the Capabilities
3156 * register is set. The actual current value is 4 times the register
3157 * value.
3158 */
3159 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3160 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3161 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3162 if (curr > 0) {
3163
3164 /* convert to SDHCI_MAX_CURRENT format */
3165 curr = curr/1000; /* convert to mA */
3166 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3167
3168 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3169 max_current_caps =
3170 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3171 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3172 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3173 }
3174 }
f2119df6
AN		 3175
3176 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3177 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3178
55c4665e 3179 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3180 SDHCI_MAX_CURRENT_330_MASK) >>
3181 SDHCI_MAX_CURRENT_330_SHIFT) *
3182 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3183 }
3184 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3185 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3186
55c4665e 3187 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3188 SDHCI_MAX_CURRENT_300_MASK) >>
3189 SDHCI_MAX_CURRENT_300_SHIFT) *
3190 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3191 }
3192 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3193 ocr_avail |= MMC_VDD_165_195;
3194
55c4665e 3195 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3196 SDHCI_MAX_CURRENT_180_MASK) >>
3197 SDHCI_MAX_CURRENT_180_SHIFT) *
3198 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3199 }
3200
5fd26c7e
UH		 3201 /* If OCR set by host, use it instead. */
3202 if (host->ocr_mask)
3203 ocr_avail = host->ocr_mask;
3204
3205 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3206 if (mmc->ocr_avail)
52221610 3207 ocr_avail = mmc->ocr_avail;
3a48edc4 3208
8f230f45
TI		 3209 mmc->ocr_avail = ocr_avail;
3210 mmc->ocr_avail_sdio = ocr_avail;
3211 if (host->ocr_avail_sdio)
3212 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3213 mmc->ocr_avail_sd = ocr_avail;
3214 if (host->ocr_avail_sd)
3215 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3216 else /* normal SD controllers don't support 1.8V */
3217 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3218 mmc->ocr_avail_mmc = ocr_avail;
3219 if (host->ocr_avail_mmc)
3220 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3221
3222 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 3223 pr_err("%s: Hardware doesn't report any support voltages.\n",
3224 mmc_hostname(mmc));
b8c86fc5 3225 return -ENODEV;
146ad66e
PO		 3226 }
3227
d129bceb
PO		 3228 spin_lock_init(&host->lock);
3229
3230 /*
2134a922
PO		 3231 * Maximum number of segments. Depends on if the hardware
3232 * can do scatter/gather or not.
d129bceb 3233 */
2134a922 3234 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3235 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3236 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3237 mmc->max_segs = 1;
2134a922 3238 else /* PIO */
4fb213f8 3239 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3240
3241 /*
ac00531d
AH		 3242 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3243 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3244 * is less anyway.
d129bceb 3245 */
55db890a 3246 mmc->max_req_size = 524288;
d129bceb
PO		 3247
3248 /*
3249 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3250 * of bytes. When doing hardware scatter/gather, each entry cannot
3251 * be larger than 64 KiB though.
d129bceb 3252 */
30652aa3
OJ		 3253 if (host->flags & SDHCI_USE_ADMA) {
3254 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3255 mmc->max_seg_size = 65535;
3256 else
3257 mmc->max_seg_size = 65536;
3258 } else {
2134a922 3259 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3260 }
d129bceb 3261
fe4a3c7a
PO		 3262 /*
3263 * Maximum block size. This varies from controller to controller and
3264 * is specified in the capabilities register.
3265 */
0633f654
AV		 3266 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3267 mmc->max_blk_size = 2;
3268 } else {
f2119df6 3269 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3270 SDHCI_MAX_BLOCK_SHIFT;
3271 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3272 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3273 mmc_hostname(mmc));
0633f654
AV		 3274 mmc->max_blk_size = 0;
3275 }
3276 }
3277
3278 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3279
55db890a
PO		 3280 /*
3281 * Maximum block count.
3282 */
1388eefd 3283 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3284
d129bceb
PO		 3285 /*
3286 * Init tasklets.
3287 */
d129bceb
PO		 3288 tasklet_init(&host->finish_tasklet,
3289 sdhci_tasklet_finish, (unsigned long)host);
3290
e4cad1b5 3291 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3292
250fb7b4 3293 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3294
2af502ca
SG		 3295 sdhci_init(host, 0);
3296
781e989c
RK		 3297 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3298 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3299 if (ret) {
3300 pr_err("%s: Failed to request IRQ %d: %d\n",
3301 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3302 goto untasklet;
0fc81ee3 3303 }
d129bceb 3304
d129bceb
PO		 3305#ifdef CONFIG_MMC_DEBUG
3306 sdhci_dumpregs(host);
3307#endif
3308
f9134319 3309#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3310 snprintf(host->led_name, sizeof(host->led_name),
3311 "%s::", mmc_hostname(mmc));
3312 host->led.name = host->led_name;
2f730fec
PO		 3313 host->led.brightness = LED_OFF;
3314 host->led.default_trigger = mmc_hostname(mmc);
3315 host->led.brightness_set = sdhci_led_control;
3316
b8c86fc5 3317 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3318 if (ret) {
3319 pr_err("%s: Failed to register LED device: %d\n",
3320 mmc_hostname(mmc), ret);
2f730fec 3321 goto reset;
0fc81ee3 3322 }
2f730fec
PO		 3323#endif
3324
5f25a66f
PO		 3325 mmiowb();
3326
d129bceb
PO		 3327 mmc_add_host(mmc);
3328
a3c76eb9 3329 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3330 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3331 (host->flags & SDHCI_USE_ADMA) ?
3332 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3333 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3334
7260cf5e
AV		 3335 sdhci_enable_card_detection(host);
3336
d129bceb
PO		 3337 return 0;
3338
f9134319 3339#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3340reset:
03231f9b 3341 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3342 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3343 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3344 free_irq(host->irq, host);
3345#endif
8ef1a143 3346untasklet:
d129bceb 3347 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3348
3349 return ret;
3350}
3351
b8c86fc5 3352EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3353
1e72859e 3354void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3355{
3a48edc4 3356 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3357 unsigned long flags;
3358
3359 if (dead) {
3360 spin_lock_irqsave(&host->lock, flags);
3361
3362 host->flags |= SDHCI_DEVICE_DEAD;
3363
3364 if (host->mrq) {
a3c76eb9 3365 pr_err("%s: Controller removed during "
4e743f1f 3366 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3367
3368 host->mrq->cmd->error = -ENOMEDIUM;
3369 tasklet_schedule(&host->finish_tasklet);
3370 }
3371
3372 spin_unlock_irqrestore(&host->lock, flags);
3373 }
3374
7260cf5e
AV		 3375 sdhci_disable_card_detection(host);
3376
4e743f1f 3377 mmc_remove_host(mmc);
d129bceb 3378
f9134319 3379#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3380 led_classdev_unregister(&host->led);
3381#endif
3382
1e72859e 3383 if (!dead)
03231f9b 3384 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3385
b537f94c
RK		 3386 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3387 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3388 free_irq(host->irq, host);
3389
3390 del_timer_sync(&host->timer);
3391
d129bceb 3392 tasklet_kill(&host->finish_tasklet);
2134a922 3393
3a48edc4
TK		 3394 if (!IS_ERR(mmc->supply.vqmmc))
3395 regulator_disable(mmc->supply.vqmmc);
6231f3de 3396
edd63fcc 3397 if (host->align_buffer)
e66e61cb
RK		 3398 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3399 host->adma_table_sz, host->align_buffer,
3400 host->align_addr);
2134a922 3401
4efaa6fb 3402 host->adma_table = NULL;
2134a922 3403 host->align_buffer = NULL;
d129bceb
PO		 3404}
3405
b8c86fc5 3406EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3407
b8c86fc5 3408void sdhci_free_host(struct sdhci_host *host)
d129bceb 3409{
b8c86fc5 3410 mmc_free_host(host->mmc);
d129bceb
PO		 3411}
3412
b8c86fc5 3413EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3414
3415/*****************************************************************************\
3416 * *
3417 * Driver init/exit *
3418 * *
3419\*****************************************************************************/
3420
3421static int __init sdhci_drv_init(void)
3422{
a3c76eb9 3423 pr_info(DRIVER_NAME
52fbf9c9 3424 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3425 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3426
b8c86fc5 3427 return 0;
d129bceb
PO		 3428}
3429
3430static void __exit sdhci_drv_exit(void)
3431{
d129bceb
PO		 3432}
3433
3434module_init(sdhci_drv_init);
3435module_exit(sdhci_drv_exit);
3436
df673b22 3437module_param(debug_quirks, uint, 0444);
66fd8ad5 3438module_param(debug_quirks2, uint, 0444);
67435274 3439
32710e8f 3440MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3441MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3442MODULE_LICENSE("GPL");
67435274 3443
df673b22 3444MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3445MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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