]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/mmc/host/sdhci.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mmc: fix detection of memory part of SD-combo card with broken SDIO
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
d129bceb 19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
11763609 21#include <linux/scatterlist.h>
9bea3c85 22#include <linux/regulator/consumer.h>
d129bceb 23
2f730fec
PO		 24#include <linux/leds.h>
25
d129bceb 26#include <linux/mmc/host.h>
d129bceb 27
d129bceb
PO		 28#include "sdhci.h"
29
30#define DRIVER_NAME "sdhci"
d129bceb 31
d129bceb 32#define DBG(f, x...) \
c6563178 33 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 34
f9134319
PO		 35#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
36 defined(CONFIG_MMC_SDHCI_MODULE))
37#define SDHCI_USE_LEDS_CLASS
38#endif
39
df673b22 40static unsigned int debug_quirks = 0;
67435274 41
d129bceb
PO		 42static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
43static void sdhci_finish_data(struct sdhci_host *);
44
45static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
46static void sdhci_finish_command(struct sdhci_host *);
47
48static void sdhci_dumpregs(struct sdhci_host *host)
49{
412ab659
PR		 50 printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
51 mmc_hostname(host->mmc));
d129bceb
PO		 52
53 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 54 sdhci_readl(host, SDHCI_DMA_ADDRESS),
55 sdhci_readw(host, SDHCI_HOST_VERSION));
d129bceb 56 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 57 sdhci_readw(host, SDHCI_BLOCK_SIZE),
58 sdhci_readw(host, SDHCI_BLOCK_COUNT));
d129bceb 59 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 60 sdhci_readl(host, SDHCI_ARGUMENT),
61 sdhci_readw(host, SDHCI_TRANSFER_MODE));
d129bceb 62 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 63 sdhci_readl(host, SDHCI_PRESENT_STATE),
64 sdhci_readb(host, SDHCI_HOST_CONTROL));
d129bceb 65 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 66 sdhci_readb(host, SDHCI_POWER_CONTROL),
67 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
d129bceb 68 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 69 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
70 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
d129bceb 71 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 72 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
73 sdhci_readl(host, SDHCI_INT_STATUS));
d129bceb 74 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 75 sdhci_readl(host, SDHCI_INT_ENABLE),
76 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
d129bceb 77 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 78 sdhci_readw(host, SDHCI_ACMD12_ERR),
79 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
e8120ad1 80 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 81 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1
PR		 82 sdhci_readl(host, SDHCI_CAPABILITIES_1));
83 printk(KERN_DEBUG DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
84 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 85 sdhci_readl(host, SDHCI_MAX_CURRENT));
d129bceb 86
be3f4ae0
BD		 87 if (host->flags & SDHCI_USE_ADMA)
88 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
89 readl(host->ioaddr + SDHCI_ADMA_ERROR),
90 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
91
d129bceb
PO		 92 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
93}
94
95/*****************************************************************************\
96 * *
97 * Low level functions *
98 * *
99\*****************************************************************************/
100
7260cf5e
AV		 101static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
102{
103 u32 ier;
104
105 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
106 ier &= ~clear;
107 ier |= set;
108 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
109 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
110}
111
112static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
113{
114 sdhci_clear_set_irqs(host, 0, irqs);
115}
116
117static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
118{
119 sdhci_clear_set_irqs(host, irqs, 0);
120}
121
122static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
123{
124 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
125
68d1fb7e
AV		 126 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
127 return;
128
7260cf5e
AV		 129 if (enable)
130 sdhci_unmask_irqs(host, irqs);
131 else
132 sdhci_mask_irqs(host, irqs);
133}
134
135static void sdhci_enable_card_detection(struct sdhci_host *host)
136{
137 sdhci_set_card_detection(host, true);
138}
139
140static void sdhci_disable_card_detection(struct sdhci_host *host)
141{
142 sdhci_set_card_detection(host, false);
143}
144
d129bceb
PO		 145static void sdhci_reset(struct sdhci_host *host, u8 mask)
146{
e16514d8 147 unsigned long timeout;
063a9dbb 148 u32 uninitialized_var(ier);
e16514d8 149
b8c86fc5 150 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 151 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 152 SDHCI_CARD_PRESENT))
153 return;
154 }
155
063a9dbb
AV		 156 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
157 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
158
4e4141a5 159 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 160
e16514d8 161 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 162 host->clock = 0;
163
e16514d8
PO		 164 /* Wait max 100 ms */
165 timeout = 100;
166
167 /* hw clears the bit when it's done */
4e4141a5 168 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 169 if (timeout == 0) {
acf1da45 170 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 171 mmc_hostname(host->mmc), (int)mask);
172 sdhci_dumpregs(host);
173 return;
174 }
175 timeout--;
176 mdelay(1);
d129bceb 177 }
063a9dbb
AV		 178
179 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
180 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
d129bceb
PO		 181}
182
2f4cbb3d
NP		 183static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
184
185static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 186{
2f4cbb3d
NP		 187 if (soft)
188 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
189 else
190 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 191
7260cf5e
AV		 192 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
193 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 194 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
195 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 196 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 197
198 if (soft) {
199 /* force clock reconfiguration */
200 host->clock = 0;
201 sdhci_set_ios(host->mmc, &host->mmc->ios);
202 }
7260cf5e 203}
d129bceb 204
7260cf5e
AV		 205static void sdhci_reinit(struct sdhci_host *host)
206{
2f4cbb3d 207 sdhci_init(host, 0);
7260cf5e 208 sdhci_enable_card_detection(host);
d129bceb
PO		 209}
210
211static void sdhci_activate_led(struct sdhci_host *host)
212{
213 u8 ctrl;
214
4e4141a5 215 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 216 ctrl |= SDHCI_CTRL_LED;
4e4141a5 217 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 218}
219
220static void sdhci_deactivate_led(struct sdhci_host *host)
221{
222 u8 ctrl;
223
4e4141a5 224 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 225 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 226 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 227}
228
f9134319 229#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 230static void sdhci_led_control(struct led_classdev *led,
231 enum led_brightness brightness)
232{
233 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
234 unsigned long flags;
235
236 spin_lock_irqsave(&host->lock, flags);
237
238 if (brightness == LED_OFF)
239 sdhci_deactivate_led(host);
240 else
241 sdhci_activate_led(host);
242
243 spin_unlock_irqrestore(&host->lock, flags);
244}
245#endif
246
d129bceb
PO		 247/*****************************************************************************\
248 * *
249 * Core functions *
250 * *
251\*****************************************************************************/
252
a406f5a3 253static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 254{
7659150c
PO		 255 unsigned long flags;
256 size_t blksize, len, chunk;
7244b85b 257 u32 uninitialized_var(scratch);
7659150c 258 u8 *buf;
d129bceb 259
a406f5a3 260 DBG("PIO reading\n");
d129bceb 261
a406f5a3 262 blksize = host->data->blksz;
7659150c 263 chunk = 0;
d129bceb 264
7659150c 265 local_irq_save(flags);
d129bceb 266
a406f5a3 267 while (blksize) {
7659150c
PO		 268 if (!sg_miter_next(&host->sg_miter))
269 BUG();
d129bceb 270
7659150c 271 len = min(host->sg_miter.length, blksize);
d129bceb 272
7659150c
PO		 273 blksize -= len;
274 host->sg_miter.consumed = len;
14d836e7 275
7659150c 276 buf = host->sg_miter.addr;
d129bceb 277
7659150c
PO		 278 while (len) {
279 if (chunk == 0) {
4e4141a5 280 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 281 chunk = 4;
a406f5a3 282 }
7659150c
PO		 283
284 *buf = scratch & 0xFF;
285
286 buf++;
287 scratch >>= 8;
288 chunk--;
289 len--;
d129bceb 290 }
a406f5a3 291 }
7659150c
PO		 292
293 sg_miter_stop(&host->sg_miter);
294
295 local_irq_restore(flags);
a406f5a3 296}
d129bceb 297
a406f5a3
PO		 298static void sdhci_write_block_pio(struct sdhci_host *host)
299{
7659150c
PO		 300 unsigned long flags;
301 size_t blksize, len, chunk;
302 u32 scratch;
303 u8 *buf;
d129bceb 304
a406f5a3
PO		 305 DBG("PIO writing\n");
306
307 blksize = host->data->blksz;
7659150c
PO		 308 chunk = 0;
309 scratch = 0;
d129bceb 310
7659150c 311 local_irq_save(flags);
d129bceb 312
a406f5a3 313 while (blksize) {
7659150c
PO		 314 if (!sg_miter_next(&host->sg_miter))
315 BUG();
a406f5a3 316
7659150c
PO		 317 len = min(host->sg_miter.length, blksize);
318
319 blksize -= len;
320 host->sg_miter.consumed = len;
321
322 buf = host->sg_miter.addr;
d129bceb 323
7659150c
PO		 324 while (len) {
325 scratch |= (u32)*buf << (chunk * 8);
326
327 buf++;
328 chunk++;
329 len--;
330
331 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 332 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 333 chunk = 0;
334 scratch = 0;
d129bceb 335 }
d129bceb
PO		 336 }
337 }
7659150c
PO		 338
339 sg_miter_stop(&host->sg_miter);
340
341 local_irq_restore(flags);
a406f5a3
PO		 342}
343
344static void sdhci_transfer_pio(struct sdhci_host *host)
345{
346 u32 mask;
347
348 BUG_ON(!host->data);
349
7659150c 350 if (host->blocks == 0)
a406f5a3
PO		 351 return;
352
353 if (host->data->flags & MMC_DATA_READ)
354 mask = SDHCI_DATA_AVAILABLE;
355 else
356 mask = SDHCI_SPACE_AVAILABLE;
357
4a3cba32
PO		 358 /*
359 * Some controllers (JMicron JMB38x) mess up the buffer bits
360 * for transfers < 4 bytes. As long as it is just one block,
361 * we can ignore the bits.
362 */
363 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
364 (host->data->blocks == 1))
365 mask = ~0;
366
4e4141a5 367 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 368 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
369 udelay(100);
370
a406f5a3
PO		 371 if (host->data->flags & MMC_DATA_READ)
372 sdhci_read_block_pio(host);
373 else
374 sdhci_write_block_pio(host);
d129bceb 375
7659150c
PO		 376 host->blocks--;
377 if (host->blocks == 0)
a406f5a3 378 break;
a406f5a3 379 }
d129bceb 380
a406f5a3 381 DBG("PIO transfer complete.\n");
d129bceb
PO		 382}
383
2134a922
PO		 384static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
385{
386 local_irq_save(*flags);
387 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
388}
389
390static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
391{
392 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
393 local_irq_restore(*flags);
394}
395
118cd17d
BD		 396static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
397{
9e506f35
BD		 398 __le32 *dataddr = (__le32 __force *)(desc + 4);
399 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 400
9e506f35
BD		 401 /* SDHCI specification says ADMA descriptors should be 4 byte
402 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 403
9e506f35
BD		 404 cmdlen[0] = cpu_to_le16(cmd);
405 cmdlen[1] = cpu_to_le16(len);
406
407 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 408}
409
8f1934ce 410static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 411 struct mmc_data *data)
412{
413 int direction;
414
415 u8 *desc;
416 u8 *align;
417 dma_addr_t addr;
418 dma_addr_t align_addr;
419 int len, offset;
420
421 struct scatterlist *sg;
422 int i;
423 char *buffer;
424 unsigned long flags;
425
426 /*
427 * The spec does not specify endianness of descriptor table.
428 * We currently guess that it is LE.
429 */
430
431 if (data->flags & MMC_DATA_READ)
432 direction = DMA_FROM_DEVICE;
433 else
434 direction = DMA_TO_DEVICE;
435
436 /*
437 * The ADMA descriptor table is mapped further down as we
438 * need to fill it with data first.
439 */
440
441 host->align_addr = dma_map_single(mmc_dev(host->mmc),
442 host->align_buffer, 128 * 4, direction);
8d8bb39b 443 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 444 goto fail;
2134a922
PO		 445 BUG_ON(host->align_addr & 0x3);
446
447 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
448 data->sg, data->sg_len, direction);
8f1934ce
PO		 449 if (host->sg_count == 0)
450 goto unmap_align;
2134a922
PO		 451
452 desc = host->adma_desc;
453 align = host->align_buffer;
454
455 align_addr = host->align_addr;
456
457 for_each_sg(data->sg, sg, host->sg_count, i) {
458 addr = sg_dma_address(sg);
459 len = sg_dma_len(sg);
460
461 /*
462 * The SDHCI specification states that ADMA
463 * addresses must be 32-bit aligned. If they
464 * aren't, then we use a bounce buffer for
465 * the (up to three) bytes that screw up the
466 * alignment.
467 */
468 offset = (4 - (addr & 0x3)) & 0x3;
469 if (offset) {
470 if (data->flags & MMC_DATA_WRITE) {
471 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 472 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 473 memcpy(align, buffer, offset);
474 sdhci_kunmap_atomic(buffer, &flags);
475 }
476
118cd17d
BD		 477 /* tran, valid */
478 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 479
480 BUG_ON(offset > 65536);
481
2134a922
PO		 482 align += 4;
483 align_addr += 4;
484
485 desc += 8;
486
487 addr += offset;
488 len -= offset;
489 }
490
2134a922
PO		 491 BUG_ON(len > 65536);
492
118cd17d
BD		 493 /* tran, valid */
494 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 495 desc += 8;
496
497 /*
498 * If this triggers then we have a calculation bug
499 * somewhere. :/
500 */
501 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
502 }
503
70764a90
TA		 504 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
505 /*
506 * Mark the last descriptor as the terminating descriptor
507 */
508 if (desc != host->adma_desc) {
509 desc -= 8;
510 desc[0] |= 0x2; /* end */
511 }
512 } else {
513 /*
514 * Add a terminating entry.
515 */
2134a922 516
70764a90
TA		 517 /* nop, end, valid */
518 sdhci_set_adma_desc(desc, 0, 0, 0x3);
519 }
2134a922
PO		 520
521 /*
522 * Resync align buffer as we might have changed it.
523 */
524 if (data->flags & MMC_DATA_WRITE) {
525 dma_sync_single_for_device(mmc_dev(host->mmc),
526 host->align_addr, 128 * 4, direction);
527 }
528
529 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
530 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 531 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 532 goto unmap_entries;
2134a922 533 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 534
535 return 0;
536
537unmap_entries:
538 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
539 data->sg_len, direction);
540unmap_align:
541 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
542 128 * 4, direction);
543fail:
544 return -EINVAL;
2134a922
PO		 545}
546
547static void sdhci_adma_table_post(struct sdhci_host *host,
548 struct mmc_data *data)
549{
550 int direction;
551
552 struct scatterlist *sg;
553 int i, size;
554 u8 *align;
555 char *buffer;
556 unsigned long flags;
557
558 if (data->flags & MMC_DATA_READ)
559 direction = DMA_FROM_DEVICE;
560 else
561 direction = DMA_TO_DEVICE;
562
563 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
564 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
565
566 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
567 128 * 4, direction);
568
569 if (data->flags & MMC_DATA_READ) {
570 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
571 data->sg_len, direction);
572
573 align = host->align_buffer;
574
575 for_each_sg(data->sg, sg, host->sg_count, i) {
576 if (sg_dma_address(sg) & 0x3) {
577 size = 4 - (sg_dma_address(sg) & 0x3);
578
579 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 580 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 581 memcpy(buffer, align, size);
582 sdhci_kunmap_atomic(buffer, &flags);
583
584 align += 4;
585 }
586 }
587 }
588
589 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
590 data->sg_len, direction);
591}
592
ee53ab5d 593static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
d129bceb 594{
1c8cde92
PO		 595 u8 count;
596 unsigned target_timeout, current_timeout;
d129bceb 597
ee53ab5d
PO		 598 /*
599 * If the host controller provides us with an incorrect timeout
600 * value, just skip the check and use 0xE. The hardware may take
601 * longer to time out, but that's much better than having a too-short
602 * timeout value.
603 */
11a2f1b7 604 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 605 return 0xE;
e538fbe8 606
1c8cde92
PO		 607 /* timeout in us */
608 target_timeout = data->timeout_ns / 1000 +
609 data->timeout_clks / host->clock;
d129bceb 610
81b39802
AV		 611 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
612 host->timeout_clk = host->clock / 1000;
613
1c8cde92
PO		 614 /*
615 * Figure out needed cycles.
616 * We do this in steps in order to fit inside a 32 bit int.
617 * The first step is the minimum timeout, which will have a
618 * minimum resolution of 6 bits:
619 * (1) 2^13*1000 > 2^22,
620 * (2) host->timeout_clk < 2^16
621 * =>
622 * (1) / (2) > 2^6
623 */
624 count = 0;
625 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
626 while (current_timeout < target_timeout) {
627 count++;
628 current_timeout <<= 1;
629 if (count >= 0xF)
630 break;
631 }
632
633 if (count >= 0xF) {
634 printk(KERN_WARNING "%s: Too large timeout requested!\n",
635 mmc_hostname(host->mmc));
636 count = 0xE;
637 }
638
ee53ab5d
PO		 639 return count;
640}
641
6aa943ab
AV		 642static void sdhci_set_transfer_irqs(struct sdhci_host *host)
643{
644 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
645 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
646
647 if (host->flags & SDHCI_REQ_USE_DMA)
648 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
649 else
650 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
651}
652
ee53ab5d
PO		 653static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
654{
655 u8 count;
2134a922 656 u8 ctrl;
8f1934ce 657 int ret;
ee53ab5d
PO		 658
659 WARN_ON(host->data);
660
661 if (data == NULL)
662 return;
663
664 /* Sanity checks */
665 BUG_ON(data->blksz * data->blocks > 524288);
666 BUG_ON(data->blksz > host->mmc->max_blk_size);
667 BUG_ON(data->blocks > 65535);
668
669 host->data = data;
670 host->data_early = 0;
671
672 count = sdhci_calc_timeout(host, data);
4e4141a5 673 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
d129bceb 674
a13abc7b 675 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 676 host->flags |= SDHCI_REQ_USE_DMA;
677
2134a922
PO		 678 /*
679 * FIXME: This doesn't account for merging when mapping the
680 * scatterlist.
681 */
682 if (host->flags & SDHCI_REQ_USE_DMA) {
683 int broken, i;
684 struct scatterlist *sg;
685
686 broken = 0;
687 if (host->flags & SDHCI_USE_ADMA) {
688 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
689 broken = 1;
690 } else {
691 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
692 broken = 1;
693 }
694
695 if (unlikely(broken)) {
696 for_each_sg(data->sg, sg, data->sg_len, i) {
697 if (sg->length & 0x3) {
698 DBG("Reverting to PIO because of "
699 "transfer size (%d)\n",
700 sg->length);
701 host->flags &= ~SDHCI_REQ_USE_DMA;
702 break;
703 }
704 }
705 }
c9fddbc4
PO		 706 }
707
708 /*
709 * The assumption here being that alignment is the same after
710 * translation to device address space.
711 */
2134a922
PO		 712 if (host->flags & SDHCI_REQ_USE_DMA) {
713 int broken, i;
714 struct scatterlist *sg;
715
716 broken = 0;
717 if (host->flags & SDHCI_USE_ADMA) {
718 /*
719 * As we use 3 byte chunks to work around
720 * alignment problems, we need to check this
721 * quirk.
722 */
723 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
724 broken = 1;
725 } else {
726 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
727 broken = 1;
728 }
729
730 if (unlikely(broken)) {
731 for_each_sg(data->sg, sg, data->sg_len, i) {
732 if (sg->offset & 0x3) {
733 DBG("Reverting to PIO because of "
734 "bad alignment\n");
735 host->flags &= ~SDHCI_REQ_USE_DMA;
736 break;
737 }
738 }
739 }
740 }
741
8f1934ce
PO		 742 if (host->flags & SDHCI_REQ_USE_DMA) {
743 if (host->flags & SDHCI_USE_ADMA) {
744 ret = sdhci_adma_table_pre(host, data);
745 if (ret) {
746 /*
747 * This only happens when someone fed
748 * us an invalid request.
749 */
750 WARN_ON(1);
ebd6d357 751 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 752 } else {
4e4141a5
AV		 753 sdhci_writel(host, host->adma_addr,
754 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 755 }
756 } else {
c8b3e02e 757 int sg_cnt;
8f1934ce 758
c8b3e02e 759 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 760 data->sg, data->sg_len,
761 (data->flags & MMC_DATA_READ) ?
762 DMA_FROM_DEVICE :
763 DMA_TO_DEVICE);
c8b3e02e 764 if (sg_cnt == 0) {
8f1934ce
PO		 765 /*
766 * This only happens when someone fed
767 * us an invalid request.
768 */
769 WARN_ON(1);
ebd6d357 770 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 771 } else {
719a61b4 772 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 773 sdhci_writel(host, sg_dma_address(data->sg),
774 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 775 }
776 }
777 }
778
2134a922
PO		 779 /*
780 * Always adjust the DMA selection as some controllers
781 * (e.g. JMicron) can't do PIO properly when the selection
782 * is ADMA.
783 */
784 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 785 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 786 ctrl &= ~SDHCI_CTRL_DMA_MASK;
787 if ((host->flags & SDHCI_REQ_USE_DMA) &&
788 (host->flags & SDHCI_USE_ADMA))
789 ctrl |= SDHCI_CTRL_ADMA32;
790 else
791 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 792 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 793 }
794
8f1934ce 795 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 796 int flags;
797
798 flags = SG_MITER_ATOMIC;
799 if (host->data->flags & MMC_DATA_READ)
800 flags |= SG_MITER_TO_SG;
801 else
802 flags |= SG_MITER_FROM_SG;
803 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 804 host->blocks = data->blocks;
d129bceb 805 }
c7fa9963 806
6aa943ab
AV		 807 sdhci_set_transfer_irqs(host);
808
bab76961 809 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
4e4141a5
AV		 810 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
811 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 812}
813
814static void sdhci_set_transfer_mode(struct sdhci_host *host,
815 struct mmc_data *data)
816{
817 u16 mode;
818
c7fa9963
PO		 819 if (data == NULL)
820 return;
821
e538fbe8
PO		 822 WARN_ON(!host->data);
823
c7fa9963 824 mode = SDHCI_TRNS_BLK_CNT_EN;
c4512f79
JH		 825 if (data->blocks > 1) {
826 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
827 mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
828 else
829 mode |= SDHCI_TRNS_MULTI;
830 }
c7fa9963
PO		 831 if (data->flags & MMC_DATA_READ)
832 mode |= SDHCI_TRNS_READ;
c9fddbc4 833 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 834 mode |= SDHCI_TRNS_DMA;
835
4e4141a5 836 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 837}
838
839static void sdhci_finish_data(struct sdhci_host *host)
840{
841 struct mmc_data *data;
d129bceb
PO		 842
843 BUG_ON(!host->data);
844
845 data = host->data;
846 host->data = NULL;
847
c9fddbc4 848 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 849 if (host->flags & SDHCI_USE_ADMA)
850 sdhci_adma_table_post(host, data);
851 else {
852 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
853 data->sg_len, (data->flags & MMC_DATA_READ) ?
854 DMA_FROM_DEVICE : DMA_TO_DEVICE);
855 }
d129bceb
PO		 856 }
857
858 /*
c9b74c5b
PO		 859 * The specification states that the block count register must
860 * be updated, but it does not specify at what point in the
861 * data flow. That makes the register entirely useless to read
862 * back so we have to assume that nothing made it to the card
863 * in the event of an error.
d129bceb 864 */
c9b74c5b
PO		 865 if (data->error)
866 data->bytes_xfered = 0;
d129bceb 867 else
c9b74c5b 868 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 869
d129bceb
PO		 870 if (data->stop) {
871 /*
872 * The controller needs a reset of internal state machines
873 * upon error conditions.
874 */
17b0429d 875 if (data->error) {
d129bceb
PO		 876 sdhci_reset(host, SDHCI_RESET_CMD);
877 sdhci_reset(host, SDHCI_RESET_DATA);
878 }
879
880 sdhci_send_command(host, data->stop);
881 } else
882 tasklet_schedule(&host->finish_tasklet);
883}
884
885static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
886{
887 int flags;
fd2208d7 888 u32 mask;
7cb2c76f 889 unsigned long timeout;
d129bceb
PO		 890
891 WARN_ON(host->cmd);
892
d129bceb 893 /* Wait max 10 ms */
7cb2c76f 894 timeout = 10;
fd2208d7
PO		 895
896 mask = SDHCI_CMD_INHIBIT;
897 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
898 mask |= SDHCI_DATA_INHIBIT;
899
900 /* We shouldn't wait for data inihibit for stop commands, even
901 though they might use busy signaling */
902 if (host->mrq->data && (cmd == host->mrq->data->stop))
903 mask &= ~SDHCI_DATA_INHIBIT;
904
4e4141a5 905 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 906 if (timeout == 0) {
d129bceb 907 printk(KERN_ERR "%s: Controller never released "
acf1da45 908 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 909 sdhci_dumpregs(host);
17b0429d 910 cmd->error = -EIO;
d129bceb
PO		 911 tasklet_schedule(&host->finish_tasklet);
912 return;
913 }
7cb2c76f
PO		 914 timeout--;
915 mdelay(1);
916 }
d129bceb
PO		 917
918 mod_timer(&host->timer, jiffies + 10 * HZ);
919
920 host->cmd = cmd;
921
922 sdhci_prepare_data(host, cmd->data);
923
4e4141a5 924 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 925
c7fa9963
PO		 926 sdhci_set_transfer_mode(host, cmd->data);
927
d129bceb 928 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 929 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb 930 mmc_hostname(host->mmc));
17b0429d 931 cmd->error = -EINVAL;
d129bceb
PO		 932 tasklet_schedule(&host->finish_tasklet);
933 return;
934 }
935
936 if (!(cmd->flags & MMC_RSP_PRESENT))
937 flags = SDHCI_CMD_RESP_NONE;
938 else if (cmd->flags & MMC_RSP_136)
939 flags = SDHCI_CMD_RESP_LONG;
940 else if (cmd->flags & MMC_RSP_BUSY)
941 flags = SDHCI_CMD_RESP_SHORT_BUSY;
942 else
943 flags = SDHCI_CMD_RESP_SHORT;
944
945 if (cmd->flags & MMC_RSP_CRC)
946 flags |= SDHCI_CMD_CRC;
947 if (cmd->flags & MMC_RSP_OPCODE)
948 flags |= SDHCI_CMD_INDEX;
949 if (cmd->data)
950 flags |= SDHCI_CMD_DATA;
951
4e4141a5 952 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 953}
954
955static void sdhci_finish_command(struct sdhci_host *host)
956{
957 int i;
958
959 BUG_ON(host->cmd == NULL);
960
961 if (host->cmd->flags & MMC_RSP_PRESENT) {
962 if (host->cmd->flags & MMC_RSP_136) {
963 /* CRC is stripped so we need to do some shifting. */
964 for (i = 0;i < 4;i++) {
4e4141a5 965 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 966 SDHCI_RESPONSE + (3-i)*4) << 8;
967 if (i != 3)
968 host->cmd->resp[i] |=
4e4141a5 969 sdhci_readb(host,
d129bceb
PO		 970 SDHCI_RESPONSE + (3-i)*4-1);
971 }
972 } else {
4e4141a5 973 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 974 }
975 }
976
17b0429d 977 host->cmd->error = 0;
d129bceb 978
e538fbe8
PO		 979 if (host->data && host->data_early)
980 sdhci_finish_data(host);
981
982 if (!host->cmd->data)
d129bceb
PO		 983 tasklet_schedule(&host->finish_tasklet);
984
985 host->cmd = NULL;
986}
987
988static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
989{
990 int div;
991 u16 clk;
7cb2c76f 992 unsigned long timeout;
d129bceb
PO		 993
994 if (clock == host->clock)
995 return;
996
8114634c
AV		 997 if (host->ops->set_clock) {
998 host->ops->set_clock(host, clock);
999 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1000 return;
1001 }
1002
4e4141a5 1003 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1004
1005 if (clock == 0)
1006 goto out;
1007
85105c53
ZG		 1008 if (host->version >= SDHCI_SPEC_300) {
1009 /* Version 3.00 divisors must be a multiple of 2. */
1010 if (host->max_clk <= clock)
1011 div = 1;
1012 else {
0397526d 1013 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
85105c53
ZG		 1014 if ((host->max_clk / div) <= clock)
1015 break;
1016 }
1017 }
1018 } else {
1019 /* Version 2.00 divisors must be a power of 2. */
0397526d 1020 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1021 if ((host->max_clk / div) <= clock)
1022 break;
1023 }
d129bceb
PO		 1024 }
1025 div >>= 1;
1026
85105c53
ZG		 1027 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1028 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1029 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1030 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1031 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1032
27f6cb16
CB		 1033 /* Wait max 20 ms */
1034 timeout = 20;
4e4141a5 1035 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1036 & SDHCI_CLOCK_INT_STABLE)) {
1037 if (timeout == 0) {
acf1da45
PO		 1038 printk(KERN_ERR "%s: Internal clock never "
1039 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1040 sdhci_dumpregs(host);
1041 return;
1042 }
7cb2c76f
PO		 1043 timeout--;
1044 mdelay(1);
1045 }
d129bceb
PO		 1046
1047 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1048 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1049
1050out:
1051 host->clock = clock;
1052}
1053
146ad66e
PO		 1054static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1055{
8364248a 1056 u8 pwr = 0;
146ad66e 1057
8364248a 1058 if (power != (unsigned short)-1) {
ae628903
PO		 1059 switch (1 << power) {
1060 case MMC_VDD_165_195:
1061 pwr = SDHCI_POWER_180;
1062 break;
1063 case MMC_VDD_29_30:
1064 case MMC_VDD_30_31:
1065 pwr = SDHCI_POWER_300;
1066 break;
1067 case MMC_VDD_32_33:
1068 case MMC_VDD_33_34:
1069 pwr = SDHCI_POWER_330;
1070 break;
1071 default:
1072 BUG();
1073 }
1074 }
1075
1076 if (host->pwr == pwr)
146ad66e
PO		 1077 return;
1078
ae628903
PO		 1079 host->pwr = pwr;
1080
1081 if (pwr == 0) {
4e4141a5 1082 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ae628903 1083 return;
9e9dc5f2
DS		 1084 }
1085
1086 /*
1087 * Spec says that we should clear the power reg before setting
1088 * a new value. Some controllers don't seem to like this though.
1089 */
b8c86fc5 1090 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1091 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1092
e08c1694 1093 /*
c71f6512 1094 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1095 * and set turn on power at the same time, so set the voltage first.
1096 */
11a2f1b7 1097 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1098 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1099
ae628903 1100 pwr |= SDHCI_POWER_ON;
146ad66e 1101
ae628903 1102 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1103
1104 /*
1105 * Some controllers need an extra 10ms delay of 10ms before they
1106 * can apply clock after applying power
1107 */
11a2f1b7 1108 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1109 mdelay(10);
146ad66e
PO		 1110}
1111
d129bceb
PO		 1112/*****************************************************************************\
1113 * *
1114 * MMC callbacks *
1115 * *
1116\*****************************************************************************/
1117
1118static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1119{
1120 struct sdhci_host *host;
68d1fb7e 1121 bool present;
d129bceb
PO		 1122 unsigned long flags;
1123
1124 host = mmc_priv(mmc);
1125
1126 spin_lock_irqsave(&host->lock, flags);
1127
1128 WARN_ON(host->mrq != NULL);
1129
f9134319 1130#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1131 sdhci_activate_led(host);
2f730fec 1132#endif
c4512f79
JH		 1133 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) {
1134 if (mrq->stop) {
1135 mrq->data->stop = NULL;
1136 mrq->stop = NULL;
1137 }
1138 }
d129bceb
PO		 1139
1140 host->mrq = mrq;
1141
68d1fb7e
AV		 1142 /* If polling, assume that the card is always present. */
1143 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1144 present = true;
1145 else
1146 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1147 SDHCI_CARD_PRESENT;
1148
1149 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1150 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1151 tasklet_schedule(&host->finish_tasklet);
1152 } else
1153 sdhci_send_command(host, mrq->cmd);
1154
5f25a66f 1155 mmiowb();
d129bceb
PO		 1156 spin_unlock_irqrestore(&host->lock, flags);
1157}
1158
1159static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1160{
1161 struct sdhci_host *host;
1162 unsigned long flags;
1163 u8 ctrl;
1164
1165 host = mmc_priv(mmc);
1166
1167 spin_lock_irqsave(&host->lock, flags);
1168
1e72859e
PO		 1169 if (host->flags & SDHCI_DEVICE_DEAD)
1170 goto out;
1171
d129bceb
PO		 1172 /*
1173 * Reset the chip on each power off.
1174 * Should clear out any weird states.
1175 */
1176 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1177 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1178 sdhci_reinit(host);
d129bceb
PO		 1179 }
1180
1181 sdhci_set_clock(host, ios->clock);
1182
1183 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 1184 sdhci_set_power(host, -1);
d129bceb 1185 else
146ad66e 1186 sdhci_set_power(host, ios->vdd);
d129bceb 1187
643a81ff
PR		 1188 if (host->ops->platform_send_init_74_clocks)
1189 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1190
15ec4461
PR		 1191 /*
1192 * If your platform has 8-bit width support but is not a v3 controller,
1193 * or if it requires special setup code, you should implement that in
1194 * platform_8bit_width().
1195 */
1196 if (host->ops->platform_8bit_width)
1197 host->ops->platform_8bit_width(host, ios->bus_width);
1198 else {
1199 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1200 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1201 ctrl &= ~SDHCI_CTRL_4BITBUS;
1202 if (host->version >= SDHCI_SPEC_300)
1203 ctrl |= SDHCI_CTRL_8BITBUS;
1204 } else {
1205 if (host->version >= SDHCI_SPEC_300)
1206 ctrl &= ~SDHCI_CTRL_8BITBUS;
1207 if (ios->bus_width == MMC_BUS_WIDTH_4)
1208 ctrl |= SDHCI_CTRL_4BITBUS;
1209 else
1210 ctrl &= ~SDHCI_CTRL_4BITBUS;
1211 }
1212 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1213 }
ae6d6c92 1214
15ec4461 1215 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1216
3ab9c8da
PR		 1217 if ((ios->timing == MMC_TIMING_SD_HS ||
1218 ios->timing == MMC_TIMING_MMC_HS)
1219 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1220 ctrl |= SDHCI_CTRL_HISPD;
1221 else
1222 ctrl &= ~SDHCI_CTRL_HISPD;
1223
4e4141a5 1224 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb 1225
b8352260
LD		 1226 /*
1227 * Some (ENE) controllers go apeshit on some ios operation,
1228 * signalling timeout and CRC errors even on CMD0. Resetting
1229 * it on each ios seems to solve the problem.
1230 */
b8c86fc5 1231 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1232 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1233
1e72859e 1234out:
5f25a66f 1235 mmiowb();
d129bceb
PO		 1236 spin_unlock_irqrestore(&host->lock, flags);
1237}
1238
1239static int sdhci_get_ro(struct mmc_host *mmc)
1240{
1241 struct sdhci_host *host;
1242 unsigned long flags;
2dfb579c 1243 int is_readonly;
d129bceb
PO		 1244
1245 host = mmc_priv(mmc);
1246
1247 spin_lock_irqsave(&host->lock, flags);
1248
1e72859e 1249 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1250 is_readonly = 0;
1251 else if (host->ops->get_ro)
1252 is_readonly = host->ops->get_ro(host);
1e72859e 1253 else
2dfb579c
WS		 1254 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1255 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1256
1257 spin_unlock_irqrestore(&host->lock, flags);
1258
2dfb579c
WS		 1259 /* This quirk needs to be replaced by a callback-function later */
1260 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1261 !is_readonly : is_readonly;
d129bceb
PO		 1262}
1263
f75979b7
PO		 1264static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1265{
1266 struct sdhci_host *host;
1267 unsigned long flags;
f75979b7
PO		 1268
1269 host = mmc_priv(mmc);
1270
1271 spin_lock_irqsave(&host->lock, flags);
1272
1e72859e
PO		 1273 if (host->flags & SDHCI_DEVICE_DEAD)
1274 goto out;
1275
f75979b7 1276 if (enable)
7260cf5e
AV		 1277 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1278 else
1279 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1280out:
f75979b7
PO		 1281 mmiowb();
1282
1283 spin_unlock_irqrestore(&host->lock, flags);
1284}
1285
ab7aefd0 1286static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1287 .request = sdhci_request,
1288 .set_ios = sdhci_set_ios,
1289 .get_ro = sdhci_get_ro,
f75979b7 1290 .enable_sdio_irq = sdhci_enable_sdio_irq,
d129bceb
PO		 1291};
1292
1293/*****************************************************************************\
1294 * *
1295 * Tasklets *
1296 * *
1297\*****************************************************************************/
1298
1299static void sdhci_tasklet_card(unsigned long param)
1300{
1301 struct sdhci_host *host;
1302 unsigned long flags;
1303
1304 host = (struct sdhci_host*)param;
1305
1306 spin_lock_irqsave(&host->lock, flags);
1307
4e4141a5 1308 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
d129bceb
PO		 1309 if (host->mrq) {
1310 printk(KERN_ERR "%s: Card removed during transfer!\n",
1311 mmc_hostname(host->mmc));
1312 printk(KERN_ERR "%s: Resetting controller.\n",
1313 mmc_hostname(host->mmc));
1314
1315 sdhci_reset(host, SDHCI_RESET_CMD);
1316 sdhci_reset(host, SDHCI_RESET_DATA);
1317
17b0429d 1318 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1319 tasklet_schedule(&host->finish_tasklet);
1320 }
1321 }
1322
1323 spin_unlock_irqrestore(&host->lock, flags);
1324
04cf585d 1325 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1326}
1327
1328static void sdhci_tasklet_finish(unsigned long param)
1329{
1330 struct sdhci_host *host;
1331 unsigned long flags;
1332 struct mmc_request *mrq;
1333
1334 host = (struct sdhci_host*)param;
1335
1336 spin_lock_irqsave(&host->lock, flags);
1337
1338 del_timer(&host->timer);
1339
1340 mrq = host->mrq;
1341
d129bceb
PO		 1342 /*
1343 * The controller needs a reset of internal state machines
1344 * upon error conditions.
1345 */
1e72859e
PO		 1346 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1347 (mrq->cmd->error ||
1348 (mrq->data && (mrq->data->error ||
1349 (mrq->data->stop && mrq->data->stop->error))) ||
1350 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1351
1352 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1353 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1354 unsigned int clock;
1355
1356 /* This is to force an update */
1357 clock = host->clock;
1358 host->clock = 0;
1359 sdhci_set_clock(host, clock);
1360 }
1361
1362 /* Spec says we should do both at the same time, but Ricoh
1363 controllers do not like that. */
d129bceb
PO		 1364 sdhci_reset(host, SDHCI_RESET_CMD);
1365 sdhci_reset(host, SDHCI_RESET_DATA);
1366 }
1367
1368 host->mrq = NULL;
1369 host->cmd = NULL;
1370 host->data = NULL;
1371
f9134319 1372#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1373 sdhci_deactivate_led(host);
2f730fec 1374#endif
d129bceb 1375
5f25a66f 1376 mmiowb();
d129bceb
PO		 1377 spin_unlock_irqrestore(&host->lock, flags);
1378
1379 mmc_request_done(host->mmc, mrq);
1380}
1381
1382static void sdhci_timeout_timer(unsigned long data)
1383{
1384 struct sdhci_host *host;
1385 unsigned long flags;
1386
1387 host = (struct sdhci_host*)data;
1388
1389 spin_lock_irqsave(&host->lock, flags);
1390
1391 if (host->mrq) {
acf1da45
PO		 1392 printk(KERN_ERR "%s: Timeout waiting for hardware "
1393 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1394 sdhci_dumpregs(host);
1395
1396 if (host->data) {
17b0429d 1397 host->data->error = -ETIMEDOUT;
d129bceb
PO		 1398 sdhci_finish_data(host);
1399 } else {
1400 if (host->cmd)
17b0429d 1401 host->cmd->error = -ETIMEDOUT;
d129bceb 1402 else
17b0429d 1403 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 1404
1405 tasklet_schedule(&host->finish_tasklet);
1406 }
1407 }
1408
5f25a66f 1409 mmiowb();
d129bceb
PO		 1410 spin_unlock_irqrestore(&host->lock, flags);
1411}
1412
1413/*****************************************************************************\
1414 * *
1415 * Interrupt handling *
1416 * *
1417\*****************************************************************************/
1418
1419static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1420{
1421 BUG_ON(intmask == 0);
1422
1423 if (!host->cmd) {
b67ac3f3
PO		 1424 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1425 "though no command operation was in progress.\n",
1426 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1427 sdhci_dumpregs(host);
1428 return;
1429 }
1430
43b58b36 1431 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 1432 host->cmd->error = -ETIMEDOUT;
1433 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1434 SDHCI_INT_INDEX))
1435 host->cmd->error = -EILSEQ;
43b58b36 1436
e809517f 1437 if (host->cmd->error) {
d129bceb 1438 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 1439 return;
1440 }
1441
1442 /*
1443 * The host can send and interrupt when the busy state has
1444 * ended, allowing us to wait without wasting CPU cycles.
1445 * Unfortunately this is overloaded on the "data complete"
1446 * interrupt, so we need to take some care when handling
1447 * it.
1448 *
1449 * Note: The 1.0 specification is a bit ambiguous about this
1450 * feature so there might be some problems with older
1451 * controllers.
1452 */
1453 if (host->cmd->flags & MMC_RSP_BUSY) {
1454 if (host->cmd->data)
1455 DBG("Cannot wait for busy signal when also "
1456 "doing a data transfer");
f945405c 1457 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 1458 return;
f945405c
BD		 1459
1460 /* The controller does not support the end-of-busy IRQ,
1461 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 1462 }
1463
1464 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 1465 sdhci_finish_command(host);
d129bceb
PO		 1466}
1467
0957c333 1468#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 1469static void sdhci_show_adma_error(struct sdhci_host *host)
1470{
1471 const char *name = mmc_hostname(host->mmc);
1472 u8 *desc = host->adma_desc;
1473 __le32 *dma;
1474 __le16 *len;
1475 u8 attr;
1476
1477 sdhci_dumpregs(host);
1478
1479 while (true) {
1480 dma = (__le32 *)(desc + 4);
1481 len = (__le16 *)(desc + 2);
1482 attr = *desc;
1483
1484 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1485 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1486
1487 desc += 8;
1488
1489 if (attr & 2)
1490 break;
1491 }
1492}
1493#else
1494static void sdhci_show_adma_error(struct sdhci_host *host) { }
1495#endif
1496
d129bceb
PO		 1497static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1498{
1499 BUG_ON(intmask == 0);
1500
1501 if (!host->data) {
1502 /*
e809517f
PO		 1503 * The "data complete" interrupt is also used to
1504 * indicate that a busy state has ended. See comment
1505 * above in sdhci_cmd_irq().
d129bceb 1506 */
e809517f
PO		 1507 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1508 if (intmask & SDHCI_INT_DATA_END) {
1509 sdhci_finish_command(host);
1510 return;
1511 }
1512 }
d129bceb 1513
b67ac3f3
PO		 1514 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1515 "though no data operation was in progress.\n",
1516 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1517 sdhci_dumpregs(host);
1518
1519 return;
1520 }
1521
1522 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d
PO		 1523 host->data->error = -ETIMEDOUT;
1524 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1525 host->data->error = -EILSEQ;
6882a8c0
BD		 1526 else if (intmask & SDHCI_INT_ADMA_ERROR) {
1527 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1528 sdhci_show_adma_error(host);
2134a922 1529 host->data->error = -EIO;
6882a8c0 1530 }
d129bceb 1531
17b0429d 1532 if (host->data->error)
d129bceb
PO		 1533 sdhci_finish_data(host);
1534 else {
a406f5a3 1535 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 1536 sdhci_transfer_pio(host);
1537
6ba736a1
PO		 1538 /*
1539 * We currently don't do anything fancy with DMA
1540 * boundaries, but as we can't disable the feature
1541 * we need to at least restart the transfer.
1542 */
1543 if (intmask & SDHCI_INT_DMA_END)
4e4141a5
AV		 1544 sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1545 SDHCI_DMA_ADDRESS);
6ba736a1 1546
e538fbe8
PO		 1547 if (intmask & SDHCI_INT_DATA_END) {
1548 if (host->cmd) {
1549 /*
1550 * Data managed to finish before the
1551 * command completed. Make sure we do
1552 * things in the proper order.
1553 */
1554 host->data_early = 1;
1555 } else {
1556 sdhci_finish_data(host);
1557 }
1558 }
d129bceb
PO		 1559 }
1560}
1561
7d12e780 1562static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 1563{
1564 irqreturn_t result;
1565 struct sdhci_host* host = dev_id;
1566 u32 intmask;
f75979b7 1567 int cardint = 0;
d129bceb
PO		 1568
1569 spin_lock(&host->lock);
1570
4e4141a5 1571 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 1572
62df67a5 1573 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 1574 result = IRQ_NONE;
1575 goto out;
1576 }
1577
b69c9058
PO		 1578 DBG("*** %s got interrupt: 0x%08x\n",
1579 mmc_hostname(host->mmc), intmask);
d129bceb 1580
3192a28f 1581 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
4e4141a5
AV		 1582 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1583 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
d129bceb 1584 tasklet_schedule(&host->card_tasklet);
3192a28f 1585 }
d129bceb 1586
3192a28f 1587 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1588
3192a28f 1589 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 1590 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1591 SDHCI_INT_STATUS);
3192a28f 1592 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1593 }
1594
1595 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 1596 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1597 SDHCI_INT_STATUS);
3192a28f 1598 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1599 }
1600
1601 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1602
964f9ce2
PO		 1603 intmask &= ~SDHCI_INT_ERROR;
1604
d129bceb 1605 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1606 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1607 mmc_hostname(host->mmc));
4e4141a5 1608 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 1609 }
1610
9d26a5d3 1611 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 1612
f75979b7
PO		 1613 if (intmask & SDHCI_INT_CARD_INT)
1614 cardint = 1;
1615
1616 intmask &= ~SDHCI_INT_CARD_INT;
1617
3192a28f 1618 if (intmask) {
acf1da45 1619 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 1620 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1621 sdhci_dumpregs(host);
1622
4e4141a5 1623 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 1624 }
d129bceb
PO		 1625
1626 result = IRQ_HANDLED;
1627
5f25a66f 1628 mmiowb();
d129bceb
PO		 1629out:
1630 spin_unlock(&host->lock);
1631
f75979b7
PO		 1632 /*
1633 * We have to delay this as it calls back into the driver.
1634 */
1635 if (cardint)
1636 mmc_signal_sdio_irq(host->mmc);
1637
d129bceb
PO		 1638 return result;
1639}
1640
1641/*****************************************************************************\
1642 * *
1643 * Suspend/resume *
1644 * *
1645\*****************************************************************************/
1646
1647#ifdef CONFIG_PM
1648
b8c86fc5 1649int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
d129bceb 1650{
b8c86fc5 1651 int ret;
a715dfc7 1652
7260cf5e
AV		 1653 sdhci_disable_card_detection(host);
1654
1a13f8fa 1655 ret = mmc_suspend_host(host->mmc);
b8c86fc5
PO		 1656 if (ret)
1657 return ret;
a715dfc7 1658
b8c86fc5 1659 free_irq(host->irq, host);
d129bceb 1660
9bea3c85
MS		 1661 if (host->vmmc)
1662 ret = regulator_disable(host->vmmc);
1663
1664 return ret;
d129bceb
PO		 1665}
1666
b8c86fc5 1667EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 1668
b8c86fc5
PO		 1669int sdhci_resume_host(struct sdhci_host *host)
1670{
1671 int ret;
d129bceb 1672
9bea3c85
MS		 1673 if (host->vmmc) {
1674 int ret = regulator_enable(host->vmmc);
1675 if (ret)
1676 return ret;
1677 }
1678
1679
a13abc7b 1680 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 1681 if (host->ops->enable_dma)
1682 host->ops->enable_dma(host);
1683 }
d129bceb 1684
b8c86fc5
PO		 1685 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1686 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 1687 if (ret)
1688 return ret;
d129bceb 1689
2f4cbb3d 1690 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
b8c86fc5
PO		 1691 mmiowb();
1692
1693 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 1694 sdhci_enable_card_detection(host);
1695
2f4cbb3d 1696 return ret;
d129bceb
PO		 1697}
1698
b8c86fc5 1699EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb 1700
5f619704
DD		 1701void sdhci_enable_irq_wakeups(struct sdhci_host *host)
1702{
1703 u8 val;
1704 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
1705 val |= SDHCI_WAKE_ON_INT;
1706 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
1707}
1708
1709EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
1710
d129bceb
PO		 1711#endif /* CONFIG_PM */
1712
1713/*****************************************************************************\
1714 * *
b8c86fc5 1715 * Device allocation/registration *
d129bceb
PO		 1716 * *
1717\*****************************************************************************/
1718
b8c86fc5
PO		 1719struct sdhci_host *sdhci_alloc_host(struct device *dev,
1720 size_t priv_size)
d129bceb 1721{
d129bceb
PO		 1722 struct mmc_host *mmc;
1723 struct sdhci_host *host;
1724
b8c86fc5 1725 WARN_ON(dev == NULL);
d129bceb 1726
b8c86fc5 1727 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 1728 if (!mmc)
b8c86fc5 1729 return ERR_PTR(-ENOMEM);
d129bceb
PO		 1730
1731 host = mmc_priv(mmc);
1732 host->mmc = mmc;
1733
b8c86fc5
PO		 1734 return host;
1735}
8a4da143 1736
b8c86fc5 1737EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 1738
b8c86fc5
PO		 1739int sdhci_add_host(struct sdhci_host *host)
1740{
1741 struct mmc_host *mmc;
8f230f45 1742 unsigned int caps, ocr_avail;
b8c86fc5 1743 int ret;
d129bceb 1744
b8c86fc5
PO		 1745 WARN_ON(host == NULL);
1746 if (host == NULL)
1747 return -EINVAL;
d129bceb 1748
b8c86fc5 1749 mmc = host->mmc;
d129bceb 1750
b8c86fc5
PO		 1751 if (debug_quirks)
1752 host->quirks = debug_quirks;
d129bceb 1753
d96649ed
PO		 1754 sdhci_reset(host, SDHCI_RESET_ALL);
1755
4e4141a5 1756 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 1757 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1758 >> SDHCI_SPEC_VER_SHIFT;
85105c53 1759 if (host->version > SDHCI_SPEC_300) {
4a965505 1760 printk(KERN_ERR "%s: Unknown controller version (%d). "
b69c9058 1761 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 1762 host->version);
4a965505
PO		 1763 }
1764
ccc92c23
ML		 1765 caps = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
1766 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 1767
b8c86fc5 1768 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b
RR		 1769 host->flags |= SDHCI_USE_SDMA;
1770 else if (!(caps & SDHCI_CAN_DO_SDMA))
1771 DBG("Controller doesn't have SDMA capability\n");
67435274 1772 else
a13abc7b 1773 host->flags |= SDHCI_USE_SDMA;
d129bceb 1774
b8c86fc5 1775 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 1776 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 1777 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 1778 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 1779 }
1780
a13abc7b
RR		 1781 if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
1782 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 1783
1784 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1785 (host->flags & SDHCI_USE_ADMA)) {
1786 DBG("Disabling ADMA as it is marked broken\n");
1787 host->flags &= ~SDHCI_USE_ADMA;
1788 }
1789
a13abc7b 1790 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 1791 if (host->ops->enable_dma) {
1792 if (host->ops->enable_dma(host)) {
1793 printk(KERN_WARNING "%s: No suitable DMA "
1794 "available. Falling back to PIO.\n",
1795 mmc_hostname(mmc));
a13abc7b
RR		 1796 host->flags &=
1797 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 1798 }
d129bceb
PO		 1799 }
1800 }
1801
2134a922
PO		 1802 if (host->flags & SDHCI_USE_ADMA) {
1803 /*
1804 * We need to allocate descriptors for all sg entries
1805 * (128) and potentially one alignment transfer for
1806 * each of those entries.
1807 */
1808 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1809 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1810 if (!host->adma_desc || !host->align_buffer) {
1811 kfree(host->adma_desc);
1812 kfree(host->align_buffer);
1813 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1814 "buffers. Falling back to standard DMA.\n",
1815 mmc_hostname(mmc));
1816 host->flags &= ~SDHCI_USE_ADMA;
1817 }
1818 }
1819
7659150c
PO		 1820 /*
1821 * If we use DMA, then it's up to the caller to set the DMA
1822 * mask, but PIO does not need the hw shim so we set a new
1823 * mask here in that case.
1824 */
a13abc7b 1825 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 1826 host->dma_mask = DMA_BIT_MASK(64);
1827 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1828 }
d129bceb 1829
c4687d5f
ZG		 1830 if (host->version >= SDHCI_SPEC_300)
1831 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK)
1832 >> SDHCI_CLOCK_BASE_SHIFT;
1833 else
1834 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK)
1835 >> SDHCI_CLOCK_BASE_SHIFT;
1836
4240ff0a 1837 host->max_clk *= 1000000;
f27f47ef
AV		 1838 if (host->max_clk == 0 || host->quirks &
1839 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a
BD		 1840 if (!host->ops->get_max_clock) {
1841 printk(KERN_ERR
1842 "%s: Hardware doesn't specify base clock "
1843 "frequency.\n", mmc_hostname(mmc));
1844 return -ENODEV;
1845 }
1846 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 1847 }
d129bceb 1848
1c8cde92
PO		 1849 host->timeout_clk =
1850 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1851 if (host->timeout_clk == 0) {
81b39802
AV		 1852 if (host->ops->get_timeout_clock) {
1853 host->timeout_clk = host->ops->get_timeout_clock(host);
1854 } else if (!(host->quirks &
1855 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4240ff0a
BD		 1856 printk(KERN_ERR
1857 "%s: Hardware doesn't specify timeout clock "
1858 "frequency.\n", mmc_hostname(mmc));
1859 return -ENODEV;
1860 }
1c8cde92
PO		 1861 }
1862 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1863 host->timeout_clk *= 1000;
d129bceb
PO		 1864
1865 /*
1866 * Set host parameters.
1867 */
1868 mmc->ops = &sdhci_ops;
ce5f036b 1869 if (host->ops->get_min_clock)
a9e58f25 1870 mmc->f_min = host->ops->get_min_clock(host);
0397526d
ZG		 1871 else if (host->version >= SDHCI_SPEC_300)
1872 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
a9e58f25 1873 else
0397526d 1874 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 1875
d129bceb 1876 mmc->f_max = host->max_clk;
c1f5977c 1877 mmc->caps |= MMC_CAP_SDIO_IRQ;
5fe23c7f 1878
15ec4461
PR		 1879 /*
1880 * A controller may support 8-bit width, but the board itself
1881 * might not have the pins brought out. Boards that support
1882 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
1883 * their platform code before calling sdhci_add_host(), and we
1884 * won't assume 8-bit width for hosts without that CAP.
1885 */
5fe23c7f 1886 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 1887 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 1888
86a6a874 1889 if (caps & SDHCI_CAN_DO_HISPD)
a29e7e18 1890 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 1891
176d1ed4
JC		 1892 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
1893 mmc_card_is_removable(mmc))
68d1fb7e
AV		 1894 mmc->caps |= MMC_CAP_NEEDS_POLL;
1895
8f230f45 1896 ocr_avail = 0;
146ad66e 1897 if (caps & SDHCI_CAN_VDD_330)
8f230f45 1898 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
c70840e8 1899 if (caps & SDHCI_CAN_VDD_300)
8f230f45 1900 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
c70840e8 1901 if (caps & SDHCI_CAN_VDD_180)
8f230f45
TI		 1902 ocr_avail |= MMC_VDD_165_195;
1903
1904 mmc->ocr_avail = ocr_avail;
1905 mmc->ocr_avail_sdio = ocr_avail;
1906 if (host->ocr_avail_sdio)
1907 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
1908 mmc->ocr_avail_sd = ocr_avail;
1909 if (host->ocr_avail_sd)
1910 mmc->ocr_avail_sd &= host->ocr_avail_sd;
1911 else /* normal SD controllers don't support 1.8V */
1912 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
1913 mmc->ocr_avail_mmc = ocr_avail;
1914 if (host->ocr_avail_mmc)
1915 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 1916
1917 if (mmc->ocr_avail == 0) {
1918 printk(KERN_ERR "%s: Hardware doesn't report any "
b69c9058 1919 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 1920 return -ENODEV;
146ad66e
PO		 1921 }
1922
d129bceb
PO		 1923 spin_lock_init(&host->lock);
1924
1925 /*
2134a922
PO		 1926 * Maximum number of segments. Depends on if the hardware
1927 * can do scatter/gather or not.
d129bceb 1928 */
2134a922 1929 if (host->flags & SDHCI_USE_ADMA)
a36274e0 1930 mmc->max_segs = 128;
a13abc7b 1931 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 1932 mmc->max_segs = 1;
2134a922 1933 else /* PIO */
a36274e0 1934 mmc->max_segs = 128;
d129bceb
PO		 1935
1936 /*
bab76961 1937 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 1938 * size (512KiB).
d129bceb 1939 */
55db890a 1940 mmc->max_req_size = 524288;
d129bceb
PO		 1941
1942 /*
1943 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 1944 * of bytes. When doing hardware scatter/gather, each entry cannot
1945 * be larger than 64 KiB though.
d129bceb 1946 */
2134a922
PO		 1947 if (host->flags & SDHCI_USE_ADMA)
1948 mmc->max_seg_size = 65536;
1949 else
1950 mmc->max_seg_size = mmc->max_req_size;
d129bceb 1951
fe4a3c7a
PO		 1952 /*
1953 * Maximum block size. This varies from controller to controller and
1954 * is specified in the capabilities register.
1955 */
0633f654
AV		 1956 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
1957 mmc->max_blk_size = 2;
1958 } else {
1959 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
1960 SDHCI_MAX_BLOCK_SHIFT;
1961 if (mmc->max_blk_size >= 3) {
1962 printk(KERN_WARNING "%s: Invalid maximum block size, "
1963 "assuming 512 bytes\n", mmc_hostname(mmc));
1964 mmc->max_blk_size = 0;
1965 }
1966 }
1967
1968 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 1969
55db890a
PO		 1970 /*
1971 * Maximum block count.
1972 */
1388eefd 1973 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 1974
d129bceb
PO		 1975 /*
1976 * Init tasklets.
1977 */
1978 tasklet_init(&host->card_tasklet,
1979 sdhci_tasklet_card, (unsigned long)host);
1980 tasklet_init(&host->finish_tasklet,
1981 sdhci_tasklet_finish, (unsigned long)host);
1982
e4cad1b5 1983 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 1984
dace1453 1985 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 1986 mmc_hostname(mmc), host);
d129bceb 1987 if (ret)
8ef1a143 1988 goto untasklet;
d129bceb 1989
9bea3c85
MS		 1990 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1991 if (IS_ERR(host->vmmc)) {
1992 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
1993 host->vmmc = NULL;
1994 } else {
1995 regulator_enable(host->vmmc);
1996 }
1997
2f4cbb3d 1998 sdhci_init(host, 0);
d129bceb
PO		 1999
2000#ifdef CONFIG_MMC_DEBUG
2001 sdhci_dumpregs(host);
2002#endif
2003
f9134319 2004#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 2005 snprintf(host->led_name, sizeof(host->led_name),
2006 "%s::", mmc_hostname(mmc));
2007 host->led.name = host->led_name;
2f730fec
PO		 2008 host->led.brightness = LED_OFF;
2009 host->led.default_trigger = mmc_hostname(mmc);
2010 host->led.brightness_set = sdhci_led_control;
2011
b8c86fc5 2012 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 2013 if (ret)
2014 goto reset;
2015#endif
2016
5f25a66f
PO		 2017 mmiowb();
2018
d129bceb
PO		 2019 mmc_add_host(mmc);
2020
a13abc7b 2021 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 2022 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 2023 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2024 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 2025
7260cf5e
AV		 2026 sdhci_enable_card_detection(host);
2027
d129bceb
PO		 2028 return 0;
2029
f9134319 2030#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2031reset:
2032 sdhci_reset(host, SDHCI_RESET_ALL);
2033 free_irq(host->irq, host);
2034#endif
8ef1a143 2035untasklet:
d129bceb
PO		 2036 tasklet_kill(&host->card_tasklet);
2037 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 2038
2039 return ret;
2040}
2041
b8c86fc5 2042EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 2043
1e72859e 2044void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 2045{
1e72859e
PO		 2046 unsigned long flags;
2047
2048 if (dead) {
2049 spin_lock_irqsave(&host->lock, flags);
2050
2051 host->flags |= SDHCI_DEVICE_DEAD;
2052
2053 if (host->mrq) {
2054 printk(KERN_ERR "%s: Controller removed during "
2055 " transfer!\n", mmc_hostname(host->mmc));
2056
2057 host->mrq->cmd->error = -ENOMEDIUM;
2058 tasklet_schedule(&host->finish_tasklet);
2059 }
2060
2061 spin_unlock_irqrestore(&host->lock, flags);
2062 }
2063
7260cf5e
AV		 2064 sdhci_disable_card_detection(host);
2065
b8c86fc5 2066 mmc_remove_host(host->mmc);
d129bceb 2067
f9134319 2068#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2069 led_classdev_unregister(&host->led);
2070#endif
2071
1e72859e
PO		 2072 if (!dead)
2073 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 2074
2075 free_irq(host->irq, host);
2076
2077 del_timer_sync(&host->timer);
2078
2079 tasklet_kill(&host->card_tasklet);
2080 tasklet_kill(&host->finish_tasklet);
2134a922 2081
9bea3c85
MS		 2082 if (host->vmmc) {
2083 regulator_disable(host->vmmc);
2084 regulator_put(host->vmmc);
2085 }
2086
2134a922
PO		 2087 kfree(host->adma_desc);
2088 kfree(host->align_buffer);
2089
2090 host->adma_desc = NULL;
2091 host->align_buffer = NULL;
d129bceb
PO		 2092}
2093
b8c86fc5 2094EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 2095
b8c86fc5 2096void sdhci_free_host(struct sdhci_host *host)
d129bceb 2097{
b8c86fc5 2098 mmc_free_host(host->mmc);
d129bceb
PO		 2099}
2100
b8c86fc5 2101EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 2102
2103/*****************************************************************************\
2104 * *
2105 * Driver init/exit *
2106 * *
2107\*****************************************************************************/
2108
2109static int __init sdhci_drv_init(void)
2110{
2111 printk(KERN_INFO DRIVER_NAME
52fbf9c9 2112 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 2113 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2114
b8c86fc5 2115 return 0;
d129bceb
PO		 2116}
2117
2118static void __exit sdhci_drv_exit(void)
2119{
d129bceb
PO		 2120}
2121
2122module_init(sdhci_drv_init);
2123module_exit(sdhci_drv_exit);
2124
df673b22 2125module_param(debug_quirks, uint, 0444);
67435274 2126
32710e8f 2127MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 2128MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 2129MODULE_LICENSE("GPL");
67435274 2130
df673b22 2131MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Ubuntu Artful kernel mirror