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Commit | Line | Data |
---|---|---|
d129bceb | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
d129bceb | 3 | * |
b69c9058 | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
d129bceb PO |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
84c46a53 PO |
10 | * |
11 | * Thanks to the following companies for their support: | |
12 | * | |
13 | * - JMicron (hardware and technical support) | |
d129bceb PO |
14 | */ |
15 | ||
d129bceb PO |
16 | #include <linux/delay.h> |
17 | #include <linux/highmem.h> | |
b8c86fc5 | 18 | #include <linux/io.h> |
88b47679 | 19 | #include <linux/module.h> |
d129bceb | 20 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 21 | #include <linux/slab.h> |
11763609 | 22 | #include <linux/scatterlist.h> |
9bea3c85 | 23 | #include <linux/regulator/consumer.h> |
66fd8ad5 | 24 | #include <linux/pm_runtime.h> |
d129bceb | 25 | |
2f730fec PO |
26 | #include <linux/leds.h> |
27 | ||
22113efd | 28 | #include <linux/mmc/mmc.h> |
d129bceb | 29 | #include <linux/mmc/host.h> |
473b095a | 30 | #include <linux/mmc/card.h> |
85cc1c33 | 31 | #include <linux/mmc/sdio.h> |
bec9d4e5 | 32 | #include <linux/mmc/slot-gpio.h> |
d129bceb | 33 | |
d129bceb PO |
34 | #include "sdhci.h" |
35 | ||
36 | #define DRIVER_NAME "sdhci" | |
d129bceb | 37 | |
d129bceb | 38 | #define DBG(f, x...) \ |
c6563178 | 39 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
d129bceb | 40 | |
f9134319 PO |
41 | #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ |
42 | defined(CONFIG_MMC_SDHCI_MODULE)) | |
43 | #define SDHCI_USE_LEDS_CLASS | |
44 | #endif | |
45 | ||
b513ea25 AN |
46 | #define MAX_TUNING_LOOP 40 |
47 | ||
df673b22 | 48 | static unsigned int debug_quirks = 0; |
66fd8ad5 | 49 | static unsigned int debug_quirks2; |
67435274 | 50 | |
d129bceb PO |
51 | static void sdhci_finish_data(struct sdhci_host *); |
52 | ||
d129bceb | 53 | static void sdhci_finish_command(struct sdhci_host *); |
069c9f14 | 54 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); |
52983382 | 55 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); |
04e079cf | 56 | static int sdhci_do_get_cd(struct sdhci_host *host); |
d129bceb PO |
57 | |
58 | static void sdhci_dumpregs(struct sdhci_host *host) | |
59 | { | |
a3c76eb9 | 60 | pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", |
412ab659 | 61 | mmc_hostname(host->mmc)); |
d129bceb | 62 | |
a3c76eb9 | 63 | pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", |
4e4141a5 AV |
64 | sdhci_readl(host, SDHCI_DMA_ADDRESS), |
65 | sdhci_readw(host, SDHCI_HOST_VERSION)); | |
a3c76eb9 | 66 | pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", |
4e4141a5 AV |
67 | sdhci_readw(host, SDHCI_BLOCK_SIZE), |
68 | sdhci_readw(host, SDHCI_BLOCK_COUNT)); | |
a3c76eb9 | 69 | pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", |
4e4141a5 AV |
70 | sdhci_readl(host, SDHCI_ARGUMENT), |
71 | sdhci_readw(host, SDHCI_TRANSFER_MODE)); | |
a3c76eb9 | 72 | pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", |
4e4141a5 AV |
73 | sdhci_readl(host, SDHCI_PRESENT_STATE), |
74 | sdhci_readb(host, SDHCI_HOST_CONTROL)); | |
a3c76eb9 | 75 | pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", |
4e4141a5 AV |
76 | sdhci_readb(host, SDHCI_POWER_CONTROL), |
77 | sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); | |
a3c76eb9 | 78 | pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", |
4e4141a5 AV |
79 | sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), |
80 | sdhci_readw(host, SDHCI_CLOCK_CONTROL)); | |
a3c76eb9 | 81 | pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", |
4e4141a5 AV |
82 | sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), |
83 | sdhci_readl(host, SDHCI_INT_STATUS)); | |
a3c76eb9 | 84 | pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", |
4e4141a5 AV |
85 | sdhci_readl(host, SDHCI_INT_ENABLE), |
86 | sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); | |
a3c76eb9 | 87 | pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", |
4e4141a5 AV |
88 | sdhci_readw(host, SDHCI_ACMD12_ERR), |
89 | sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); | |
a3c76eb9 | 90 | pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", |
4e4141a5 | 91 | sdhci_readl(host, SDHCI_CAPABILITIES), |
e8120ad1 | 92 | sdhci_readl(host, SDHCI_CAPABILITIES_1)); |
a3c76eb9 | 93 | pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", |
e8120ad1 | 94 | sdhci_readw(host, SDHCI_COMMAND), |
4e4141a5 | 95 | sdhci_readl(host, SDHCI_MAX_CURRENT)); |
a3c76eb9 | 96 | pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", |
f2119df6 | 97 | sdhci_readw(host, SDHCI_HOST_CONTROL2)); |
d129bceb | 98 | |
e57a5f61 AH |
99 | if (host->flags & SDHCI_USE_ADMA) { |
100 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
101 | pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", | |
102 | readl(host->ioaddr + SDHCI_ADMA_ERROR), | |
103 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI), | |
104 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); | |
105 | else | |
106 | pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", | |
107 | readl(host->ioaddr + SDHCI_ADMA_ERROR), | |
108 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); | |
109 | } | |
be3f4ae0 | 110 | |
a3c76eb9 | 111 | pr_debug(DRIVER_NAME ": ===========================================\n"); |
d129bceb PO |
112 | } |
113 | ||
114 | /*****************************************************************************\ | |
115 | * * | |
116 | * Low level functions * | |
117 | * * | |
118 | \*****************************************************************************/ | |
119 | ||
7260cf5e AV |
120 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) |
121 | { | |
5b4f1f6c | 122 | u32 present; |
7260cf5e | 123 | |
c79396c1 | 124 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || |
87b87a3f | 125 | (host->mmc->caps & MMC_CAP_NONREMOVABLE)) |
66fd8ad5 AH |
126 | return; |
127 | ||
5b4f1f6c RK |
128 | if (enable) { |
129 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
130 | SDHCI_CARD_PRESENT; | |
d25928d1 | 131 | |
5b4f1f6c RK |
132 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : |
133 | SDHCI_INT_CARD_INSERT; | |
134 | } else { | |
135 | host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); | |
136 | } | |
b537f94c RK |
137 | |
138 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
139 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
7260cf5e AV |
140 | } |
141 | ||
142 | static void sdhci_enable_card_detection(struct sdhci_host *host) | |
143 | { | |
144 | sdhci_set_card_detection(host, true); | |
145 | } | |
146 | ||
147 | static void sdhci_disable_card_detection(struct sdhci_host *host) | |
148 | { | |
149 | sdhci_set_card_detection(host, false); | |
150 | } | |
151 | ||
02d0b685 UH |
152 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) |
153 | { | |
154 | if (host->bus_on) | |
155 | return; | |
156 | host->bus_on = true; | |
157 | pm_runtime_get_noresume(host->mmc->parent); | |
158 | } | |
159 | ||
160 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) | |
161 | { | |
162 | if (!host->bus_on) | |
163 | return; | |
164 | host->bus_on = false; | |
165 | pm_runtime_put_noidle(host->mmc->parent); | |
166 | } | |
167 | ||
03231f9b | 168 | void sdhci_reset(struct sdhci_host *host, u8 mask) |
d129bceb | 169 | { |
e16514d8 | 170 | unsigned long timeout; |
393c1a34 | 171 | |
4e4141a5 | 172 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
d129bceb | 173 | |
f0710a55 | 174 | if (mask & SDHCI_RESET_ALL) { |
d129bceb | 175 | host->clock = 0; |
f0710a55 AH |
176 | /* Reset-all turns off SD Bus Power */ |
177 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) | |
178 | sdhci_runtime_pm_bus_off(host); | |
179 | } | |
d129bceb | 180 | |
e16514d8 PO |
181 | /* Wait max 100 ms */ |
182 | timeout = 100; | |
183 | ||
184 | /* hw clears the bit when it's done */ | |
4e4141a5 | 185 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { |
e16514d8 | 186 | if (timeout == 0) { |
a3c76eb9 | 187 | pr_err("%s: Reset 0x%x never completed.\n", |
e16514d8 PO |
188 | mmc_hostname(host->mmc), (int)mask); |
189 | sdhci_dumpregs(host); | |
190 | return; | |
191 | } | |
192 | timeout--; | |
193 | mdelay(1); | |
d129bceb | 194 | } |
03231f9b RK |
195 | } |
196 | EXPORT_SYMBOL_GPL(sdhci_reset); | |
197 | ||
198 | static void sdhci_do_reset(struct sdhci_host *host, u8 mask) | |
199 | { | |
200 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { | |
135b0a28 | 201 | if (!sdhci_do_get_cd(host)) |
03231f9b RK |
202 | return; |
203 | } | |
063a9dbb | 204 | |
03231f9b | 205 | host->ops->reset(host, mask); |
393c1a34 | 206 | |
da91a8f9 RK |
207 | if (mask & SDHCI_RESET_ALL) { |
208 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { | |
209 | if (host->ops->enable_dma) | |
210 | host->ops->enable_dma(host); | |
211 | } | |
212 | ||
213 | /* Resetting the controller clears many */ | |
214 | host->preset_enabled = false; | |
3abc1e80 | 215 | } |
d129bceb PO |
216 | } |
217 | ||
2f4cbb3d NP |
218 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); |
219 | ||
220 | static void sdhci_init(struct sdhci_host *host, int soft) | |
d129bceb | 221 | { |
2f4cbb3d | 222 | if (soft) |
03231f9b | 223 | sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); |
2f4cbb3d | 224 | else |
03231f9b | 225 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
d129bceb | 226 | |
b537f94c RK |
227 | host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | |
228 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | | |
229 | SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | | |
230 | SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | | |
231 | SDHCI_INT_RESPONSE; | |
232 | ||
233 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
234 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
2f4cbb3d NP |
235 | |
236 | if (soft) { | |
237 | /* force clock reconfiguration */ | |
238 | host->clock = 0; | |
239 | sdhci_set_ios(host->mmc, &host->mmc->ios); | |
240 | } | |
7260cf5e | 241 | } |
d129bceb | 242 | |
7260cf5e AV |
243 | static void sdhci_reinit(struct sdhci_host *host) |
244 | { | |
2f4cbb3d | 245 | sdhci_init(host, 0); |
7260cf5e | 246 | sdhci_enable_card_detection(host); |
d129bceb PO |
247 | } |
248 | ||
249 | static void sdhci_activate_led(struct sdhci_host *host) | |
250 | { | |
251 | u8 ctrl; | |
252 | ||
4e4141a5 | 253 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 254 | ctrl |= SDHCI_CTRL_LED; |
4e4141a5 | 255 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
256 | } |
257 | ||
258 | static void sdhci_deactivate_led(struct sdhci_host *host) | |
259 | { | |
260 | u8 ctrl; | |
261 | ||
4e4141a5 | 262 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 263 | ctrl &= ~SDHCI_CTRL_LED; |
4e4141a5 | 264 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
265 | } |
266 | ||
f9134319 | 267 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
268 | static void sdhci_led_control(struct led_classdev *led, |
269 | enum led_brightness brightness) | |
270 | { | |
271 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); | |
272 | unsigned long flags; | |
273 | ||
274 | spin_lock_irqsave(&host->lock, flags); | |
275 | ||
66fd8ad5 AH |
276 | if (host->runtime_suspended) |
277 | goto out; | |
278 | ||
2f730fec PO |
279 | if (brightness == LED_OFF) |
280 | sdhci_deactivate_led(host); | |
281 | else | |
282 | sdhci_activate_led(host); | |
66fd8ad5 | 283 | out: |
2f730fec PO |
284 | spin_unlock_irqrestore(&host->lock, flags); |
285 | } | |
286 | #endif | |
287 | ||
d129bceb PO |
288 | /*****************************************************************************\ |
289 | * * | |
290 | * Core functions * | |
291 | * * | |
292 | \*****************************************************************************/ | |
293 | ||
a406f5a3 | 294 | static void sdhci_read_block_pio(struct sdhci_host *host) |
d129bceb | 295 | { |
7659150c PO |
296 | unsigned long flags; |
297 | size_t blksize, len, chunk; | |
7244b85b | 298 | u32 uninitialized_var(scratch); |
7659150c | 299 | u8 *buf; |
d129bceb | 300 | |
a406f5a3 | 301 | DBG("PIO reading\n"); |
d129bceb | 302 | |
a406f5a3 | 303 | blksize = host->data->blksz; |
7659150c | 304 | chunk = 0; |
d129bceb | 305 | |
7659150c | 306 | local_irq_save(flags); |
d129bceb | 307 | |
a406f5a3 | 308 | while (blksize) { |
bf3a35ac | 309 | BUG_ON(!sg_miter_next(&host->sg_miter)); |
d129bceb | 310 | |
7659150c | 311 | len = min(host->sg_miter.length, blksize); |
d129bceb | 312 | |
7659150c PO |
313 | blksize -= len; |
314 | host->sg_miter.consumed = len; | |
14d836e7 | 315 | |
7659150c | 316 | buf = host->sg_miter.addr; |
d129bceb | 317 | |
7659150c PO |
318 | while (len) { |
319 | if (chunk == 0) { | |
4e4141a5 | 320 | scratch = sdhci_readl(host, SDHCI_BUFFER); |
7659150c | 321 | chunk = 4; |
a406f5a3 | 322 | } |
7659150c PO |
323 | |
324 | *buf = scratch & 0xFF; | |
325 | ||
326 | buf++; | |
327 | scratch >>= 8; | |
328 | chunk--; | |
329 | len--; | |
d129bceb | 330 | } |
a406f5a3 | 331 | } |
7659150c PO |
332 | |
333 | sg_miter_stop(&host->sg_miter); | |
334 | ||
335 | local_irq_restore(flags); | |
a406f5a3 | 336 | } |
d129bceb | 337 | |
a406f5a3 PO |
338 | static void sdhci_write_block_pio(struct sdhci_host *host) |
339 | { | |
7659150c PO |
340 | unsigned long flags; |
341 | size_t blksize, len, chunk; | |
342 | u32 scratch; | |
343 | u8 *buf; | |
d129bceb | 344 | |
a406f5a3 PO |
345 | DBG("PIO writing\n"); |
346 | ||
347 | blksize = host->data->blksz; | |
7659150c PO |
348 | chunk = 0; |
349 | scratch = 0; | |
d129bceb | 350 | |
7659150c | 351 | local_irq_save(flags); |
d129bceb | 352 | |
a406f5a3 | 353 | while (blksize) { |
bf3a35ac | 354 | BUG_ON(!sg_miter_next(&host->sg_miter)); |
a406f5a3 | 355 | |
7659150c PO |
356 | len = min(host->sg_miter.length, blksize); |
357 | ||
358 | blksize -= len; | |
359 | host->sg_miter.consumed = len; | |
360 | ||
361 | buf = host->sg_miter.addr; | |
d129bceb | 362 | |
7659150c PO |
363 | while (len) { |
364 | scratch |= (u32)*buf << (chunk * 8); | |
365 | ||
366 | buf++; | |
367 | chunk++; | |
368 | len--; | |
369 | ||
370 | if ((chunk == 4) || ((len == 0) && (blksize == 0))) { | |
4e4141a5 | 371 | sdhci_writel(host, scratch, SDHCI_BUFFER); |
7659150c PO |
372 | chunk = 0; |
373 | scratch = 0; | |
d129bceb | 374 | } |
d129bceb PO |
375 | } |
376 | } | |
7659150c PO |
377 | |
378 | sg_miter_stop(&host->sg_miter); | |
379 | ||
380 | local_irq_restore(flags); | |
a406f5a3 PO |
381 | } |
382 | ||
383 | static void sdhci_transfer_pio(struct sdhci_host *host) | |
384 | { | |
385 | u32 mask; | |
386 | ||
387 | BUG_ON(!host->data); | |
388 | ||
7659150c | 389 | if (host->blocks == 0) |
a406f5a3 PO |
390 | return; |
391 | ||
392 | if (host->data->flags & MMC_DATA_READ) | |
393 | mask = SDHCI_DATA_AVAILABLE; | |
394 | else | |
395 | mask = SDHCI_SPACE_AVAILABLE; | |
396 | ||
4a3cba32 PO |
397 | /* |
398 | * Some controllers (JMicron JMB38x) mess up the buffer bits | |
399 | * for transfers < 4 bytes. As long as it is just one block, | |
400 | * we can ignore the bits. | |
401 | */ | |
402 | if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && | |
403 | (host->data->blocks == 1)) | |
404 | mask = ~0; | |
405 | ||
4e4141a5 | 406 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
3e3bf207 AV |
407 | if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) |
408 | udelay(100); | |
409 | ||
a406f5a3 PO |
410 | if (host->data->flags & MMC_DATA_READ) |
411 | sdhci_read_block_pio(host); | |
412 | else | |
413 | sdhci_write_block_pio(host); | |
d129bceb | 414 | |
7659150c PO |
415 | host->blocks--; |
416 | if (host->blocks == 0) | |
a406f5a3 | 417 | break; |
a406f5a3 | 418 | } |
d129bceb | 419 | |
a406f5a3 | 420 | DBG("PIO transfer complete.\n"); |
d129bceb PO |
421 | } |
422 | ||
48857d9b | 423 | static int sdhci_pre_dma_transfer(struct sdhci_host *host, |
c0999b72 | 424 | struct mmc_data *data, int cookie) |
48857d9b RK |
425 | { |
426 | int sg_count; | |
427 | ||
94538e51 RK |
428 | /* |
429 | * If the data buffers are already mapped, return the previous | |
430 | * dma_map_sg() result. | |
431 | */ | |
432 | if (data->host_cookie == COOKIE_PRE_MAPPED) | |
48857d9b | 433 | return data->sg_count; |
48857d9b RK |
434 | |
435 | sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, | |
436 | data->flags & MMC_DATA_WRITE ? | |
437 | DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
438 | ||
439 | if (sg_count == 0) | |
440 | return -ENOSPC; | |
441 | ||
442 | data->sg_count = sg_count; | |
c0999b72 | 443 | data->host_cookie = cookie; |
48857d9b RK |
444 | |
445 | return sg_count; | |
446 | } | |
447 | ||
2134a922 PO |
448 | static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) |
449 | { | |
450 | local_irq_save(*flags); | |
482fce99 | 451 | return kmap_atomic(sg_page(sg)) + sg->offset; |
2134a922 PO |
452 | } |
453 | ||
454 | static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) | |
455 | { | |
482fce99 | 456 | kunmap_atomic(buffer); |
2134a922 PO |
457 | local_irq_restore(*flags); |
458 | } | |
459 | ||
e57a5f61 AH |
460 | static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc, |
461 | dma_addr_t addr, int len, unsigned cmd) | |
118cd17d | 462 | { |
e57a5f61 | 463 | struct sdhci_adma2_64_desc *dma_desc = desc; |
118cd17d | 464 | |
e57a5f61 | 465 | /* 32-bit and 64-bit descriptors have these members in same position */ |
0545230f AH |
466 | dma_desc->cmd = cpu_to_le16(cmd); |
467 | dma_desc->len = cpu_to_le16(len); | |
e57a5f61 AH |
468 | dma_desc->addr_lo = cpu_to_le32((u32)addr); |
469 | ||
470 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
471 | dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32); | |
118cd17d BD |
472 | } |
473 | ||
b5ffa674 AH |
474 | static void sdhci_adma_mark_end(void *desc) |
475 | { | |
e57a5f61 | 476 | struct sdhci_adma2_64_desc *dma_desc = desc; |
b5ffa674 | 477 | |
e57a5f61 | 478 | /* 32-bit and 64-bit descriptors have 'cmd' in same position */ |
0545230f | 479 | dma_desc->cmd |= cpu_to_le16(ADMA2_END); |
b5ffa674 AH |
480 | } |
481 | ||
60c64762 RK |
482 | static void sdhci_adma_table_pre(struct sdhci_host *host, |
483 | struct mmc_data *data, int sg_count) | |
2134a922 | 484 | { |
2134a922 | 485 | struct scatterlist *sg; |
2134a922 | 486 | unsigned long flags; |
acc3ad13 RK |
487 | dma_addr_t addr, align_addr; |
488 | void *desc, *align; | |
489 | char *buffer; | |
490 | int len, offset, i; | |
2134a922 PO |
491 | |
492 | /* | |
493 | * The spec does not specify endianness of descriptor table. | |
494 | * We currently guess that it is LE. | |
495 | */ | |
496 | ||
60c64762 | 497 | host->sg_count = sg_count; |
2134a922 | 498 | |
4efaa6fb | 499 | desc = host->adma_table; |
2134a922 PO |
500 | align = host->align_buffer; |
501 | ||
502 | align_addr = host->align_addr; | |
503 | ||
504 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
505 | addr = sg_dma_address(sg); | |
506 | len = sg_dma_len(sg); | |
507 | ||
508 | /* | |
acc3ad13 RK |
509 | * The SDHCI specification states that ADMA addresses must |
510 | * be 32-bit aligned. If they aren't, then we use a bounce | |
511 | * buffer for the (up to three) bytes that screw up the | |
2134a922 PO |
512 | * alignment. |
513 | */ | |
04a5ae6f AH |
514 | offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) & |
515 | SDHCI_ADMA2_MASK; | |
2134a922 PO |
516 | if (offset) { |
517 | if (data->flags & MMC_DATA_WRITE) { | |
518 | buffer = sdhci_kmap_atomic(sg, &flags); | |
519 | memcpy(align, buffer, offset); | |
520 | sdhci_kunmap_atomic(buffer, &flags); | |
521 | } | |
522 | ||
118cd17d | 523 | /* tran, valid */ |
e57a5f61 | 524 | sdhci_adma_write_desc(host, desc, align_addr, offset, |
739d46dc | 525 | ADMA2_TRAN_VALID); |
2134a922 PO |
526 | |
527 | BUG_ON(offset > 65536); | |
528 | ||
04a5ae6f AH |
529 | align += SDHCI_ADMA2_ALIGN; |
530 | align_addr += SDHCI_ADMA2_ALIGN; | |
2134a922 | 531 | |
76fe379a | 532 | desc += host->desc_sz; |
2134a922 PO |
533 | |
534 | addr += offset; | |
535 | len -= offset; | |
536 | } | |
537 | ||
2134a922 PO |
538 | BUG_ON(len > 65536); |
539 | ||
347ea32d AH |
540 | if (len) { |
541 | /* tran, valid */ | |
542 | sdhci_adma_write_desc(host, desc, addr, len, | |
543 | ADMA2_TRAN_VALID); | |
544 | desc += host->desc_sz; | |
545 | } | |
2134a922 PO |
546 | |
547 | /* | |
548 | * If this triggers then we have a calculation bug | |
549 | * somewhere. :/ | |
550 | */ | |
76fe379a | 551 | WARN_ON((desc - host->adma_table) >= host->adma_table_sz); |
2134a922 PO |
552 | } |
553 | ||
70764a90 | 554 | if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { |
acc3ad13 | 555 | /* Mark the last descriptor as the terminating descriptor */ |
4efaa6fb | 556 | if (desc != host->adma_table) { |
76fe379a | 557 | desc -= host->desc_sz; |
b5ffa674 | 558 | sdhci_adma_mark_end(desc); |
70764a90 TA |
559 | } |
560 | } else { | |
acc3ad13 | 561 | /* Add a terminating entry - nop, end, valid */ |
e57a5f61 | 562 | sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID); |
70764a90 | 563 | } |
2134a922 PO |
564 | } |
565 | ||
566 | static void sdhci_adma_table_post(struct sdhci_host *host, | |
567 | struct mmc_data *data) | |
568 | { | |
2134a922 PO |
569 | struct scatterlist *sg; |
570 | int i, size; | |
1c3d5f6d | 571 | void *align; |
2134a922 PO |
572 | char *buffer; |
573 | unsigned long flags; | |
574 | ||
47fa9613 RK |
575 | if (data->flags & MMC_DATA_READ) { |
576 | bool has_unaligned = false; | |
de0b65a7 | 577 | |
47fa9613 RK |
578 | /* Do a quick scan of the SG list for any unaligned mappings */ |
579 | for_each_sg(data->sg, sg, host->sg_count, i) | |
580 | if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { | |
581 | has_unaligned = true; | |
582 | break; | |
583 | } | |
2134a922 | 584 | |
47fa9613 RK |
585 | if (has_unaligned) { |
586 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, | |
f55c98f7 | 587 | data->sg_len, DMA_FROM_DEVICE); |
2134a922 | 588 | |
47fa9613 | 589 | align = host->align_buffer; |
2134a922 | 590 | |
47fa9613 RK |
591 | for_each_sg(data->sg, sg, host->sg_count, i) { |
592 | if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { | |
593 | size = SDHCI_ADMA2_ALIGN - | |
594 | (sg_dma_address(sg) & SDHCI_ADMA2_MASK); | |
595 | ||
596 | buffer = sdhci_kmap_atomic(sg, &flags); | |
597 | memcpy(buffer, align, size); | |
598 | sdhci_kunmap_atomic(buffer, &flags); | |
2134a922 | 599 | |
47fa9613 RK |
600 | align += SDHCI_ADMA2_ALIGN; |
601 | } | |
2134a922 PO |
602 | } |
603 | } | |
604 | } | |
2134a922 PO |
605 | } |
606 | ||
a3c7778f | 607 | static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
d129bceb | 608 | { |
1c8cde92 | 609 | u8 count; |
a3c7778f | 610 | struct mmc_data *data = cmd->data; |
1c8cde92 | 611 | unsigned target_timeout, current_timeout; |
d129bceb | 612 | |
ee53ab5d PO |
613 | /* |
614 | * If the host controller provides us with an incorrect timeout | |
615 | * value, just skip the check and use 0xE. The hardware may take | |
616 | * longer to time out, but that's much better than having a too-short | |
617 | * timeout value. | |
618 | */ | |
11a2f1b7 | 619 | if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) |
ee53ab5d | 620 | return 0xE; |
e538fbe8 | 621 | |
a3c7778f | 622 | /* Unspecified timeout, assume max */ |
1d4d7744 | 623 | if (!data && !cmd->busy_timeout) |
a3c7778f | 624 | return 0xE; |
d129bceb | 625 | |
a3c7778f AW |
626 | /* timeout in us */ |
627 | if (!data) | |
1d4d7744 | 628 | target_timeout = cmd->busy_timeout * 1000; |
78a2ca27 | 629 | else { |
fafcfda9 | 630 | target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000); |
7f05538a RK |
631 | if (host->clock && data->timeout_clks) { |
632 | unsigned long long val; | |
633 | ||
634 | /* | |
635 | * data->timeout_clks is in units of clock cycles. | |
636 | * host->clock is in Hz. target_timeout is in us. | |
637 | * Hence, us = 1000000 * cycles / Hz. Round up. | |
638 | */ | |
639 | val = 1000000 * data->timeout_clks; | |
640 | if (do_div(val, host->clock)) | |
641 | target_timeout++; | |
642 | target_timeout += val; | |
643 | } | |
78a2ca27 | 644 | } |
81b39802 | 645 | |
1c8cde92 PO |
646 | /* |
647 | * Figure out needed cycles. | |
648 | * We do this in steps in order to fit inside a 32 bit int. | |
649 | * The first step is the minimum timeout, which will have a | |
650 | * minimum resolution of 6 bits: | |
651 | * (1) 2^13*1000 > 2^22, | |
652 | * (2) host->timeout_clk < 2^16 | |
653 | * => | |
654 | * (1) / (2) > 2^6 | |
655 | */ | |
656 | count = 0; | |
657 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; | |
658 | while (current_timeout < target_timeout) { | |
659 | count++; | |
660 | current_timeout <<= 1; | |
661 | if (count >= 0xF) | |
662 | break; | |
663 | } | |
664 | ||
665 | if (count >= 0xF) { | |
09eeff52 CB |
666 | DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", |
667 | mmc_hostname(host->mmc), count, cmd->opcode); | |
1c8cde92 PO |
668 | count = 0xE; |
669 | } | |
670 | ||
ee53ab5d PO |
671 | return count; |
672 | } | |
673 | ||
6aa943ab AV |
674 | static void sdhci_set_transfer_irqs(struct sdhci_host *host) |
675 | { | |
676 | u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; | |
677 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; | |
678 | ||
679 | if (host->flags & SDHCI_REQ_USE_DMA) | |
b537f94c | 680 | host->ier = (host->ier & ~pio_irqs) | dma_irqs; |
6aa943ab | 681 | else |
b537f94c RK |
682 | host->ier = (host->ier & ~dma_irqs) | pio_irqs; |
683 | ||
684 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
685 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
6aa943ab AV |
686 | } |
687 | ||
b45e668a | 688 | static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
ee53ab5d PO |
689 | { |
690 | u8 count; | |
b45e668a AD |
691 | |
692 | if (host->ops->set_timeout) { | |
693 | host->ops->set_timeout(host, cmd); | |
694 | } else { | |
695 | count = sdhci_calc_timeout(host, cmd); | |
696 | sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); | |
697 | } | |
698 | } | |
699 | ||
700 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) | |
701 | { | |
2134a922 | 702 | u8 ctrl; |
a3c7778f | 703 | struct mmc_data *data = cmd->data; |
ee53ab5d PO |
704 | |
705 | WARN_ON(host->data); | |
706 | ||
b45e668a AD |
707 | if (data || (cmd->flags & MMC_RSP_BUSY)) |
708 | sdhci_set_timeout(host, cmd); | |
a3c7778f AW |
709 | |
710 | if (!data) | |
ee53ab5d PO |
711 | return; |
712 | ||
713 | /* Sanity checks */ | |
714 | BUG_ON(data->blksz * data->blocks > 524288); | |
715 | BUG_ON(data->blksz > host->mmc->max_blk_size); | |
716 | BUG_ON(data->blocks > 65535); | |
717 | ||
718 | host->data = data; | |
719 | host->data_early = 0; | |
f6a03cbf | 720 | host->data->bytes_xfered = 0; |
ee53ab5d | 721 | |
fce14421 | 722 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
2134a922 | 723 | struct scatterlist *sg; |
df953925 | 724 | unsigned int length_mask, offset_mask; |
a0eaf0f9 | 725 | int i; |
2134a922 | 726 | |
fce14421 RK |
727 | host->flags |= SDHCI_REQ_USE_DMA; |
728 | ||
729 | /* | |
730 | * FIXME: This doesn't account for merging when mapping the | |
731 | * scatterlist. | |
732 | * | |
733 | * The assumption here being that alignment and lengths are | |
734 | * the same after DMA mapping to device address space. | |
735 | */ | |
a0eaf0f9 | 736 | length_mask = 0; |
df953925 | 737 | offset_mask = 0; |
2134a922 | 738 | if (host->flags & SDHCI_USE_ADMA) { |
df953925 | 739 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) { |
a0eaf0f9 | 740 | length_mask = 3; |
df953925 RK |
741 | /* |
742 | * As we use up to 3 byte chunks to work | |
743 | * around alignment problems, we need to | |
744 | * check the offset as well. | |
745 | */ | |
746 | offset_mask = 3; | |
747 | } | |
2134a922 PO |
748 | } else { |
749 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) | |
a0eaf0f9 | 750 | length_mask = 3; |
df953925 RK |
751 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) |
752 | offset_mask = 3; | |
2134a922 PO |
753 | } |
754 | ||
df953925 | 755 | if (unlikely(length_mask | offset_mask)) { |
2134a922 | 756 | for_each_sg(data->sg, sg, data->sg_len, i) { |
a0eaf0f9 | 757 | if (sg->length & length_mask) { |
2e4456f0 | 758 | DBG("Reverting to PIO because of transfer size (%d)\n", |
a0eaf0f9 | 759 | sg->length); |
2134a922 PO |
760 | host->flags &= ~SDHCI_REQ_USE_DMA; |
761 | break; | |
762 | } | |
a0eaf0f9 | 763 | if (sg->offset & offset_mask) { |
2e4456f0 | 764 | DBG("Reverting to PIO because of bad alignment\n"); |
2134a922 PO |
765 | host->flags &= ~SDHCI_REQ_USE_DMA; |
766 | break; | |
767 | } | |
768 | } | |
769 | } | |
770 | } | |
771 | ||
8f1934ce | 772 | if (host->flags & SDHCI_REQ_USE_DMA) { |
c0999b72 | 773 | int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED); |
60c64762 RK |
774 | |
775 | if (sg_cnt <= 0) { | |
776 | /* | |
777 | * This only happens when someone fed | |
778 | * us an invalid request. | |
779 | */ | |
780 | WARN_ON(1); | |
781 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
782 | } else if (host->flags & SDHCI_USE_ADMA) { | |
783 | sdhci_adma_table_pre(host, data, sg_cnt); | |
784 | ||
785 | sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS); | |
786 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
787 | sdhci_writel(host, | |
788 | (u64)host->adma_addr >> 32, | |
789 | SDHCI_ADMA_ADDRESS_HI); | |
8f1934ce | 790 | } else { |
60c64762 RK |
791 | WARN_ON(sg_cnt != 1); |
792 | sdhci_writel(host, sg_dma_address(data->sg), | |
793 | SDHCI_DMA_ADDRESS); | |
8f1934ce PO |
794 | } |
795 | } | |
796 | ||
2134a922 PO |
797 | /* |
798 | * Always adjust the DMA selection as some controllers | |
799 | * (e.g. JMicron) can't do PIO properly when the selection | |
800 | * is ADMA. | |
801 | */ | |
802 | if (host->version >= SDHCI_SPEC_200) { | |
4e4141a5 | 803 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
2134a922 PO |
804 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
805 | if ((host->flags & SDHCI_REQ_USE_DMA) && | |
e57a5f61 AH |
806 | (host->flags & SDHCI_USE_ADMA)) { |
807 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
808 | ctrl |= SDHCI_CTRL_ADMA64; | |
809 | else | |
810 | ctrl |= SDHCI_CTRL_ADMA32; | |
811 | } else { | |
2134a922 | 812 | ctrl |= SDHCI_CTRL_SDMA; |
e57a5f61 | 813 | } |
4e4141a5 | 814 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
c9fddbc4 PO |
815 | } |
816 | ||
8f1934ce | 817 | if (!(host->flags & SDHCI_REQ_USE_DMA)) { |
da60a91d SAS |
818 | int flags; |
819 | ||
820 | flags = SG_MITER_ATOMIC; | |
821 | if (host->data->flags & MMC_DATA_READ) | |
822 | flags |= SG_MITER_TO_SG; | |
823 | else | |
824 | flags |= SG_MITER_FROM_SG; | |
825 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
7659150c | 826 | host->blocks = data->blocks; |
d129bceb | 827 | } |
c7fa9963 | 828 | |
6aa943ab AV |
829 | sdhci_set_transfer_irqs(host); |
830 | ||
f6a03cbf MV |
831 | /* Set the DMA boundary value and block size */ |
832 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, | |
833 | data->blksz), SDHCI_BLOCK_SIZE); | |
4e4141a5 | 834 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); |
c7fa9963 PO |
835 | } |
836 | ||
837 | static void sdhci_set_transfer_mode(struct sdhci_host *host, | |
e89d456f | 838 | struct mmc_command *cmd) |
c7fa9963 | 839 | { |
d3fc5d71 | 840 | u16 mode = 0; |
e89d456f | 841 | struct mmc_data *data = cmd->data; |
c7fa9963 | 842 | |
2b558c13 | 843 | if (data == NULL) { |
9b8ffea6 VW |
844 | if (host->quirks2 & |
845 | SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) { | |
846 | sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); | |
847 | } else { | |
2b558c13 | 848 | /* clear Auto CMD settings for no data CMDs */ |
9b8ffea6 VW |
849 | mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); |
850 | sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | | |
2b558c13 | 851 | SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); |
9b8ffea6 | 852 | } |
c7fa9963 | 853 | return; |
2b558c13 | 854 | } |
c7fa9963 | 855 | |
e538fbe8 PO |
856 | WARN_ON(!host->data); |
857 | ||
d3fc5d71 VY |
858 | if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) |
859 | mode = SDHCI_TRNS_BLK_CNT_EN; | |
860 | ||
e89d456f | 861 | if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { |
d3fc5d71 | 862 | mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; |
e89d456f AW |
863 | /* |
864 | * If we are sending CMD23, CMD12 never gets sent | |
865 | * on successful completion (so no Auto-CMD12). | |
866 | */ | |
85cc1c33 CD |
867 | if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) && |
868 | (cmd->opcode != SD_IO_RW_EXTENDED)) | |
e89d456f | 869 | mode |= SDHCI_TRNS_AUTO_CMD12; |
8edf6371 AW |
870 | else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { |
871 | mode |= SDHCI_TRNS_AUTO_CMD23; | |
872 | sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); | |
873 | } | |
c4512f79 | 874 | } |
8edf6371 | 875 | |
c7fa9963 PO |
876 | if (data->flags & MMC_DATA_READ) |
877 | mode |= SDHCI_TRNS_READ; | |
c9fddbc4 | 878 | if (host->flags & SDHCI_REQ_USE_DMA) |
c7fa9963 PO |
879 | mode |= SDHCI_TRNS_DMA; |
880 | ||
4e4141a5 | 881 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
d129bceb PO |
882 | } |
883 | ||
884 | static void sdhci_finish_data(struct sdhci_host *host) | |
885 | { | |
886 | struct mmc_data *data; | |
d129bceb PO |
887 | |
888 | BUG_ON(!host->data); | |
889 | ||
890 | data = host->data; | |
891 | host->data = NULL; | |
892 | ||
add8913d RK |
893 | if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) == |
894 | (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) | |
895 | sdhci_adma_table_post(host, data); | |
d129bceb PO |
896 | |
897 | /* | |
c9b74c5b PO |
898 | * The specification states that the block count register must |
899 | * be updated, but it does not specify at what point in the | |
900 | * data flow. That makes the register entirely useless to read | |
901 | * back so we have to assume that nothing made it to the card | |
902 | * in the event of an error. | |
d129bceb | 903 | */ |
c9b74c5b PO |
904 | if (data->error) |
905 | data->bytes_xfered = 0; | |
d129bceb | 906 | else |
c9b74c5b | 907 | data->bytes_xfered = data->blksz * data->blocks; |
d129bceb | 908 | |
e89d456f AW |
909 | /* |
910 | * Need to send CMD12 if - | |
911 | * a) open-ended multiblock transfer (no CMD23) | |
912 | * b) error in multiblock transfer | |
913 | */ | |
914 | if (data->stop && | |
915 | (data->error || | |
916 | !host->mrq->sbc)) { | |
917 | ||
d129bceb PO |
918 | /* |
919 | * The controller needs a reset of internal state machines | |
920 | * upon error conditions. | |
921 | */ | |
17b0429d | 922 | if (data->error) { |
03231f9b RK |
923 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
924 | sdhci_do_reset(host, SDHCI_RESET_DATA); | |
d129bceb PO |
925 | } |
926 | ||
927 | sdhci_send_command(host, data->stop); | |
928 | } else | |
929 | tasklet_schedule(&host->finish_tasklet); | |
930 | } | |
931 | ||
c0e55129 | 932 | void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) |
d129bceb PO |
933 | { |
934 | int flags; | |
fd2208d7 | 935 | u32 mask; |
7cb2c76f | 936 | unsigned long timeout; |
d129bceb PO |
937 | |
938 | WARN_ON(host->cmd); | |
939 | ||
96776200 RK |
940 | /* Initially, a command has no error */ |
941 | cmd->error = 0; | |
942 | ||
d129bceb | 943 | /* Wait max 10 ms */ |
7cb2c76f | 944 | timeout = 10; |
fd2208d7 PO |
945 | |
946 | mask = SDHCI_CMD_INHIBIT; | |
947 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) | |
948 | mask |= SDHCI_DATA_INHIBIT; | |
949 | ||
950 | /* We shouldn't wait for data inihibit for stop commands, even | |
951 | though they might use busy signaling */ | |
952 | if (host->mrq->data && (cmd == host->mrq->data->stop)) | |
953 | mask &= ~SDHCI_DATA_INHIBIT; | |
954 | ||
4e4141a5 | 955 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
7cb2c76f | 956 | if (timeout == 0) { |
2e4456f0 MV |
957 | pr_err("%s: Controller never released inhibit bit(s).\n", |
958 | mmc_hostname(host->mmc)); | |
d129bceb | 959 | sdhci_dumpregs(host); |
17b0429d | 960 | cmd->error = -EIO; |
d129bceb PO |
961 | tasklet_schedule(&host->finish_tasklet); |
962 | return; | |
963 | } | |
7cb2c76f PO |
964 | timeout--; |
965 | mdelay(1); | |
966 | } | |
d129bceb | 967 | |
3e1a6892 | 968 | timeout = jiffies; |
1d4d7744 UH |
969 | if (!cmd->data && cmd->busy_timeout > 9000) |
970 | timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; | |
3e1a6892 AH |
971 | else |
972 | timeout += 10 * HZ; | |
973 | mod_timer(&host->timer, timeout); | |
d129bceb PO |
974 | |
975 | host->cmd = cmd; | |
e99783a4 | 976 | host->busy_handle = 0; |
d129bceb | 977 | |
a3c7778f | 978 | sdhci_prepare_data(host, cmd); |
d129bceb | 979 | |
4e4141a5 | 980 | sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); |
d129bceb | 981 | |
e89d456f | 982 | sdhci_set_transfer_mode(host, cmd); |
c7fa9963 | 983 | |
d129bceb | 984 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
a3c76eb9 | 985 | pr_err("%s: Unsupported response type!\n", |
d129bceb | 986 | mmc_hostname(host->mmc)); |
17b0429d | 987 | cmd->error = -EINVAL; |
d129bceb PO |
988 | tasklet_schedule(&host->finish_tasklet); |
989 | return; | |
990 | } | |
991 | ||
992 | if (!(cmd->flags & MMC_RSP_PRESENT)) | |
993 | flags = SDHCI_CMD_RESP_NONE; | |
994 | else if (cmd->flags & MMC_RSP_136) | |
995 | flags = SDHCI_CMD_RESP_LONG; | |
996 | else if (cmd->flags & MMC_RSP_BUSY) | |
997 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
998 | else | |
999 | flags = SDHCI_CMD_RESP_SHORT; | |
1000 | ||
1001 | if (cmd->flags & MMC_RSP_CRC) | |
1002 | flags |= SDHCI_CMD_CRC; | |
1003 | if (cmd->flags & MMC_RSP_OPCODE) | |
1004 | flags |= SDHCI_CMD_INDEX; | |
b513ea25 AN |
1005 | |
1006 | /* CMD19 is special in that the Data Present Select should be set */ | |
069c9f14 G |
1007 | if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || |
1008 | cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) | |
d129bceb PO |
1009 | flags |= SDHCI_CMD_DATA; |
1010 | ||
4e4141a5 | 1011 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); |
d129bceb | 1012 | } |
c0e55129 | 1013 | EXPORT_SYMBOL_GPL(sdhci_send_command); |
d129bceb PO |
1014 | |
1015 | static void sdhci_finish_command(struct sdhci_host *host) | |
1016 | { | |
1017 | int i; | |
1018 | ||
1019 | BUG_ON(host->cmd == NULL); | |
1020 | ||
1021 | if (host->cmd->flags & MMC_RSP_PRESENT) { | |
1022 | if (host->cmd->flags & MMC_RSP_136) { | |
1023 | /* CRC is stripped so we need to do some shifting. */ | |
1024 | for (i = 0;i < 4;i++) { | |
4e4141a5 | 1025 | host->cmd->resp[i] = sdhci_readl(host, |
d129bceb PO |
1026 | SDHCI_RESPONSE + (3-i)*4) << 8; |
1027 | if (i != 3) | |
1028 | host->cmd->resp[i] |= | |
4e4141a5 | 1029 | sdhci_readb(host, |
d129bceb PO |
1030 | SDHCI_RESPONSE + (3-i)*4-1); |
1031 | } | |
1032 | } else { | |
4e4141a5 | 1033 | host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); |
d129bceb PO |
1034 | } |
1035 | } | |
1036 | ||
e89d456f AW |
1037 | /* Finished CMD23, now send actual command. */ |
1038 | if (host->cmd == host->mrq->sbc) { | |
1039 | host->cmd = NULL; | |
1040 | sdhci_send_command(host, host->mrq->cmd); | |
1041 | } else { | |
e538fbe8 | 1042 | |
e89d456f AW |
1043 | /* Processed actual command. */ |
1044 | if (host->data && host->data_early) | |
1045 | sdhci_finish_data(host); | |
d129bceb | 1046 | |
e89d456f AW |
1047 | if (!host->cmd->data) |
1048 | tasklet_schedule(&host->finish_tasklet); | |
1049 | ||
1050 | host->cmd = NULL; | |
1051 | } | |
d129bceb PO |
1052 | } |
1053 | ||
52983382 KL |
1054 | static u16 sdhci_get_preset_value(struct sdhci_host *host) |
1055 | { | |
d975f121 | 1056 | u16 preset = 0; |
52983382 | 1057 | |
d975f121 RK |
1058 | switch (host->timing) { |
1059 | case MMC_TIMING_UHS_SDR12: | |
52983382 KL |
1060 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); |
1061 | break; | |
d975f121 | 1062 | case MMC_TIMING_UHS_SDR25: |
52983382 KL |
1063 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); |
1064 | break; | |
d975f121 | 1065 | case MMC_TIMING_UHS_SDR50: |
52983382 KL |
1066 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); |
1067 | break; | |
d975f121 RK |
1068 | case MMC_TIMING_UHS_SDR104: |
1069 | case MMC_TIMING_MMC_HS200: | |
52983382 KL |
1070 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); |
1071 | break; | |
d975f121 | 1072 | case MMC_TIMING_UHS_DDR50: |
0dafa60e | 1073 | case MMC_TIMING_MMC_DDR52: |
52983382 KL |
1074 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); |
1075 | break; | |
e9fb05d5 AH |
1076 | case MMC_TIMING_MMC_HS400: |
1077 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400); | |
1078 | break; | |
52983382 KL |
1079 | default: |
1080 | pr_warn("%s: Invalid UHS-I mode selected\n", | |
1081 | mmc_hostname(host->mmc)); | |
1082 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); | |
1083 | break; | |
1084 | } | |
1085 | return preset; | |
1086 | } | |
1087 | ||
fb9ee047 LD |
1088 | u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, |
1089 | unsigned int *actual_clock) | |
d129bceb | 1090 | { |
c3ed3877 | 1091 | int div = 0; /* Initialized for compiler warning */ |
df16219f | 1092 | int real_div = div, clk_mul = 1; |
c3ed3877 | 1093 | u16 clk = 0; |
5497159c | 1094 | bool switch_base_clk = false; |
d129bceb | 1095 | |
85105c53 | 1096 | if (host->version >= SDHCI_SPEC_300) { |
da91a8f9 | 1097 | if (host->preset_enabled) { |
52983382 KL |
1098 | u16 pre_val; |
1099 | ||
1100 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1101 | pre_val = sdhci_get_preset_value(host); | |
1102 | div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) | |
1103 | >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; | |
1104 | if (host->clk_mul && | |
1105 | (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { | |
1106 | clk = SDHCI_PROG_CLOCK_MODE; | |
1107 | real_div = div + 1; | |
1108 | clk_mul = host->clk_mul; | |
1109 | } else { | |
1110 | real_div = max_t(int, 1, div << 1); | |
1111 | } | |
1112 | goto clock_set; | |
1113 | } | |
1114 | ||
c3ed3877 AN |
1115 | /* |
1116 | * Check if the Host Controller supports Programmable Clock | |
1117 | * Mode. | |
1118 | */ | |
1119 | if (host->clk_mul) { | |
52983382 KL |
1120 | for (div = 1; div <= 1024; div++) { |
1121 | if ((host->max_clk * host->clk_mul / div) | |
1122 | <= clock) | |
1123 | break; | |
1124 | } | |
5497159c | 1125 | if ((host->max_clk * host->clk_mul / div) <= clock) { |
1126 | /* | |
1127 | * Set Programmable Clock Mode in the Clock | |
1128 | * Control register. | |
1129 | */ | |
1130 | clk = SDHCI_PROG_CLOCK_MODE; | |
1131 | real_div = div; | |
1132 | clk_mul = host->clk_mul; | |
1133 | div--; | |
1134 | } else { | |
1135 | /* | |
1136 | * Divisor can be too small to reach clock | |
1137 | * speed requirement. Then use the base clock. | |
1138 | */ | |
1139 | switch_base_clk = true; | |
1140 | } | |
1141 | } | |
1142 | ||
1143 | if (!host->clk_mul || switch_base_clk) { | |
c3ed3877 AN |
1144 | /* Version 3.00 divisors must be a multiple of 2. */ |
1145 | if (host->max_clk <= clock) | |
1146 | div = 1; | |
1147 | else { | |
1148 | for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; | |
1149 | div += 2) { | |
1150 | if ((host->max_clk / div) <= clock) | |
1151 | break; | |
1152 | } | |
85105c53 | 1153 | } |
df16219f | 1154 | real_div = div; |
c3ed3877 | 1155 | div >>= 1; |
d1955c3a SG |
1156 | if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) |
1157 | && !div && host->max_clk <= 25000000) | |
1158 | div = 1; | |
85105c53 ZG |
1159 | } |
1160 | } else { | |
1161 | /* Version 2.00 divisors must be a power of 2. */ | |
0397526d | 1162 | for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { |
85105c53 ZG |
1163 | if ((host->max_clk / div) <= clock) |
1164 | break; | |
1165 | } | |
df16219f | 1166 | real_div = div; |
c3ed3877 | 1167 | div >>= 1; |
d129bceb | 1168 | } |
d129bceb | 1169 | |
52983382 | 1170 | clock_set: |
03d6f5ff | 1171 | if (real_div) |
fb9ee047 | 1172 | *actual_clock = (host->max_clk * clk_mul) / real_div; |
c3ed3877 | 1173 | clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; |
85105c53 ZG |
1174 | clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) |
1175 | << SDHCI_DIVIDER_HI_SHIFT; | |
fb9ee047 LD |
1176 | |
1177 | return clk; | |
1178 | } | |
1179 | EXPORT_SYMBOL_GPL(sdhci_calc_clk); | |
1180 | ||
1181 | void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) | |
1182 | { | |
1183 | u16 clk; | |
1184 | unsigned long timeout; | |
1185 | ||
1186 | host->mmc->actual_clock = 0; | |
1187 | ||
1188 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); | |
fb9ee047 LD |
1189 | |
1190 | if (clock == 0) | |
1191 | return; | |
1192 | ||
1193 | clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); | |
1194 | ||
d129bceb | 1195 | clk |= SDHCI_CLOCK_INT_EN; |
4e4141a5 | 1196 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb | 1197 | |
27f6cb16 CB |
1198 | /* Wait max 20 ms */ |
1199 | timeout = 20; | |
4e4141a5 | 1200 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
7cb2c76f PO |
1201 | & SDHCI_CLOCK_INT_STABLE)) { |
1202 | if (timeout == 0) { | |
2e4456f0 MV |
1203 | pr_err("%s: Internal clock never stabilised.\n", |
1204 | mmc_hostname(host->mmc)); | |
d129bceb PO |
1205 | sdhci_dumpregs(host); |
1206 | return; | |
1207 | } | |
7cb2c76f PO |
1208 | timeout--; |
1209 | mdelay(1); | |
1210 | } | |
d129bceb PO |
1211 | |
1212 | clk |= SDHCI_CLOCK_CARD_EN; | |
4e4141a5 | 1213 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb | 1214 | } |
1771059c | 1215 | EXPORT_SYMBOL_GPL(sdhci_set_clock); |
d129bceb | 1216 | |
1dceb041 AH |
1217 | static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode, |
1218 | unsigned short vdd) | |
146ad66e | 1219 | { |
3a48edc4 | 1220 | struct mmc_host *mmc = host->mmc; |
1dceb041 AH |
1221 | |
1222 | spin_unlock_irq(&host->lock); | |
1223 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); | |
1224 | spin_lock_irq(&host->lock); | |
1225 | ||
1226 | if (mode != MMC_POWER_OFF) | |
1227 | sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL); | |
1228 | else | |
1229 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); | |
1230 | } | |
1231 | ||
1232 | void sdhci_set_power(struct sdhci_host *host, unsigned char mode, | |
1233 | unsigned short vdd) | |
1234 | { | |
8364248a | 1235 | u8 pwr = 0; |
146ad66e | 1236 | |
24fbb3ca RK |
1237 | if (mode != MMC_POWER_OFF) { |
1238 | switch (1 << vdd) { | |
ae628903 PO |
1239 | case MMC_VDD_165_195: |
1240 | pwr = SDHCI_POWER_180; | |
1241 | break; | |
1242 | case MMC_VDD_29_30: | |
1243 | case MMC_VDD_30_31: | |
1244 | pwr = SDHCI_POWER_300; | |
1245 | break; | |
1246 | case MMC_VDD_32_33: | |
1247 | case MMC_VDD_33_34: | |
1248 | pwr = SDHCI_POWER_330; | |
1249 | break; | |
1250 | default: | |
9d5de93f AH |
1251 | WARN(1, "%s: Invalid vdd %#x\n", |
1252 | mmc_hostname(host->mmc), vdd); | |
1253 | break; | |
ae628903 PO |
1254 | } |
1255 | } | |
1256 | ||
1257 | if (host->pwr == pwr) | |
e921a8b6 | 1258 | return; |
146ad66e | 1259 | |
ae628903 PO |
1260 | host->pwr = pwr; |
1261 | ||
1262 | if (pwr == 0) { | |
4e4141a5 | 1263 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
f0710a55 AH |
1264 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
1265 | sdhci_runtime_pm_bus_off(host); | |
e921a8b6 RK |
1266 | } else { |
1267 | /* | |
1268 | * Spec says that we should clear the power reg before setting | |
1269 | * a new value. Some controllers don't seem to like this though. | |
1270 | */ | |
1271 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) | |
1272 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); | |
146ad66e | 1273 | |
e921a8b6 RK |
1274 | /* |
1275 | * At least the Marvell CaFe chip gets confused if we set the | |
1276 | * voltage and set turn on power at the same time, so set the | |
1277 | * voltage first. | |
1278 | */ | |
1279 | if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) | |
1280 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); | |
e08c1694 | 1281 | |
e921a8b6 | 1282 | pwr |= SDHCI_POWER_ON; |
146ad66e | 1283 | |
e921a8b6 | 1284 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
557b0697 | 1285 | |
e921a8b6 RK |
1286 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
1287 | sdhci_runtime_pm_bus_on(host); | |
f0710a55 | 1288 | |
e921a8b6 RK |
1289 | /* |
1290 | * Some controllers need an extra 10ms delay of 10ms before | |
1291 | * they can apply clock after applying power | |
1292 | */ | |
1293 | if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) | |
1294 | mdelay(10); | |
1295 | } | |
1dceb041 AH |
1296 | } |
1297 | EXPORT_SYMBOL_GPL(sdhci_set_power); | |
918f4cbd | 1298 | |
1dceb041 AH |
1299 | static void __sdhci_set_power(struct sdhci_host *host, unsigned char mode, |
1300 | unsigned short vdd) | |
1301 | { | |
1302 | struct mmc_host *mmc = host->mmc; | |
1303 | ||
1304 | if (host->ops->set_power) | |
1305 | host->ops->set_power(host, mode, vdd); | |
1306 | else if (!IS_ERR(mmc->supply.vmmc)) | |
1307 | sdhci_set_power_reg(host, mode, vdd); | |
1308 | else | |
1309 | sdhci_set_power(host, mode, vdd); | |
146ad66e PO |
1310 | } |
1311 | ||
d129bceb PO |
1312 | /*****************************************************************************\ |
1313 | * * | |
1314 | * MMC callbacks * | |
1315 | * * | |
1316 | \*****************************************************************************/ | |
1317 | ||
1318 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1319 | { | |
1320 | struct sdhci_host *host; | |
505a8680 | 1321 | int present; |
d129bceb PO |
1322 | unsigned long flags; |
1323 | ||
1324 | host = mmc_priv(mmc); | |
1325 | ||
04e079cf | 1326 | /* Firstly check card presence */ |
8d28b7a7 | 1327 | present = mmc->ops->get_cd(mmc); |
2836766a | 1328 | |
d129bceb PO |
1329 | spin_lock_irqsave(&host->lock, flags); |
1330 | ||
1331 | WARN_ON(host->mrq != NULL); | |
1332 | ||
f9134319 | 1333 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1334 | sdhci_activate_led(host); |
2f730fec | 1335 | #endif |
e89d456f AW |
1336 | |
1337 | /* | |
1338 | * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED | |
1339 | * requests if Auto-CMD12 is enabled. | |
1340 | */ | |
1341 | if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { | |
c4512f79 JH |
1342 | if (mrq->stop) { |
1343 | mrq->data->stop = NULL; | |
1344 | mrq->stop = NULL; | |
1345 | } | |
1346 | } | |
d129bceb PO |
1347 | |
1348 | host->mrq = mrq; | |
1349 | ||
68d1fb7e | 1350 | if (!present || host->flags & SDHCI_DEVICE_DEAD) { |
17b0429d | 1351 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb | 1352 | tasklet_schedule(&host->finish_tasklet); |
cf2b5eea | 1353 | } else { |
8edf6371 | 1354 | if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) |
e89d456f AW |
1355 | sdhci_send_command(host, mrq->sbc); |
1356 | else | |
1357 | sdhci_send_command(host, mrq->cmd); | |
cf2b5eea | 1358 | } |
d129bceb | 1359 | |
5f25a66f | 1360 | mmiowb(); |
d129bceb PO |
1361 | spin_unlock_irqrestore(&host->lock, flags); |
1362 | } | |
1363 | ||
2317f56c RK |
1364 | void sdhci_set_bus_width(struct sdhci_host *host, int width) |
1365 | { | |
1366 | u8 ctrl; | |
1367 | ||
1368 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
1369 | if (width == MMC_BUS_WIDTH_8) { | |
1370 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1371 | if (host->version >= SDHCI_SPEC_300) | |
1372 | ctrl |= SDHCI_CTRL_8BITBUS; | |
1373 | } else { | |
1374 | if (host->version >= SDHCI_SPEC_300) | |
1375 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
1376 | if (width == MMC_BUS_WIDTH_4) | |
1377 | ctrl |= SDHCI_CTRL_4BITBUS; | |
1378 | else | |
1379 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1380 | } | |
1381 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
1382 | } | |
1383 | EXPORT_SYMBOL_GPL(sdhci_set_bus_width); | |
1384 | ||
96d7b78c RK |
1385 | void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) |
1386 | { | |
1387 | u16 ctrl_2; | |
1388 | ||
1389 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1390 | /* Select Bus Speed Mode for host */ | |
1391 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
1392 | if ((timing == MMC_TIMING_MMC_HS200) || | |
1393 | (timing == MMC_TIMING_UHS_SDR104)) | |
1394 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; | |
1395 | else if (timing == MMC_TIMING_UHS_SDR12) | |
1396 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; | |
1397 | else if (timing == MMC_TIMING_UHS_SDR25) | |
1398 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; | |
1399 | else if (timing == MMC_TIMING_UHS_SDR50) | |
1400 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; | |
1401 | else if ((timing == MMC_TIMING_UHS_DDR50) || | |
1402 | (timing == MMC_TIMING_MMC_DDR52)) | |
1403 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; | |
e9fb05d5 AH |
1404 | else if (timing == MMC_TIMING_MMC_HS400) |
1405 | ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ | |
96d7b78c RK |
1406 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
1407 | } | |
1408 | EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); | |
1409 | ||
66fd8ad5 | 1410 | static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) |
d129bceb | 1411 | { |
d129bceb PO |
1412 | unsigned long flags; |
1413 | u8 ctrl; | |
3a48edc4 | 1414 | struct mmc_host *mmc = host->mmc; |
d129bceb | 1415 | |
d129bceb PO |
1416 | spin_lock_irqsave(&host->lock, flags); |
1417 | ||
ceb6143b AH |
1418 | if (host->flags & SDHCI_DEVICE_DEAD) { |
1419 | spin_unlock_irqrestore(&host->lock, flags); | |
3a48edc4 TK |
1420 | if (!IS_ERR(mmc->supply.vmmc) && |
1421 | ios->power_mode == MMC_POWER_OFF) | |
4e743f1f | 1422 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); |
ceb6143b AH |
1423 | return; |
1424 | } | |
1e72859e | 1425 | |
d129bceb PO |
1426 | /* |
1427 | * Reset the chip on each power off. | |
1428 | * Should clear out any weird states. | |
1429 | */ | |
1430 | if (ios->power_mode == MMC_POWER_OFF) { | |
4e4141a5 | 1431 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
7260cf5e | 1432 | sdhci_reinit(host); |
d129bceb PO |
1433 | } |
1434 | ||
52983382 | 1435 | if (host->version >= SDHCI_SPEC_300 && |
372c4634 DA |
1436 | (ios->power_mode == MMC_POWER_UP) && |
1437 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) | |
52983382 KL |
1438 | sdhci_enable_preset_value(host, false); |
1439 | ||
373073ef | 1440 | if (!ios->clock || ios->clock != host->clock) { |
1771059c | 1441 | host->ops->set_clock(host, ios->clock); |
373073ef | 1442 | host->clock = ios->clock; |
03d6f5ff AD |
1443 | |
1444 | if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && | |
1445 | host->clock) { | |
1446 | host->timeout_clk = host->mmc->actual_clock ? | |
1447 | host->mmc->actual_clock / 1000 : | |
1448 | host->clock / 1000; | |
1449 | host->mmc->max_busy_timeout = | |
1450 | host->ops->get_max_timeout_count ? | |
1451 | host->ops->get_max_timeout_count(host) : | |
1452 | 1 << 27; | |
1453 | host->mmc->max_busy_timeout /= host->timeout_clk; | |
1454 | } | |
373073ef | 1455 | } |
d129bceb | 1456 | |
1dceb041 | 1457 | __sdhci_set_power(host, ios->power_mode, ios->vdd); |
d129bceb | 1458 | |
643a81ff PR |
1459 | if (host->ops->platform_send_init_74_clocks) |
1460 | host->ops->platform_send_init_74_clocks(host, ios->power_mode); | |
1461 | ||
2317f56c | 1462 | host->ops->set_bus_width(host, ios->bus_width); |
ae6d6c92 | 1463 | |
15ec4461 | 1464 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
cd9277c0 | 1465 | |
3ab9c8da PR |
1466 | if ((ios->timing == MMC_TIMING_SD_HS || |
1467 | ios->timing == MMC_TIMING_MMC_HS) | |
1468 | && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) | |
cd9277c0 PO |
1469 | ctrl |= SDHCI_CTRL_HISPD; |
1470 | else | |
1471 | ctrl &= ~SDHCI_CTRL_HISPD; | |
1472 | ||
d6d50a15 | 1473 | if (host->version >= SDHCI_SPEC_300) { |
49c468fc | 1474 | u16 clk, ctrl_2; |
49c468fc AN |
1475 | |
1476 | /* In case of UHS-I modes, set High Speed Enable */ | |
e9fb05d5 AH |
1477 | if ((ios->timing == MMC_TIMING_MMC_HS400) || |
1478 | (ios->timing == MMC_TIMING_MMC_HS200) || | |
bb8175a8 | 1479 | (ios->timing == MMC_TIMING_MMC_DDR52) || |
069c9f14 | 1480 | (ios->timing == MMC_TIMING_UHS_SDR50) || |
49c468fc AN |
1481 | (ios->timing == MMC_TIMING_UHS_SDR104) || |
1482 | (ios->timing == MMC_TIMING_UHS_DDR50) || | |
dd8df17f | 1483 | (ios->timing == MMC_TIMING_UHS_SDR25)) |
49c468fc | 1484 | ctrl |= SDHCI_CTRL_HISPD; |
d6d50a15 | 1485 | |
da91a8f9 | 1486 | if (!host->preset_enabled) { |
758535c4 | 1487 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d6d50a15 AN |
1488 | /* |
1489 | * We only need to set Driver Strength if the | |
1490 | * preset value enable is not set. | |
1491 | */ | |
da91a8f9 | 1492 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
d6d50a15 AN |
1493 | ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; |
1494 | if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) | |
1495 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; | |
43e943a0 PG |
1496 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B) |
1497 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; | |
d6d50a15 AN |
1498 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) |
1499 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; | |
43e943a0 PG |
1500 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D) |
1501 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D; | |
1502 | else { | |
2e4456f0 MV |
1503 | pr_warn("%s: invalid driver type, default to driver type B\n", |
1504 | mmc_hostname(mmc)); | |
43e943a0 PG |
1505 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; |
1506 | } | |
d6d50a15 AN |
1507 | |
1508 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | |
758535c4 AN |
1509 | } else { |
1510 | /* | |
1511 | * According to SDHC Spec v3.00, if the Preset Value | |
1512 | * Enable in the Host Control 2 register is set, we | |
1513 | * need to reset SD Clock Enable before changing High | |
1514 | * Speed Enable to avoid generating clock gliches. | |
1515 | */ | |
758535c4 AN |
1516 | |
1517 | /* Reset SD Clock Enable */ | |
1518 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1519 | clk &= ~SDHCI_CLOCK_CARD_EN; | |
1520 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
1521 | ||
1522 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
1523 | ||
1524 | /* Re-enable SD Clock */ | |
1771059c | 1525 | host->ops->set_clock(host, host->clock); |
d6d50a15 | 1526 | } |
49c468fc | 1527 | |
49c468fc AN |
1528 | /* Reset SD Clock Enable */ |
1529 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1530 | clk &= ~SDHCI_CLOCK_CARD_EN; | |
1531 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
1532 | ||
96d7b78c | 1533 | host->ops->set_uhs_signaling(host, ios->timing); |
d975f121 | 1534 | host->timing = ios->timing; |
49c468fc | 1535 | |
52983382 KL |
1536 | if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && |
1537 | ((ios->timing == MMC_TIMING_UHS_SDR12) || | |
1538 | (ios->timing == MMC_TIMING_UHS_SDR25) || | |
1539 | (ios->timing == MMC_TIMING_UHS_SDR50) || | |
1540 | (ios->timing == MMC_TIMING_UHS_SDR104) || | |
0dafa60e JZ |
1541 | (ios->timing == MMC_TIMING_UHS_DDR50) || |
1542 | (ios->timing == MMC_TIMING_MMC_DDR52))) { | |
52983382 KL |
1543 | u16 preset; |
1544 | ||
1545 | sdhci_enable_preset_value(host, true); | |
1546 | preset = sdhci_get_preset_value(host); | |
1547 | ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) | |
1548 | >> SDHCI_PRESET_DRV_SHIFT; | |
1549 | } | |
1550 | ||
49c468fc | 1551 | /* Re-enable SD Clock */ |
1771059c | 1552 | host->ops->set_clock(host, host->clock); |
758535c4 AN |
1553 | } else |
1554 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
d6d50a15 | 1555 | |
b8352260 LD |
1556 | /* |
1557 | * Some (ENE) controllers go apeshit on some ios operation, | |
1558 | * signalling timeout and CRC errors even on CMD0. Resetting | |
1559 | * it on each ios seems to solve the problem. | |
1560 | */ | |
c63705e1 | 1561 | if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
03231f9b | 1562 | sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
b8352260 | 1563 | |
5f25a66f | 1564 | mmiowb(); |
d129bceb PO |
1565 | spin_unlock_irqrestore(&host->lock, flags); |
1566 | } | |
1567 | ||
66fd8ad5 AH |
1568 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
1569 | { | |
1570 | struct sdhci_host *host = mmc_priv(mmc); | |
1571 | ||
66fd8ad5 | 1572 | sdhci_do_set_ios(host, ios); |
66fd8ad5 AH |
1573 | } |
1574 | ||
94144a46 KL |
1575 | static int sdhci_do_get_cd(struct sdhci_host *host) |
1576 | { | |
1577 | int gpio_cd = mmc_gpio_get_cd(host->mmc); | |
1578 | ||
1579 | if (host->flags & SDHCI_DEVICE_DEAD) | |
1580 | return 0; | |
1581 | ||
88af5655 II |
1582 | /* If nonremovable, assume that the card is always present. */ |
1583 | if (host->mmc->caps & MMC_CAP_NONREMOVABLE) | |
94144a46 KL |
1584 | return 1; |
1585 | ||
88af5655 II |
1586 | /* |
1587 | * Try slot gpio detect, if defined it take precedence | |
1588 | * over build in controller functionality | |
1589 | */ | |
94144a46 KL |
1590 | if (!IS_ERR_VALUE(gpio_cd)) |
1591 | return !!gpio_cd; | |
1592 | ||
88af5655 II |
1593 | /* If polling, assume that the card is always present. */ |
1594 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) | |
1595 | return 1; | |
1596 | ||
94144a46 KL |
1597 | /* Host native card detect */ |
1598 | return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); | |
1599 | } | |
1600 | ||
1601 | static int sdhci_get_cd(struct mmc_host *mmc) | |
1602 | { | |
1603 | struct sdhci_host *host = mmc_priv(mmc); | |
94144a46 | 1604 | |
15e82076 | 1605 | return sdhci_do_get_cd(host); |
94144a46 KL |
1606 | } |
1607 | ||
66fd8ad5 | 1608 | static int sdhci_check_ro(struct sdhci_host *host) |
d129bceb | 1609 | { |
d129bceb | 1610 | unsigned long flags; |
2dfb579c | 1611 | int is_readonly; |
d129bceb | 1612 | |
d129bceb PO |
1613 | spin_lock_irqsave(&host->lock, flags); |
1614 | ||
1e72859e | 1615 | if (host->flags & SDHCI_DEVICE_DEAD) |
2dfb579c WS |
1616 | is_readonly = 0; |
1617 | else if (host->ops->get_ro) | |
1618 | is_readonly = host->ops->get_ro(host); | |
1e72859e | 1619 | else |
2dfb579c WS |
1620 | is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) |
1621 | & SDHCI_WRITE_PROTECT); | |
d129bceb PO |
1622 | |
1623 | spin_unlock_irqrestore(&host->lock, flags); | |
1624 | ||
2dfb579c WS |
1625 | /* This quirk needs to be replaced by a callback-function later */ |
1626 | return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? | |
1627 | !is_readonly : is_readonly; | |
d129bceb PO |
1628 | } |
1629 | ||
82b0e23a TI |
1630 | #define SAMPLE_COUNT 5 |
1631 | ||
66fd8ad5 | 1632 | static int sdhci_do_get_ro(struct sdhci_host *host) |
82b0e23a | 1633 | { |
82b0e23a TI |
1634 | int i, ro_count; |
1635 | ||
82b0e23a | 1636 | if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) |
66fd8ad5 | 1637 | return sdhci_check_ro(host); |
82b0e23a TI |
1638 | |
1639 | ro_count = 0; | |
1640 | for (i = 0; i < SAMPLE_COUNT; i++) { | |
66fd8ad5 | 1641 | if (sdhci_check_ro(host)) { |
82b0e23a TI |
1642 | if (++ro_count > SAMPLE_COUNT / 2) |
1643 | return 1; | |
1644 | } | |
1645 | msleep(30); | |
1646 | } | |
1647 | return 0; | |
1648 | } | |
1649 | ||
20758b66 AH |
1650 | static void sdhci_hw_reset(struct mmc_host *mmc) |
1651 | { | |
1652 | struct sdhci_host *host = mmc_priv(mmc); | |
1653 | ||
1654 | if (host->ops && host->ops->hw_reset) | |
1655 | host->ops->hw_reset(host); | |
1656 | } | |
1657 | ||
66fd8ad5 | 1658 | static int sdhci_get_ro(struct mmc_host *mmc) |
f75979b7 | 1659 | { |
66fd8ad5 | 1660 | struct sdhci_host *host = mmc_priv(mmc); |
f75979b7 | 1661 | |
15e82076 | 1662 | return sdhci_do_get_ro(host); |
66fd8ad5 | 1663 | } |
f75979b7 | 1664 | |
66fd8ad5 AH |
1665 | static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) |
1666 | { | |
be138554 | 1667 | if (!(host->flags & SDHCI_DEVICE_DEAD)) { |
ef104333 | 1668 | if (enable) |
b537f94c | 1669 | host->ier |= SDHCI_INT_CARD_INT; |
ef104333 | 1670 | else |
b537f94c RK |
1671 | host->ier &= ~SDHCI_INT_CARD_INT; |
1672 | ||
1673 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
1674 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
ef104333 RK |
1675 | mmiowb(); |
1676 | } | |
66fd8ad5 AH |
1677 | } |
1678 | ||
1679 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) | |
1680 | { | |
1681 | struct sdhci_host *host = mmc_priv(mmc); | |
1682 | unsigned long flags; | |
f75979b7 | 1683 | |
66fd8ad5 | 1684 | spin_lock_irqsave(&host->lock, flags); |
ef104333 RK |
1685 | if (enable) |
1686 | host->flags |= SDHCI_SDIO_IRQ_ENABLED; | |
1687 | else | |
1688 | host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; | |
1689 | ||
66fd8ad5 | 1690 | sdhci_enable_sdio_irq_nolock(host, enable); |
f75979b7 PO |
1691 | spin_unlock_irqrestore(&host->lock, flags); |
1692 | } | |
1693 | ||
20b92a30 | 1694 | static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, |
21f5998f | 1695 | struct mmc_ios *ios) |
f2119df6 | 1696 | { |
3a48edc4 | 1697 | struct mmc_host *mmc = host->mmc; |
20b92a30 | 1698 | u16 ctrl; |
6231f3de | 1699 | int ret; |
f2119df6 | 1700 | |
20b92a30 KL |
1701 | /* |
1702 | * Signal Voltage Switching is only applicable for Host Controllers | |
1703 | * v3.00 and above. | |
1704 | */ | |
1705 | if (host->version < SDHCI_SPEC_300) | |
1706 | return 0; | |
6231f3de | 1707 | |
f2119df6 | 1708 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
f2119df6 | 1709 | |
21f5998f | 1710 | switch (ios->signal_voltage) { |
20b92a30 KL |
1711 | case MMC_SIGNAL_VOLTAGE_330: |
1712 | /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ | |
1713 | ctrl &= ~SDHCI_CTRL_VDD_180; | |
1714 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
f2119df6 | 1715 | |
3a48edc4 TK |
1716 | if (!IS_ERR(mmc->supply.vqmmc)) { |
1717 | ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000, | |
1718 | 3600000); | |
20b92a30 | 1719 | if (ret) { |
6606110d JP |
1720 | pr_warn("%s: Switching to 3.3V signalling voltage failed\n", |
1721 | mmc_hostname(mmc)); | |
20b92a30 KL |
1722 | return -EIO; |
1723 | } | |
1724 | } | |
1725 | /* Wait for 5ms */ | |
1726 | usleep_range(5000, 5500); | |
f2119df6 | 1727 | |
20b92a30 KL |
1728 | /* 3.3V regulator output should be stable within 5 ms */ |
1729 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1730 | if (!(ctrl & SDHCI_CTRL_VDD_180)) | |
1731 | return 0; | |
6231f3de | 1732 | |
6606110d JP |
1733 | pr_warn("%s: 3.3V regulator output did not became stable\n", |
1734 | mmc_hostname(mmc)); | |
20b92a30 KL |
1735 | |
1736 | return -EAGAIN; | |
1737 | case MMC_SIGNAL_VOLTAGE_180: | |
3a48edc4 TK |
1738 | if (!IS_ERR(mmc->supply.vqmmc)) { |
1739 | ret = regulator_set_voltage(mmc->supply.vqmmc, | |
20b92a30 KL |
1740 | 1700000, 1950000); |
1741 | if (ret) { | |
6606110d JP |
1742 | pr_warn("%s: Switching to 1.8V signalling voltage failed\n", |
1743 | mmc_hostname(mmc)); | |
20b92a30 KL |
1744 | return -EIO; |
1745 | } | |
1746 | } | |
6231f3de | 1747 | |
6231f3de PR |
1748 | /* |
1749 | * Enable 1.8V Signal Enable in the Host Control2 | |
1750 | * register | |
1751 | */ | |
20b92a30 KL |
1752 | ctrl |= SDHCI_CTRL_VDD_180; |
1753 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
6231f3de | 1754 | |
9d967a61 VY |
1755 | /* Some controller need to do more when switching */ |
1756 | if (host->ops->voltage_switch) | |
1757 | host->ops->voltage_switch(host); | |
1758 | ||
20b92a30 KL |
1759 | /* 1.8V regulator output should be stable within 5 ms */ |
1760 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1761 | if (ctrl & SDHCI_CTRL_VDD_180) | |
1762 | return 0; | |
f2119df6 | 1763 | |
6606110d JP |
1764 | pr_warn("%s: 1.8V regulator output did not became stable\n", |
1765 | mmc_hostname(mmc)); | |
f2119df6 | 1766 | |
20b92a30 KL |
1767 | return -EAGAIN; |
1768 | case MMC_SIGNAL_VOLTAGE_120: | |
3a48edc4 TK |
1769 | if (!IS_ERR(mmc->supply.vqmmc)) { |
1770 | ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000, | |
1771 | 1300000); | |
20b92a30 | 1772 | if (ret) { |
6606110d JP |
1773 | pr_warn("%s: Switching to 1.2V signalling voltage failed\n", |
1774 | mmc_hostname(mmc)); | |
20b92a30 | 1775 | return -EIO; |
f2119df6 AN |
1776 | } |
1777 | } | |
6231f3de | 1778 | return 0; |
20b92a30 | 1779 | default: |
f2119df6 AN |
1780 | /* No signal voltage switch required */ |
1781 | return 0; | |
20b92a30 | 1782 | } |
f2119df6 AN |
1783 | } |
1784 | ||
66fd8ad5 | 1785 | static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, |
21f5998f | 1786 | struct mmc_ios *ios) |
66fd8ad5 AH |
1787 | { |
1788 | struct sdhci_host *host = mmc_priv(mmc); | |
66fd8ad5 AH |
1789 | |
1790 | if (host->version < SDHCI_SPEC_300) | |
1791 | return 0; | |
15e82076 UH |
1792 | |
1793 | return sdhci_do_start_signal_voltage_switch(host, ios); | |
66fd8ad5 AH |
1794 | } |
1795 | ||
20b92a30 KL |
1796 | static int sdhci_card_busy(struct mmc_host *mmc) |
1797 | { | |
1798 | struct sdhci_host *host = mmc_priv(mmc); | |
1799 | u32 present_state; | |
1800 | ||
20b92a30 KL |
1801 | /* Check whether DAT[3:0] is 0000 */ |
1802 | present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
20b92a30 KL |
1803 | |
1804 | return !(present_state & SDHCI_DATA_LVL_MASK); | |
1805 | } | |
1806 | ||
b5540ce1 AH |
1807 | static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) |
1808 | { | |
1809 | struct sdhci_host *host = mmc_priv(mmc); | |
1810 | unsigned long flags; | |
1811 | ||
1812 | spin_lock_irqsave(&host->lock, flags); | |
1813 | host->flags |= SDHCI_HS400_TUNING; | |
1814 | spin_unlock_irqrestore(&host->lock, flags); | |
1815 | ||
1816 | return 0; | |
1817 | } | |
1818 | ||
069c9f14 | 1819 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) |
b513ea25 | 1820 | { |
4b6f37d3 | 1821 | struct sdhci_host *host = mmc_priv(mmc); |
b513ea25 | 1822 | u16 ctrl; |
b513ea25 | 1823 | int tuning_loop_counter = MAX_TUNING_LOOP; |
b513ea25 | 1824 | int err = 0; |
2b35bd83 | 1825 | unsigned long flags; |
38e40bf5 | 1826 | unsigned int tuning_count = 0; |
b5540ce1 | 1827 | bool hs400_tuning; |
b513ea25 | 1828 | |
2b35bd83 | 1829 | spin_lock_irqsave(&host->lock, flags); |
b513ea25 | 1830 | |
b5540ce1 AH |
1831 | hs400_tuning = host->flags & SDHCI_HS400_TUNING; |
1832 | host->flags &= ~SDHCI_HS400_TUNING; | |
1833 | ||
38e40bf5 AH |
1834 | if (host->tuning_mode == SDHCI_TUNING_MODE_1) |
1835 | tuning_count = host->tuning_count; | |
1836 | ||
b513ea25 | 1837 | /* |
9faac7b9 WY |
1838 | * The Host Controller needs tuning in case of SDR104 and DDR50 |
1839 | * mode, and for SDR50 mode when Use Tuning for SDR50 is set in | |
1840 | * the Capabilities register. | |
069c9f14 G |
1841 | * If the Host Controller supports the HS200 mode then the |
1842 | * tuning function has to be executed. | |
b513ea25 | 1843 | */ |
4b6f37d3 | 1844 | switch (host->timing) { |
b5540ce1 | 1845 | /* HS400 tuning is done in HS200 mode */ |
e9fb05d5 | 1846 | case MMC_TIMING_MMC_HS400: |
b5540ce1 AH |
1847 | err = -EINVAL; |
1848 | goto out_unlock; | |
1849 | ||
4b6f37d3 | 1850 | case MMC_TIMING_MMC_HS200: |
b5540ce1 AH |
1851 | /* |
1852 | * Periodic re-tuning for HS400 is not expected to be needed, so | |
1853 | * disable it here. | |
1854 | */ | |
1855 | if (hs400_tuning) | |
1856 | tuning_count = 0; | |
1857 | break; | |
1858 | ||
4b6f37d3 | 1859 | case MMC_TIMING_UHS_SDR104: |
9faac7b9 | 1860 | case MMC_TIMING_UHS_DDR50: |
4b6f37d3 RK |
1861 | break; |
1862 | ||
1863 | case MMC_TIMING_UHS_SDR50: | |
1864 | if (host->flags & SDHCI_SDR50_NEEDS_TUNING || | |
1865 | host->flags & SDHCI_SDR104_NEEDS_TUNING) | |
1866 | break; | |
1867 | /* FALLTHROUGH */ | |
1868 | ||
1869 | default: | |
d519c863 | 1870 | goto out_unlock; |
b513ea25 AN |
1871 | } |
1872 | ||
45251812 | 1873 | if (host->ops->platform_execute_tuning) { |
2b35bd83 | 1874 | spin_unlock_irqrestore(&host->lock, flags); |
45251812 | 1875 | err = host->ops->platform_execute_tuning(host, opcode); |
45251812 DA |
1876 | return err; |
1877 | } | |
1878 | ||
4b6f37d3 RK |
1879 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
1880 | ctrl |= SDHCI_CTRL_EXEC_TUNING; | |
67d0d04a VY |
1881 | if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND) |
1882 | ctrl |= SDHCI_CTRL_TUNED_CLK; | |
b513ea25 AN |
1883 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
1884 | ||
1885 | /* | |
1886 | * As per the Host Controller spec v3.00, tuning command | |
1887 | * generates Buffer Read Ready interrupt, so enable that. | |
1888 | * | |
1889 | * Note: The spec clearly says that when tuning sequence | |
1890 | * is being performed, the controller does not generate | |
1891 | * interrupts other than Buffer Read Ready interrupt. But | |
1892 | * to make sure we don't hit a controller bug, we _only_ | |
1893 | * enable Buffer Read Ready interrupt here. | |
1894 | */ | |
b537f94c RK |
1895 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); |
1896 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); | |
b513ea25 AN |
1897 | |
1898 | /* | |
1899 | * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number | |
1900 | * of loops reaches 40 times or a timeout of 150ms occurs. | |
1901 | */ | |
b513ea25 AN |
1902 | do { |
1903 | struct mmc_command cmd = {0}; | |
66fd8ad5 | 1904 | struct mmc_request mrq = {NULL}; |
b513ea25 | 1905 | |
069c9f14 | 1906 | cmd.opcode = opcode; |
b513ea25 AN |
1907 | cmd.arg = 0; |
1908 | cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; | |
1909 | cmd.retries = 0; | |
1910 | cmd.data = NULL; | |
1911 | cmd.error = 0; | |
1912 | ||
7ce45e95 AC |
1913 | if (tuning_loop_counter-- == 0) |
1914 | break; | |
1915 | ||
b513ea25 AN |
1916 | mrq.cmd = &cmd; |
1917 | host->mrq = &mrq; | |
1918 | ||
1919 | /* | |
1920 | * In response to CMD19, the card sends 64 bytes of tuning | |
1921 | * block to the Host Controller. So we set the block size | |
1922 | * to 64 here. | |
1923 | */ | |
069c9f14 G |
1924 | if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { |
1925 | if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
1926 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), | |
1927 | SDHCI_BLOCK_SIZE); | |
1928 | else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) | |
1929 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), | |
1930 | SDHCI_BLOCK_SIZE); | |
1931 | } else { | |
1932 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), | |
1933 | SDHCI_BLOCK_SIZE); | |
1934 | } | |
b513ea25 AN |
1935 | |
1936 | /* | |
1937 | * The tuning block is sent by the card to the host controller. | |
1938 | * So we set the TRNS_READ bit in the Transfer Mode register. | |
1939 | * This also takes care of setting DMA Enable and Multi Block | |
1940 | * Select in the same register to 0. | |
1941 | */ | |
1942 | sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); | |
1943 | ||
1944 | sdhci_send_command(host, &cmd); | |
1945 | ||
1946 | host->cmd = NULL; | |
1947 | host->mrq = NULL; | |
1948 | ||
2b35bd83 | 1949 | spin_unlock_irqrestore(&host->lock, flags); |
b513ea25 AN |
1950 | /* Wait for Buffer Read Ready interrupt */ |
1951 | wait_event_interruptible_timeout(host->buf_ready_int, | |
1952 | (host->tuning_done == 1), | |
1953 | msecs_to_jiffies(50)); | |
2b35bd83 | 1954 | spin_lock_irqsave(&host->lock, flags); |
b513ea25 AN |
1955 | |
1956 | if (!host->tuning_done) { | |
2e4456f0 | 1957 | pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n"); |
b513ea25 AN |
1958 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
1959 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; | |
1960 | ctrl &= ~SDHCI_CTRL_EXEC_TUNING; | |
1961 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
1962 | ||
1963 | err = -EIO; | |
1964 | goto out; | |
1965 | } | |
1966 | ||
1967 | host->tuning_done = 0; | |
1968 | ||
1969 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
197160d5 NS |
1970 | |
1971 | /* eMMC spec does not require a delay between tuning cycles */ | |
1972 | if (opcode == MMC_SEND_TUNING_BLOCK) | |
1973 | mdelay(1); | |
b513ea25 AN |
1974 | } while (ctrl & SDHCI_CTRL_EXEC_TUNING); |
1975 | ||
1976 | /* | |
1977 | * The Host Driver has exhausted the maximum number of loops allowed, | |
1978 | * so use fixed sampling frequency. | |
1979 | */ | |
7ce45e95 | 1980 | if (tuning_loop_counter < 0) { |
b513ea25 AN |
1981 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; |
1982 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
7ce45e95 AC |
1983 | } |
1984 | if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { | |
2e4456f0 | 1985 | pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n"); |
114f2bf6 | 1986 | err = -EIO; |
b513ea25 AN |
1987 | } |
1988 | ||
1989 | out: | |
38e40bf5 | 1990 | if (tuning_count) { |
66c39dfc AH |
1991 | /* |
1992 | * In case tuning fails, host controllers which support | |
1993 | * re-tuning can try tuning again at a later time, when the | |
1994 | * re-tuning timer expires. So for these controllers, we | |
1995 | * return 0. Since there might be other controllers who do not | |
1996 | * have this capability, we return error for them. | |
1997 | */ | |
1998 | err = 0; | |
cf2b5eea AN |
1999 | } |
2000 | ||
66c39dfc | 2001 | host->mmc->retune_period = err ? 0 : tuning_count; |
cf2b5eea | 2002 | |
b537f94c RK |
2003 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
2004 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
d519c863 | 2005 | out_unlock: |
2b35bd83 | 2006 | spin_unlock_irqrestore(&host->lock, flags); |
b513ea25 AN |
2007 | return err; |
2008 | } | |
2009 | ||
cb849648 AH |
2010 | static int sdhci_select_drive_strength(struct mmc_card *card, |
2011 | unsigned int max_dtr, int host_drv, | |
2012 | int card_drv, int *drv_type) | |
2013 | { | |
2014 | struct sdhci_host *host = mmc_priv(card->host); | |
2015 | ||
2016 | if (!host->ops->select_drive_strength) | |
2017 | return 0; | |
2018 | ||
2019 | return host->ops->select_drive_strength(host, card, max_dtr, host_drv, | |
2020 | card_drv, drv_type); | |
2021 | } | |
52983382 KL |
2022 | |
2023 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) | |
4d55c5a1 | 2024 | { |
4d55c5a1 AN |
2025 | /* Host Controller v3.00 defines preset value registers */ |
2026 | if (host->version < SDHCI_SPEC_300) | |
2027 | return; | |
2028 | ||
4d55c5a1 AN |
2029 | /* |
2030 | * We only enable or disable Preset Value if they are not already | |
2031 | * enabled or disabled respectively. Otherwise, we bail out. | |
2032 | */ | |
da91a8f9 RK |
2033 | if (host->preset_enabled != enable) { |
2034 | u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
2035 | ||
2036 | if (enable) | |
2037 | ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; | |
2038 | else | |
2039 | ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; | |
2040 | ||
4d55c5a1 | 2041 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
da91a8f9 RK |
2042 | |
2043 | if (enable) | |
2044 | host->flags |= SDHCI_PV_ENABLED; | |
2045 | else | |
2046 | host->flags &= ~SDHCI_PV_ENABLED; | |
2047 | ||
2048 | host->preset_enabled = enable; | |
4d55c5a1 | 2049 | } |
66fd8ad5 AH |
2050 | } |
2051 | ||
348487cb HC |
2052 | static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, |
2053 | int err) | |
2054 | { | |
2055 | struct sdhci_host *host = mmc_priv(mmc); | |
2056 | struct mmc_data *data = mrq->data; | |
2057 | ||
f48f039c | 2058 | if (data->host_cookie != COOKIE_UNMAPPED) |
771a3dc2 RK |
2059 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, |
2060 | data->flags & MMC_DATA_WRITE ? | |
2061 | DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
2062 | ||
2063 | data->host_cookie = COOKIE_UNMAPPED; | |
348487cb HC |
2064 | } |
2065 | ||
348487cb HC |
2066 | static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, |
2067 | bool is_first_req) | |
2068 | { | |
2069 | struct sdhci_host *host = mmc_priv(mmc); | |
2070 | ||
d31911b9 | 2071 | mrq->data->host_cookie = COOKIE_UNMAPPED; |
348487cb HC |
2072 | |
2073 | if (host->flags & SDHCI_REQ_USE_DMA) | |
94538e51 | 2074 | sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED); |
348487cb HC |
2075 | } |
2076 | ||
71e69211 | 2077 | static void sdhci_card_event(struct mmc_host *mmc) |
d129bceb | 2078 | { |
71e69211 | 2079 | struct sdhci_host *host = mmc_priv(mmc); |
d129bceb | 2080 | unsigned long flags; |
2836766a | 2081 | int present; |
d129bceb | 2082 | |
722e1280 CD |
2083 | /* First check if client has provided their own card event */ |
2084 | if (host->ops->card_event) | |
2085 | host->ops->card_event(host); | |
2086 | ||
2836766a KK |
2087 | present = sdhci_do_get_cd(host); |
2088 | ||
d129bceb PO |
2089 | spin_lock_irqsave(&host->lock, flags); |
2090 | ||
66fd8ad5 | 2091 | /* Check host->mrq first in case we are runtime suspended */ |
2836766a | 2092 | if (host->mrq && !present) { |
a3c76eb9 | 2093 | pr_err("%s: Card removed during transfer!\n", |
66fd8ad5 | 2094 | mmc_hostname(host->mmc)); |
a3c76eb9 | 2095 | pr_err("%s: Resetting controller.\n", |
66fd8ad5 | 2096 | mmc_hostname(host->mmc)); |
d129bceb | 2097 | |
03231f9b RK |
2098 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
2099 | sdhci_do_reset(host, SDHCI_RESET_DATA); | |
d129bceb | 2100 | |
66fd8ad5 AH |
2101 | host->mrq->cmd->error = -ENOMEDIUM; |
2102 | tasklet_schedule(&host->finish_tasklet); | |
d129bceb PO |
2103 | } |
2104 | ||
2105 | spin_unlock_irqrestore(&host->lock, flags); | |
71e69211 GL |
2106 | } |
2107 | ||
2108 | static const struct mmc_host_ops sdhci_ops = { | |
2109 | .request = sdhci_request, | |
348487cb HC |
2110 | .post_req = sdhci_post_req, |
2111 | .pre_req = sdhci_pre_req, | |
71e69211 | 2112 | .set_ios = sdhci_set_ios, |
94144a46 | 2113 | .get_cd = sdhci_get_cd, |
71e69211 GL |
2114 | .get_ro = sdhci_get_ro, |
2115 | .hw_reset = sdhci_hw_reset, | |
2116 | .enable_sdio_irq = sdhci_enable_sdio_irq, | |
2117 | .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, | |
b5540ce1 | 2118 | .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, |
71e69211 | 2119 | .execute_tuning = sdhci_execute_tuning, |
cb849648 | 2120 | .select_drive_strength = sdhci_select_drive_strength, |
71e69211 | 2121 | .card_event = sdhci_card_event, |
20b92a30 | 2122 | .card_busy = sdhci_card_busy, |
71e69211 GL |
2123 | }; |
2124 | ||
2125 | /*****************************************************************************\ | |
2126 | * * | |
2127 | * Tasklets * | |
2128 | * * | |
2129 | \*****************************************************************************/ | |
2130 | ||
d129bceb PO |
2131 | static void sdhci_tasklet_finish(unsigned long param) |
2132 | { | |
2133 | struct sdhci_host *host; | |
2134 | unsigned long flags; | |
2135 | struct mmc_request *mrq; | |
2136 | ||
2137 | host = (struct sdhci_host*)param; | |
2138 | ||
66fd8ad5 AH |
2139 | spin_lock_irqsave(&host->lock, flags); |
2140 | ||
0c9c99a7 CB |
2141 | /* |
2142 | * If this tasklet gets rescheduled while running, it will | |
2143 | * be run again afterwards but without any active request. | |
2144 | */ | |
66fd8ad5 AH |
2145 | if (!host->mrq) { |
2146 | spin_unlock_irqrestore(&host->lock, flags); | |
0c9c99a7 | 2147 | return; |
66fd8ad5 | 2148 | } |
d129bceb PO |
2149 | |
2150 | del_timer(&host->timer); | |
2151 | ||
2152 | mrq = host->mrq; | |
2153 | ||
054cedff RK |
2154 | /* |
2155 | * Always unmap the data buffers if they were mapped by | |
2156 | * sdhci_prepare_data() whenever we finish with a request. | |
2157 | * This avoids leaking DMA mappings on error. | |
2158 | */ | |
2159 | if (host->flags & SDHCI_REQ_USE_DMA) { | |
2160 | struct mmc_data *data = mrq->data; | |
2161 | ||
2162 | if (data && data->host_cookie == COOKIE_MAPPED) { | |
2163 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, | |
2164 | (data->flags & MMC_DATA_READ) ? | |
2165 | DMA_FROM_DEVICE : DMA_TO_DEVICE); | |
2166 | data->host_cookie = COOKIE_UNMAPPED; | |
2167 | } | |
2168 | } | |
2169 | ||
d129bceb PO |
2170 | /* |
2171 | * The controller needs a reset of internal state machines | |
2172 | * upon error conditions. | |
2173 | */ | |
1e72859e | 2174 | if (!(host->flags & SDHCI_DEVICE_DEAD) && |
b7b4d342 | 2175 | ((mrq->cmd && mrq->cmd->error) || |
fce9d33f AG |
2176 | (mrq->sbc && mrq->sbc->error) || |
2177 | (mrq->data && ((mrq->data->error && !mrq->data->stop) || | |
2178 | (mrq->data->stop && mrq->data->stop->error))) || | |
2179 | (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { | |
645289dc PO |
2180 | |
2181 | /* Some controllers need this kick or reset won't work here */ | |
8213af3b | 2182 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) |
645289dc | 2183 | /* This is to force an update */ |
1771059c | 2184 | host->ops->set_clock(host, host->clock); |
645289dc PO |
2185 | |
2186 | /* Spec says we should do both at the same time, but Ricoh | |
2187 | controllers do not like that. */ | |
03231f9b RK |
2188 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
2189 | sdhci_do_reset(host, SDHCI_RESET_DATA); | |
d129bceb PO |
2190 | } |
2191 | ||
2192 | host->mrq = NULL; | |
2193 | host->cmd = NULL; | |
2194 | host->data = NULL; | |
2195 | ||
f9134319 | 2196 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 2197 | sdhci_deactivate_led(host); |
2f730fec | 2198 | #endif |
d129bceb | 2199 | |
5f25a66f | 2200 | mmiowb(); |
d129bceb PO |
2201 | spin_unlock_irqrestore(&host->lock, flags); |
2202 | ||
2203 | mmc_request_done(host->mmc, mrq); | |
2204 | } | |
2205 | ||
2206 | static void sdhci_timeout_timer(unsigned long data) | |
2207 | { | |
2208 | struct sdhci_host *host; | |
2209 | unsigned long flags; | |
2210 | ||
2211 | host = (struct sdhci_host*)data; | |
2212 | ||
2213 | spin_lock_irqsave(&host->lock, flags); | |
2214 | ||
2215 | if (host->mrq) { | |
2e4456f0 MV |
2216 | pr_err("%s: Timeout waiting for hardware interrupt.\n", |
2217 | mmc_hostname(host->mmc)); | |
d129bceb PO |
2218 | sdhci_dumpregs(host); |
2219 | ||
2220 | if (host->data) { | |
17b0429d | 2221 | host->data->error = -ETIMEDOUT; |
d129bceb PO |
2222 | sdhci_finish_data(host); |
2223 | } else { | |
2224 | if (host->cmd) | |
17b0429d | 2225 | host->cmd->error = -ETIMEDOUT; |
d129bceb | 2226 | else |
17b0429d | 2227 | host->mrq->cmd->error = -ETIMEDOUT; |
d129bceb PO |
2228 | |
2229 | tasklet_schedule(&host->finish_tasklet); | |
2230 | } | |
2231 | } | |
2232 | ||
5f25a66f | 2233 | mmiowb(); |
d129bceb PO |
2234 | spin_unlock_irqrestore(&host->lock, flags); |
2235 | } | |
2236 | ||
2237 | /*****************************************************************************\ | |
2238 | * * | |
2239 | * Interrupt handling * | |
2240 | * * | |
2241 | \*****************************************************************************/ | |
2242 | ||
61541397 | 2243 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask) |
d129bceb PO |
2244 | { |
2245 | BUG_ON(intmask == 0); | |
2246 | ||
2247 | if (!host->cmd) { | |
2e4456f0 MV |
2248 | pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n", |
2249 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
2250 | sdhci_dumpregs(host); |
2251 | return; | |
2252 | } | |
2253 | ||
ec014cba RK |
2254 | if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | |
2255 | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) { | |
2256 | if (intmask & SDHCI_INT_TIMEOUT) | |
2257 | host->cmd->error = -ETIMEDOUT; | |
2258 | else | |
2259 | host->cmd->error = -EILSEQ; | |
43b58b36 | 2260 | |
71fcbda0 RK |
2261 | /* |
2262 | * If this command initiates a data phase and a response | |
2263 | * CRC error is signalled, the card can start transferring | |
2264 | * data - the card may have received the command without | |
2265 | * error. We must not terminate the mmc_request early. | |
2266 | * | |
2267 | * If the card did not receive the command or returned an | |
2268 | * error which prevented it sending data, the data phase | |
2269 | * will time out. | |
2270 | */ | |
2271 | if (host->cmd->data && | |
2272 | (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) == | |
2273 | SDHCI_INT_CRC) { | |
2274 | host->cmd = NULL; | |
2275 | return; | |
2276 | } | |
2277 | ||
d129bceb | 2278 | tasklet_schedule(&host->finish_tasklet); |
e809517f PO |
2279 | return; |
2280 | } | |
2281 | ||
2282 | /* | |
2283 | * The host can send and interrupt when the busy state has | |
2284 | * ended, allowing us to wait without wasting CPU cycles. | |
2285 | * Unfortunately this is overloaded on the "data complete" | |
2286 | * interrupt, so we need to take some care when handling | |
2287 | * it. | |
2288 | * | |
2289 | * Note: The 1.0 specification is a bit ambiguous about this | |
2290 | * feature so there might be some problems with older | |
2291 | * controllers. | |
2292 | */ | |
2293 | if (host->cmd->flags & MMC_RSP_BUSY) { | |
2294 | if (host->cmd->data) | |
2e4456f0 | 2295 | DBG("Cannot wait for busy signal when also doing a data transfer"); |
e99783a4 CM |
2296 | else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) |
2297 | && !host->busy_handle) { | |
2298 | /* Mark that command complete before busy is ended */ | |
2299 | host->busy_handle = 1; | |
e809517f | 2300 | return; |
e99783a4 | 2301 | } |
f945405c BD |
2302 | |
2303 | /* The controller does not support the end-of-busy IRQ, | |
2304 | * fall through and take the SDHCI_INT_RESPONSE */ | |
61541397 AH |
2305 | } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && |
2306 | host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) { | |
2307 | *mask &= ~SDHCI_INT_DATA_END; | |
e809517f PO |
2308 | } |
2309 | ||
2310 | if (intmask & SDHCI_INT_RESPONSE) | |
43b58b36 | 2311 | sdhci_finish_command(host); |
d129bceb PO |
2312 | } |
2313 | ||
0957c333 | 2314 | #ifdef CONFIG_MMC_DEBUG |
08621b18 | 2315 | static void sdhci_adma_show_error(struct sdhci_host *host) |
6882a8c0 BD |
2316 | { |
2317 | const char *name = mmc_hostname(host->mmc); | |
1c3d5f6d | 2318 | void *desc = host->adma_table; |
6882a8c0 BD |
2319 | |
2320 | sdhci_dumpregs(host); | |
2321 | ||
2322 | while (true) { | |
e57a5f61 AH |
2323 | struct sdhci_adma2_64_desc *dma_desc = desc; |
2324 | ||
2325 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
2326 | DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n", | |
2327 | name, desc, le32_to_cpu(dma_desc->addr_hi), | |
2328 | le32_to_cpu(dma_desc->addr_lo), | |
2329 | le16_to_cpu(dma_desc->len), | |
2330 | le16_to_cpu(dma_desc->cmd)); | |
2331 | else | |
2332 | DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", | |
2333 | name, desc, le32_to_cpu(dma_desc->addr_lo), | |
2334 | le16_to_cpu(dma_desc->len), | |
2335 | le16_to_cpu(dma_desc->cmd)); | |
6882a8c0 | 2336 | |
76fe379a | 2337 | desc += host->desc_sz; |
6882a8c0 | 2338 | |
0545230f | 2339 | if (dma_desc->cmd & cpu_to_le16(ADMA2_END)) |
6882a8c0 BD |
2340 | break; |
2341 | } | |
2342 | } | |
2343 | #else | |
08621b18 | 2344 | static void sdhci_adma_show_error(struct sdhci_host *host) { } |
6882a8c0 BD |
2345 | #endif |
2346 | ||
d129bceb PO |
2347 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) |
2348 | { | |
069c9f14 | 2349 | u32 command; |
d129bceb PO |
2350 | BUG_ON(intmask == 0); |
2351 | ||
b513ea25 AN |
2352 | /* CMD19 generates _only_ Buffer Read Ready interrupt */ |
2353 | if (intmask & SDHCI_INT_DATA_AVAIL) { | |
069c9f14 G |
2354 | command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); |
2355 | if (command == MMC_SEND_TUNING_BLOCK || | |
2356 | command == MMC_SEND_TUNING_BLOCK_HS200) { | |
b513ea25 AN |
2357 | host->tuning_done = 1; |
2358 | wake_up(&host->buf_ready_int); | |
2359 | return; | |
2360 | } | |
2361 | } | |
2362 | ||
d129bceb PO |
2363 | if (!host->data) { |
2364 | /* | |
e809517f PO |
2365 | * The "data complete" interrupt is also used to |
2366 | * indicate that a busy state has ended. See comment | |
2367 | * above in sdhci_cmd_irq(). | |
d129bceb | 2368 | */ |
e809517f | 2369 | if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { |
c5abd5e8 MC |
2370 | if (intmask & SDHCI_INT_DATA_TIMEOUT) { |
2371 | host->cmd->error = -ETIMEDOUT; | |
2372 | tasklet_schedule(&host->finish_tasklet); | |
2373 | return; | |
2374 | } | |
e809517f | 2375 | if (intmask & SDHCI_INT_DATA_END) { |
e99783a4 CM |
2376 | /* |
2377 | * Some cards handle busy-end interrupt | |
2378 | * before the command completed, so make | |
2379 | * sure we do things in the proper order. | |
2380 | */ | |
2381 | if (host->busy_handle) | |
2382 | sdhci_finish_command(host); | |
2383 | else | |
2384 | host->busy_handle = 1; | |
e809517f PO |
2385 | return; |
2386 | } | |
2387 | } | |
d129bceb | 2388 | |
2e4456f0 MV |
2389 | pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n", |
2390 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
2391 | sdhci_dumpregs(host); |
2392 | ||
2393 | return; | |
2394 | } | |
2395 | ||
2396 | if (intmask & SDHCI_INT_DATA_TIMEOUT) | |
17b0429d | 2397 | host->data->error = -ETIMEDOUT; |
22113efd AL |
2398 | else if (intmask & SDHCI_INT_DATA_END_BIT) |
2399 | host->data->error = -EILSEQ; | |
2400 | else if ((intmask & SDHCI_INT_DATA_CRC) && | |
2401 | SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) | |
2402 | != MMC_BUS_TEST_R) | |
17b0429d | 2403 | host->data->error = -EILSEQ; |
6882a8c0 | 2404 | else if (intmask & SDHCI_INT_ADMA_ERROR) { |
a3c76eb9 | 2405 | pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); |
08621b18 | 2406 | sdhci_adma_show_error(host); |
2134a922 | 2407 | host->data->error = -EIO; |
a4071fbb HZ |
2408 | if (host->ops->adma_workaround) |
2409 | host->ops->adma_workaround(host, intmask); | |
6882a8c0 | 2410 | } |
d129bceb | 2411 | |
17b0429d | 2412 | if (host->data->error) |
d129bceb PO |
2413 | sdhci_finish_data(host); |
2414 | else { | |
a406f5a3 | 2415 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
d129bceb PO |
2416 | sdhci_transfer_pio(host); |
2417 | ||
6ba736a1 PO |
2418 | /* |
2419 | * We currently don't do anything fancy with DMA | |
2420 | * boundaries, but as we can't disable the feature | |
2421 | * we need to at least restart the transfer. | |
f6a03cbf MV |
2422 | * |
2423 | * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) | |
2424 | * should return a valid address to continue from, but as | |
2425 | * some controllers are faulty, don't trust them. | |
6ba736a1 | 2426 | */ |
f6a03cbf MV |
2427 | if (intmask & SDHCI_INT_DMA_END) { |
2428 | u32 dmastart, dmanow; | |
2429 | dmastart = sg_dma_address(host->data->sg); | |
2430 | dmanow = dmastart + host->data->bytes_xfered; | |
2431 | /* | |
2432 | * Force update to the next DMA block boundary. | |
2433 | */ | |
2434 | dmanow = (dmanow & | |
2435 | ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + | |
2436 | SDHCI_DEFAULT_BOUNDARY_SIZE; | |
2437 | host->data->bytes_xfered = dmanow - dmastart; | |
2438 | DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," | |
2439 | " next 0x%08x\n", | |
2440 | mmc_hostname(host->mmc), dmastart, | |
2441 | host->data->bytes_xfered, dmanow); | |
2442 | sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); | |
2443 | } | |
6ba736a1 | 2444 | |
e538fbe8 PO |
2445 | if (intmask & SDHCI_INT_DATA_END) { |
2446 | if (host->cmd) { | |
2447 | /* | |
2448 | * Data managed to finish before the | |
2449 | * command completed. Make sure we do | |
2450 | * things in the proper order. | |
2451 | */ | |
2452 | host->data_early = 1; | |
2453 | } else { | |
2454 | sdhci_finish_data(host); | |
2455 | } | |
2456 | } | |
d129bceb PO |
2457 | } |
2458 | } | |
2459 | ||
7d12e780 | 2460 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
d129bceb | 2461 | { |
781e989c | 2462 | irqreturn_t result = IRQ_NONE; |
66fd8ad5 | 2463 | struct sdhci_host *host = dev_id; |
41005003 | 2464 | u32 intmask, mask, unexpected = 0; |
781e989c | 2465 | int max_loops = 16; |
d129bceb PO |
2466 | |
2467 | spin_lock(&host->lock); | |
2468 | ||
be138554 | 2469 | if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { |
66fd8ad5 | 2470 | spin_unlock(&host->lock); |
655bca76 | 2471 | return IRQ_NONE; |
66fd8ad5 AH |
2472 | } |
2473 | ||
4e4141a5 | 2474 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
62df67a5 | 2475 | if (!intmask || intmask == 0xffffffff) { |
d129bceb PO |
2476 | result = IRQ_NONE; |
2477 | goto out; | |
2478 | } | |
2479 | ||
41005003 RK |
2480 | do { |
2481 | /* Clear selected interrupts. */ | |
2482 | mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | | |
2483 | SDHCI_INT_BUS_POWER); | |
2484 | sdhci_writel(host, mask, SDHCI_INT_STATUS); | |
d129bceb | 2485 | |
41005003 RK |
2486 | DBG("*** %s got interrupt: 0x%08x\n", |
2487 | mmc_hostname(host->mmc), intmask); | |
d129bceb | 2488 | |
41005003 RK |
2489 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
2490 | u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
2491 | SDHCI_CARD_PRESENT; | |
d129bceb | 2492 | |
41005003 RK |
2493 | /* |
2494 | * There is a observation on i.mx esdhc. INSERT | |
2495 | * bit will be immediately set again when it gets | |
2496 | * cleared, if a card is inserted. We have to mask | |
2497 | * the irq to prevent interrupt storm which will | |
2498 | * freeze the system. And the REMOVE gets the | |
2499 | * same situation. | |
2500 | * | |
2501 | * More testing are needed here to ensure it works | |
2502 | * for other platforms though. | |
2503 | */ | |
b537f94c RK |
2504 | host->ier &= ~(SDHCI_INT_CARD_INSERT | |
2505 | SDHCI_INT_CARD_REMOVE); | |
2506 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : | |
2507 | SDHCI_INT_CARD_INSERT; | |
2508 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
2509 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
41005003 RK |
2510 | |
2511 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | | |
2512 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); | |
3560db8e RK |
2513 | |
2514 | host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | | |
2515 | SDHCI_INT_CARD_REMOVE); | |
2516 | result = IRQ_WAKE_THREAD; | |
41005003 | 2517 | } |
d129bceb | 2518 | |
41005003 | 2519 | if (intmask & SDHCI_INT_CMD_MASK) |
61541397 AH |
2520 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, |
2521 | &intmask); | |
964f9ce2 | 2522 | |
41005003 RK |
2523 | if (intmask & SDHCI_INT_DATA_MASK) |
2524 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); | |
d129bceb | 2525 | |
41005003 RK |
2526 | if (intmask & SDHCI_INT_BUS_POWER) |
2527 | pr_err("%s: Card is consuming too much power!\n", | |
2528 | mmc_hostname(host->mmc)); | |
3192a28f | 2529 | |
781e989c RK |
2530 | if (intmask & SDHCI_INT_CARD_INT) { |
2531 | sdhci_enable_sdio_irq_nolock(host, false); | |
2532 | host->thread_isr |= SDHCI_INT_CARD_INT; | |
2533 | result = IRQ_WAKE_THREAD; | |
2534 | } | |
f75979b7 | 2535 | |
41005003 RK |
2536 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | |
2537 | SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | | |
2538 | SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | | |
2539 | SDHCI_INT_CARD_INT); | |
f75979b7 | 2540 | |
41005003 RK |
2541 | if (intmask) { |
2542 | unexpected |= intmask; | |
2543 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); | |
2544 | } | |
d129bceb | 2545 | |
781e989c RK |
2546 | if (result == IRQ_NONE) |
2547 | result = IRQ_HANDLED; | |
d129bceb | 2548 | |
41005003 | 2549 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
41005003 | 2550 | } while (intmask && --max_loops); |
d129bceb PO |
2551 | out: |
2552 | spin_unlock(&host->lock); | |
2553 | ||
6379b237 AS |
2554 | if (unexpected) { |
2555 | pr_err("%s: Unexpected interrupt 0x%08x.\n", | |
2556 | mmc_hostname(host->mmc), unexpected); | |
2557 | sdhci_dumpregs(host); | |
2558 | } | |
f75979b7 | 2559 | |
d129bceb PO |
2560 | return result; |
2561 | } | |
2562 | ||
781e989c RK |
2563 | static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) |
2564 | { | |
2565 | struct sdhci_host *host = dev_id; | |
2566 | unsigned long flags; | |
2567 | u32 isr; | |
2568 | ||
2569 | spin_lock_irqsave(&host->lock, flags); | |
2570 | isr = host->thread_isr; | |
2571 | host->thread_isr = 0; | |
2572 | spin_unlock_irqrestore(&host->lock, flags); | |
2573 | ||
3560db8e RK |
2574 | if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
2575 | sdhci_card_event(host->mmc); | |
2576 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); | |
2577 | } | |
2578 | ||
781e989c RK |
2579 | if (isr & SDHCI_INT_CARD_INT) { |
2580 | sdio_run_irqs(host->mmc); | |
2581 | ||
2582 | spin_lock_irqsave(&host->lock, flags); | |
2583 | if (host->flags & SDHCI_SDIO_IRQ_ENABLED) | |
2584 | sdhci_enable_sdio_irq_nolock(host, true); | |
2585 | spin_unlock_irqrestore(&host->lock, flags); | |
2586 | } | |
2587 | ||
2588 | return isr ? IRQ_HANDLED : IRQ_NONE; | |
2589 | } | |
2590 | ||
d129bceb PO |
2591 | /*****************************************************************************\ |
2592 | * * | |
2593 | * Suspend/resume * | |
2594 | * * | |
2595 | \*****************************************************************************/ | |
2596 | ||
2597 | #ifdef CONFIG_PM | |
ad080d79 KL |
2598 | void sdhci_enable_irq_wakeups(struct sdhci_host *host) |
2599 | { | |
2600 | u8 val; | |
2601 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE | |
2602 | | SDHCI_WAKE_ON_INT; | |
2603 | ||
2604 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); | |
2605 | val |= mask ; | |
2606 | /* Avoid fake wake up */ | |
2607 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) | |
2608 | val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); | |
2609 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); | |
2610 | } | |
2611 | EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); | |
2612 | ||
0b10f478 | 2613 | static void sdhci_disable_irq_wakeups(struct sdhci_host *host) |
ad080d79 KL |
2614 | { |
2615 | u8 val; | |
2616 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE | |
2617 | | SDHCI_WAKE_ON_INT; | |
2618 | ||
2619 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); | |
2620 | val &= ~mask; | |
2621 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); | |
2622 | } | |
d129bceb | 2623 | |
29495aa0 | 2624 | int sdhci_suspend_host(struct sdhci_host *host) |
d129bceb | 2625 | { |
7260cf5e AV |
2626 | sdhci_disable_card_detection(host); |
2627 | ||
66c39dfc AH |
2628 | mmc_retune_timer_stop(host->mmc); |
2629 | mmc_retune_needed(host->mmc); | |
cf2b5eea | 2630 | |
ad080d79 | 2631 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
b537f94c RK |
2632 | host->ier = 0; |
2633 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); | |
2634 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); | |
ad080d79 KL |
2635 | free_irq(host->irq, host); |
2636 | } else { | |
2637 | sdhci_enable_irq_wakeups(host); | |
2638 | enable_irq_wake(host->irq); | |
2639 | } | |
4ee14ec6 | 2640 | return 0; |
d129bceb PO |
2641 | } |
2642 | ||
b8c86fc5 | 2643 | EXPORT_SYMBOL_GPL(sdhci_suspend_host); |
d129bceb | 2644 | |
b8c86fc5 PO |
2645 | int sdhci_resume_host(struct sdhci_host *host) |
2646 | { | |
4ee14ec6 | 2647 | int ret = 0; |
d129bceb | 2648 | |
a13abc7b | 2649 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
2650 | if (host->ops->enable_dma) |
2651 | host->ops->enable_dma(host); | |
2652 | } | |
d129bceb | 2653 | |
6308d290 AH |
2654 | if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && |
2655 | (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { | |
2656 | /* Card keeps power but host controller does not */ | |
2657 | sdhci_init(host, 0); | |
2658 | host->pwr = 0; | |
2659 | host->clock = 0; | |
2660 | sdhci_do_set_ios(host, &host->mmc->ios); | |
2661 | } else { | |
2662 | sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); | |
2663 | mmiowb(); | |
2664 | } | |
b8c86fc5 | 2665 | |
14a7b416 HC |
2666 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
2667 | ret = request_threaded_irq(host->irq, sdhci_irq, | |
2668 | sdhci_thread_irq, IRQF_SHARED, | |
2669 | mmc_hostname(host->mmc), host); | |
2670 | if (ret) | |
2671 | return ret; | |
2672 | } else { | |
2673 | sdhci_disable_irq_wakeups(host); | |
2674 | disable_irq_wake(host->irq); | |
2675 | } | |
2676 | ||
7260cf5e AV |
2677 | sdhci_enable_card_detection(host); |
2678 | ||
2f4cbb3d | 2679 | return ret; |
d129bceb PO |
2680 | } |
2681 | ||
b8c86fc5 | 2682 | EXPORT_SYMBOL_GPL(sdhci_resume_host); |
66fd8ad5 | 2683 | |
66fd8ad5 AH |
2684 | int sdhci_runtime_suspend_host(struct sdhci_host *host) |
2685 | { | |
2686 | unsigned long flags; | |
66fd8ad5 | 2687 | |
66c39dfc AH |
2688 | mmc_retune_timer_stop(host->mmc); |
2689 | mmc_retune_needed(host->mmc); | |
66fd8ad5 AH |
2690 | |
2691 | spin_lock_irqsave(&host->lock, flags); | |
b537f94c RK |
2692 | host->ier &= SDHCI_INT_CARD_INT; |
2693 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
2694 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
66fd8ad5 AH |
2695 | spin_unlock_irqrestore(&host->lock, flags); |
2696 | ||
781e989c | 2697 | synchronize_hardirq(host->irq); |
66fd8ad5 AH |
2698 | |
2699 | spin_lock_irqsave(&host->lock, flags); | |
2700 | host->runtime_suspended = true; | |
2701 | spin_unlock_irqrestore(&host->lock, flags); | |
2702 | ||
8a125bad | 2703 | return 0; |
66fd8ad5 AH |
2704 | } |
2705 | EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); | |
2706 | ||
2707 | int sdhci_runtime_resume_host(struct sdhci_host *host) | |
2708 | { | |
2709 | unsigned long flags; | |
8a125bad | 2710 | int host_flags = host->flags; |
66fd8ad5 AH |
2711 | |
2712 | if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { | |
2713 | if (host->ops->enable_dma) | |
2714 | host->ops->enable_dma(host); | |
2715 | } | |
2716 | ||
2717 | sdhci_init(host, 0); | |
2718 | ||
2719 | /* Force clock and power re-program */ | |
2720 | host->pwr = 0; | |
2721 | host->clock = 0; | |
3396e736 | 2722 | sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); |
66fd8ad5 AH |
2723 | sdhci_do_set_ios(host, &host->mmc->ios); |
2724 | ||
52983382 KL |
2725 | if ((host_flags & SDHCI_PV_ENABLED) && |
2726 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { | |
2727 | spin_lock_irqsave(&host->lock, flags); | |
2728 | sdhci_enable_preset_value(host, true); | |
2729 | spin_unlock_irqrestore(&host->lock, flags); | |
2730 | } | |
66fd8ad5 | 2731 | |
66fd8ad5 AH |
2732 | spin_lock_irqsave(&host->lock, flags); |
2733 | ||
2734 | host->runtime_suspended = false; | |
2735 | ||
2736 | /* Enable SDIO IRQ */ | |
ef104333 | 2737 | if (host->flags & SDHCI_SDIO_IRQ_ENABLED) |
66fd8ad5 AH |
2738 | sdhci_enable_sdio_irq_nolock(host, true); |
2739 | ||
2740 | /* Enable Card Detection */ | |
2741 | sdhci_enable_card_detection(host); | |
2742 | ||
2743 | spin_unlock_irqrestore(&host->lock, flags); | |
2744 | ||
8a125bad | 2745 | return 0; |
66fd8ad5 AH |
2746 | } |
2747 | EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); | |
2748 | ||
162d6f98 | 2749 | #endif /* CONFIG_PM */ |
66fd8ad5 | 2750 | |
d129bceb PO |
2751 | /*****************************************************************************\ |
2752 | * * | |
b8c86fc5 | 2753 | * Device allocation/registration * |
d129bceb PO |
2754 | * * |
2755 | \*****************************************************************************/ | |
2756 | ||
b8c86fc5 PO |
2757 | struct sdhci_host *sdhci_alloc_host(struct device *dev, |
2758 | size_t priv_size) | |
d129bceb | 2759 | { |
d129bceb PO |
2760 | struct mmc_host *mmc; |
2761 | struct sdhci_host *host; | |
2762 | ||
b8c86fc5 | 2763 | WARN_ON(dev == NULL); |
d129bceb | 2764 | |
b8c86fc5 | 2765 | mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); |
d129bceb | 2766 | if (!mmc) |
b8c86fc5 | 2767 | return ERR_PTR(-ENOMEM); |
d129bceb PO |
2768 | |
2769 | host = mmc_priv(mmc); | |
2770 | host->mmc = mmc; | |
bf60e592 AH |
2771 | host->mmc_host_ops = sdhci_ops; |
2772 | mmc->ops = &host->mmc_host_ops; | |
d129bceb | 2773 | |
b8c86fc5 PO |
2774 | return host; |
2775 | } | |
8a4da143 | 2776 | |
b8c86fc5 | 2777 | EXPORT_SYMBOL_GPL(sdhci_alloc_host); |
d129bceb | 2778 | |
7b91369b AC |
2779 | static int sdhci_set_dma_mask(struct sdhci_host *host) |
2780 | { | |
2781 | struct mmc_host *mmc = host->mmc; | |
2782 | struct device *dev = mmc_dev(mmc); | |
2783 | int ret = -EINVAL; | |
2784 | ||
2785 | if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) | |
2786 | host->flags &= ~SDHCI_USE_64_BIT_DMA; | |
2787 | ||
2788 | /* Try 64-bit mask if hardware is capable of it */ | |
2789 | if (host->flags & SDHCI_USE_64_BIT_DMA) { | |
2790 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); | |
2791 | if (ret) { | |
2792 | pr_warn("%s: Failed to set 64-bit DMA mask.\n", | |
2793 | mmc_hostname(mmc)); | |
2794 | host->flags &= ~SDHCI_USE_64_BIT_DMA; | |
2795 | } | |
2796 | } | |
2797 | ||
2798 | /* 32-bit mask as default & fallback */ | |
2799 | if (ret) { | |
2800 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); | |
2801 | if (ret) | |
2802 | pr_warn("%s: Failed to set 32-bit DMA mask.\n", | |
2803 | mmc_hostname(mmc)); | |
2804 | } | |
2805 | ||
2806 | return ret; | |
2807 | } | |
2808 | ||
b8c86fc5 PO |
2809 | int sdhci_add_host(struct sdhci_host *host) |
2810 | { | |
2811 | struct mmc_host *mmc; | |
bd6a8c30 | 2812 | u32 caps[2] = {0, 0}; |
f2119df6 AN |
2813 | u32 max_current_caps; |
2814 | unsigned int ocr_avail; | |
f5fa92e5 | 2815 | unsigned int override_timeout_clk; |
59241757 | 2816 | u32 max_clk; |
b8c86fc5 | 2817 | int ret; |
d129bceb | 2818 | |
b8c86fc5 PO |
2819 | WARN_ON(host == NULL); |
2820 | if (host == NULL) | |
2821 | return -EINVAL; | |
d129bceb | 2822 | |
b8c86fc5 | 2823 | mmc = host->mmc; |
d129bceb | 2824 | |
b8c86fc5 PO |
2825 | if (debug_quirks) |
2826 | host->quirks = debug_quirks; | |
66fd8ad5 AH |
2827 | if (debug_quirks2) |
2828 | host->quirks2 = debug_quirks2; | |
d129bceb | 2829 | |
f5fa92e5 AH |
2830 | override_timeout_clk = host->timeout_clk; |
2831 | ||
03231f9b | 2832 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
d96649ed | 2833 | |
4e4141a5 | 2834 | host->version = sdhci_readw(host, SDHCI_HOST_VERSION); |
2134a922 PO |
2835 | host->version = (host->version & SDHCI_SPEC_VER_MASK) |
2836 | >> SDHCI_SPEC_VER_SHIFT; | |
85105c53 | 2837 | if (host->version > SDHCI_SPEC_300) { |
2e4456f0 MV |
2838 | pr_err("%s: Unknown controller version (%d). You may experience problems.\n", |
2839 | mmc_hostname(mmc), host->version); | |
4a965505 PO |
2840 | } |
2841 | ||
f2119df6 | 2842 | caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : |
ccc92c23 | 2843 | sdhci_readl(host, SDHCI_CAPABILITIES); |
d129bceb | 2844 | |
bd6a8c30 PR |
2845 | if (host->version >= SDHCI_SPEC_300) |
2846 | caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? | |
2847 | host->caps1 : | |
2848 | sdhci_readl(host, SDHCI_CAPABILITIES_1); | |
f2119df6 | 2849 | |
b8c86fc5 | 2850 | if (host->quirks & SDHCI_QUIRK_FORCE_DMA) |
a13abc7b | 2851 | host->flags |= SDHCI_USE_SDMA; |
f2119df6 | 2852 | else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) |
a13abc7b | 2853 | DBG("Controller doesn't have SDMA capability\n"); |
67435274 | 2854 | else |
a13abc7b | 2855 | host->flags |= SDHCI_USE_SDMA; |
d129bceb | 2856 | |
b8c86fc5 | 2857 | if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
a13abc7b | 2858 | (host->flags & SDHCI_USE_SDMA)) { |
cee687ce | 2859 | DBG("Disabling DMA as it is marked broken\n"); |
a13abc7b | 2860 | host->flags &= ~SDHCI_USE_SDMA; |
7c168e3d FT |
2861 | } |
2862 | ||
f2119df6 AN |
2863 | if ((host->version >= SDHCI_SPEC_200) && |
2864 | (caps[0] & SDHCI_CAN_DO_ADMA2)) | |
a13abc7b | 2865 | host->flags |= SDHCI_USE_ADMA; |
2134a922 PO |
2866 | |
2867 | if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && | |
2868 | (host->flags & SDHCI_USE_ADMA)) { | |
2869 | DBG("Disabling ADMA as it is marked broken\n"); | |
2870 | host->flags &= ~SDHCI_USE_ADMA; | |
2871 | } | |
2872 | ||
e57a5f61 AH |
2873 | /* |
2874 | * It is assumed that a 64-bit capable device has set a 64-bit DMA mask | |
2875 | * and *must* do 64-bit DMA. A driver has the opportunity to change | |
2876 | * that during the first call to ->enable_dma(). Similarly | |
2877 | * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to | |
2878 | * implement. | |
2879 | */ | |
5eaa7476 | 2880 | if (caps[0] & SDHCI_CAN_64BIT) |
e57a5f61 AH |
2881 | host->flags |= SDHCI_USE_64_BIT_DMA; |
2882 | ||
a13abc7b | 2883 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
7b91369b AC |
2884 | ret = sdhci_set_dma_mask(host); |
2885 | ||
2886 | if (!ret && host->ops->enable_dma) | |
2887 | ret = host->ops->enable_dma(host); | |
2888 | ||
2889 | if (ret) { | |
2890 | pr_warn("%s: No suitable DMA available - falling back to PIO\n", | |
2891 | mmc_hostname(mmc)); | |
2892 | host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); | |
2893 | ||
2894 | ret = 0; | |
d129bceb PO |
2895 | } |
2896 | } | |
2897 | ||
e57a5f61 AH |
2898 | /* SDMA does not support 64-bit DMA */ |
2899 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
2900 | host->flags &= ~SDHCI_USE_SDMA; | |
2901 | ||
2134a922 | 2902 | if (host->flags & SDHCI_USE_ADMA) { |
e66e61cb RK |
2903 | dma_addr_t dma; |
2904 | void *buf; | |
2905 | ||
2134a922 | 2906 | /* |
76fe379a AH |
2907 | * The DMA descriptor table size is calculated as the maximum |
2908 | * number of segments times 2, to allow for an alignment | |
2909 | * descriptor for each segment, plus 1 for a nop end descriptor, | |
2910 | * all multipled by the descriptor size. | |
2134a922 | 2911 | */ |
e57a5f61 AH |
2912 | if (host->flags & SDHCI_USE_64_BIT_DMA) { |
2913 | host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * | |
2914 | SDHCI_ADMA2_64_DESC_SZ; | |
e57a5f61 | 2915 | host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; |
e57a5f61 AH |
2916 | } else { |
2917 | host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * | |
2918 | SDHCI_ADMA2_32_DESC_SZ; | |
e57a5f61 | 2919 | host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; |
e57a5f61 | 2920 | } |
e66e61cb | 2921 | |
04a5ae6f | 2922 | host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; |
e66e61cb RK |
2923 | buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + |
2924 | host->adma_table_sz, &dma, GFP_KERNEL); | |
2925 | if (!buf) { | |
6606110d | 2926 | pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", |
2134a922 PO |
2927 | mmc_hostname(mmc)); |
2928 | host->flags &= ~SDHCI_USE_ADMA; | |
e66e61cb RK |
2929 | } else if ((dma + host->align_buffer_sz) & |
2930 | (SDHCI_ADMA2_DESC_ALIGN - 1)) { | |
6606110d JP |
2931 | pr_warn("%s: unable to allocate aligned ADMA descriptor\n", |
2932 | mmc_hostname(mmc)); | |
d1e49f77 | 2933 | host->flags &= ~SDHCI_USE_ADMA; |
e66e61cb RK |
2934 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + |
2935 | host->adma_table_sz, buf, dma); | |
2936 | } else { | |
2937 | host->align_buffer = buf; | |
2938 | host->align_addr = dma; | |
edd63fcc | 2939 | |
e66e61cb RK |
2940 | host->adma_table = buf + host->align_buffer_sz; |
2941 | host->adma_addr = dma + host->align_buffer_sz; | |
2942 | } | |
2134a922 PO |
2943 | } |
2944 | ||
7659150c PO |
2945 | /* |
2946 | * If we use DMA, then it's up to the caller to set the DMA | |
2947 | * mask, but PIO does not need the hw shim so we set a new | |
2948 | * mask here in that case. | |
2949 | */ | |
a13abc7b | 2950 | if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { |
7659150c | 2951 | host->dma_mask = DMA_BIT_MASK(64); |
4e743f1f | 2952 | mmc_dev(mmc)->dma_mask = &host->dma_mask; |
7659150c | 2953 | } |
d129bceb | 2954 | |
c4687d5f | 2955 | if (host->version >= SDHCI_SPEC_300) |
f2119df6 | 2956 | host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) |
c4687d5f ZG |
2957 | >> SDHCI_CLOCK_BASE_SHIFT; |
2958 | else | |
f2119df6 | 2959 | host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) |
c4687d5f ZG |
2960 | >> SDHCI_CLOCK_BASE_SHIFT; |
2961 | ||
4240ff0a | 2962 | host->max_clk *= 1000000; |
f27f47ef AV |
2963 | if (host->max_clk == 0 || host->quirks & |
2964 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { | |
4240ff0a | 2965 | if (!host->ops->get_max_clock) { |
2e4456f0 MV |
2966 | pr_err("%s: Hardware doesn't specify base clock frequency.\n", |
2967 | mmc_hostname(mmc)); | |
eb5c20de AH |
2968 | ret = -ENODEV; |
2969 | goto undma; | |
4240ff0a BD |
2970 | } |
2971 | host->max_clk = host->ops->get_max_clock(host); | |
8ef1a143 | 2972 | } |
d129bceb | 2973 | |
c3ed3877 AN |
2974 | /* |
2975 | * In case of Host Controller v3.00, find out whether clock | |
2976 | * multiplier is supported. | |
2977 | */ | |
2978 | host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> | |
2979 | SDHCI_CLOCK_MUL_SHIFT; | |
2980 | ||
2981 | /* | |
2982 | * In case the value in Clock Multiplier is 0, then programmable | |
2983 | * clock mode is not supported, otherwise the actual clock | |
2984 | * multiplier is one more than the value of Clock Multiplier | |
2985 | * in the Capabilities Register. | |
2986 | */ | |
2987 | if (host->clk_mul) | |
2988 | host->clk_mul += 1; | |
2989 | ||
d129bceb PO |
2990 | /* |
2991 | * Set host parameters. | |
2992 | */ | |
59241757 DA |
2993 | max_clk = host->max_clk; |
2994 | ||
ce5f036b | 2995 | if (host->ops->get_min_clock) |
a9e58f25 | 2996 | mmc->f_min = host->ops->get_min_clock(host); |
c3ed3877 AN |
2997 | else if (host->version >= SDHCI_SPEC_300) { |
2998 | if (host->clk_mul) { | |
2999 | mmc->f_min = (host->max_clk * host->clk_mul) / 1024; | |
59241757 | 3000 | max_clk = host->max_clk * host->clk_mul; |
c3ed3877 AN |
3001 | } else |
3002 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; | |
3003 | } else | |
0397526d | 3004 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; |
15ec4461 | 3005 | |
d310ae49 | 3006 | if (!mmc->f_max || mmc->f_max > max_clk) |
59241757 DA |
3007 | mmc->f_max = max_clk; |
3008 | ||
28aab053 AD |
3009 | if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { |
3010 | host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> | |
3011 | SDHCI_TIMEOUT_CLK_SHIFT; | |
3012 | if (host->timeout_clk == 0) { | |
3013 | if (host->ops->get_timeout_clock) { | |
3014 | host->timeout_clk = | |
3015 | host->ops->get_timeout_clock(host); | |
3016 | } else { | |
3017 | pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", | |
3018 | mmc_hostname(mmc)); | |
eb5c20de AH |
3019 | ret = -ENODEV; |
3020 | goto undma; | |
28aab053 | 3021 | } |
272308ca | 3022 | } |
272308ca | 3023 | |
28aab053 AD |
3024 | if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) |
3025 | host->timeout_clk *= 1000; | |
272308ca | 3026 | |
99513624 AH |
3027 | if (override_timeout_clk) |
3028 | host->timeout_clk = override_timeout_clk; | |
3029 | ||
28aab053 | 3030 | mmc->max_busy_timeout = host->ops->get_max_timeout_count ? |
a6ff5aeb | 3031 | host->ops->get_max_timeout_count(host) : 1 << 27; |
28aab053 AD |
3032 | mmc->max_busy_timeout /= host->timeout_clk; |
3033 | } | |
58d1246d | 3034 | |
e89d456f | 3035 | mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; |
781e989c | 3036 | mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; |
e89d456f AW |
3037 | |
3038 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) | |
3039 | host->flags |= SDHCI_AUTO_CMD12; | |
5fe23c7f | 3040 | |
8edf6371 | 3041 | /* Auto-CMD23 stuff only works in ADMA or PIO. */ |
4f3d3e9b | 3042 | if ((host->version >= SDHCI_SPEC_300) && |
8edf6371 | 3043 | ((host->flags & SDHCI_USE_ADMA) || |
3bfa6f03 SB |
3044 | !(host->flags & SDHCI_USE_SDMA)) && |
3045 | !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { | |
8edf6371 AW |
3046 | host->flags |= SDHCI_AUTO_CMD23; |
3047 | DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); | |
3048 | } else { | |
3049 | DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); | |
3050 | } | |
3051 | ||
15ec4461 PR |
3052 | /* |
3053 | * A controller may support 8-bit width, but the board itself | |
3054 | * might not have the pins brought out. Boards that support | |
3055 | * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in | |
3056 | * their platform code before calling sdhci_add_host(), and we | |
3057 | * won't assume 8-bit width for hosts without that CAP. | |
3058 | */ | |
5fe23c7f | 3059 | if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) |
15ec4461 | 3060 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
d129bceb | 3061 | |
63ef5d8c JH |
3062 | if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) |
3063 | mmc->caps &= ~MMC_CAP_CMD23; | |
3064 | ||
f2119df6 | 3065 | if (caps[0] & SDHCI_CAN_DO_HISPD) |
a29e7e18 | 3066 | mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; |
cd9277c0 | 3067 | |
176d1ed4 | 3068 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && |
c31d22eb II |
3069 | !(mmc->caps & MMC_CAP_NONREMOVABLE) && |
3070 | IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc))) | |
68d1fb7e AV |
3071 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
3072 | ||
3a48edc4 | 3073 | /* If there are external regulators, get them */ |
eb5c20de AH |
3074 | ret = mmc_regulator_get_supply(mmc); |
3075 | if (ret == -EPROBE_DEFER) | |
3076 | goto undma; | |
3a48edc4 | 3077 | |
6231f3de | 3078 | /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ |
3a48edc4 TK |
3079 | if (!IS_ERR(mmc->supply.vqmmc)) { |
3080 | ret = regulator_enable(mmc->supply.vqmmc); | |
3081 | if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, | |
3082 | 1950000)) | |
8363c374 KL |
3083 | caps[1] &= ~(SDHCI_SUPPORT_SDR104 | |
3084 | SDHCI_SUPPORT_SDR50 | | |
3085 | SDHCI_SUPPORT_DDR50); | |
a3361aba CB |
3086 | if (ret) { |
3087 | pr_warn("%s: Failed to enable vqmmc regulator: %d\n", | |
3088 | mmc_hostname(mmc), ret); | |
4bb74313 | 3089 | mmc->supply.vqmmc = ERR_PTR(-EINVAL); |
a3361aba | 3090 | } |
8363c374 | 3091 | } |
6231f3de | 3092 | |
6a66180a DD |
3093 | if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) |
3094 | caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | | |
3095 | SDHCI_SUPPORT_DDR50); | |
3096 | ||
4188bba0 AC |
3097 | /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ |
3098 | if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | | |
3099 | SDHCI_SUPPORT_DDR50)) | |
f2119df6 AN |
3100 | mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; |
3101 | ||
3102 | /* SDR104 supports also implies SDR50 support */ | |
156e14b1 | 3103 | if (caps[1] & SDHCI_SUPPORT_SDR104) { |
f2119df6 | 3104 | mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; |
156e14b1 GC |
3105 | /* SD3.0: SDR104 is supported so (for eMMC) the caps2 |
3106 | * field can be promoted to support HS200. | |
3107 | */ | |
549c0b18 | 3108 | if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) |
13868bf2 | 3109 | mmc->caps2 |= MMC_CAP2_HS200; |
156e14b1 | 3110 | } else if (caps[1] & SDHCI_SUPPORT_SDR50) |
f2119df6 AN |
3111 | mmc->caps |= MMC_CAP_UHS_SDR50; |
3112 | ||
e9fb05d5 AH |
3113 | if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && |
3114 | (caps[1] & SDHCI_SUPPORT_HS400)) | |
3115 | mmc->caps2 |= MMC_CAP2_HS400; | |
3116 | ||
549c0b18 AH |
3117 | if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && |
3118 | (IS_ERR(mmc->supply.vqmmc) || | |
3119 | !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000, | |
3120 | 1300000))) | |
3121 | mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V; | |
3122 | ||
9107ebbf MC |
3123 | if ((caps[1] & SDHCI_SUPPORT_DDR50) && |
3124 | !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) | |
f2119df6 AN |
3125 | mmc->caps |= MMC_CAP_UHS_DDR50; |
3126 | ||
069c9f14 | 3127 | /* Does the host need tuning for SDR50? */ |
b513ea25 AN |
3128 | if (caps[1] & SDHCI_USE_SDR50_TUNING) |
3129 | host->flags |= SDHCI_SDR50_NEEDS_TUNING; | |
3130 | ||
156e14b1 | 3131 | /* Does the host need tuning for SDR104 / HS200? */ |
069c9f14 | 3132 | if (mmc->caps2 & MMC_CAP2_HS200) |
156e14b1 | 3133 | host->flags |= SDHCI_SDR104_NEEDS_TUNING; |
069c9f14 | 3134 | |
d6d50a15 AN |
3135 | /* Driver Type(s) (A, C, D) supported by the host */ |
3136 | if (caps[1] & SDHCI_DRIVER_TYPE_A) | |
3137 | mmc->caps |= MMC_CAP_DRIVER_TYPE_A; | |
3138 | if (caps[1] & SDHCI_DRIVER_TYPE_C) | |
3139 | mmc->caps |= MMC_CAP_DRIVER_TYPE_C; | |
3140 | if (caps[1] & SDHCI_DRIVER_TYPE_D) | |
3141 | mmc->caps |= MMC_CAP_DRIVER_TYPE_D; | |
3142 | ||
cf2b5eea AN |
3143 | /* Initial value for re-tuning timer count */ |
3144 | host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> | |
3145 | SDHCI_RETUNING_TIMER_COUNT_SHIFT; | |
3146 | ||
3147 | /* | |
3148 | * In case Re-tuning Timer is not disabled, the actual value of | |
3149 | * re-tuning timer will be 2 ^ (n - 1). | |
3150 | */ | |
3151 | if (host->tuning_count) | |
3152 | host->tuning_count = 1 << (host->tuning_count - 1); | |
3153 | ||
3154 | /* Re-tuning mode supported by the Host Controller */ | |
3155 | host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> | |
3156 | SDHCI_RETUNING_MODE_SHIFT; | |
3157 | ||
8f230f45 | 3158 | ocr_avail = 0; |
bad37e1a | 3159 | |
f2119df6 AN |
3160 | /* |
3161 | * According to SD Host Controller spec v3.00, if the Host System | |
3162 | * can afford more than 150mA, Host Driver should set XPC to 1. Also | |
3163 | * the value is meaningful only if Voltage Support in the Capabilities | |
3164 | * register is set. The actual current value is 4 times the register | |
3165 | * value. | |
3166 | */ | |
3167 | max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); | |
3a48edc4 | 3168 | if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { |
ae906037 | 3169 | int curr = regulator_get_current_limit(mmc->supply.vmmc); |
bad37e1a PR |
3170 | if (curr > 0) { |
3171 | ||
3172 | /* convert to SDHCI_MAX_CURRENT format */ | |
3173 | curr = curr/1000; /* convert to mA */ | |
3174 | curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; | |
3175 | ||
3176 | curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); | |
3177 | max_current_caps = | |
3178 | (curr << SDHCI_MAX_CURRENT_330_SHIFT) | | |
3179 | (curr << SDHCI_MAX_CURRENT_300_SHIFT) | | |
3180 | (curr << SDHCI_MAX_CURRENT_180_SHIFT); | |
3181 | } | |
3182 | } | |
f2119df6 AN |
3183 | |
3184 | if (caps[0] & SDHCI_CAN_VDD_330) { | |
8f230f45 | 3185 | ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; |
f2119df6 | 3186 | |
55c4665e | 3187 | mmc->max_current_330 = ((max_current_caps & |
f2119df6 AN |
3188 | SDHCI_MAX_CURRENT_330_MASK) >> |
3189 | SDHCI_MAX_CURRENT_330_SHIFT) * | |
3190 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
f2119df6 AN |
3191 | } |
3192 | if (caps[0] & SDHCI_CAN_VDD_300) { | |
8f230f45 | 3193 | ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; |
f2119df6 | 3194 | |
55c4665e | 3195 | mmc->max_current_300 = ((max_current_caps & |
f2119df6 AN |
3196 | SDHCI_MAX_CURRENT_300_MASK) >> |
3197 | SDHCI_MAX_CURRENT_300_SHIFT) * | |
3198 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
f2119df6 AN |
3199 | } |
3200 | if (caps[0] & SDHCI_CAN_VDD_180) { | |
8f230f45 TI |
3201 | ocr_avail |= MMC_VDD_165_195; |
3202 | ||
55c4665e | 3203 | mmc->max_current_180 = ((max_current_caps & |
f2119df6 AN |
3204 | SDHCI_MAX_CURRENT_180_MASK) >> |
3205 | SDHCI_MAX_CURRENT_180_SHIFT) * | |
3206 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
f2119df6 AN |
3207 | } |
3208 | ||
5fd26c7e UH |
3209 | /* If OCR set by host, use it instead. */ |
3210 | if (host->ocr_mask) | |
3211 | ocr_avail = host->ocr_mask; | |
3212 | ||
3213 | /* If OCR set by external regulators, give it highest prio. */ | |
3a48edc4 | 3214 | if (mmc->ocr_avail) |
52221610 | 3215 | ocr_avail = mmc->ocr_avail; |
3a48edc4 | 3216 | |
8f230f45 TI |
3217 | mmc->ocr_avail = ocr_avail; |
3218 | mmc->ocr_avail_sdio = ocr_avail; | |
3219 | if (host->ocr_avail_sdio) | |
3220 | mmc->ocr_avail_sdio &= host->ocr_avail_sdio; | |
3221 | mmc->ocr_avail_sd = ocr_avail; | |
3222 | if (host->ocr_avail_sd) | |
3223 | mmc->ocr_avail_sd &= host->ocr_avail_sd; | |
3224 | else /* normal SD controllers don't support 1.8V */ | |
3225 | mmc->ocr_avail_sd &= ~MMC_VDD_165_195; | |
3226 | mmc->ocr_avail_mmc = ocr_avail; | |
3227 | if (host->ocr_avail_mmc) | |
3228 | mmc->ocr_avail_mmc &= host->ocr_avail_mmc; | |
146ad66e PO |
3229 | |
3230 | if (mmc->ocr_avail == 0) { | |
2e4456f0 MV |
3231 | pr_err("%s: Hardware doesn't report any support voltages.\n", |
3232 | mmc_hostname(mmc)); | |
eb5c20de AH |
3233 | ret = -ENODEV; |
3234 | goto unreg; | |
146ad66e PO |
3235 | } |
3236 | ||
d129bceb PO |
3237 | spin_lock_init(&host->lock); |
3238 | ||
3239 | /* | |
2134a922 PO |
3240 | * Maximum number of segments. Depends on if the hardware |
3241 | * can do scatter/gather or not. | |
d129bceb | 3242 | */ |
2134a922 | 3243 | if (host->flags & SDHCI_USE_ADMA) |
4fb213f8 | 3244 | mmc->max_segs = SDHCI_MAX_SEGS; |
a13abc7b | 3245 | else if (host->flags & SDHCI_USE_SDMA) |
a36274e0 | 3246 | mmc->max_segs = 1; |
2134a922 | 3247 | else /* PIO */ |
4fb213f8 | 3248 | mmc->max_segs = SDHCI_MAX_SEGS; |
d129bceb PO |
3249 | |
3250 | /* | |
ac00531d AH |
3251 | * Maximum number of sectors in one transfer. Limited by SDMA boundary |
3252 | * size (512KiB). Note some tuning modes impose a 4MiB limit, but this | |
3253 | * is less anyway. | |
d129bceb | 3254 | */ |
55db890a | 3255 | mmc->max_req_size = 524288; |
d129bceb PO |
3256 | |
3257 | /* | |
3258 | * Maximum segment size. Could be one segment with the maximum number | |
2134a922 PO |
3259 | * of bytes. When doing hardware scatter/gather, each entry cannot |
3260 | * be larger than 64 KiB though. | |
d129bceb | 3261 | */ |
30652aa3 OJ |
3262 | if (host->flags & SDHCI_USE_ADMA) { |
3263 | if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) | |
3264 | mmc->max_seg_size = 65535; | |
3265 | else | |
3266 | mmc->max_seg_size = 65536; | |
3267 | } else { | |
2134a922 | 3268 | mmc->max_seg_size = mmc->max_req_size; |
30652aa3 | 3269 | } |
d129bceb | 3270 | |
fe4a3c7a PO |
3271 | /* |
3272 | * Maximum block size. This varies from controller to controller and | |
3273 | * is specified in the capabilities register. | |
3274 | */ | |
0633f654 AV |
3275 | if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { |
3276 | mmc->max_blk_size = 2; | |
3277 | } else { | |
f2119df6 | 3278 | mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> |
0633f654 AV |
3279 | SDHCI_MAX_BLOCK_SHIFT; |
3280 | if (mmc->max_blk_size >= 3) { | |
6606110d JP |
3281 | pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", |
3282 | mmc_hostname(mmc)); | |
0633f654 AV |
3283 | mmc->max_blk_size = 0; |
3284 | } | |
3285 | } | |
3286 | ||
3287 | mmc->max_blk_size = 512 << mmc->max_blk_size; | |
fe4a3c7a | 3288 | |
55db890a PO |
3289 | /* |
3290 | * Maximum block count. | |
3291 | */ | |
1388eefd | 3292 | mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; |
55db890a | 3293 | |
d129bceb PO |
3294 | /* |
3295 | * Init tasklets. | |
3296 | */ | |
d129bceb PO |
3297 | tasklet_init(&host->finish_tasklet, |
3298 | sdhci_tasklet_finish, (unsigned long)host); | |
3299 | ||
e4cad1b5 | 3300 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
d129bceb | 3301 | |
250fb7b4 | 3302 | init_waitqueue_head(&host->buf_ready_int); |
b513ea25 | 3303 | |
2af502ca SG |
3304 | sdhci_init(host, 0); |
3305 | ||
781e989c RK |
3306 | ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, |
3307 | IRQF_SHARED, mmc_hostname(mmc), host); | |
0fc81ee3 MB |
3308 | if (ret) { |
3309 | pr_err("%s: Failed to request IRQ %d: %d\n", | |
3310 | mmc_hostname(mmc), host->irq, ret); | |
8ef1a143 | 3311 | goto untasklet; |
0fc81ee3 | 3312 | } |
d129bceb | 3313 | |
d129bceb PO |
3314 | #ifdef CONFIG_MMC_DEBUG |
3315 | sdhci_dumpregs(host); | |
3316 | #endif | |
3317 | ||
f9134319 | 3318 | #ifdef SDHCI_USE_LEDS_CLASS |
5dbace0c HS |
3319 | snprintf(host->led_name, sizeof(host->led_name), |
3320 | "%s::", mmc_hostname(mmc)); | |
3321 | host->led.name = host->led_name; | |
2f730fec PO |
3322 | host->led.brightness = LED_OFF; |
3323 | host->led.default_trigger = mmc_hostname(mmc); | |
3324 | host->led.brightness_set = sdhci_led_control; | |
3325 | ||
b8c86fc5 | 3326 | ret = led_classdev_register(mmc_dev(mmc), &host->led); |
0fc81ee3 MB |
3327 | if (ret) { |
3328 | pr_err("%s: Failed to register LED device: %d\n", | |
3329 | mmc_hostname(mmc), ret); | |
eb5c20de | 3330 | goto unirq; |
0fc81ee3 | 3331 | } |
2f730fec PO |
3332 | #endif |
3333 | ||
5f25a66f PO |
3334 | mmiowb(); |
3335 | ||
eb5c20de AH |
3336 | ret = mmc_add_host(mmc); |
3337 | if (ret) | |
3338 | goto unled; | |
d129bceb | 3339 | |
a3c76eb9 | 3340 | pr_info("%s: SDHCI controller on %s [%s] using %s\n", |
d1b26863 | 3341 | mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), |
e57a5f61 AH |
3342 | (host->flags & SDHCI_USE_ADMA) ? |
3343 | (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : | |
a13abc7b | 3344 | (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); |
d129bceb | 3345 | |
7260cf5e AV |
3346 | sdhci_enable_card_detection(host); |
3347 | ||
d129bceb PO |
3348 | return 0; |
3349 | ||
eb5c20de | 3350 | unled: |
f9134319 | 3351 | #ifdef SDHCI_USE_LEDS_CLASS |
eb5c20de AH |
3352 | led_classdev_unregister(&host->led); |
3353 | unirq: | |
3354 | #endif | |
03231f9b | 3355 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
b537f94c RK |
3356 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
3357 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); | |
2f730fec | 3358 | free_irq(host->irq, host); |
8ef1a143 | 3359 | untasklet: |
d129bceb | 3360 | tasklet_kill(&host->finish_tasklet); |
eb5c20de AH |
3361 | unreg: |
3362 | if (!IS_ERR(mmc->supply.vqmmc)) | |
3363 | regulator_disable(mmc->supply.vqmmc); | |
3364 | undma: | |
3365 | if (host->align_buffer) | |
3366 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + | |
3367 | host->adma_table_sz, host->align_buffer, | |
3368 | host->align_addr); | |
3369 | host->adma_table = NULL; | |
3370 | host->align_buffer = NULL; | |
d129bceb PO |
3371 | |
3372 | return ret; | |
3373 | } | |
3374 | ||
b8c86fc5 | 3375 | EXPORT_SYMBOL_GPL(sdhci_add_host); |
d129bceb | 3376 | |
1e72859e | 3377 | void sdhci_remove_host(struct sdhci_host *host, int dead) |
b8c86fc5 | 3378 | { |
3a48edc4 | 3379 | struct mmc_host *mmc = host->mmc; |
1e72859e PO |
3380 | unsigned long flags; |
3381 | ||
3382 | if (dead) { | |
3383 | spin_lock_irqsave(&host->lock, flags); | |
3384 | ||
3385 | host->flags |= SDHCI_DEVICE_DEAD; | |
3386 | ||
3387 | if (host->mrq) { | |
a3c76eb9 | 3388 | pr_err("%s: Controller removed during " |
4e743f1f | 3389 | " transfer!\n", mmc_hostname(mmc)); |
1e72859e PO |
3390 | |
3391 | host->mrq->cmd->error = -ENOMEDIUM; | |
3392 | tasklet_schedule(&host->finish_tasklet); | |
3393 | } | |
3394 | ||
3395 | spin_unlock_irqrestore(&host->lock, flags); | |
3396 | } | |
3397 | ||
7260cf5e AV |
3398 | sdhci_disable_card_detection(host); |
3399 | ||
4e743f1f | 3400 | mmc_remove_host(mmc); |
d129bceb | 3401 | |
f9134319 | 3402 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
3403 | led_classdev_unregister(&host->led); |
3404 | #endif | |
3405 | ||
1e72859e | 3406 | if (!dead) |
03231f9b | 3407 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
d129bceb | 3408 | |
b537f94c RK |
3409 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
3410 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); | |
d129bceb PO |
3411 | free_irq(host->irq, host); |
3412 | ||
3413 | del_timer_sync(&host->timer); | |
3414 | ||
d129bceb | 3415 | tasklet_kill(&host->finish_tasklet); |
2134a922 | 3416 | |
3a48edc4 TK |
3417 | if (!IS_ERR(mmc->supply.vqmmc)) |
3418 | regulator_disable(mmc->supply.vqmmc); | |
6231f3de | 3419 | |
edd63fcc | 3420 | if (host->align_buffer) |
e66e61cb RK |
3421 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + |
3422 | host->adma_table_sz, host->align_buffer, | |
3423 | host->align_addr); | |
2134a922 | 3424 | |
4efaa6fb | 3425 | host->adma_table = NULL; |
2134a922 | 3426 | host->align_buffer = NULL; |
d129bceb PO |
3427 | } |
3428 | ||
b8c86fc5 | 3429 | EXPORT_SYMBOL_GPL(sdhci_remove_host); |
d129bceb | 3430 | |
b8c86fc5 | 3431 | void sdhci_free_host(struct sdhci_host *host) |
d129bceb | 3432 | { |
b8c86fc5 | 3433 | mmc_free_host(host->mmc); |
d129bceb PO |
3434 | } |
3435 | ||
b8c86fc5 | 3436 | EXPORT_SYMBOL_GPL(sdhci_free_host); |
d129bceb PO |
3437 | |
3438 | /*****************************************************************************\ | |
3439 | * * | |
3440 | * Driver init/exit * | |
3441 | * * | |
3442 | \*****************************************************************************/ | |
3443 | ||
3444 | static int __init sdhci_drv_init(void) | |
3445 | { | |
a3c76eb9 | 3446 | pr_info(DRIVER_NAME |
52fbf9c9 | 3447 | ": Secure Digital Host Controller Interface driver\n"); |
a3c76eb9 | 3448 | pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
d129bceb | 3449 | |
b8c86fc5 | 3450 | return 0; |
d129bceb PO |
3451 | } |
3452 | ||
3453 | static void __exit sdhci_drv_exit(void) | |
3454 | { | |
d129bceb PO |
3455 | } |
3456 | ||
3457 | module_init(sdhci_drv_init); | |
3458 | module_exit(sdhci_drv_exit); | |
3459 | ||
df673b22 | 3460 | module_param(debug_quirks, uint, 0444); |
66fd8ad5 | 3461 | module_param(debug_quirks2, uint, 0444); |
67435274 | 3462 | |
32710e8f | 3463 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 | 3464 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); |
d129bceb | 3465 | MODULE_LICENSE("GPL"); |
67435274 | 3466 | |
df673b22 | 3467 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |
66fd8ad5 | 3468 | MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); |