]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/mmc/host/sdhci.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mmc: sdhci: fix data timeout (part 1)
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
f9134319
PO		 41#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43#define SDHCI_USE_LEDS_CLASS
44#endif
45
b513ea25
AN		 46#define MAX_TUNING_LOOP 40
47
df673b22 48static unsigned int debug_quirks = 0;
66fd8ad5 49static unsigned int debug_quirks2;
67435274 50
d129bceb
PO		 51static void sdhci_finish_data(struct sdhci_host *);
52
d129bceb 53static void sdhci_finish_command(struct sdhci_host *);
069c9f14 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
348487cb 56static int sdhci_pre_dma_transfer(struct sdhci_host *host,
d31911b9 57 struct mmc_data *data);
04e079cf 58static int sdhci_do_get_cd(struct sdhci_host *host);
d129bceb 59
162d6f98 60#ifdef CONFIG_PM
66fd8ad5
AH		 61static int sdhci_runtime_pm_get(struct sdhci_host *host);
62static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 63static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
64static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 65#else
66static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
67{
68 return 0;
69}
70static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
71{
72 return 0;
73}
f0710a55
AH		 74static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
75{
76}
77static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
78{
79}
66fd8ad5
AH		 80#endif
81
d129bceb
PO		 82static void sdhci_dumpregs(struct sdhci_host *host)
83{
a3c76eb9 84 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 85 mmc_hostname(host->mmc));
d129bceb 86
a3c76eb9 87 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 88 sdhci_readl(host, SDHCI_DMA_ADDRESS),
89 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 90 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 91 sdhci_readw(host, SDHCI_BLOCK_SIZE),
92 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 93 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 94 sdhci_readl(host, SDHCI_ARGUMENT),
95 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 96 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 97 sdhci_readl(host, SDHCI_PRESENT_STATE),
98 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 99 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 100 sdhci_readb(host, SDHCI_POWER_CONTROL),
101 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 102 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 103 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
104 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 105 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 106 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
107 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 108 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 109 sdhci_readl(host, SDHCI_INT_ENABLE),
110 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 111 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 112 sdhci_readw(host, SDHCI_ACMD12_ERR),
113 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 114 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 115 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 116 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 117 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 118 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 119 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 120 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 121 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 122
e57a5f61
AH		 123 if (host->flags & SDHCI_USE_ADMA) {
124 if (host->flags & SDHCI_USE_64_BIT_DMA)
125 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
126 readl(host->ioaddr + SDHCI_ADMA_ERROR),
127 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
128 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
129 else
130 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
131 readl(host->ioaddr + SDHCI_ADMA_ERROR),
132 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
133 }
be3f4ae0 134
a3c76eb9 135 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 136}
137
138/*****************************************************************************\
139 * *
140 * Low level functions *
141 * *
142\*****************************************************************************/
143
7260cf5e
AV		 144static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
145{
5b4f1f6c 146 u32 present;
7260cf5e 147
c79396c1 148 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 149 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 150 return;
151
5b4f1f6c
RK		 152 if (enable) {
153 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
154 SDHCI_CARD_PRESENT;
d25928d1 155
5b4f1f6c
RK		 156 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
157 SDHCI_INT_CARD_INSERT;
158 } else {
159 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
160 }
b537f94c
RK		 161
162 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
163 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 164}
165
166static void sdhci_enable_card_detection(struct sdhci_host *host)
167{
168 sdhci_set_card_detection(host, true);
169}
170
171static void sdhci_disable_card_detection(struct sdhci_host *host)
172{
173 sdhci_set_card_detection(host, false);
174}
175
03231f9b 176void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 177{
e16514d8 178 unsigned long timeout;
393c1a34 179
4e4141a5 180 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 181
f0710a55 182 if (mask & SDHCI_RESET_ALL) {
d129bceb 183 host->clock = 0;
f0710a55
AH		 184 /* Reset-all turns off SD Bus Power */
185 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
186 sdhci_runtime_pm_bus_off(host);
187 }
d129bceb 188
e16514d8
PO		 189 /* Wait max 100 ms */
190 timeout = 100;
191
192 /* hw clears the bit when it's done */
4e4141a5 193 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 194 if (timeout == 0) {
a3c76eb9 195 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 196 mmc_hostname(host->mmc), (int)mask);
197 sdhci_dumpregs(host);
198 return;
199 }
200 timeout--;
201 mdelay(1);
d129bceb 202 }
03231f9b
RK		 203}
204EXPORT_SYMBOL_GPL(sdhci_reset);
205
206static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
207{
208 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
135b0a28 209 if (!sdhci_do_get_cd(host))
03231f9b
RK		 210 return;
211 }
063a9dbb 212
03231f9b 213 host->ops->reset(host, mask);
393c1a34 214
da91a8f9
RK		 215 if (mask & SDHCI_RESET_ALL) {
216 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
217 if (host->ops->enable_dma)
218 host->ops->enable_dma(host);
219 }
220
221 /* Resetting the controller clears many */
222 host->preset_enabled = false;
3abc1e80 223 }
d129bceb
PO		 224}
225
2f4cbb3d
NP		 226static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
227
228static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 229{
2f4cbb3d 230 if (soft)
03231f9b 231 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 232 else
03231f9b 233 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 234
b537f94c
RK		 235 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
236 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
237 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
238 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
239 SDHCI_INT_RESPONSE;
240
241 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
242 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 243
244 if (soft) {
245 /* force clock reconfiguration */
246 host->clock = 0;
247 sdhci_set_ios(host->mmc, &host->mmc->ios);
248 }
7260cf5e 249}
d129bceb 250
7260cf5e
AV		 251static void sdhci_reinit(struct sdhci_host *host)
252{
2f4cbb3d 253 sdhci_init(host, 0);
7260cf5e 254 sdhci_enable_card_detection(host);
d129bceb
PO		 255}
256
257static void sdhci_activate_led(struct sdhci_host *host)
258{
259 u8 ctrl;
260
4e4141a5 261 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 262 ctrl |= SDHCI_CTRL_LED;
4e4141a5 263 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 264}
265
266static void sdhci_deactivate_led(struct sdhci_host *host)
267{
268 u8 ctrl;
269
4e4141a5 270 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 271 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 272 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 273}
274
f9134319 275#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 276static void sdhci_led_control(struct led_classdev *led,
277 enum led_brightness brightness)
278{
279 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
280 unsigned long flags;
281
282 spin_lock_irqsave(&host->lock, flags);
283
66fd8ad5
AH		 284 if (host->runtime_suspended)
285 goto out;
286
2f730fec
PO		 287 if (brightness == LED_OFF)
288 sdhci_deactivate_led(host);
289 else
290 sdhci_activate_led(host);
66fd8ad5 291out:
2f730fec
PO		 292 spin_unlock_irqrestore(&host->lock, flags);
293}
294#endif
295
d129bceb
PO		 296/*****************************************************************************\
297 * *
298 * Core functions *
299 * *
300\*****************************************************************************/
301
a406f5a3 302static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 303{
7659150c
PO		 304 unsigned long flags;
305 size_t blksize, len, chunk;
7244b85b 306 u32 uninitialized_var(scratch);
7659150c 307 u8 *buf;
d129bceb 308
a406f5a3 309 DBG("PIO reading\n");
d129bceb 310
a406f5a3 311 blksize = host->data->blksz;
7659150c 312 chunk = 0;
d129bceb 313
7659150c 314 local_irq_save(flags);
d129bceb 315
a406f5a3 316 while (blksize) {
bf3a35ac 317 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 318
7659150c 319 len = min(host->sg_miter.length, blksize);
d129bceb 320
7659150c
PO		 321 blksize -= len;
322 host->sg_miter.consumed = len;
14d836e7 323
7659150c 324 buf = host->sg_miter.addr;
d129bceb 325
7659150c
PO		 326 while (len) {
327 if (chunk == 0) {
4e4141a5 328 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 329 chunk = 4;
a406f5a3 330 }
7659150c
PO		 331
332 *buf = scratch & 0xFF;
333
334 buf++;
335 scratch >>= 8;
336 chunk--;
337 len--;
d129bceb 338 }
a406f5a3 339 }
7659150c
PO		 340
341 sg_miter_stop(&host->sg_miter);
342
343 local_irq_restore(flags);
a406f5a3 344}
d129bceb 345
a406f5a3
PO		 346static void sdhci_write_block_pio(struct sdhci_host *host)
347{
7659150c
PO		 348 unsigned long flags;
349 size_t blksize, len, chunk;
350 u32 scratch;
351 u8 *buf;
d129bceb 352
a406f5a3
PO		 353 DBG("PIO writing\n");
354
355 blksize = host->data->blksz;
7659150c
PO		 356 chunk = 0;
357 scratch = 0;
d129bceb 358
7659150c 359 local_irq_save(flags);
d129bceb 360
a406f5a3 361 while (blksize) {
bf3a35ac 362 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 363
7659150c
PO		 364 len = min(host->sg_miter.length, blksize);
365
366 blksize -= len;
367 host->sg_miter.consumed = len;
368
369 buf = host->sg_miter.addr;
d129bceb 370
7659150c
PO		 371 while (len) {
372 scratch |= (u32)*buf << (chunk * 8);
373
374 buf++;
375 chunk++;
376 len--;
377
378 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 379 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 380 chunk = 0;
381 scratch = 0;
d129bceb 382 }
d129bceb
PO		 383 }
384 }
7659150c
PO		 385
386 sg_miter_stop(&host->sg_miter);
387
388 local_irq_restore(flags);
a406f5a3
PO		 389}
390
391static void sdhci_transfer_pio(struct sdhci_host *host)
392{
393 u32 mask;
394
395 BUG_ON(!host->data);
396
7659150c 397 if (host->blocks == 0)
a406f5a3
PO		 398 return;
399
400 if (host->data->flags & MMC_DATA_READ)
401 mask = SDHCI_DATA_AVAILABLE;
402 else
403 mask = SDHCI_SPACE_AVAILABLE;
404
4a3cba32
PO		 405 /*
406 * Some controllers (JMicron JMB38x) mess up the buffer bits
407 * for transfers < 4 bytes. As long as it is just one block,
408 * we can ignore the bits.
409 */
410 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
411 (host->data->blocks == 1))
412 mask = ~0;
413
4e4141a5 414 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 415 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
416 udelay(100);
417
a406f5a3
PO		 418 if (host->data->flags & MMC_DATA_READ)
419 sdhci_read_block_pio(host);
420 else
421 sdhci_write_block_pio(host);
d129bceb 422
7659150c
PO		 423 host->blocks--;
424 if (host->blocks == 0)
a406f5a3 425 break;
a406f5a3 426 }
d129bceb 427
a406f5a3 428 DBG("PIO transfer complete.\n");
d129bceb
PO		 429}
430
2134a922
PO		 431static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
432{
433 local_irq_save(*flags);
482fce99 434 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 435}
436
437static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
438{
482fce99 439 kunmap_atomic(buffer);
2134a922
PO		 440 local_irq_restore(*flags);
441}
442
e57a5f61
AH		 443static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
444 dma_addr_t addr, int len, unsigned cmd)
118cd17d 445{
e57a5f61 446 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 447
e57a5f61 448 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 449 dma_desc->cmd = cpu_to_le16(cmd);
450 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 451 dma_desc->addr_lo = cpu_to_le32((u32)addr);
452
453 if (host->flags & SDHCI_USE_64_BIT_DMA)
454 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 455}
456
b5ffa674
AH		 457static void sdhci_adma_mark_end(void *desc)
458{
e57a5f61 459 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 460
e57a5f61 461 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 462 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 463}
464
8f1934ce 465static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 466 struct mmc_data *data)
467{
1c3d5f6d
AH		 468 void *desc;
469 void *align;
2134a922
PO		 470 dma_addr_t addr;
471 dma_addr_t align_addr;
472 int len, offset;
473
474 struct scatterlist *sg;
475 int i;
476 char *buffer;
477 unsigned long flags;
478
479 /*
480 * The spec does not specify endianness of descriptor table.
481 * We currently guess that it is LE.
482 */
483
d31911b9 484 host->sg_count = sdhci_pre_dma_transfer(host, data);
348487cb 485 if (host->sg_count < 0)
edd63fcc 486 return -EINVAL;
2134a922 487
4efaa6fb 488 desc = host->adma_table;
2134a922
PO		 489 align = host->align_buffer;
490
491 align_addr = host->align_addr;
492
493 for_each_sg(data->sg, sg, host->sg_count, i) {
494 addr = sg_dma_address(sg);
495 len = sg_dma_len(sg);
496
497 /*
498 * The SDHCI specification states that ADMA
499 * addresses must be 32-bit aligned. If they
500 * aren't, then we use a bounce buffer for
501 * the (up to three) bytes that screw up the
502 * alignment.
503 */
04a5ae6f
AH		 504 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
505 SDHCI_ADMA2_MASK;
2134a922
PO		 506 if (offset) {
507 if (data->flags & MMC_DATA_WRITE) {
508 buffer = sdhci_kmap_atomic(sg, &flags);
509 memcpy(align, buffer, offset);
510 sdhci_kunmap_atomic(buffer, &flags);
511 }
512
118cd17d 513 /* tran, valid */
e57a5f61 514 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 515 ADMA2_TRAN_VALID);
2134a922
PO		 516
517 BUG_ON(offset > 65536);
518
04a5ae6f
AH		 519 align += SDHCI_ADMA2_ALIGN;
520 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 521
76fe379a 522 desc += host->desc_sz;
2134a922
PO		 523
524 addr += offset;
525 len -= offset;
526 }
527
2134a922
PO		 528 BUG_ON(len > 65536);
529
347ea32d
AH		 530 if (len) {
531 /* tran, valid */
532 sdhci_adma_write_desc(host, desc, addr, len,
533 ADMA2_TRAN_VALID);
534 desc += host->desc_sz;
535 }
2134a922
PO		 536
537 /*
538 * If this triggers then we have a calculation bug
539 * somewhere. :/
540 */
76fe379a 541 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 542 }
543
70764a90
TA		 544 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
545 /*
546 * Mark the last descriptor as the terminating descriptor
547 */
4efaa6fb 548 if (desc != host->adma_table) {
76fe379a 549 desc -= host->desc_sz;
b5ffa674 550 sdhci_adma_mark_end(desc);
70764a90
TA		 551 }
552 } else {
553 /*
554 * Add a terminating entry.
555 */
2134a922 556
70764a90 557 /* nop, end, valid */
e57a5f61 558 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 559 }
8f1934ce 560 return 0;
2134a922
PO		 561}
562
563static void sdhci_adma_table_post(struct sdhci_host *host,
564 struct mmc_data *data)
565{
566 int direction;
567
568 struct scatterlist *sg;
569 int i, size;
1c3d5f6d 570 void *align;
2134a922
PO		 571 char *buffer;
572 unsigned long flags;
de0b65a7 573 bool has_unaligned;
2134a922
PO		 574
575 if (data->flags & MMC_DATA_READ)
576 direction = DMA_FROM_DEVICE;
577 else
578 direction = DMA_TO_DEVICE;
579
de0b65a7
RK		 580 /* Do a quick scan of the SG list for any unaligned mappings */
581 has_unaligned = false;
582 for_each_sg(data->sg, sg, host->sg_count, i)
04a5ae6f 583 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
de0b65a7
RK		 584 has_unaligned = true;
585 break;
586 }
587
588 if (has_unaligned && data->flags & MMC_DATA_READ) {
2134a922
PO		 589 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
590 data->sg_len, direction);
591
592 align = host->align_buffer;
593
594 for_each_sg(data->sg, sg, host->sg_count, i) {
04a5ae6f
AH		 595 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
596 size = SDHCI_ADMA2_ALIGN -
597 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
2134a922
PO		 598
599 buffer = sdhci_kmap_atomic(sg, &flags);
600 memcpy(buffer, align, size);
601 sdhci_kunmap_atomic(buffer, &flags);
602
04a5ae6f 603 align += SDHCI_ADMA2_ALIGN;
2134a922
PO		 604 }
605 }
606 }
607
d31911b9 608 if (data->host_cookie == COOKIE_MAPPED) {
348487cb
HC		 609 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
610 data->sg_len, direction);
d31911b9
HC		 611 data->host_cookie = COOKIE_UNMAPPED;
612 }
2134a922
PO		 613}
614
a3c7778f 615static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 616{
1c8cde92 617 u8 count;
a3c7778f 618 struct mmc_data *data = cmd->data;
1c8cde92 619 unsigned target_timeout, current_timeout;
d129bceb 620
ee53ab5d
PO		 621 /*
622 * If the host controller provides us with an incorrect timeout
623 * value, just skip the check and use 0xE. The hardware may take
624 * longer to time out, but that's much better than having a too-short
625 * timeout value.
626 */
11a2f1b7 627 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 628 return 0xE;
e538fbe8 629
a3c7778f 630 /* Unspecified timeout, assume max */
1d4d7744 631 if (!data && !cmd->busy_timeout)
a3c7778f 632 return 0xE;
d129bceb 633
a3c7778f
AW		 634 /* timeout in us */
635 if (!data)
1d4d7744 636 target_timeout = cmd->busy_timeout * 1000;
78a2ca27 637 else {
fafcfda9 638 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
78a2ca27
AS		 639 if (host->clock)
640 target_timeout += data->timeout_clks / host->clock;
641 }
81b39802 642
1c8cde92
PO		 643 /*
644 * Figure out needed cycles.
645 * We do this in steps in order to fit inside a 32 bit int.
646 * The first step is the minimum timeout, which will have a
647 * minimum resolution of 6 bits:
648 * (1) 2^13*1000 > 2^22,
649 * (2) host->timeout_clk < 2^16
650 * =>
651 * (1) / (2) > 2^6
652 */
653 count = 0;
654 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
655 while (current_timeout < target_timeout) {
656 count++;
657 current_timeout <<= 1;
658 if (count >= 0xF)
659 break;
660 }
661
662 if (count >= 0xF) {
09eeff52
CB		 663 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
664 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 665 count = 0xE;
666 }
667
ee53ab5d
PO		 668 return count;
669}
670
6aa943ab
AV		 671static void sdhci_set_transfer_irqs(struct sdhci_host *host)
672{
673 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
674 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
675
676 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 677 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 678 else
b537f94c
RK		 679 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
680
681 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
682 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 683}
684
b45e668a 685static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 686{
687 u8 count;
b45e668a
AD		 688
689 if (host->ops->set_timeout) {
690 host->ops->set_timeout(host, cmd);
691 } else {
692 count = sdhci_calc_timeout(host, cmd);
693 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
694 }
695}
696
697static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
698{
2134a922 699 u8 ctrl;
a3c7778f 700 struct mmc_data *data = cmd->data;
8f1934ce 701 int ret;
ee53ab5d
PO		 702
703 WARN_ON(host->data);
704
b45e668a
AD		 705 if (data || (cmd->flags & MMC_RSP_BUSY))
706 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 707
708 if (!data)
ee53ab5d
PO		 709 return;
710
711 /* Sanity checks */
712 BUG_ON(data->blksz * data->blocks > 524288);
713 BUG_ON(data->blksz > host->mmc->max_blk_size);
714 BUG_ON(data->blocks > 65535);
715
716 host->data = data;
717 host->data_early = 0;
f6a03cbf 718 host->data->bytes_xfered = 0;
ee53ab5d 719
a13abc7b 720 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 721 host->flags |= SDHCI_REQ_USE_DMA;
722
2134a922
PO		 723 /*
724 * FIXME: This doesn't account for merging when mapping the
725 * scatterlist.
726 */
727 if (host->flags & SDHCI_REQ_USE_DMA) {
728 int broken, i;
729 struct scatterlist *sg;
730
731 broken = 0;
732 if (host->flags & SDHCI_USE_ADMA) {
733 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
734 broken = 1;
735 } else {
736 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
737 broken = 1;
738 }
739
740 if (unlikely(broken)) {
741 for_each_sg(data->sg, sg, data->sg_len, i) {
742 if (sg->length & 0x3) {
2e4456f0 743 DBG("Reverting to PIO because of transfer size (%d)\n",
2134a922
PO		 744 sg->length);
745 host->flags &= ~SDHCI_REQ_USE_DMA;
746 break;
747 }
748 }
749 }
c9fddbc4
PO		 750 }
751
752 /*
753 * The assumption here being that alignment is the same after
754 * translation to device address space.
755 */
2134a922
PO		 756 if (host->flags & SDHCI_REQ_USE_DMA) {
757 int broken, i;
758 struct scatterlist *sg;
759
760 broken = 0;
761 if (host->flags & SDHCI_USE_ADMA) {
762 /*
763 * As we use 3 byte chunks to work around
764 * alignment problems, we need to check this
765 * quirk.
766 */
767 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
768 broken = 1;
769 } else {
770 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
771 broken = 1;
772 }
773
774 if (unlikely(broken)) {
775 for_each_sg(data->sg, sg, data->sg_len, i) {
776 if (sg->offset & 0x3) {
2e4456f0 777 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 778 host->flags &= ~SDHCI_REQ_USE_DMA;
779 break;
780 }
781 }
782 }
783 }
784
8f1934ce
PO		 785 if (host->flags & SDHCI_REQ_USE_DMA) {
786 if (host->flags & SDHCI_USE_ADMA) {
787 ret = sdhci_adma_table_pre(host, data);
788 if (ret) {
789 /*
790 * This only happens when someone fed
791 * us an invalid request.
792 */
793 WARN_ON(1);
ebd6d357 794 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 795 } else {
4e4141a5
AV		 796 sdhci_writel(host, host->adma_addr,
797 SDHCI_ADMA_ADDRESS);
e57a5f61
AH		 798 if (host->flags & SDHCI_USE_64_BIT_DMA)
799 sdhci_writel(host,
800 (u64)host->adma_addr >> 32,
801 SDHCI_ADMA_ADDRESS_HI);
8f1934ce
PO		 802 }
803 } else {
c8b3e02e 804 int sg_cnt;
8f1934ce 805
d31911b9 806 sg_cnt = sdhci_pre_dma_transfer(host, data);
62a7f368 807 if (sg_cnt <= 0) {
8f1934ce
PO		 808 /*
809 * This only happens when someone fed
810 * us an invalid request.
811 */
812 WARN_ON(1);
ebd6d357 813 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 814 } else {
719a61b4 815 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 816 sdhci_writel(host, sg_dma_address(data->sg),
817 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 818 }
819 }
820 }
821
2134a922
PO		 822 /*
823 * Always adjust the DMA selection as some controllers
824 * (e.g. JMicron) can't do PIO properly when the selection
825 * is ADMA.
826 */
827 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 828 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 829 ctrl &= ~SDHCI_CTRL_DMA_MASK;
830 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 831 (host->flags & SDHCI_USE_ADMA)) {
832 if (host->flags & SDHCI_USE_64_BIT_DMA)
833 ctrl |= SDHCI_CTRL_ADMA64;
834 else
835 ctrl |= SDHCI_CTRL_ADMA32;
836 } else {
2134a922 837 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 838 }
4e4141a5 839 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 840 }
841
8f1934ce 842 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 843 int flags;
844
845 flags = SG_MITER_ATOMIC;
846 if (host->data->flags & MMC_DATA_READ)
847 flags |= SG_MITER_TO_SG;
848 else
849 flags |= SG_MITER_FROM_SG;
850 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 851 host->blocks = data->blocks;
d129bceb 852 }
c7fa9963 853
6aa943ab
AV		 854 sdhci_set_transfer_irqs(host);
855
f6a03cbf
MV		 856 /* Set the DMA boundary value and block size */
857 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
858 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 859 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 860}
861
862static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 863 struct mmc_command *cmd)
c7fa9963 864{
d3fc5d71 865 u16 mode = 0;
e89d456f 866 struct mmc_data *data = cmd->data;
c7fa9963 867
2b558c13 868 if (data == NULL) {
9b8ffea6
VW		 869 if (host->quirks2 &
870 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
871 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
872 } else {
2b558c13 873 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 874 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
875 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 876 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 877 }
c7fa9963 878 return;
2b558c13 879 }
c7fa9963 880
e538fbe8
PO		 881 WARN_ON(!host->data);
882
d3fc5d71
VY		 883 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
884 mode = SDHCI_TRNS_BLK_CNT_EN;
885
e89d456f 886 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 887 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 888 /*
889 * If we are sending CMD23, CMD12 never gets sent
890 * on successful completion (so no Auto-CMD12).
891 */
85cc1c33
CD		 892 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
893 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 894 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 895 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
896 mode |= SDHCI_TRNS_AUTO_CMD23;
897 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
898 }
c4512f79 899 }
8edf6371 900
c7fa9963
PO		 901 if (data->flags & MMC_DATA_READ)
902 mode |= SDHCI_TRNS_READ;
c9fddbc4 903 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 904 mode |= SDHCI_TRNS_DMA;
905
4e4141a5 906 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 907}
908
909static void sdhci_finish_data(struct sdhci_host *host)
910{
911 struct mmc_data *data;
d129bceb
PO		 912
913 BUG_ON(!host->data);
914
915 data = host->data;
916 host->data = NULL;
917
c9fddbc4 918 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 919 if (host->flags & SDHCI_USE_ADMA)
920 sdhci_adma_table_post(host, data);
921 else {
d31911b9 922 if (data->host_cookie == COOKIE_MAPPED) {
348487cb
HC		 923 dma_unmap_sg(mmc_dev(host->mmc),
924 data->sg, data->sg_len,
925 (data->flags & MMC_DATA_READ) ?
2134a922 926 DMA_FROM_DEVICE : DMA_TO_DEVICE);
d31911b9
HC		 927 data->host_cookie = COOKIE_UNMAPPED;
928 }
2134a922 929 }
d129bceb
PO		 930 }
931
932 /*
c9b74c5b
PO		 933 * The specification states that the block count register must
934 * be updated, but it does not specify at what point in the
935 * data flow. That makes the register entirely useless to read
936 * back so we have to assume that nothing made it to the card
937 * in the event of an error.
d129bceb 938 */
c9b74c5b
PO		 939 if (data->error)
940 data->bytes_xfered = 0;
d129bceb 941 else
c9b74c5b 942 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 943
e89d456f
AW		 944 /*
945 * Need to send CMD12 if -
946 * a) open-ended multiblock transfer (no CMD23)
947 * b) error in multiblock transfer
948 */
949 if (data->stop &&
950 (data->error ||
951 !host->mrq->sbc)) {
952
d129bceb
PO		 953 /*
954 * The controller needs a reset of internal state machines
955 * upon error conditions.
956 */
17b0429d 957 if (data->error) {
03231f9b
RK		 958 sdhci_do_reset(host, SDHCI_RESET_CMD);
959 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 960 }
961
962 sdhci_send_command(host, data->stop);
963 } else
964 tasklet_schedule(&host->finish_tasklet);
965}
966
c0e55129 967void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 968{
969 int flags;
fd2208d7 970 u32 mask;
7cb2c76f 971 unsigned long timeout;
d129bceb
PO		 972
973 WARN_ON(host->cmd);
974
96776200
RK		 975 /* Initially, a command has no error */
976 cmd->error = 0;
977
d129bceb 978 /* Wait max 10 ms */
7cb2c76f 979 timeout = 10;
fd2208d7
PO		 980
981 mask = SDHCI_CMD_INHIBIT;
982 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
983 mask |= SDHCI_DATA_INHIBIT;
984
985 /* We shouldn't wait for data inihibit for stop commands, even
986 though they might use busy signaling */
987 if (host->mrq->data && (cmd == host->mrq->data->stop))
988 mask &= ~SDHCI_DATA_INHIBIT;
989
4e4141a5 990 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 991 if (timeout == 0) {
2e4456f0
MV		 992 pr_err("%s: Controller never released inhibit bit(s).\n",
993 mmc_hostname(host->mmc));
d129bceb 994 sdhci_dumpregs(host);
17b0429d 995 cmd->error = -EIO;
d129bceb
PO		 996 tasklet_schedule(&host->finish_tasklet);
997 return;
998 }
7cb2c76f
PO		 999 timeout--;
1000 mdelay(1);
1001 }
d129bceb 1002
3e1a6892 1003 timeout = jiffies;
1d4d7744
UH		 1004 if (!cmd->data && cmd->busy_timeout > 9000)
1005 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1006 else
1007 timeout += 10 * HZ;
1008 mod_timer(&host->timer, timeout);
d129bceb
PO		 1009
1010 host->cmd = cmd;
e99783a4 1011 host->busy_handle = 0;
d129bceb 1012
a3c7778f 1013 sdhci_prepare_data(host, cmd);
d129bceb 1014
4e4141a5 1015 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1016
e89d456f 1017 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1018
d129bceb 1019 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1020 pr_err("%s: Unsupported response type!\n",
d129bceb 1021 mmc_hostname(host->mmc));
17b0429d 1022 cmd->error = -EINVAL;
d129bceb
PO		 1023 tasklet_schedule(&host->finish_tasklet);
1024 return;
1025 }
1026
1027 if (!(cmd->flags & MMC_RSP_PRESENT))
1028 flags = SDHCI_CMD_RESP_NONE;
1029 else if (cmd->flags & MMC_RSP_136)
1030 flags = SDHCI_CMD_RESP_LONG;
1031 else if (cmd->flags & MMC_RSP_BUSY)
1032 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1033 else
1034 flags = SDHCI_CMD_RESP_SHORT;
1035
1036 if (cmd->flags & MMC_RSP_CRC)
1037 flags |= SDHCI_CMD_CRC;
1038 if (cmd->flags & MMC_RSP_OPCODE)
1039 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1040
1041 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1042 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1043 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1044 flags |= SDHCI_CMD_DATA;
1045
4e4141a5 1046 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1047}
c0e55129 1048EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1049
1050static void sdhci_finish_command(struct sdhci_host *host)
1051{
1052 int i;
1053
1054 BUG_ON(host->cmd == NULL);
1055
1056 if (host->cmd->flags & MMC_RSP_PRESENT) {
1057 if (host->cmd->flags & MMC_RSP_136) {
1058 /* CRC is stripped so we need to do some shifting. */
1059 for (i = 0;i < 4;i++) {
4e4141a5 1060 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1061 SDHCI_RESPONSE + (3-i)*4) << 8;
1062 if (i != 3)
1063 host->cmd->resp[i] |=
4e4141a5 1064 sdhci_readb(host,
d129bceb
PO		 1065 SDHCI_RESPONSE + (3-i)*4-1);
1066 }
1067 } else {
4e4141a5 1068 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1069 }
1070 }
1071
e89d456f
AW		 1072 /* Finished CMD23, now send actual command. */
1073 if (host->cmd == host->mrq->sbc) {
1074 host->cmd = NULL;
1075 sdhci_send_command(host, host->mrq->cmd);
1076 } else {
e538fbe8 1077
e89d456f
AW		 1078 /* Processed actual command. */
1079 if (host->data && host->data_early)
1080 sdhci_finish_data(host);
d129bceb 1081
e89d456f
AW		 1082 if (!host->cmd->data)
1083 tasklet_schedule(&host->finish_tasklet);
1084
1085 host->cmd = NULL;
1086 }
d129bceb
PO		 1087}
1088
52983382
KL		 1089static u16 sdhci_get_preset_value(struct sdhci_host *host)
1090{
d975f121 1091 u16 preset = 0;
52983382 1092
d975f121
RK		 1093 switch (host->timing) {
1094 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1095 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1096 break;
d975f121 1097 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1098 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1099 break;
d975f121 1100 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1101 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1102 break;
d975f121
RK		 1103 case MMC_TIMING_UHS_SDR104:
1104 case MMC_TIMING_MMC_HS200:
52983382
KL		 1105 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1106 break;
d975f121 1107 case MMC_TIMING_UHS_DDR50:
0dafa60e 1108 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1109 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1110 break;
e9fb05d5
AH		 1111 case MMC_TIMING_MMC_HS400:
1112 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1113 break;
52983382
KL		 1114 default:
1115 pr_warn("%s: Invalid UHS-I mode selected\n",
1116 mmc_hostname(host->mmc));
1117 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1118 break;
1119 }
1120 return preset;
1121}
1122
1771059c 1123void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1124{
c3ed3877 1125 int div = 0; /* Initialized for compiler warning */
df16219f 1126 int real_div = div, clk_mul = 1;
c3ed3877 1127 u16 clk = 0;
7cb2c76f 1128 unsigned long timeout;
5497159c 1129 bool switch_base_clk = false;
d129bceb 1130
1650d0c7
RK		 1131 host->mmc->actual_clock = 0;
1132
4e4141a5 1133 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
af951761 1134 if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1135 mdelay(1);
d129bceb
PO		 1136
1137 if (clock == 0)
373073ef 1138 return;
d129bceb 1139
85105c53 1140 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1141 if (host->preset_enabled) {
52983382
KL		 1142 u16 pre_val;
1143
1144 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1145 pre_val = sdhci_get_preset_value(host);
1146 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1147 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1148 if (host->clk_mul &&
1149 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1150 clk = SDHCI_PROG_CLOCK_MODE;
1151 real_div = div + 1;
1152 clk_mul = host->clk_mul;
1153 } else {
1154 real_div = max_t(int, 1, div << 1);
1155 }
1156 goto clock_set;
1157 }
1158
c3ed3877
AN		 1159 /*
1160 * Check if the Host Controller supports Programmable Clock
1161 * Mode.
1162 */
1163 if (host->clk_mul) {
52983382
KL		 1164 for (div = 1; div <= 1024; div++) {
1165 if ((host->max_clk * host->clk_mul / div)
1166 <= clock)
1167 break;
1168 }
5497159c 1169 if ((host->max_clk * host->clk_mul / div) <= clock) {
1170 /*
1171 * Set Programmable Clock Mode in the Clock
1172 * Control register.
1173 */
1174 clk = SDHCI_PROG_CLOCK_MODE;
1175 real_div = div;
1176 clk_mul = host->clk_mul;
1177 div--;
1178 } else {
1179 /*
1180 * Divisor can be too small to reach clock
1181 * speed requirement. Then use the base clock.
1182 */
1183 switch_base_clk = true;
1184 }
1185 }
1186
1187 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1188 /* Version 3.00 divisors must be a multiple of 2. */
1189 if (host->max_clk <= clock)
1190 div = 1;
1191 else {
1192 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1193 div += 2) {
1194 if ((host->max_clk / div) <= clock)
1195 break;
1196 }
85105c53 1197 }
df16219f 1198 real_div = div;
c3ed3877 1199 div >>= 1;
d1955c3a
SG		 1200 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1201 && !div && host->max_clk <= 25000000)
1202 div = 1;
85105c53
ZG		 1203 }
1204 } else {
1205 /* Version 2.00 divisors must be a power of 2. */
0397526d 1206 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1207 if ((host->max_clk / div) <= clock)
1208 break;
1209 }
df16219f 1210 real_div = div;
c3ed3877 1211 div >>= 1;
d129bceb 1212 }
d129bceb 1213
52983382 1214clock_set:
03d6f5ff 1215 if (real_div)
df16219f 1216 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1217 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1218 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1219 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1220 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1221 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1222
27f6cb16
CB		 1223 /* Wait max 20 ms */
1224 timeout = 20;
4e4141a5 1225 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1226 & SDHCI_CLOCK_INT_STABLE)) {
1227 if (timeout == 0) {
2e4456f0
MV		 1228 pr_err("%s: Internal clock never stabilised.\n",
1229 mmc_hostname(host->mmc));
d129bceb
PO		 1230 sdhci_dumpregs(host);
1231 return;
1232 }
7cb2c76f
PO		 1233 timeout--;
1234 mdelay(1);
1235 }
d129bceb
PO		 1236
1237 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1238 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1239}
1771059c 1240EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1241
24fbb3ca
RK		 1242static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1243 unsigned short vdd)
146ad66e 1244{
3a48edc4 1245 struct mmc_host *mmc = host->mmc;
8364248a 1246 u8 pwr = 0;
146ad66e 1247
24fbb3ca
RK		 1248 if (mode != MMC_POWER_OFF) {
1249 switch (1 << vdd) {
ae628903
PO		 1250 case MMC_VDD_165_195:
1251 pwr = SDHCI_POWER_180;
1252 break;
1253 case MMC_VDD_29_30:
1254 case MMC_VDD_30_31:
1255 pwr = SDHCI_POWER_300;
1256 break;
1257 case MMC_VDD_32_33:
1258 case MMC_VDD_33_34:
1259 pwr = SDHCI_POWER_330;
1260 break;
1261 default:
9d5de93f
AH		 1262 WARN(1, "%s: Invalid vdd %#x\n",
1263 mmc_hostname(host->mmc), vdd);
1264 break;
ae628903
PO		 1265 }
1266 }
1267
1268 if (host->pwr == pwr)
e921a8b6 1269 return;
146ad66e 1270
ae628903
PO		 1271 host->pwr = pwr;
1272
1273 if (pwr == 0) {
4e4141a5 1274 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1275 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1276 sdhci_runtime_pm_bus_off(host);
24fbb3ca 1277 vdd = 0;
e921a8b6
RK		 1278 } else {
1279 /*
1280 * Spec says that we should clear the power reg before setting
1281 * a new value. Some controllers don't seem to like this though.
1282 */
1283 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1284 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1285
e921a8b6
RK		 1286 /*
1287 * At least the Marvell CaFe chip gets confused if we set the
1288 * voltage and set turn on power at the same time, so set the
1289 * voltage first.
1290 */
1291 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1292 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1293
e921a8b6 1294 pwr |= SDHCI_POWER_ON;
146ad66e 1295
e921a8b6 1296 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1297
e921a8b6
RK		 1298 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1299 sdhci_runtime_pm_bus_on(host);
f0710a55 1300
e921a8b6
RK		 1301 /*
1302 * Some controllers need an extra 10ms delay of 10ms before
1303 * they can apply clock after applying power
1304 */
1305 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1306 mdelay(10);
1307 }
918f4cbd
JZ		 1308
1309 if (!IS_ERR(mmc->supply.vmmc)) {
1310 spin_unlock_irq(&host->lock);
1311 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1312 spin_lock_irq(&host->lock);
1313 }
146ad66e
PO		 1314}
1315
d129bceb
PO		 1316/*****************************************************************************\
1317 * *
1318 * MMC callbacks *
1319 * *
1320\*****************************************************************************/
1321
1322static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1323{
1324 struct sdhci_host *host;
505a8680 1325 int present;
d129bceb
PO		 1326 unsigned long flags;
1327
1328 host = mmc_priv(mmc);
1329
66fd8ad5
AH		 1330 sdhci_runtime_pm_get(host);
1331
04e079cf 1332 /* Firstly check card presence */
8d28b7a7 1333 present = mmc->ops->get_cd(mmc);
2836766a 1334
d129bceb
PO		 1335 spin_lock_irqsave(&host->lock, flags);
1336
1337 WARN_ON(host->mrq != NULL);
1338
f9134319 1339#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1340 sdhci_activate_led(host);
2f730fec 1341#endif
e89d456f
AW		 1342
1343 /*
1344 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1345 * requests if Auto-CMD12 is enabled.
1346 */
1347 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1348 if (mrq->stop) {
1349 mrq->data->stop = NULL;
1350 mrq->stop = NULL;
1351 }
1352 }
d129bceb
PO		 1353
1354 host->mrq = mrq;
1355
68d1fb7e 1356 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1357 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1358 tasklet_schedule(&host->finish_tasklet);
cf2b5eea 1359 } else {
8edf6371 1360 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1361 sdhci_send_command(host, mrq->sbc);
1362 else
1363 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1364 }
d129bceb 1365
5f25a66f 1366 mmiowb();
d129bceb
PO		 1367 spin_unlock_irqrestore(&host->lock, flags);
1368}
1369
2317f56c
RK		 1370void sdhci_set_bus_width(struct sdhci_host *host, int width)
1371{
1372 u8 ctrl;
1373
1374 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1375 if (width == MMC_BUS_WIDTH_8) {
1376 ctrl &= ~SDHCI_CTRL_4BITBUS;
1377 if (host->version >= SDHCI_SPEC_300)
1378 ctrl |= SDHCI_CTRL_8BITBUS;
1379 } else {
1380 if (host->version >= SDHCI_SPEC_300)
1381 ctrl &= ~SDHCI_CTRL_8BITBUS;
1382 if (width == MMC_BUS_WIDTH_4)
1383 ctrl |= SDHCI_CTRL_4BITBUS;
1384 else
1385 ctrl &= ~SDHCI_CTRL_4BITBUS;
1386 }
1387 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1388}
1389EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1390
96d7b78c
RK		 1391void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1392{
1393 u16 ctrl_2;
1394
1395 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1396 /* Select Bus Speed Mode for host */
1397 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1398 if ((timing == MMC_TIMING_MMC_HS200) ||
1399 (timing == MMC_TIMING_UHS_SDR104))
1400 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1401 else if (timing == MMC_TIMING_UHS_SDR12)
1402 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1403 else if (timing == MMC_TIMING_UHS_SDR25)
1404 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1405 else if (timing == MMC_TIMING_UHS_SDR50)
1406 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1407 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1408 (timing == MMC_TIMING_MMC_DDR52))
1409 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1410 else if (timing == MMC_TIMING_MMC_HS400)
1411 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1412 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1413}
1414EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1415
66fd8ad5 1416static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1417{
d129bceb
PO		 1418 unsigned long flags;
1419 u8 ctrl;
3a48edc4 1420 struct mmc_host *mmc = host->mmc;
d129bceb 1421
d129bceb
PO		 1422 spin_lock_irqsave(&host->lock, flags);
1423
ceb6143b
AH		 1424 if (host->flags & SDHCI_DEVICE_DEAD) {
1425 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1426 if (!IS_ERR(mmc->supply.vmmc) &&
1427 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1428 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1429 return;
1430 }
1e72859e 1431
d129bceb
PO		 1432 /*
1433 * Reset the chip on each power off.
1434 * Should clear out any weird states.
1435 */
1436 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1437 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1438 sdhci_reinit(host);
d129bceb
PO		 1439 }
1440
52983382 1441 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1442 (ios->power_mode == MMC_POWER_UP) &&
1443 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1444 sdhci_enable_preset_value(host, false);
1445
373073ef 1446 if (!ios->clock || ios->clock != host->clock) {
1771059c 1447 host->ops->set_clock(host, ios->clock);
373073ef 1448 host->clock = ios->clock;
03d6f5ff
AD		 1449
1450 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1451 host->clock) {
1452 host->timeout_clk = host->mmc->actual_clock ?
1453 host->mmc->actual_clock / 1000 :
1454 host->clock / 1000;
1455 host->mmc->max_busy_timeout =
1456 host->ops->get_max_timeout_count ?
1457 host->ops->get_max_timeout_count(host) :
1458 1 << 27;
1459 host->mmc->max_busy_timeout /= host->timeout_clk;
1460 }
373073ef 1461 }
d129bceb 1462
24fbb3ca 1463 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1464
643a81ff
PR		 1465 if (host->ops->platform_send_init_74_clocks)
1466 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1467
2317f56c 1468 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1469
15ec4461 1470 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1471
3ab9c8da
PR		 1472 if ((ios->timing == MMC_TIMING_SD_HS ||
1473 ios->timing == MMC_TIMING_MMC_HS)
1474 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1475 ctrl |= SDHCI_CTRL_HISPD;
1476 else
1477 ctrl &= ~SDHCI_CTRL_HISPD;
1478
d6d50a15 1479 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1480 u16 clk, ctrl_2;
49c468fc
AN		 1481
1482 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1483 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1484 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1485 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1486 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1487 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1488 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1489 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1490 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1491
da91a8f9 1492 if (!host->preset_enabled) {
758535c4 1493 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1494 /*
1495 * We only need to set Driver Strength if the
1496 * preset value enable is not set.
1497 */
da91a8f9 1498 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1499 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1500 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1501 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1502 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1503 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1504 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1505 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1506 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1507 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1508 else {
2e4456f0
MV		 1509 pr_warn("%s: invalid driver type, default to driver type B\n",
1510 mmc_hostname(mmc));
43e943a0
PG		 1511 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1512 }
d6d50a15
AN		 1513
1514 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1515 } else {
1516 /*
1517 * According to SDHC Spec v3.00, if the Preset Value
1518 * Enable in the Host Control 2 register is set, we
1519 * need to reset SD Clock Enable before changing High
1520 * Speed Enable to avoid generating clock gliches.
1521 */
758535c4
AN		 1522
1523 /* Reset SD Clock Enable */
1524 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1525 clk &= ~SDHCI_CLOCK_CARD_EN;
1526 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1527
1528 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1529
1530 /* Re-enable SD Clock */
1771059c 1531 host->ops->set_clock(host, host->clock);
d6d50a15 1532 }
49c468fc 1533
49c468fc
AN		 1534 /* Reset SD Clock Enable */
1535 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1536 clk &= ~SDHCI_CLOCK_CARD_EN;
1537 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1538
96d7b78c 1539 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1540 host->timing = ios->timing;
49c468fc 1541
52983382
KL		 1542 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1543 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1544 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1545 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1546 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 1547 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1548 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 1549 u16 preset;
1550
1551 sdhci_enable_preset_value(host, true);
1552 preset = sdhci_get_preset_value(host);
1553 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1554 >> SDHCI_PRESET_DRV_SHIFT;
1555 }
1556
49c468fc 1557 /* Re-enable SD Clock */
1771059c 1558 host->ops->set_clock(host, host->clock);
758535c4
AN		 1559 } else
1560 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1561
b8352260
LD		 1562 /*
1563 * Some (ENE) controllers go apeshit on some ios operation,
1564 * signalling timeout and CRC errors even on CMD0. Resetting
1565 * it on each ios seems to solve the problem.
1566 */
c63705e1 1567 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1568 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1569
5f25a66f 1570 mmiowb();
d129bceb
PO		 1571 spin_unlock_irqrestore(&host->lock, flags);
1572}
1573
66fd8ad5
AH		 1574static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1575{
1576 struct sdhci_host *host = mmc_priv(mmc);
1577
1578 sdhci_runtime_pm_get(host);
1579 sdhci_do_set_ios(host, ios);
1580 sdhci_runtime_pm_put(host);
1581}
1582
94144a46
KL		 1583static int sdhci_do_get_cd(struct sdhci_host *host)
1584{
1585 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1586
1587 if (host->flags & SDHCI_DEVICE_DEAD)
1588 return 0;
1589
88af5655
II		 1590 /* If nonremovable, assume that the card is always present. */
1591 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
94144a46
KL		 1592 return 1;
1593
88af5655
II		 1594 /*
1595 * Try slot gpio detect, if defined it take precedence
1596 * over build in controller functionality
1597 */
94144a46
KL		 1598 if (!IS_ERR_VALUE(gpio_cd))
1599 return !!gpio_cd;
1600
88af5655
II		 1601 /* If polling, assume that the card is always present. */
1602 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1603 return 1;
1604
94144a46
KL		 1605 /* Host native card detect */
1606 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1607}
1608
1609static int sdhci_get_cd(struct mmc_host *mmc)
1610{
1611 struct sdhci_host *host = mmc_priv(mmc);
1612 int ret;
1613
1614 sdhci_runtime_pm_get(host);
1615 ret = sdhci_do_get_cd(host);
1616 sdhci_runtime_pm_put(host);
1617 return ret;
1618}
1619
66fd8ad5 1620static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1621{
d129bceb 1622 unsigned long flags;
2dfb579c 1623 int is_readonly;
d129bceb 1624
d129bceb
PO		 1625 spin_lock_irqsave(&host->lock, flags);
1626
1e72859e 1627 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1628 is_readonly = 0;
1629 else if (host->ops->get_ro)
1630 is_readonly = host->ops->get_ro(host);
1e72859e 1631 else
2dfb579c
WS		 1632 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1633 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1634
1635 spin_unlock_irqrestore(&host->lock, flags);
1636
2dfb579c
WS		 1637 /* This quirk needs to be replaced by a callback-function later */
1638 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1639 !is_readonly : is_readonly;
d129bceb
PO		 1640}
1641
82b0e23a
TI		 1642#define SAMPLE_COUNT 5
1643
66fd8ad5 1644static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1645{
82b0e23a
TI		 1646 int i, ro_count;
1647
82b0e23a 1648 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1649 return sdhci_check_ro(host);
82b0e23a
TI		 1650
1651 ro_count = 0;
1652 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1653 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1654 if (++ro_count > SAMPLE_COUNT / 2)
1655 return 1;
1656 }
1657 msleep(30);
1658 }
1659 return 0;
1660}
1661
20758b66
AH		 1662static void sdhci_hw_reset(struct mmc_host *mmc)
1663{
1664 struct sdhci_host *host = mmc_priv(mmc);
1665
1666 if (host->ops && host->ops->hw_reset)
1667 host->ops->hw_reset(host);
1668}
1669
66fd8ad5 1670static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1671{
66fd8ad5
AH		 1672 struct sdhci_host *host = mmc_priv(mmc);
1673 int ret;
f75979b7 1674
66fd8ad5
AH		 1675 sdhci_runtime_pm_get(host);
1676 ret = sdhci_do_get_ro(host);
1677 sdhci_runtime_pm_put(host);
1678 return ret;
1679}
f75979b7 1680
66fd8ad5
AH		 1681static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1682{
be138554 1683 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1684 if (enable)
b537f94c 1685 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1686 else
b537f94c
RK		 1687 host->ier &= ~SDHCI_INT_CARD_INT;
1688
1689 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1690 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1691 mmiowb();
1692 }
66fd8ad5
AH		 1693}
1694
1695static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1696{
1697 struct sdhci_host *host = mmc_priv(mmc);
1698 unsigned long flags;
f75979b7 1699
ef104333
RK		 1700 sdhci_runtime_pm_get(host);
1701
66fd8ad5 1702 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1703 if (enable)
1704 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1705 else
1706 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1707
66fd8ad5 1708 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1709 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1710
1711 sdhci_runtime_pm_put(host);
f75979b7
PO		 1712}
1713
20b92a30 1714static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1715 struct mmc_ios *ios)
f2119df6 1716{
3a48edc4 1717 struct mmc_host *mmc = host->mmc;
20b92a30 1718 u16 ctrl;
6231f3de 1719 int ret;
f2119df6 1720
20b92a30
KL		 1721 /*
1722 * Signal Voltage Switching is only applicable for Host Controllers
1723 * v3.00 and above.
1724 */
1725 if (host->version < SDHCI_SPEC_300)
1726 return 0;
6231f3de 1727
f2119df6 1728 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1729
21f5998f 1730 switch (ios->signal_voltage) {
20b92a30
KL		 1731 case MMC_SIGNAL_VOLTAGE_330:
1732 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1733 ctrl &= ~SDHCI_CTRL_VDD_180;
1734 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1735
3a48edc4
TK		 1736 if (!IS_ERR(mmc->supply.vqmmc)) {
1737 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1738 3600000);
20b92a30 1739 if (ret) {
6606110d
JP		 1740 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1741 mmc_hostname(mmc));
20b92a30
KL		 1742 return -EIO;
1743 }
1744 }
1745 /* Wait for 5ms */
1746 usleep_range(5000, 5500);
f2119df6 1747
20b92a30
KL		 1748 /* 3.3V regulator output should be stable within 5 ms */
1749 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1750 if (!(ctrl & SDHCI_CTRL_VDD_180))
1751 return 0;
6231f3de 1752
6606110d
JP		 1753 pr_warn("%s: 3.3V regulator output did not became stable\n",
1754 mmc_hostname(mmc));
20b92a30
KL		 1755
1756 return -EAGAIN;
1757 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1758 if (!IS_ERR(mmc->supply.vqmmc)) {
1759 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1760 1700000, 1950000);
1761 if (ret) {
6606110d
JP		 1762 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1763 mmc_hostname(mmc));
20b92a30
KL		 1764 return -EIO;
1765 }
1766 }
6231f3de 1767
6231f3de
PR		 1768 /*
1769 * Enable 1.8V Signal Enable in the Host Control2
1770 * register
1771 */
20b92a30
KL		 1772 ctrl |= SDHCI_CTRL_VDD_180;
1773 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1774
9d967a61
VY		 1775 /* Some controller need to do more when switching */
1776 if (host->ops->voltage_switch)
1777 host->ops->voltage_switch(host);
1778
20b92a30
KL		 1779 /* 1.8V regulator output should be stable within 5 ms */
1780 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1781 if (ctrl & SDHCI_CTRL_VDD_180)
1782 return 0;
f2119df6 1783
6606110d
JP		 1784 pr_warn("%s: 1.8V regulator output did not became stable\n",
1785 mmc_hostname(mmc));
f2119df6 1786
20b92a30
KL		 1787 return -EAGAIN;
1788 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1789 if (!IS_ERR(mmc->supply.vqmmc)) {
1790 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1791 1300000);
20b92a30 1792 if (ret) {
6606110d
JP		 1793 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1794 mmc_hostname(mmc));
20b92a30 1795 return -EIO;
f2119df6
AN		 1796 }
1797 }
6231f3de 1798 return 0;
20b92a30 1799 default:
f2119df6
AN		 1800 /* No signal voltage switch required */
1801 return 0;
20b92a30 1802 }
f2119df6
AN		 1803}
1804
66fd8ad5 1805static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1806 struct mmc_ios *ios)
66fd8ad5
AH		 1807{
1808 struct sdhci_host *host = mmc_priv(mmc);
1809 int err;
1810
1811 if (host->version < SDHCI_SPEC_300)
1812 return 0;
1813 sdhci_runtime_pm_get(host);
21f5998f 1814 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1815 sdhci_runtime_pm_put(host);
1816 return err;
1817}
1818
20b92a30
KL		 1819static int sdhci_card_busy(struct mmc_host *mmc)
1820{
1821 struct sdhci_host *host = mmc_priv(mmc);
1822 u32 present_state;
1823
1824 sdhci_runtime_pm_get(host);
1825 /* Check whether DAT[3:0] is 0000 */
1826 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1827 sdhci_runtime_pm_put(host);
1828
1829 return !(present_state & SDHCI_DATA_LVL_MASK);
1830}
1831
b5540ce1
AH		 1832static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1833{
1834 struct sdhci_host *host = mmc_priv(mmc);
1835 unsigned long flags;
1836
1837 spin_lock_irqsave(&host->lock, flags);
1838 host->flags |= SDHCI_HS400_TUNING;
1839 spin_unlock_irqrestore(&host->lock, flags);
1840
1841 return 0;
1842}
1843
069c9f14 1844static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1845{
4b6f37d3 1846 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1847 u16 ctrl;
b513ea25 1848 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1849 int err = 0;
2b35bd83 1850 unsigned long flags;
38e40bf5 1851 unsigned int tuning_count = 0;
b5540ce1 1852 bool hs400_tuning;
b513ea25 1853
66fd8ad5 1854 sdhci_runtime_pm_get(host);
2b35bd83 1855 spin_lock_irqsave(&host->lock, flags);
b513ea25 1856
b5540ce1
AH		 1857 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1858 host->flags &= ~SDHCI_HS400_TUNING;
1859
38e40bf5
AH		 1860 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1861 tuning_count = host->tuning_count;
1862
b513ea25 1863 /*
9faac7b9
WY		 1864 * The Host Controller needs tuning in case of SDR104 and DDR50
1865 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1866 * the Capabilities register.
069c9f14
G		 1867 * If the Host Controller supports the HS200 mode then the
1868 * tuning function has to be executed.
b513ea25 1869 */
4b6f37d3 1870 switch (host->timing) {
b5540ce1 1871 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1872 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1873 err = -EINVAL;
1874 goto out_unlock;
1875
4b6f37d3 1876 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1877 /*
1878 * Periodic re-tuning for HS400 is not expected to be needed, so
1879 * disable it here.
1880 */
1881 if (hs400_tuning)
1882 tuning_count = 0;
1883 break;
1884
4b6f37d3 1885 case MMC_TIMING_UHS_SDR104:
9faac7b9 1886 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 1887 break;
1888
1889 case MMC_TIMING_UHS_SDR50:
1890 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1891 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1892 break;
1893 /* FALLTHROUGH */
1894
1895 default:
d519c863 1896 goto out_unlock;
b513ea25
AN		 1897 }
1898
45251812 1899 if (host->ops->platform_execute_tuning) {
2b35bd83 1900 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1901 err = host->ops->platform_execute_tuning(host, opcode);
1902 sdhci_runtime_pm_put(host);
1903 return err;
1904 }
1905
4b6f37d3
RK		 1906 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1907 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 1908 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1909 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 1910 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1911
1912 /*
1913 * As per the Host Controller spec v3.00, tuning command
1914 * generates Buffer Read Ready interrupt, so enable that.
1915 *
1916 * Note: The spec clearly says that when tuning sequence
1917 * is being performed, the controller does not generate
1918 * interrupts other than Buffer Read Ready interrupt. But
1919 * to make sure we don't hit a controller bug, we _only_
1920 * enable Buffer Read Ready interrupt here.
1921 */
b537f94c
RK		 1922 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1923 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1924
1925 /*
1926 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1927 * of loops reaches 40 times or a timeout of 150ms occurs.
1928 */
b513ea25
AN		 1929 do {
1930 struct mmc_command cmd = {0};
66fd8ad5 1931 struct mmc_request mrq = {NULL};
b513ea25 1932
069c9f14 1933 cmd.opcode = opcode;
b513ea25
AN		 1934 cmd.arg = 0;
1935 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1936 cmd.retries = 0;
1937 cmd.data = NULL;
1938 cmd.error = 0;
1939
7ce45e95
AC		 1940 if (tuning_loop_counter-- == 0)
1941 break;
1942
b513ea25
AN		 1943 mrq.cmd = &cmd;
1944 host->mrq = &mrq;
1945
1946 /*
1947 * In response to CMD19, the card sends 64 bytes of tuning
1948 * block to the Host Controller. So we set the block size
1949 * to 64 here.
1950 */
069c9f14
G		 1951 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1952 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1953 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1954 SDHCI_BLOCK_SIZE);
1955 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1956 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1957 SDHCI_BLOCK_SIZE);
1958 } else {
1959 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1960 SDHCI_BLOCK_SIZE);
1961 }
b513ea25
AN		 1962
1963 /*
1964 * The tuning block is sent by the card to the host controller.
1965 * So we set the TRNS_READ bit in the Transfer Mode register.
1966 * This also takes care of setting DMA Enable and Multi Block
1967 * Select in the same register to 0.
1968 */
1969 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1970
1971 sdhci_send_command(host, &cmd);
1972
1973 host->cmd = NULL;
1974 host->mrq = NULL;
1975
2b35bd83 1976 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1977 /* Wait for Buffer Read Ready interrupt */
1978 wait_event_interruptible_timeout(host->buf_ready_int,
1979 (host->tuning_done == 1),
1980 msecs_to_jiffies(50));
2b35bd83 1981 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1982
1983 if (!host->tuning_done) {
2e4456f0 1984 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
b513ea25
AN		 1985 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1986 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1987 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1988 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1989
1990 err = -EIO;
1991 goto out;
1992 }
1993
1994 host->tuning_done = 0;
1995
1996 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 1997
1998 /* eMMC spec does not require a delay between tuning cycles */
1999 if (opcode == MMC_SEND_TUNING_BLOCK)
2000 mdelay(1);
b513ea25
AN		 2001 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2002
2003 /*
2004 * The Host Driver has exhausted the maximum number of loops allowed,
2005 * so use fixed sampling frequency.
2006 */
7ce45e95 2007 if (tuning_loop_counter < 0) {
b513ea25
AN		 2008 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2009 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2010 }
2011 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2e4456f0 2012 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
114f2bf6 2013 err = -EIO;
b513ea25
AN		 2014 }
2015
2016out:
38e40bf5 2017 if (tuning_count) {
66c39dfc
AH		 2018 /*
2019 * In case tuning fails, host controllers which support
2020 * re-tuning can try tuning again at a later time, when the
2021 * re-tuning timer expires. So for these controllers, we
2022 * return 0. Since there might be other controllers who do not
2023 * have this capability, we return error for them.
2024 */
2025 err = 0;
cf2b5eea
AN		 2026 }
2027
66c39dfc 2028 host->mmc->retune_period = err ? 0 : tuning_count;
cf2b5eea 2029
b537f94c
RK		 2030 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2031 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2032out_unlock:
2b35bd83 2033 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2034 sdhci_runtime_pm_put(host);
b513ea25
AN		 2035
2036 return err;
2037}
2038
cb849648
AH		 2039static int sdhci_select_drive_strength(struct mmc_card *card,
2040 unsigned int max_dtr, int host_drv,
2041 int card_drv, int *drv_type)
2042{
2043 struct sdhci_host *host = mmc_priv(card->host);
2044
2045 if (!host->ops->select_drive_strength)
2046 return 0;
2047
2048 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2049 card_drv, drv_type);
2050}
52983382
KL		 2051
2052static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2053{
4d55c5a1
AN		 2054 /* Host Controller v3.00 defines preset value registers */
2055 if (host->version < SDHCI_SPEC_300)
2056 return;
2057
4d55c5a1
AN		 2058 /*
2059 * We only enable or disable Preset Value if they are not already
2060 * enabled or disabled respectively. Otherwise, we bail out.
2061 */
da91a8f9
RK		 2062 if (host->preset_enabled != enable) {
2063 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2064
2065 if (enable)
2066 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2067 else
2068 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2069
4d55c5a1 2070 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2071
2072 if (enable)
2073 host->flags |= SDHCI_PV_ENABLED;
2074 else
2075 host->flags &= ~SDHCI_PV_ENABLED;
2076
2077 host->preset_enabled = enable;
4d55c5a1 2078 }
66fd8ad5
AH		 2079}
2080
348487cb
HC		 2081static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2082 int err)
2083{
2084 struct sdhci_host *host = mmc_priv(mmc);
2085 struct mmc_data *data = mrq->data;
2086
771a3dc2
RK		 2087 if (data->host_cookie == COOKIE_GIVEN ||
2088 data->host_cookie == COOKIE_MAPPED)
2089 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2090 data->flags & MMC_DATA_WRITE ?
2091 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2092
2093 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2094}
2095
2096static int sdhci_pre_dma_transfer(struct sdhci_host *host,
d31911b9 2097 struct mmc_data *data)
348487cb
HC		 2098{
2099 int sg_count;
2100
d31911b9
HC		 2101 if (data->host_cookie == COOKIE_MAPPED) {
2102 data->host_cookie = COOKIE_GIVEN;
2103 return data->sg_count;
348487cb
HC		 2104 }
2105
d31911b9 2106 WARN_ON(data->host_cookie == COOKIE_GIVEN);
348487cb 2107
d31911b9
HC		 2108 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2109 data->flags & MMC_DATA_WRITE ?
2110 DMA_TO_DEVICE : DMA_FROM_DEVICE);
348487cb
HC		 2111
2112 if (sg_count == 0)
d31911b9 2113 return -ENOSPC;
348487cb 2114
d31911b9
HC		 2115 data->sg_count = sg_count;
2116 data->host_cookie = COOKIE_MAPPED;
348487cb
HC		 2117
2118 return sg_count;
2119}
2120
2121static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2122 bool is_first_req)
2123{
2124 struct sdhci_host *host = mmc_priv(mmc);
2125
d31911b9 2126 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2127
2128 if (host->flags & SDHCI_REQ_USE_DMA)
d31911b9 2129 sdhci_pre_dma_transfer(host, mrq->data);
348487cb
HC		 2130}
2131
71e69211 2132static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2133{
71e69211 2134 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2135 unsigned long flags;
2836766a 2136 int present;
d129bceb 2137
722e1280
CD		 2138 /* First check if client has provided their own card event */
2139 if (host->ops->card_event)
2140 host->ops->card_event(host);
2141
2836766a
KK		 2142 present = sdhci_do_get_cd(host);
2143
d129bceb
PO		 2144 spin_lock_irqsave(&host->lock, flags);
2145
66fd8ad5 2146 /* Check host->mrq first in case we are runtime suspended */
2836766a 2147 if (host->mrq && !present) {
a3c76eb9 2148 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2149 mmc_hostname(host->mmc));
a3c76eb9 2150 pr_err("%s: Resetting controller.\n",
66fd8ad5 2151 mmc_hostname(host->mmc));
d129bceb 2152
03231f9b
RK		 2153 sdhci_do_reset(host, SDHCI_RESET_CMD);
2154 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2155
66fd8ad5
AH		 2156 host->mrq->cmd->error = -ENOMEDIUM;
2157 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2158 }
2159
2160 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2161}
2162
2163static const struct mmc_host_ops sdhci_ops = {
2164 .request = sdhci_request,
348487cb
HC		 2165 .post_req = sdhci_post_req,
2166 .pre_req = sdhci_pre_req,
71e69211 2167 .set_ios = sdhci_set_ios,
94144a46 2168 .get_cd = sdhci_get_cd,
71e69211
GL		 2169 .get_ro = sdhci_get_ro,
2170 .hw_reset = sdhci_hw_reset,
2171 .enable_sdio_irq = sdhci_enable_sdio_irq,
2172 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2173 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2174 .execute_tuning = sdhci_execute_tuning,
cb849648 2175 .select_drive_strength = sdhci_select_drive_strength,
71e69211 2176 .card_event = sdhci_card_event,
20b92a30 2177 .card_busy = sdhci_card_busy,
71e69211
GL		 2178};
2179
2180/*****************************************************************************\
2181 * *
2182 * Tasklets *
2183 * *
2184\*****************************************************************************/
2185
d129bceb
PO		 2186static void sdhci_tasklet_finish(unsigned long param)
2187{
2188 struct sdhci_host *host;
2189 unsigned long flags;
2190 struct mmc_request *mrq;
2191
2192 host = (struct sdhci_host*)param;
2193
66fd8ad5
AH		 2194 spin_lock_irqsave(&host->lock, flags);
2195
0c9c99a7
CB		 2196 /*
2197 * If this tasklet gets rescheduled while running, it will
2198 * be run again afterwards but without any active request.
2199 */
66fd8ad5
AH		 2200 if (!host->mrq) {
2201 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2202 return;
66fd8ad5 2203 }
d129bceb
PO		 2204
2205 del_timer(&host->timer);
2206
2207 mrq = host->mrq;
2208
054cedff
RK		 2209 /*
2210 * Always unmap the data buffers if they were mapped by
2211 * sdhci_prepare_data() whenever we finish with a request.
2212 * This avoids leaking DMA mappings on error.
2213 */
2214 if (host->flags & SDHCI_REQ_USE_DMA) {
2215 struct mmc_data *data = mrq->data;
2216
2217 if (data && data->host_cookie == COOKIE_MAPPED) {
2218 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2219 (data->flags & MMC_DATA_READ) ?
2220 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2221 data->host_cookie = COOKIE_UNMAPPED;
2222 }
2223 }
2224
d129bceb
PO		 2225 /*
2226 * The controller needs a reset of internal state machines
2227 * upon error conditions.
2228 */
1e72859e 2229 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2230 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2231 (mrq->sbc && mrq->sbc->error) ||
2232 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2233 (mrq->data->stop && mrq->data->stop->error))) ||
2234 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2235
2236 /* Some controllers need this kick or reset won't work here */
8213af3b 2237 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2238 /* This is to force an update */
1771059c 2239 host->ops->set_clock(host, host->clock);
645289dc
PO		 2240
2241 /* Spec says we should do both at the same time, but Ricoh
2242 controllers do not like that. */
03231f9b
RK		 2243 sdhci_do_reset(host, SDHCI_RESET_CMD);
2244 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2245 }
2246
2247 host->mrq = NULL;
2248 host->cmd = NULL;
2249 host->data = NULL;
2250
f9134319 2251#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2252 sdhci_deactivate_led(host);
2f730fec 2253#endif
d129bceb 2254
5f25a66f 2255 mmiowb();
d129bceb
PO		 2256 spin_unlock_irqrestore(&host->lock, flags);
2257
2258 mmc_request_done(host->mmc, mrq);
66fd8ad5 2259 sdhci_runtime_pm_put(host);
d129bceb
PO		 2260}
2261
2262static void sdhci_timeout_timer(unsigned long data)
2263{
2264 struct sdhci_host *host;
2265 unsigned long flags;
2266
2267 host = (struct sdhci_host*)data;
2268
2269 spin_lock_irqsave(&host->lock, flags);
2270
2271 if (host->mrq) {
2e4456f0
MV		 2272 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2273 mmc_hostname(host->mmc));
d129bceb
PO		 2274 sdhci_dumpregs(host);
2275
2276 if (host->data) {
17b0429d 2277 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2278 sdhci_finish_data(host);
2279 } else {
2280 if (host->cmd)
17b0429d 2281 host->cmd->error = -ETIMEDOUT;
d129bceb 2282 else
17b0429d 2283 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2284
2285 tasklet_schedule(&host->finish_tasklet);
2286 }
2287 }
2288
5f25a66f 2289 mmiowb();
d129bceb
PO		 2290 spin_unlock_irqrestore(&host->lock, flags);
2291}
2292
2293/*****************************************************************************\
2294 * *
2295 * Interrupt handling *
2296 * *
2297\*****************************************************************************/
2298
61541397 2299static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb
PO		 2300{
2301 BUG_ON(intmask == 0);
2302
2303 if (!host->cmd) {
2e4456f0
MV		 2304 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2305 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2306 sdhci_dumpregs(host);
2307 return;
2308 }
2309
ec014cba
RK		 2310 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2311 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2312 if (intmask & SDHCI_INT_TIMEOUT)
2313 host->cmd->error = -ETIMEDOUT;
2314 else
2315 host->cmd->error = -EILSEQ;
43b58b36 2316
71fcbda0
RK		 2317 /*
2318 * If this command initiates a data phase and a response
2319 * CRC error is signalled, the card can start transferring
2320 * data - the card may have received the command without
2321 * error. We must not terminate the mmc_request early.
2322 *
2323 * If the card did not receive the command or returned an
2324 * error which prevented it sending data, the data phase
2325 * will time out.
2326 */
2327 if (host->cmd->data &&
2328 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2329 SDHCI_INT_CRC) {
2330 host->cmd = NULL;
2331 return;
2332 }
2333
d129bceb 2334 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2335 return;
2336 }
2337
2338 /*
2339 * The host can send and interrupt when the busy state has
2340 * ended, allowing us to wait without wasting CPU cycles.
2341 * Unfortunately this is overloaded on the "data complete"
2342 * interrupt, so we need to take some care when handling
2343 * it.
2344 *
2345 * Note: The 1.0 specification is a bit ambiguous about this
2346 * feature so there might be some problems with older
2347 * controllers.
2348 */
2349 if (host->cmd->flags & MMC_RSP_BUSY) {
2350 if (host->cmd->data)
2e4456f0 2351 DBG("Cannot wait for busy signal when also doing a data transfer");
e99783a4
CM		 2352 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2353 && !host->busy_handle) {
2354 /* Mark that command complete before busy is ended */
2355 host->busy_handle = 1;
e809517f 2356 return;
e99783a4 2357 }
f945405c
BD		 2358
2359 /* The controller does not support the end-of-busy IRQ,
2360 * fall through and take the SDHCI_INT_RESPONSE */
61541397
AH		 2361 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2362 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2363 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2364 }
2365
2366 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2367 sdhci_finish_command(host);
d129bceb
PO		 2368}
2369
0957c333 2370#ifdef CONFIG_MMC_DEBUG
08621b18 2371static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2372{
2373 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2374 void *desc = host->adma_table;
6882a8c0
BD		 2375
2376 sdhci_dumpregs(host);
2377
2378 while (true) {
e57a5f61
AH		 2379 struct sdhci_adma2_64_desc *dma_desc = desc;
2380
2381 if (host->flags & SDHCI_USE_64_BIT_DMA)
2382 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2383 name, desc, le32_to_cpu(dma_desc->addr_hi),
2384 le32_to_cpu(dma_desc->addr_lo),
2385 le16_to_cpu(dma_desc->len),
2386 le16_to_cpu(dma_desc->cmd));
2387 else
2388 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2389 name, desc, le32_to_cpu(dma_desc->addr_lo),
2390 le16_to_cpu(dma_desc->len),
2391 le16_to_cpu(dma_desc->cmd));
6882a8c0 2392
76fe379a 2393 desc += host->desc_sz;
6882a8c0 2394
0545230f 2395 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2396 break;
2397 }
2398}
2399#else
08621b18 2400static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2401#endif
2402
d129bceb
PO		 2403static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2404{
069c9f14 2405 u32 command;
d129bceb
PO		 2406 BUG_ON(intmask == 0);
2407
b513ea25
AN		 2408 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2409 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2410 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2411 if (command == MMC_SEND_TUNING_BLOCK ||
2412 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2413 host->tuning_done = 1;
2414 wake_up(&host->buf_ready_int);
2415 return;
2416 }
2417 }
2418
d129bceb
PO		 2419 if (!host->data) {
2420 /*
e809517f
PO		 2421 * The "data complete" interrupt is also used to
2422 * indicate that a busy state has ended. See comment
2423 * above in sdhci_cmd_irq().
d129bceb 2424 */
e809517f 2425 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2426 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2427 host->cmd->error = -ETIMEDOUT;
2428 tasklet_schedule(&host->finish_tasklet);
2429 return;
2430 }
e809517f 2431 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2432 /*
2433 * Some cards handle busy-end interrupt
2434 * before the command completed, so make
2435 * sure we do things in the proper order.
2436 */
2437 if (host->busy_handle)
2438 sdhci_finish_command(host);
2439 else
2440 host->busy_handle = 1;
e809517f
PO		 2441 return;
2442 }
2443 }
d129bceb 2444
2e4456f0
MV		 2445 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2446 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2447 sdhci_dumpregs(host);
2448
2449 return;
2450 }
2451
2452 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2453 host->data->error = -ETIMEDOUT;
22113efd
AL		 2454 else if (intmask & SDHCI_INT_DATA_END_BIT)
2455 host->data->error = -EILSEQ;
2456 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2457 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2458 != MMC_BUS_TEST_R)
17b0429d 2459 host->data->error = -EILSEQ;
6882a8c0 2460 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2461 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2462 sdhci_adma_show_error(host);
2134a922 2463 host->data->error = -EIO;
a4071fbb
HZ		 2464 if (host->ops->adma_workaround)
2465 host->ops->adma_workaround(host, intmask);
6882a8c0 2466 }
d129bceb 2467
17b0429d 2468 if (host->data->error)
d129bceb
PO		 2469 sdhci_finish_data(host);
2470 else {
a406f5a3 2471 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2472 sdhci_transfer_pio(host);
2473
6ba736a1
PO		 2474 /*
2475 * We currently don't do anything fancy with DMA
2476 * boundaries, but as we can't disable the feature
2477 * we need to at least restart the transfer.
f6a03cbf
MV		 2478 *
2479 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2480 * should return a valid address to continue from, but as
2481 * some controllers are faulty, don't trust them.
6ba736a1 2482 */
f6a03cbf
MV		 2483 if (intmask & SDHCI_INT_DMA_END) {
2484 u32 dmastart, dmanow;
2485 dmastart = sg_dma_address(host->data->sg);
2486 dmanow = dmastart + host->data->bytes_xfered;
2487 /*
2488 * Force update to the next DMA block boundary.
2489 */
2490 dmanow = (dmanow &
2491 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2492 SDHCI_DEFAULT_BOUNDARY_SIZE;
2493 host->data->bytes_xfered = dmanow - dmastart;
2494 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2495 " next 0x%08x\n",
2496 mmc_hostname(host->mmc), dmastart,
2497 host->data->bytes_xfered, dmanow);
2498 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2499 }
6ba736a1 2500
e538fbe8
PO		 2501 if (intmask & SDHCI_INT_DATA_END) {
2502 if (host->cmd) {
2503 /*
2504 * Data managed to finish before the
2505 * command completed. Make sure we do
2506 * things in the proper order.
2507 */
2508 host->data_early = 1;
2509 } else {
2510 sdhci_finish_data(host);
2511 }
2512 }
d129bceb
PO		 2513 }
2514}
2515
7d12e780 2516static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2517{
781e989c 2518 irqreturn_t result = IRQ_NONE;
66fd8ad5 2519 struct sdhci_host *host = dev_id;
41005003 2520 u32 intmask, mask, unexpected = 0;
781e989c 2521 int max_loops = 16;
d129bceb
PO		 2522
2523 spin_lock(&host->lock);
2524
be138554 2525 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2526 spin_unlock(&host->lock);
655bca76 2527 return IRQ_NONE;
66fd8ad5
AH		 2528 }
2529
4e4141a5 2530 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2531 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2532 result = IRQ_NONE;
2533 goto out;
2534 }
2535
41005003
RK		 2536 do {
2537 /* Clear selected interrupts. */
2538 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2539 SDHCI_INT_BUS_POWER);
2540 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2541
41005003
RK		 2542 DBG("*** %s got interrupt: 0x%08x\n",
2543 mmc_hostname(host->mmc), intmask);
d129bceb 2544
41005003
RK		 2545 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2546 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2547 SDHCI_CARD_PRESENT;
d129bceb 2548
41005003
RK		 2549 /*
2550 * There is a observation on i.mx esdhc. INSERT
2551 * bit will be immediately set again when it gets
2552 * cleared, if a card is inserted. We have to mask
2553 * the irq to prevent interrupt storm which will
2554 * freeze the system. And the REMOVE gets the
2555 * same situation.
2556 *
2557 * More testing are needed here to ensure it works
2558 * for other platforms though.
2559 */
b537f94c
RK		 2560 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2561 SDHCI_INT_CARD_REMOVE);
2562 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2563 SDHCI_INT_CARD_INSERT;
2564 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2565 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2566
2567 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2568 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2569
2570 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2571 SDHCI_INT_CARD_REMOVE);
2572 result = IRQ_WAKE_THREAD;
41005003 2573 }
d129bceb 2574
41005003 2575 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2576 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2577 &intmask);
964f9ce2 2578
41005003
RK		 2579 if (intmask & SDHCI_INT_DATA_MASK)
2580 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2581
41005003
RK		 2582 if (intmask & SDHCI_INT_BUS_POWER)
2583 pr_err("%s: Card is consuming too much power!\n",
2584 mmc_hostname(host->mmc));
3192a28f 2585
781e989c
RK		 2586 if (intmask & SDHCI_INT_CARD_INT) {
2587 sdhci_enable_sdio_irq_nolock(host, false);
2588 host->thread_isr |= SDHCI_INT_CARD_INT;
2589 result = IRQ_WAKE_THREAD;
2590 }
f75979b7 2591
41005003
RK		 2592 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2593 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2594 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2595 SDHCI_INT_CARD_INT);
f75979b7 2596
41005003
RK		 2597 if (intmask) {
2598 unexpected |= intmask;
2599 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2600 }
d129bceb 2601
781e989c
RK		 2602 if (result == IRQ_NONE)
2603 result = IRQ_HANDLED;
d129bceb 2604
41005003 2605 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2606 } while (intmask && --max_loops);
d129bceb
PO		 2607out:
2608 spin_unlock(&host->lock);
2609
6379b237
AS		 2610 if (unexpected) {
2611 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2612 mmc_hostname(host->mmc), unexpected);
2613 sdhci_dumpregs(host);
2614 }
f75979b7 2615
d129bceb
PO		 2616 return result;
2617}
2618
781e989c
RK		 2619static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2620{
2621 struct sdhci_host *host = dev_id;
2622 unsigned long flags;
2623 u32 isr;
2624
2625 spin_lock_irqsave(&host->lock, flags);
2626 isr = host->thread_isr;
2627 host->thread_isr = 0;
2628 spin_unlock_irqrestore(&host->lock, flags);
2629
3560db8e
RK		 2630 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2631 sdhci_card_event(host->mmc);
2632 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2633 }
2634
781e989c
RK		 2635 if (isr & SDHCI_INT_CARD_INT) {
2636 sdio_run_irqs(host->mmc);
2637
2638 spin_lock_irqsave(&host->lock, flags);
2639 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2640 sdhci_enable_sdio_irq_nolock(host, true);
2641 spin_unlock_irqrestore(&host->lock, flags);
2642 }
2643
2644 return isr ? IRQ_HANDLED : IRQ_NONE;
2645}
2646
d129bceb
PO		 2647/*****************************************************************************\
2648 * *
2649 * Suspend/resume *
2650 * *
2651\*****************************************************************************/
2652
2653#ifdef CONFIG_PM
ad080d79
KL		 2654void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2655{
2656 u8 val;
2657 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2658 | SDHCI_WAKE_ON_INT;
2659
2660 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2661 val |= mask ;
2662 /* Avoid fake wake up */
2663 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2664 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2665 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2666}
2667EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2668
0b10f478 2669static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2670{
2671 u8 val;
2672 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2673 | SDHCI_WAKE_ON_INT;
2674
2675 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2676 val &= ~mask;
2677 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2678}
d129bceb 2679
29495aa0 2680int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2681{
7260cf5e
AV		 2682 sdhci_disable_card_detection(host);
2683
66c39dfc
AH		 2684 mmc_retune_timer_stop(host->mmc);
2685 mmc_retune_needed(host->mmc);
cf2b5eea 2686
ad080d79 2687 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2688 host->ier = 0;
2689 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2690 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2691 free_irq(host->irq, host);
2692 } else {
2693 sdhci_enable_irq_wakeups(host);
2694 enable_irq_wake(host->irq);
2695 }
4ee14ec6 2696 return 0;
d129bceb
PO		 2697}
2698
b8c86fc5 2699EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2700
b8c86fc5
PO		 2701int sdhci_resume_host(struct sdhci_host *host)
2702{
4ee14ec6 2703 int ret = 0;
d129bceb 2704
a13abc7b 2705 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2706 if (host->ops->enable_dma)
2707 host->ops->enable_dma(host);
2708 }
d129bceb 2709
6308d290
AH		 2710 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2711 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2712 /* Card keeps power but host controller does not */
2713 sdhci_init(host, 0);
2714 host->pwr = 0;
2715 host->clock = 0;
2716 sdhci_do_set_ios(host, &host->mmc->ios);
2717 } else {
2718 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2719 mmiowb();
2720 }
b8c86fc5 2721
14a7b416
HC		 2722 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2723 ret = request_threaded_irq(host->irq, sdhci_irq,
2724 sdhci_thread_irq, IRQF_SHARED,
2725 mmc_hostname(host->mmc), host);
2726 if (ret)
2727 return ret;
2728 } else {
2729 sdhci_disable_irq_wakeups(host);
2730 disable_irq_wake(host->irq);
2731 }
2732
7260cf5e
AV		 2733 sdhci_enable_card_detection(host);
2734
2f4cbb3d 2735 return ret;
d129bceb
PO		 2736}
2737
b8c86fc5 2738EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5
AH		 2739
2740static int sdhci_runtime_pm_get(struct sdhci_host *host)
2741{
2742 return pm_runtime_get_sync(host->mmc->parent);
2743}
2744
2745static int sdhci_runtime_pm_put(struct sdhci_host *host)
2746{
2747 pm_runtime_mark_last_busy(host->mmc->parent);
2748 return pm_runtime_put_autosuspend(host->mmc->parent);
2749}
2750
f0710a55
AH		 2751static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2752{
5c671c41 2753 if (host->bus_on)
f0710a55
AH		 2754 return;
2755 host->bus_on = true;
2756 pm_runtime_get_noresume(host->mmc->parent);
2757}
2758
2759static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2760{
5c671c41 2761 if (!host->bus_on)
f0710a55
AH		 2762 return;
2763 host->bus_on = false;
2764 pm_runtime_put_noidle(host->mmc->parent);
2765}
2766
66fd8ad5
AH		 2767int sdhci_runtime_suspend_host(struct sdhci_host *host)
2768{
2769 unsigned long flags;
66fd8ad5 2770
66c39dfc
AH		 2771 mmc_retune_timer_stop(host->mmc);
2772 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2773
2774 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2775 host->ier &= SDHCI_INT_CARD_INT;
2776 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2777 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2778 spin_unlock_irqrestore(&host->lock, flags);
2779
781e989c 2780 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2781
2782 spin_lock_irqsave(&host->lock, flags);
2783 host->runtime_suspended = true;
2784 spin_unlock_irqrestore(&host->lock, flags);
2785
8a125bad 2786 return 0;
66fd8ad5
AH		 2787}
2788EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2789
2790int sdhci_runtime_resume_host(struct sdhci_host *host)
2791{
2792 unsigned long flags;
8a125bad 2793 int host_flags = host->flags;
66fd8ad5
AH		 2794
2795 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2796 if (host->ops->enable_dma)
2797 host->ops->enable_dma(host);
2798 }
2799
2800 sdhci_init(host, 0);
2801
2802 /* Force clock and power re-program */
2803 host->pwr = 0;
2804 host->clock = 0;
3396e736 2805 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
66fd8ad5
AH		 2806 sdhci_do_set_ios(host, &host->mmc->ios);
2807
52983382
KL		 2808 if ((host_flags & SDHCI_PV_ENABLED) &&
2809 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2810 spin_lock_irqsave(&host->lock, flags);
2811 sdhci_enable_preset_value(host, true);
2812 spin_unlock_irqrestore(&host->lock, flags);
2813 }
66fd8ad5 2814
66fd8ad5
AH		 2815 spin_lock_irqsave(&host->lock, flags);
2816
2817 host->runtime_suspended = false;
2818
2819 /* Enable SDIO IRQ */
ef104333 2820 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2821 sdhci_enable_sdio_irq_nolock(host, true);
2822
2823 /* Enable Card Detection */
2824 sdhci_enable_card_detection(host);
2825
2826 spin_unlock_irqrestore(&host->lock, flags);
2827
8a125bad 2828 return 0;
66fd8ad5
AH		 2829}
2830EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2831
162d6f98 2832#endif /* CONFIG_PM */
66fd8ad5 2833
d129bceb
PO		 2834/*****************************************************************************\
2835 * *
b8c86fc5 2836 * Device allocation/registration *
d129bceb
PO		 2837 * *
2838\*****************************************************************************/
2839
b8c86fc5
PO		 2840struct sdhci_host *sdhci_alloc_host(struct device *dev,
2841 size_t priv_size)
d129bceb 2842{
d129bceb
PO		 2843 struct mmc_host *mmc;
2844 struct sdhci_host *host;
2845
b8c86fc5 2846 WARN_ON(dev == NULL);
d129bceb 2847
b8c86fc5 2848 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2849 if (!mmc)
b8c86fc5 2850 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2851
2852 host = mmc_priv(mmc);
2853 host->mmc = mmc;
bf60e592
AH		 2854 host->mmc_host_ops = sdhci_ops;
2855 mmc->ops = &host->mmc_host_ops;
d129bceb 2856
b8c86fc5
PO		 2857 return host;
2858}
8a4da143 2859
b8c86fc5 2860EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2861
b8c86fc5
PO		 2862int sdhci_add_host(struct sdhci_host *host)
2863{
2864 struct mmc_host *mmc;
bd6a8c30 2865 u32 caps[2] = {0, 0};
f2119df6
AN		 2866 u32 max_current_caps;
2867 unsigned int ocr_avail;
f5fa92e5 2868 unsigned int override_timeout_clk;
59241757 2869 u32 max_clk;
b8c86fc5 2870 int ret;
d129bceb 2871
b8c86fc5
PO		 2872 WARN_ON(host == NULL);
2873 if (host == NULL)
2874 return -EINVAL;
d129bceb 2875
b8c86fc5 2876 mmc = host->mmc;
d129bceb 2877
b8c86fc5
PO		 2878 if (debug_quirks)
2879 host->quirks = debug_quirks;
66fd8ad5
AH		 2880 if (debug_quirks2)
2881 host->quirks2 = debug_quirks2;
d129bceb 2882
f5fa92e5
AH		 2883 override_timeout_clk = host->timeout_clk;
2884
03231f9b 2885 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2886
4e4141a5 2887 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2888 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2889 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2890 if (host->version > SDHCI_SPEC_300) {
2e4456f0
MV		 2891 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2892 mmc_hostname(mmc), host->version);
4a965505
PO		 2893 }
2894
f2119df6 2895 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2896 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2897
bd6a8c30
PR		 2898 if (host->version >= SDHCI_SPEC_300)
2899 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2900 host->caps1 :
2901 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2902
b8c86fc5 2903 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2904 host->flags |= SDHCI_USE_SDMA;
f2119df6 2905 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2906 DBG("Controller doesn't have SDMA capability\n");
67435274 2907 else
a13abc7b 2908 host->flags |= SDHCI_USE_SDMA;
d129bceb 2909
b8c86fc5 2910 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2911 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2912 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2913 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2914 }
2915
f2119df6
AN		 2916 if ((host->version >= SDHCI_SPEC_200) &&
2917 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2918 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2919
2920 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2921 (host->flags & SDHCI_USE_ADMA)) {
2922 DBG("Disabling ADMA as it is marked broken\n");
2923 host->flags &= ~SDHCI_USE_ADMA;
2924 }
2925
e57a5f61
AH		 2926 /*
2927 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2928 * and *must* do 64-bit DMA. A driver has the opportunity to change
2929 * that during the first call to ->enable_dma(). Similarly
2930 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2931 * implement.
2932 */
5eaa7476 2933 if (caps[0] & SDHCI_CAN_64BIT)
e57a5f61
AH		 2934 host->flags |= SDHCI_USE_64_BIT_DMA;
2935
a13abc7b 2936 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2937 if (host->ops->enable_dma) {
2938 if (host->ops->enable_dma(host)) {
6606110d 2939 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
b8c86fc5 2940 mmc_hostname(mmc));
a13abc7b
RR		 2941 host->flags &=
2942 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2943 }
d129bceb
PO		 2944 }
2945 }
2946
e57a5f61
AH		 2947 /* SDMA does not support 64-bit DMA */
2948 if (host->flags & SDHCI_USE_64_BIT_DMA)
2949 host->flags &= ~SDHCI_USE_SDMA;
2950
2134a922
PO		 2951 if (host->flags & SDHCI_USE_ADMA) {
2952 /*
76fe379a
AH		 2953 * The DMA descriptor table size is calculated as the maximum
2954 * number of segments times 2, to allow for an alignment
2955 * descriptor for each segment, plus 1 for a nop end descriptor,
2956 * all multipled by the descriptor size.
2134a922 2957 */
e57a5f61
AH		 2958 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2959 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2960 SDHCI_ADMA2_64_DESC_SZ;
e57a5f61 2961 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
e57a5f61
AH		 2962 } else {
2963 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2964 SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2965 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2966 }
4efaa6fb 2967 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
76fe379a 2968 host->adma_table_sz,
4efaa6fb
AH		 2969 &host->adma_addr,
2970 GFP_KERNEL);
04a5ae6f 2971 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
edd63fcc
RK		 2972 host->align_buffer = dma_alloc_coherent(mmc_dev(mmc),
2973 host->align_buffer_sz,
2974 &host->align_addr,
2975 GFP_KERNEL);
4efaa6fb 2976 if (!host->adma_table || !host->align_buffer) {
7ac02036
PF		 2977 if (host->adma_table)
2978 dma_free_coherent(mmc_dev(mmc),
2979 host->adma_table_sz,
2980 host->adma_table,
2981 host->adma_addr);
edd63fcc
RK		 2982 if (host->align_buffer)
2983 dma_free_coherent(mmc_dev(mmc),
2984 host->align_buffer_sz,
2985 host->align_buffer,
2986 host->align_addr);
6606110d 2987 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 2988 mmc_hostname(mmc));
2989 host->flags &= ~SDHCI_USE_ADMA;
4efaa6fb 2990 host->adma_table = NULL;
d1e49f77 2991 host->align_buffer = NULL;
04a5ae6f 2992 } else if (host->adma_addr & (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 2993 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2994 mmc_hostname(mmc));
d1e49f77 2995 host->flags &= ~SDHCI_USE_ADMA;
76fe379a 2996 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 2997 host->adma_table, host->adma_addr);
edd63fcc
RK		 2998 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz,
2999 host->align_buffer, host->align_addr);
4efaa6fb 3000 host->adma_table = NULL;
d1e49f77 3001 host->align_buffer = NULL;
2134a922 3002 }
edd63fcc
RK		 3003
3004 /* dma_alloc_coherent returns page aligned and sized buffers */
3005 BUG_ON(host->align_addr & SDHCI_ADMA2_MASK);
2134a922
PO		 3006 }
3007
7659150c
PO		 3008 /*
3009 * If we use DMA, then it's up to the caller to set the DMA
3010 * mask, but PIO does not need the hw shim so we set a new
3011 * mask here in that case.
3012 */
a13abc7b 3013 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 3014 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 3015 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 3016 }
d129bceb 3017
c4687d5f 3018 if (host->version >= SDHCI_SPEC_300)
f2119df6 3019 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 3020 >> SDHCI_CLOCK_BASE_SHIFT;
3021 else
f2119df6 3022 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 3023 >> SDHCI_CLOCK_BASE_SHIFT;
3024
4240ff0a 3025 host->max_clk *= 1000000;
f27f47ef
AV		 3026 if (host->max_clk == 0 || host->quirks &
3027 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 3028 if (!host->ops->get_max_clock) {
2e4456f0
MV		 3029 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3030 mmc_hostname(mmc));
4240ff0a
BD		 3031 return -ENODEV;
3032 }
3033 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3034 }
d129bceb 3035
c3ed3877
AN		 3036 /*
3037 * In case of Host Controller v3.00, find out whether clock
3038 * multiplier is supported.
3039 */
3040 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3041 SDHCI_CLOCK_MUL_SHIFT;
3042
3043 /*
3044 * In case the value in Clock Multiplier is 0, then programmable
3045 * clock mode is not supported, otherwise the actual clock
3046 * multiplier is one more than the value of Clock Multiplier
3047 * in the Capabilities Register.
3048 */
3049 if (host->clk_mul)
3050 host->clk_mul += 1;
3051
d129bceb
PO		 3052 /*
3053 * Set host parameters.
3054 */
59241757
DA		 3055 max_clk = host->max_clk;
3056
ce5f036b 3057 if (host->ops->get_min_clock)
a9e58f25 3058 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3059 else if (host->version >= SDHCI_SPEC_300) {
3060 if (host->clk_mul) {
3061 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3062 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3063 } else
3064 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3065 } else
0397526d 3066 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3067
59241757
DA		 3068 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3069 mmc->f_max = max_clk;
3070
28aab053
AD		 3071 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3072 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3073 SDHCI_TIMEOUT_CLK_SHIFT;
3074 if (host->timeout_clk == 0) {
3075 if (host->ops->get_timeout_clock) {
3076 host->timeout_clk =
3077 host->ops->get_timeout_clock(host);
3078 } else {
3079 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3080 mmc_hostname(mmc));
3081 return -ENODEV;
3082 }
272308ca 3083 }
272308ca 3084
28aab053
AD		 3085 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3086 host->timeout_clk *= 1000;
272308ca 3087
28aab053 3088 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3089 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3090 mmc->max_busy_timeout /= host->timeout_clk;
3091 }
58d1246d 3092
f5fa92e5
AH		 3093 if (override_timeout_clk)
3094 host->timeout_clk = override_timeout_clk;
3095
e89d456f 3096 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3097 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3098
3099 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3100 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3101
8edf6371 3102 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3103 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3104 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3105 !(host->flags & SDHCI_USE_SDMA)) &&
3106 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3107 host->flags |= SDHCI_AUTO_CMD23;
3108 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3109 } else {
3110 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3111 }
3112
15ec4461
PR		 3113 /*
3114 * A controller may support 8-bit width, but the board itself
3115 * might not have the pins brought out. Boards that support
3116 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3117 * their platform code before calling sdhci_add_host(), and we
3118 * won't assume 8-bit width for hosts without that CAP.
3119 */
5fe23c7f 3120 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3121 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3122
63ef5d8c
JH		 3123 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3124 mmc->caps &= ~MMC_CAP_CMD23;
3125
f2119df6 3126 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 3127 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3128
176d1ed4 3129 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
c31d22eb
II		 3130 !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3131 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
68d1fb7e
AV		 3132 mmc->caps |= MMC_CAP_NEEDS_POLL;
3133
3a48edc4
TK		 3134 /* If there are external regulators, get them */
3135 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3136 return -EPROBE_DEFER;
3137
6231f3de 3138 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3139 if (!IS_ERR(mmc->supply.vqmmc)) {
3140 ret = regulator_enable(mmc->supply.vqmmc);
3141 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3142 1950000))
8363c374
KL		 3143 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3144 SDHCI_SUPPORT_SDR50 |
3145 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3146 if (ret) {
3147 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3148 mmc_hostname(mmc), ret);
4bb74313 3149 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3150 }
8363c374 3151 }
6231f3de 3152
6a66180a
DD		 3153 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3154 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3155 SDHCI_SUPPORT_DDR50);
3156
4188bba0
AC		 3157 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3158 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3159 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3160 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3161
3162 /* SDR104 supports also implies SDR50 support */
156e14b1 3163 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3164 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3165 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3166 * field can be promoted to support HS200.
3167 */
549c0b18 3168 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3169 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3170 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3171 mmc->caps |= MMC_CAP_UHS_SDR50;
3172
e9fb05d5
AH		 3173 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3174 (caps[1] & SDHCI_SUPPORT_HS400))
3175 mmc->caps2 |= MMC_CAP2_HS400;
3176
549c0b18
AH		 3177 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3178 (IS_ERR(mmc->supply.vqmmc) ||
3179 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3180 1300000)))
3181 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3182
9107ebbf
MC		 3183 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3184 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3185 mmc->caps |= MMC_CAP_UHS_DDR50;
3186
069c9f14 3187 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3188 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3189 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3190
156e14b1 3191 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3192 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3193 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3194
d6d50a15
AN		 3195 /* Driver Type(s) (A, C, D) supported by the host */
3196 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3197 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3198 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3199 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3200 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3201 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3202
cf2b5eea
AN		 3203 /* Initial value for re-tuning timer count */
3204 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3205 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3206
3207 /*
3208 * In case Re-tuning Timer is not disabled, the actual value of
3209 * re-tuning timer will be 2 ^ (n - 1).
3210 */
3211 if (host->tuning_count)
3212 host->tuning_count = 1 << (host->tuning_count - 1);
3213
3214 /* Re-tuning mode supported by the Host Controller */
3215 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3216 SDHCI_RETUNING_MODE_SHIFT;
3217
8f230f45 3218 ocr_avail = 0;
bad37e1a 3219
f2119df6
AN		 3220 /*
3221 * According to SD Host Controller spec v3.00, if the Host System
3222 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3223 * the value is meaningful only if Voltage Support in the Capabilities
3224 * register is set. The actual current value is 4 times the register
3225 * value.
3226 */
3227 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3228 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3229 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3230 if (curr > 0) {
3231
3232 /* convert to SDHCI_MAX_CURRENT format */
3233 curr = curr/1000; /* convert to mA */
3234 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3235
3236 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3237 max_current_caps =
3238 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3239 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3240 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3241 }
3242 }
f2119df6
AN		 3243
3244 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3245 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3246
55c4665e 3247 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3248 SDHCI_MAX_CURRENT_330_MASK) >>
3249 SDHCI_MAX_CURRENT_330_SHIFT) *
3250 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3251 }
3252 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3253 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3254
55c4665e 3255 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3256 SDHCI_MAX_CURRENT_300_MASK) >>
3257 SDHCI_MAX_CURRENT_300_SHIFT) *
3258 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3259 }
3260 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3261 ocr_avail |= MMC_VDD_165_195;
3262
55c4665e 3263 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3264 SDHCI_MAX_CURRENT_180_MASK) >>
3265 SDHCI_MAX_CURRENT_180_SHIFT) *
3266 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3267 }
3268
5fd26c7e
UH		 3269 /* If OCR set by host, use it instead. */
3270 if (host->ocr_mask)
3271 ocr_avail = host->ocr_mask;
3272
3273 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3274 if (mmc->ocr_avail)
52221610 3275 ocr_avail = mmc->ocr_avail;
3a48edc4 3276
8f230f45
TI		 3277 mmc->ocr_avail = ocr_avail;
3278 mmc->ocr_avail_sdio = ocr_avail;
3279 if (host->ocr_avail_sdio)
3280 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3281 mmc->ocr_avail_sd = ocr_avail;
3282 if (host->ocr_avail_sd)
3283 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3284 else /* normal SD controllers don't support 1.8V */
3285 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3286 mmc->ocr_avail_mmc = ocr_avail;
3287 if (host->ocr_avail_mmc)
3288 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3289
3290 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 3291 pr_err("%s: Hardware doesn't report any support voltages.\n",
3292 mmc_hostname(mmc));
b8c86fc5 3293 return -ENODEV;
146ad66e
PO		 3294 }
3295
d129bceb
PO		 3296 spin_lock_init(&host->lock);
3297
3298 /*
2134a922
PO		 3299 * Maximum number of segments. Depends on if the hardware
3300 * can do scatter/gather or not.
d129bceb 3301 */
2134a922 3302 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3303 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3304 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3305 mmc->max_segs = 1;
2134a922 3306 else /* PIO */
4fb213f8 3307 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3308
3309 /*
ac00531d
AH		 3310 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3311 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3312 * is less anyway.
d129bceb 3313 */
55db890a 3314 mmc->max_req_size = 524288;
d129bceb
PO		 3315
3316 /*
3317 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3318 * of bytes. When doing hardware scatter/gather, each entry cannot
3319 * be larger than 64 KiB though.
d129bceb 3320 */
30652aa3
OJ		 3321 if (host->flags & SDHCI_USE_ADMA) {
3322 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3323 mmc->max_seg_size = 65535;
3324 else
3325 mmc->max_seg_size = 65536;
3326 } else {
2134a922 3327 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3328 }
d129bceb 3329
fe4a3c7a
PO		 3330 /*
3331 * Maximum block size. This varies from controller to controller and
3332 * is specified in the capabilities register.
3333 */
0633f654
AV		 3334 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3335 mmc->max_blk_size = 2;
3336 } else {
f2119df6 3337 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3338 SDHCI_MAX_BLOCK_SHIFT;
3339 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3340 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3341 mmc_hostname(mmc));
0633f654
AV		 3342 mmc->max_blk_size = 0;
3343 }
3344 }
3345
3346 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3347
55db890a
PO		 3348 /*
3349 * Maximum block count.
3350 */
1388eefd 3351 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3352
d129bceb
PO		 3353 /*
3354 * Init tasklets.
3355 */
d129bceb
PO		 3356 tasklet_init(&host->finish_tasklet,
3357 sdhci_tasklet_finish, (unsigned long)host);
3358
e4cad1b5 3359 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3360
250fb7b4 3361 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3362
2af502ca
SG		 3363 sdhci_init(host, 0);
3364
781e989c
RK		 3365 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3366 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3367 if (ret) {
3368 pr_err("%s: Failed to request IRQ %d: %d\n",
3369 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3370 goto untasklet;
0fc81ee3 3371 }
d129bceb 3372
d129bceb
PO		 3373#ifdef CONFIG_MMC_DEBUG
3374 sdhci_dumpregs(host);
3375#endif
3376
f9134319 3377#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3378 snprintf(host->led_name, sizeof(host->led_name),
3379 "%s::", mmc_hostname(mmc));
3380 host->led.name = host->led_name;
2f730fec
PO		 3381 host->led.brightness = LED_OFF;
3382 host->led.default_trigger = mmc_hostname(mmc);
3383 host->led.brightness_set = sdhci_led_control;
3384
b8c86fc5 3385 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3386 if (ret) {
3387 pr_err("%s: Failed to register LED device: %d\n",
3388 mmc_hostname(mmc), ret);
2f730fec 3389 goto reset;
0fc81ee3 3390 }
2f730fec
PO		 3391#endif
3392
5f25a66f
PO		 3393 mmiowb();
3394
d129bceb
PO		 3395 mmc_add_host(mmc);
3396
a3c76eb9 3397 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3398 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3399 (host->flags & SDHCI_USE_ADMA) ?
3400 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3401 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3402
7260cf5e
AV		 3403 sdhci_enable_card_detection(host);
3404
d129bceb
PO		 3405 return 0;
3406
f9134319 3407#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3408reset:
03231f9b 3409 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3410 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3411 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3412 free_irq(host->irq, host);
3413#endif
8ef1a143 3414untasklet:
d129bceb 3415 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3416
3417 return ret;
3418}
3419
b8c86fc5 3420EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3421
1e72859e 3422void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3423{
3a48edc4 3424 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3425 unsigned long flags;
3426
3427 if (dead) {
3428 spin_lock_irqsave(&host->lock, flags);
3429
3430 host->flags |= SDHCI_DEVICE_DEAD;
3431
3432 if (host->mrq) {
a3c76eb9 3433 pr_err("%s: Controller removed during "
4e743f1f 3434 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3435
3436 host->mrq->cmd->error = -ENOMEDIUM;
3437 tasklet_schedule(&host->finish_tasklet);
3438 }
3439
3440 spin_unlock_irqrestore(&host->lock, flags);
3441 }
3442
7260cf5e
AV		 3443 sdhci_disable_card_detection(host);
3444
4e743f1f 3445 mmc_remove_host(mmc);
d129bceb 3446
f9134319 3447#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3448 led_classdev_unregister(&host->led);
3449#endif
3450
1e72859e 3451 if (!dead)
03231f9b 3452 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3453
b537f94c
RK		 3454 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3455 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3456 free_irq(host->irq, host);
3457
3458 del_timer_sync(&host->timer);
3459
d129bceb 3460 tasklet_kill(&host->finish_tasklet);
2134a922 3461
3a48edc4
TK		 3462 if (!IS_ERR(mmc->supply.vqmmc))
3463 regulator_disable(mmc->supply.vqmmc);
6231f3de 3464
4efaa6fb 3465 if (host->adma_table)
76fe379a 3466 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 3467 host->adma_table, host->adma_addr);
edd63fcc
RK		 3468 if (host->align_buffer)
3469 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz,
3470 host->align_buffer, host->align_addr);
2134a922 3471
4efaa6fb 3472 host->adma_table = NULL;
2134a922 3473 host->align_buffer = NULL;
d129bceb
PO		 3474}
3475
b8c86fc5 3476EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3477
b8c86fc5 3478void sdhci_free_host(struct sdhci_host *host)
d129bceb 3479{
b8c86fc5 3480 mmc_free_host(host->mmc);
d129bceb
PO		 3481}
3482
b8c86fc5 3483EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3484
3485/*****************************************************************************\
3486 * *
3487 * Driver init/exit *
3488 * *
3489\*****************************************************************************/
3490
3491static int __init sdhci_drv_init(void)
3492{
a3c76eb9 3493 pr_info(DRIVER_NAME
52fbf9c9 3494 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3495 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3496
b8c86fc5 3497 return 0;
d129bceb
PO		 3498}
3499
3500static void __exit sdhci_drv_exit(void)
3501{
d129bceb
PO		 3502}
3503
3504module_init(sdhci_drv_init);
3505module_exit(sdhci_drv_exit);
3506
df673b22 3507module_param(debug_quirks, uint, 0444);
66fd8ad5 3508module_param(debug_quirks2, uint, 0444);
67435274 3509
32710e8f 3510MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3511MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3512MODULE_LICENSE("GPL");
67435274 3513
df673b22 3514MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3515MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Ubuntu Artful kernel mirror