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UBUNTU: Ubuntu-5.11.0-22.23
[mirror_ubuntu-hirsute-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
d129bceb 2/*
70f10482 3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 4 *
b69c9058 5 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb 6 *
84c46a53
PO		 7 * Thanks to the following companies for their support:
8 *
9 * - JMicron (hardware and technical support)
d129bceb
PO		 10 */
11
fa091010 12#include <linux/bitfield.h>
d129bceb 13#include <linux/delay.h>
18e762e3 14#include <linux/dmaengine.h>
5a436cc0 15#include <linux/ktime.h>
d129bceb 16#include <linux/highmem.h>
b8c86fc5 17#include <linux/io.h>
88b47679 18#include <linux/module.h>
d129bceb 19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
11763609 21#include <linux/scatterlist.h>
bd9b9027 22#include <linux/sizes.h>
250dcd11 23#include <linux/swiotlb.h>
9bea3c85 24#include <linux/regulator/consumer.h>
66fd8ad5 25#include <linux/pm_runtime.h>
92e0c44b 26#include <linux/of.h>
d129bceb 27
2f730fec
PO		 28#include <linux/leds.h>
29
22113efd 30#include <linux/mmc/mmc.h>
d129bceb 31#include <linux/mmc/host.h>
473b095a 32#include <linux/mmc/card.h>
85cc1c33 33#include <linux/mmc/sdio.h>
bec9d4e5 34#include <linux/mmc/slot-gpio.h>
d129bceb 35
d129bceb
PO		 36#include "sdhci.h"
37
38#define DRIVER_NAME "sdhci"
d129bceb 39
d129bceb 40#define DBG(f, x...) \
f421865d 41 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
d129bceb 42
85ad90e2
AH		 43#define SDHCI_DUMP(f, x...) \
44 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
45
b513ea25
AN		 46#define MAX_TUNING_LOOP 40
47
df673b22 48static unsigned int debug_quirks = 0;
66fd8ad5 49static unsigned int debug_quirks2;
67435274 50
52983382 51static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 52
845c939e 53static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
a374a72b 54
d2898172 55void sdhci_dumpregs(struct sdhci_host *host)
d129bceb 56{
85ad90e2
AH		 57 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
58
59 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
60 sdhci_readl(host, SDHCI_DMA_ADDRESS),
61 sdhci_readw(host, SDHCI_HOST_VERSION));
62 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
63 sdhci_readw(host, SDHCI_BLOCK_SIZE),
64 sdhci_readw(host, SDHCI_BLOCK_COUNT));
65 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
66 sdhci_readl(host, SDHCI_ARGUMENT),
67 sdhci_readw(host, SDHCI_TRANSFER_MODE));
68 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
69 sdhci_readl(host, SDHCI_PRESENT_STATE),
70 sdhci_readb(host, SDHCI_HOST_CONTROL));
71 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
72 sdhci_readb(host, SDHCI_POWER_CONTROL),
73 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
74 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
75 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
76 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
77 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
78 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
79 sdhci_readl(host, SDHCI_INT_STATUS));
80 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
81 sdhci_readl(host, SDHCI_INT_ENABLE),
82 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
869f8a69
AH		 83 SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
84 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
85ad90e2
AH		 85 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
86 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
87 sdhci_readl(host, SDHCI_CAPABILITIES),
88 sdhci_readl(host, SDHCI_CAPABILITIES_1));
89 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
90 sdhci_readw(host, SDHCI_COMMAND),
91 sdhci_readl(host, SDHCI_MAX_CURRENT));
92 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
7962302f
AH		 93 sdhci_readl(host, SDHCI_RESPONSE),
94 sdhci_readl(host, SDHCI_RESPONSE + 4));
85ad90e2 95 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
7962302f
AH		 96 sdhci_readl(host, SDHCI_RESPONSE + 8),
97 sdhci_readl(host, SDHCI_RESPONSE + 12));
85ad90e2
AH		 98 SDHCI_DUMP("Host ctl2: 0x%08x\n",
99 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 100
e57a5f61 101 if (host->flags & SDHCI_USE_ADMA) {
85ad90e2
AH		 102 if (host->flags & SDHCI_USE_64_BIT_DMA) {
103 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
104 sdhci_readl(host, SDHCI_ADMA_ERROR),
105 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
106 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
107 } else {
108 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
109 sdhci_readl(host, SDHCI_ADMA_ERROR),
110 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
111 }
e57a5f61 112 }
be3f4ae0 113
d1fe0762
SG		 114 if (host->ops->dump_vendor_regs)
115 host->ops->dump_vendor_regs(host);
116
85ad90e2 117 SDHCI_DUMP("============================================\n");
d129bceb 118}
d2898172 119EXPORT_SYMBOL_GPL(sdhci_dumpregs);
d129bceb
PO		 120
121/*****************************************************************************\
122 * *
123 * Low level functions *
124 * *
125\*****************************************************************************/
126
b3f80b43
CZ		 127static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
128{
129 u16 ctrl2;
130
97207c12 131 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
b3f80b43
CZ		 132 if (ctrl2 & SDHCI_CTRL_V4_MODE)
133 return;
134
135 ctrl2 |= SDHCI_CTRL_V4_MODE;
97207c12 136 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
b3f80b43
CZ		 137}
138
139/*
140 * This can be called before sdhci_add_host() by Vendor's host controller
141 * driver to enable v4 mode if supported.
142 */
143void sdhci_enable_v4_mode(struct sdhci_host *host)
144{
145 host->v4_mode = true;
146 sdhci_do_enable_v4_mode(host);
147}
148EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
149
56a590dc
AH		 150static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
151{
152 return cmd->data || cmd->flags & MMC_RSP_BUSY;
153}
154
7260cf5e
AV		 155static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
156{
5b4f1f6c 157 u32 present;
7260cf5e 158
c79396c1 159 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
e65bb388 160 !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
66fd8ad5
AH		 161 return;
162
5b4f1f6c
RK		 163 if (enable) {
164 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
165 SDHCI_CARD_PRESENT;
d25928d1 166
5b4f1f6c
RK		 167 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
168 SDHCI_INT_CARD_INSERT;
169 } else {
170 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
171 }
b537f94c
RK		 172
173 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
174 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 175}
176
177static void sdhci_enable_card_detection(struct sdhci_host *host)
178{
179 sdhci_set_card_detection(host, true);
180}
181
182static void sdhci_disable_card_detection(struct sdhci_host *host)
183{
184 sdhci_set_card_detection(host, false);
185}
186
02d0b685
UH		 187static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
188{
189 if (host->bus_on)
190 return;
191 host->bus_on = true;
192 pm_runtime_get_noresume(host->mmc->parent);
193}
194
195static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
196{
197 if (!host->bus_on)
198 return;
199 host->bus_on = false;
200 pm_runtime_put_noidle(host->mmc->parent);
201}
202
03231f9b 203void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 204{
5a436cc0 205 ktime_t timeout;
393c1a34 206
4e4141a5 207 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 208
f0710a55 209 if (mask & SDHCI_RESET_ALL) {
d129bceb 210 host->clock = 0;
f0710a55
AH		 211 /* Reset-all turns off SD Bus Power */
212 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
213 sdhci_runtime_pm_bus_off(host);
214 }
d129bceb 215
e16514d8 216 /* Wait max 100 ms */
5a436cc0 217 timeout = ktime_add_ms(ktime_get(), 100);
e16514d8
PO		 218
219 /* hw clears the bit when it's done */
b704441e
AD		 220 while (1) {
221 bool timedout = ktime_after(ktime_get(), timeout);
222
223 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
224 break;
225 if (timedout) {
a3c76eb9 226 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 227 mmc_hostname(host->mmc), (int)mask);
228 sdhci_dumpregs(host);
229 return;
230 }
5a436cc0 231 udelay(10);
d129bceb 232 }
03231f9b
RK		 233}
234EXPORT_SYMBOL_GPL(sdhci_reset);
235
236static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
237{
238 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
d3940f27
AH		 239 struct mmc_host *mmc = host->mmc;
240
241 if (!mmc->ops->get_cd(mmc))
03231f9b
RK		 242 return;
243 }
063a9dbb 244
03231f9b 245 host->ops->reset(host, mask);
393c1a34 246
da91a8f9
RK		 247 if (mask & SDHCI_RESET_ALL) {
248 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
249 if (host->ops->enable_dma)
250 host->ops->enable_dma(host);
251 }
252
253 /* Resetting the controller clears many */
254 host->preset_enabled = false;
3abc1e80 255 }
d129bceb
PO		 256}
257
f5c1ab82 258static void sdhci_set_default_irqs(struct sdhci_host *host)
d129bceb 259{
b537f94c
RK		 260 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
261 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
262 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
263 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
264 SDHCI_INT_RESPONSE;
265
f37b20eb
DA		 266 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
267 host->tuning_mode == SDHCI_TUNING_MODE_3)
268 host->ier |= SDHCI_INT_RETUNE;
269
b537f94c
RK		 270 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
271 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
f5c1ab82
AH		 272}
273
685e444b
CZ		 274static void sdhci_config_dma(struct sdhci_host *host)
275{
276 u8 ctrl;
277 u16 ctrl2;
278
279 if (host->version < SDHCI_SPEC_200)
280 return;
281
282 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
283
284 /*
285 * Always adjust the DMA selection as some controllers
286 * (e.g. JMicron) can't do PIO properly when the selection
287 * is ADMA.
288 */
289 ctrl &= ~SDHCI_CTRL_DMA_MASK;
290 if (!(host->flags & SDHCI_REQ_USE_DMA))
291 goto out;
292
293 /* Note if DMA Select is zero then SDMA is selected */
294 if (host->flags & SDHCI_USE_ADMA)
295 ctrl |= SDHCI_CTRL_ADMA32;
296
297 if (host->flags & SDHCI_USE_64_BIT_DMA) {
298 /*
299 * If v4 mode, all supported DMA can be 64-bit addressing if
300 * controller supports 64-bit system address, otherwise only
301 * ADMA can support 64-bit addressing.
302 */
303 if (host->v4_mode) {
304 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
305 ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
306 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
307 } else if (host->flags & SDHCI_USE_ADMA) {
308 /*
309 * Don't need to undo SDHCI_CTRL_ADMA32 in order to
310 * set SDHCI_CTRL_ADMA64.
311 */
312 ctrl |= SDHCI_CTRL_ADMA64;
313 }
314 }
315
316out:
317 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
318}
319
f5c1ab82
AH		 320static void sdhci_init(struct sdhci_host *host, int soft)
321{
322 struct mmc_host *mmc = host->mmc;
49769d4d 323 unsigned long flags;
f5c1ab82
AH		 324
325 if (soft)
326 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
327 else
328 sdhci_do_reset(host, SDHCI_RESET_ALL);
329
b3f80b43
CZ		 330 if (host->v4_mode)
331 sdhci_do_enable_v4_mode(host);
332
49769d4d 333 spin_lock_irqsave(&host->lock, flags);
f5c1ab82 334 sdhci_set_default_irqs(host);
49769d4d 335 spin_unlock_irqrestore(&host->lock, flags);
2f4cbb3d 336
f12e39db
AH		 337 host->cqe_on = false;
338
2f4cbb3d
NP		 339 if (soft) {
340 /* force clock reconfiguration */
341 host->clock = 0;
d3940f27 342 mmc->ops->set_ios(mmc, &mmc->ios);
2f4cbb3d 343 }
7260cf5e 344}
d129bceb 345
7260cf5e
AV		 346static void sdhci_reinit(struct sdhci_host *host)
347{
dcaac3f7
RR		 348 u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
349
2f4cbb3d 350 sdhci_init(host, 0);
7260cf5e 351 sdhci_enable_card_detection(host);
dcaac3f7
RR		 352
353 /*
354 * A change to the card detect bits indicates a change in present state,
355 * refer sdhci_set_card_detection(). A card detect interrupt might have
356 * been missed while the host controller was being reset, so trigger a
357 * rescan to check.
358 */
359 if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
360 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 361}
362
061d17a6 363static void __sdhci_led_activate(struct sdhci_host *host)
d129bceb
PO		 364{
365 u8 ctrl;
366
bd29f58b
AH		 367 if (host->quirks & SDHCI_QUIRK_NO_LED)
368 return;
369
4e4141a5 370 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 371 ctrl |= SDHCI_CTRL_LED;
4e4141a5 372 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 373}
374
061d17a6 375static void __sdhci_led_deactivate(struct sdhci_host *host)
d129bceb
PO		 376{
377 u8 ctrl;
378
bd29f58b
AH		 379 if (host->quirks & SDHCI_QUIRK_NO_LED)
380 return;
381
4e4141a5 382 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 383 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 384 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 385}
386
4f78230f 387#if IS_REACHABLE(CONFIG_LEDS_CLASS)
2f730fec 388static void sdhci_led_control(struct led_classdev *led,
061d17a6 389 enum led_brightness brightness)
2f730fec
PO		 390{
391 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
392 unsigned long flags;
393
394 spin_lock_irqsave(&host->lock, flags);
395
66fd8ad5
AH		 396 if (host->runtime_suspended)
397 goto out;
398
2f730fec 399 if (brightness == LED_OFF)
061d17a6 400 __sdhci_led_deactivate(host);
2f730fec 401 else
061d17a6 402 __sdhci_led_activate(host);
66fd8ad5 403out:
2f730fec
PO		 404 spin_unlock_irqrestore(&host->lock, flags);
405}
061d17a6
AH		 406
407static int sdhci_led_register(struct sdhci_host *host)
408{
409 struct mmc_host *mmc = host->mmc;
410
bd29f58b
AH		 411 if (host->quirks & SDHCI_QUIRK_NO_LED)
412 return 0;
413
061d17a6
AH		 414 snprintf(host->led_name, sizeof(host->led_name),
415 "%s::", mmc_hostname(mmc));
416
417 host->led.name = host->led_name;
418 host->led.brightness = LED_OFF;
419 host->led.default_trigger = mmc_hostname(mmc);
420 host->led.brightness_set = sdhci_led_control;
421
422 return led_classdev_register(mmc_dev(mmc), &host->led);
423}
424
425static void sdhci_led_unregister(struct sdhci_host *host)
426{
bd29f58b
AH		 427 if (host->quirks & SDHCI_QUIRK_NO_LED)
428 return;
429
061d17a6
AH		 430 led_classdev_unregister(&host->led);
431}
432
433static inline void sdhci_led_activate(struct sdhci_host *host)
434{
435}
436
437static inline void sdhci_led_deactivate(struct sdhci_host *host)
438{
439}
440
441#else
442
443static inline int sdhci_led_register(struct sdhci_host *host)
444{
445 return 0;
446}
447
448static inline void sdhci_led_unregister(struct sdhci_host *host)
449{
450}
451
452static inline void sdhci_led_activate(struct sdhci_host *host)
453{
454 __sdhci_led_activate(host);
455}
456
457static inline void sdhci_led_deactivate(struct sdhci_host *host)
458{
459 __sdhci_led_deactivate(host);
460}
461
2f730fec
PO		 462#endif
463
97a1abae
AH		 464static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
465 unsigned long timeout)
466{
467 if (sdhci_data_line_cmd(mrq->cmd))
468 mod_timer(&host->data_timer, timeout);
469 else
470 mod_timer(&host->timer, timeout);
471}
472
473static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
474{
475 if (sdhci_data_line_cmd(mrq->cmd))
476 del_timer(&host->data_timer);
477 else
478 del_timer(&host->timer);
479}
480
481static inline bool sdhci_has_requests(struct sdhci_host *host)
482{
483 return host->cmd || host->data_cmd;
484}
485
d129bceb
PO		 486/*****************************************************************************\
487 * *
488 * Core functions *
489 * *
490\*****************************************************************************/
491
a406f5a3 492static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 493{
7659150c
PO		 494 unsigned long flags;
495 size_t blksize, len, chunk;
3f649ab7 496 u32 scratch;
7659150c 497 u8 *buf;
d129bceb 498
a406f5a3 499 DBG("PIO reading\n");
d129bceb 500
a406f5a3 501 blksize = host->data->blksz;
7659150c 502 chunk = 0;
d129bceb 503
7659150c 504 local_irq_save(flags);
d129bceb 505
a406f5a3 506 while (blksize) {
bf3a35ac 507 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 508
7659150c 509 len = min(host->sg_miter.length, blksize);
d129bceb 510
7659150c
PO		 511 blksize -= len;
512 host->sg_miter.consumed = len;
14d836e7 513
7659150c 514 buf = host->sg_miter.addr;
d129bceb 515
7659150c
PO		 516 while (len) {
517 if (chunk == 0) {
4e4141a5 518 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 519 chunk = 4;
a406f5a3 520 }
7659150c
PO		 521
522 *buf = scratch & 0xFF;
523
524 buf++;
525 scratch >>= 8;
526 chunk--;
527 len--;
d129bceb 528 }
a406f5a3 529 }
7659150c
PO		 530
531 sg_miter_stop(&host->sg_miter);
532
533 local_irq_restore(flags);
a406f5a3 534}
d129bceb 535
a406f5a3
PO		 536static void sdhci_write_block_pio(struct sdhci_host *host)
537{
7659150c
PO		 538 unsigned long flags;
539 size_t blksize, len, chunk;
540 u32 scratch;
541 u8 *buf;
d129bceb 542
a406f5a3
PO		 543 DBG("PIO writing\n");
544
545 blksize = host->data->blksz;
7659150c
PO		 546 chunk = 0;
547 scratch = 0;
d129bceb 548
7659150c 549 local_irq_save(flags);
d129bceb 550
a406f5a3 551 while (blksize) {
bf3a35ac 552 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 553
7659150c
PO		 554 len = min(host->sg_miter.length, blksize);
555
556 blksize -= len;
557 host->sg_miter.consumed = len;
558
559 buf = host->sg_miter.addr;
d129bceb 560
7659150c
PO		 561 while (len) {
562 scratch |= (u32)*buf << (chunk * 8);
563
564 buf++;
565 chunk++;
566 len--;
567
568 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 569 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 570 chunk = 0;
571 scratch = 0;
d129bceb 572 }
d129bceb
PO		 573 }
574 }
7659150c
PO		 575
576 sg_miter_stop(&host->sg_miter);
577
578 local_irq_restore(flags);
a406f5a3
PO		 579}
580
581static void sdhci_transfer_pio(struct sdhci_host *host)
582{
583 u32 mask;
584
7659150c 585 if (host->blocks == 0)
a406f5a3
PO		 586 return;
587
588 if (host->data->flags & MMC_DATA_READ)
589 mask = SDHCI_DATA_AVAILABLE;
590 else
591 mask = SDHCI_SPACE_AVAILABLE;
592
4a3cba32
PO		 593 /*
594 * Some controllers (JMicron JMB38x) mess up the buffer bits
595 * for transfers < 4 bytes. As long as it is just one block,
596 * we can ignore the bits.
597 */
598 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
599 (host->data->blocks == 1))
600 mask = ~0;
601
4e4141a5 602 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 603 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
604 udelay(100);
605
a406f5a3
PO		 606 if (host->data->flags & MMC_DATA_READ)
607 sdhci_read_block_pio(host);
608 else
609 sdhci_write_block_pio(host);
d129bceb 610
7659150c
PO		 611 host->blocks--;
612 if (host->blocks == 0)
a406f5a3 613 break;
a406f5a3 614 }
d129bceb 615
a406f5a3 616 DBG("PIO transfer complete.\n");
d129bceb
PO		 617}
618
48857d9b 619static int sdhci_pre_dma_transfer(struct sdhci_host *host,
c0999b72 620 struct mmc_data *data, int cookie)
48857d9b
RK		 621{
622 int sg_count;
623
94538e51
RK		 624 /*
625 * If the data buffers are already mapped, return the previous
626 * dma_map_sg() result.
627 */
628 if (data->host_cookie == COOKIE_PRE_MAPPED)
48857d9b 629 return data->sg_count;
48857d9b 630
bd9b9027
LW		 631 /* Bounce write requests to the bounce buffer */
632 if (host->bounce_buffer) {
633 unsigned int length = data->blksz * data->blocks;
634
635 if (length > host->bounce_buffer_size) {
636 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
637 mmc_hostname(host->mmc), length,
638 host->bounce_buffer_size);
639 return -EIO;
640 }
641 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
642 /* Copy the data to the bounce buffer */
e93577ec
AD		 643 if (host->ops->copy_to_bounce_buffer) {
644 host->ops->copy_to_bounce_buffer(host,
645 data, length);
646 } else {
647 sg_copy_to_buffer(data->sg, data->sg_len,
648 host->bounce_buffer, length);
649 }
bd9b9027
LW		 650 }
651 /* Switch ownership to the DMA */
652 dma_sync_single_for_device(host->mmc->parent,
653 host->bounce_addr,
654 host->bounce_buffer_size,
655 mmc_get_dma_dir(data));
656 /* Just a dummy value */
657 sg_count = 1;
658 } else {
659 /* Just access the data directly from memory */
660 sg_count = dma_map_sg(mmc_dev(host->mmc),
661 data->sg, data->sg_len,
662 mmc_get_dma_dir(data));
663 }
48857d9b
RK		 664
665 if (sg_count == 0)
666 return -ENOSPC;
667
668 data->sg_count = sg_count;
c0999b72 669 data->host_cookie = cookie;
48857d9b
RK		 670
671 return sg_count;
672}
673
2134a922
PO		 674static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
675{
676 local_irq_save(*flags);
482fce99 677 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 678}
679
680static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
681{
482fce99 682 kunmap_atomic(buffer);
2134a922
PO		 683 local_irq_restore(*flags);
684}
685
54552e49
JZ		 686void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
687 dma_addr_t addr, int len, unsigned int cmd)
118cd17d 688{
54552e49 689 struct sdhci_adma2_64_desc *dma_desc = *desc;
118cd17d 690
e57a5f61 691 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 692 dma_desc->cmd = cpu_to_le16(cmd);
693 dma_desc->len = cpu_to_le16(len);
38eee2e8 694 dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
e57a5f61
AH		 695
696 if (host->flags & SDHCI_USE_64_BIT_DMA)
38eee2e8 697 dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
54552e49
JZ		 698
699 *desc += host->desc_sz;
700}
701EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
702
703static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
704 void **desc, dma_addr_t addr,
705 int len, unsigned int cmd)
706{
707 if (host->ops->adma_write_desc)
708 host->ops->adma_write_desc(host, desc, addr, len, cmd);
07be55b5
JZ		 709 else
710 sdhci_adma_write_desc(host, desc, addr, len, cmd);
118cd17d
BD		 711}
712
b5ffa674
AH		 713static void sdhci_adma_mark_end(void *desc)
714{
e57a5f61 715 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 716
e57a5f61 717 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 718 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 719}
720
60c64762
RK		 721static void sdhci_adma_table_pre(struct sdhci_host *host,
722 struct mmc_data *data, int sg_count)
2134a922 723{
2134a922 724 struct scatterlist *sg;
2134a922 725 unsigned long flags;
acc3ad13
RK		 726 dma_addr_t addr, align_addr;
727 void *desc, *align;
728 char *buffer;
729 int len, offset, i;
2134a922
PO		 730
731 /*
732 * The spec does not specify endianness of descriptor table.
733 * We currently guess that it is LE.
734 */
735
60c64762 736 host->sg_count = sg_count;
2134a922 737
4efaa6fb 738 desc = host->adma_table;
2134a922
PO		 739 align = host->align_buffer;
740
741 align_addr = host->align_addr;
742
743 for_each_sg(data->sg, sg, host->sg_count, i) {
744 addr = sg_dma_address(sg);
745 len = sg_dma_len(sg);
746
747 /*
acc3ad13
RK		 748 * The SDHCI specification states that ADMA addresses must
749 * be 32-bit aligned. If they aren't, then we use a bounce
750 * buffer for the (up to three) bytes that screw up the
2134a922
PO		 751 * alignment.
752 */
04a5ae6f
AH		 753 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
754 SDHCI_ADMA2_MASK;
2134a922
PO		 755 if (offset) {
756 if (data->flags & MMC_DATA_WRITE) {
757 buffer = sdhci_kmap_atomic(sg, &flags);
758 memcpy(align, buffer, offset);
759 sdhci_kunmap_atomic(buffer, &flags);
760 }
761
118cd17d 762 /* tran, valid */
54552e49
JZ		 763 __sdhci_adma_write_desc(host, &desc, align_addr,
764 offset, ADMA2_TRAN_VALID);
2134a922
PO		 765
766 BUG_ON(offset > 65536);
767
04a5ae6f
AH		 768 align += SDHCI_ADMA2_ALIGN;
769 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 770
2134a922
PO		 771 addr += offset;
772 len -= offset;
773 }
774
2134a922
PO		 775 BUG_ON(len > 65536);
776
54552e49
JZ		 777 /* tran, valid */
778 if (len)
779 __sdhci_adma_write_desc(host, &desc, addr, len,
780 ADMA2_TRAN_VALID);
2134a922
PO		 781
782 /*
783 * If this triggers then we have a calculation bug
784 * somewhere. :/
785 */
76fe379a 786 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 787 }
788
70764a90 789 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
acc3ad13 790 /* Mark the last descriptor as the terminating descriptor */
4efaa6fb 791 if (desc != host->adma_table) {
76fe379a 792 desc -= host->desc_sz;
b5ffa674 793 sdhci_adma_mark_end(desc);
70764a90
TA		 794 }
795 } else {
acc3ad13 796 /* Add a terminating entry - nop, end, valid */
54552e49 797 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 798 }
2134a922
PO		 799}
800
801static void sdhci_adma_table_post(struct sdhci_host *host,
802 struct mmc_data *data)
803{
2134a922
PO		 804 struct scatterlist *sg;
805 int i, size;
1c3d5f6d 806 void *align;
2134a922
PO		 807 char *buffer;
808 unsigned long flags;
809
47fa9613
RK		 810 if (data->flags & MMC_DATA_READ) {
811 bool has_unaligned = false;
de0b65a7 812
47fa9613
RK		 813 /* Do a quick scan of the SG list for any unaligned mappings */
814 for_each_sg(data->sg, sg, host->sg_count, i)
815 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
816 has_unaligned = true;
817 break;
818 }
2134a922 819
47fa9613
RK		 820 if (has_unaligned) {
821 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
f55c98f7 822 data->sg_len, DMA_FROM_DEVICE);
2134a922 823
47fa9613 824 align = host->align_buffer;
2134a922 825
47fa9613
RK		 826 for_each_sg(data->sg, sg, host->sg_count, i) {
827 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
828 size = SDHCI_ADMA2_ALIGN -
829 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
830
831 buffer = sdhci_kmap_atomic(sg, &flags);
832 memcpy(buffer, align, size);
833 sdhci_kunmap_atomic(buffer, &flags);
2134a922 834
47fa9613
RK		 835 align += SDHCI_ADMA2_ALIGN;
836 }
2134a922
PO		 837 }
838 }
839 }
2134a922
PO		 840}
841
38eee2e8
MY		 842static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
843{
844 sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
845 if (host->flags & SDHCI_USE_64_BIT_DMA)
846 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
847}
848
917a0c52 849static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
bd9b9027
LW		 850{
851 if (host->bounce_buffer)
852 return host->bounce_addr;
853 else
854 return sg_dma_address(host->data->sg);
855}
856
917a0c52
CZ		 857static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
858{
38eee2e8
MY		 859 if (host->v4_mode)
860 sdhci_set_adma_addr(host, addr);
861 else
917a0c52 862 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
917a0c52
CZ		 863}
864
0bb28d73
AH		 865static unsigned int sdhci_target_timeout(struct sdhci_host *host,
866 struct mmc_command *cmd,
867 struct mmc_data *data)
868{
869 unsigned int target_timeout;
870
871 /* timeout in us */
872 if (!data) {
873 target_timeout = cmd->busy_timeout * 1000;
874 } else {
875 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
876 if (host->clock && data->timeout_clks) {
877 unsigned long long val;
878
879 /*
880 * data->timeout_clks is in units of clock cycles.
881 * host->clock is in Hz. target_timeout is in us.
882 * Hence, us = 1000000 * cycles / Hz. Round up.
883 */
884 val = 1000000ULL * data->timeout_clks;
885 if (do_div(val, host->clock))
886 target_timeout++;
887 target_timeout += val;
888 }
889 }
890
891 return target_timeout;
892}
893
fc1fa1b7
KVA		 894static void sdhci_calc_sw_timeout(struct sdhci_host *host,
895 struct mmc_command *cmd)
896{
897 struct mmc_data *data = cmd->data;
898 struct mmc_host *mmc = host->mmc;
899 struct mmc_ios *ios = &mmc->ios;
900 unsigned char bus_width = 1 << ios->bus_width;
901 unsigned int blksz;
902 unsigned int freq;
903 u64 target_timeout;
904 u64 transfer_time;
905
906 target_timeout = sdhci_target_timeout(host, cmd, data);
907 target_timeout *= NSEC_PER_USEC;
908
909 if (data) {
910 blksz = data->blksz;
911 freq = host->mmc->actual_clock ? : host->clock;
912 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
913 do_div(transfer_time, freq);
914 /* multiply by '2' to account for any unknowns */
915 transfer_time = transfer_time * 2;
916 /* calculate timeout for the entire data */
917 host->data_timeout = data->blocks * target_timeout +
918 transfer_time;
919 } else {
920 host->data_timeout = target_timeout;
921 }
922
923 if (host->data_timeout)
924 host->data_timeout += MMC_CMD_TRANSFER_TIME;
925}
926
a999fd93
AH		 927static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
928 bool *too_big)
d129bceb 929{
1c8cde92 930 u8 count;
401059df 931 struct mmc_data *data;
1c8cde92 932 unsigned target_timeout, current_timeout;
d129bceb 933
a999fd93
AH		 934 *too_big = true;
935
ee53ab5d
PO		 936 /*
937 * If the host controller provides us with an incorrect timeout
938 * value, just skip the check and use 0xE. The hardware may take
939 * longer to time out, but that's much better than having a too-short
940 * timeout value.
941 */
11a2f1b7 942 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 943 return 0xE;
e538fbe8 944
401059df
BC		 945 /* Unspecified command, asume max */
946 if (cmd == NULL)
947 return 0xE;
948
949 data = cmd->data;
a3c7778f 950 /* Unspecified timeout, assume max */
1d4d7744 951 if (!data && !cmd->busy_timeout)
a3c7778f 952 return 0xE;
d129bceb 953
a3c7778f 954 /* timeout in us */
0bb28d73 955 target_timeout = sdhci_target_timeout(host, cmd, data);
81b39802 956
1c8cde92
PO		 957 /*
958 * Figure out needed cycles.
959 * We do this in steps in order to fit inside a 32 bit int.
960 * The first step is the minimum timeout, which will have a
961 * minimum resolution of 6 bits:
962 * (1) 2^13*1000 > 2^22,
963 * (2) host->timeout_clk < 2^16
964 * =>
965 * (1) / (2) > 2^6
966 */
967 count = 0;
968 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
969 while (current_timeout < target_timeout) {
970 count++;
971 current_timeout <<= 1;
972 if (count >= 0xF)
973 break;
974 }
975
976 if (count >= 0xF) {
a999fd93
AH		 977 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
978 DBG("Too large timeout 0x%x requested for CMD%d!\n",
979 count, cmd->opcode);
1c8cde92 980 count = 0xE;
a999fd93
AH		 981 } else {
982 *too_big = false;
1c8cde92
PO		 983 }
984
ee53ab5d
PO		 985 return count;
986}
987
6aa943ab
AV		 988static void sdhci_set_transfer_irqs(struct sdhci_host *host)
989{
990 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
991 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
992
993 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 994 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 995 else
b537f94c
RK		 996 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
997
af849c86
AH		 998 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
999 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
1000 else
1001 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
1002
b537f94c
RK		 1003 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1004 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 1005}
1006
7907ebe7 1007void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
a999fd93
AH		 1008{
1009 if (enable)
1010 host->ier |= SDHCI_INT_DATA_TIMEOUT;
1011 else
1012 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
1013 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1014 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1015}
7907ebe7 1016EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
a999fd93 1017
7d76ed77 1018void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d 1019{
7d76ed77
FA		 1020 bool too_big = false;
1021 u8 count = sdhci_calc_timeout(host, cmd, &too_big);
1022
1023 if (too_big &&
1024 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1025 sdhci_calc_sw_timeout(host, cmd);
1026 sdhci_set_data_timeout_irq(host, false);
1027 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1028 sdhci_set_data_timeout_irq(host, true);
1029 }
a999fd93 1030
7d76ed77
FA		 1031 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1032}
1033EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
a999fd93 1034
7d76ed77
FA		 1035static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1036{
1037 if (host->ops->set_timeout)
1038 host->ops->set_timeout(host, cmd);
1039 else
1040 __sdhci_set_timeout(host, cmd);
b45e668a
AD		 1041}
1042
15db1836
FA		 1043static void sdhci_initialize_data(struct sdhci_host *host,
1044 struct mmc_data *data)
b45e668a 1045{
43dea098
AH		 1046 WARN_ON(host->data);
1047
ee53ab5d
PO		 1048 /* Sanity checks */
1049 BUG_ON(data->blksz * data->blocks > 524288);
1050 BUG_ON(data->blksz > host->mmc->max_blk_size);
1051 BUG_ON(data->blocks > 65535);
1052
1053 host->data = data;
1054 host->data_early = 0;
f6a03cbf 1055 host->data->bytes_xfered = 0;
15db1836
FA		 1056}
1057
1058static inline void sdhci_set_block_info(struct sdhci_host *host,
1059 struct mmc_data *data)
1060{
1061 /* Set the DMA boundary value and block size */
1062 sdhci_writew(host,
1063 SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1064 SDHCI_BLOCK_SIZE);
1065 /*
1066 * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
1067 * can be supported, in that case 16-bit block count register must be 0.
1068 */
1069 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1070 (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1071 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1072 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1073 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1074 } else {
1075 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1076 }
1077}
1078
1079static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1080{
1081 struct mmc_data *data = cmd->data;
1082
1083 sdhci_initialize_data(host, data);
ee53ab5d 1084
fce14421 1085 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2134a922 1086 struct scatterlist *sg;
df953925 1087 unsigned int length_mask, offset_mask;
a0eaf0f9 1088 int i;
2134a922 1089
fce14421
RK		 1090 host->flags |= SDHCI_REQ_USE_DMA;
1091
1092 /*
1093 * FIXME: This doesn't account for merging when mapping the
1094 * scatterlist.
1095 *
1096 * The assumption here being that alignment and lengths are
1097 * the same after DMA mapping to device address space.
1098 */
a0eaf0f9 1099 length_mask = 0;
df953925 1100 offset_mask = 0;
2134a922 1101 if (host->flags & SDHCI_USE_ADMA) {
df953925 1102 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
a0eaf0f9 1103 length_mask = 3;
df953925
RK		 1104 /*
1105 * As we use up to 3 byte chunks to work
1106 * around alignment problems, we need to
1107 * check the offset as well.
1108 */
1109 offset_mask = 3;
1110 }
2134a922
PO		 1111 } else {
1112 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
a0eaf0f9 1113 length_mask = 3;
df953925
RK		 1114 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1115 offset_mask = 3;
2134a922
PO		 1116 }
1117
df953925 1118 if (unlikely(length_mask | offset_mask)) {
2134a922 1119 for_each_sg(data->sg, sg, data->sg_len, i) {
a0eaf0f9 1120 if (sg->length & length_mask) {
2e4456f0 1121 DBG("Reverting to PIO because of transfer size (%d)\n",
a0eaf0f9 1122 sg->length);
2134a922
PO		 1123 host->flags &= ~SDHCI_REQ_USE_DMA;
1124 break;
1125 }
a0eaf0f9 1126 if (sg->offset & offset_mask) {
2e4456f0 1127 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 1128 host->flags &= ~SDHCI_REQ_USE_DMA;
1129 break;
1130 }
1131 }
1132 }
1133 }
1134
8f1934ce 1135 if (host->flags & SDHCI_REQ_USE_DMA) {
c0999b72 1136 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
60c64762
RK		 1137
1138 if (sg_cnt <= 0) {
1139 /*
1140 * This only happens when someone fed
1141 * us an invalid request.
1142 */
1143 WARN_ON(1);
1144 host->flags &= ~SDHCI_REQ_USE_DMA;
1145 } else if (host->flags & SDHCI_USE_ADMA) {
1146 sdhci_adma_table_pre(host, data, sg_cnt);
38eee2e8 1147 sdhci_set_adma_addr(host, host->adma_addr);
8f1934ce 1148 } else {
60c64762 1149 WARN_ON(sg_cnt != 1);
917a0c52 1150 sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
8f1934ce
PO		 1151 }
1152 }
1153
685e444b 1154 sdhci_config_dma(host);
c9fddbc4 1155
8f1934ce 1156 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 1157 int flags;
1158
1159 flags = SG_MITER_ATOMIC;
1160 if (host->data->flags & MMC_DATA_READ)
1161 flags |= SG_MITER_TO_SG;
1162 else
1163 flags |= SG_MITER_FROM_SG;
1164 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 1165 host->blocks = data->blocks;
d129bceb 1166 }
c7fa9963 1167
6aa943ab
AV		 1168 sdhci_set_transfer_irqs(host);
1169
15db1836 1170 sdhci_set_block_info(host, data);
c7fa9963
PO		 1171}
1172
18e762e3
CZ		 1173#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
1174
1175static int sdhci_external_dma_init(struct sdhci_host *host)
1176{
1177 int ret = 0;
1178 struct mmc_host *mmc = host->mmc;
1179
1180 host->tx_chan = dma_request_chan(mmc->parent, "tx");
1181 if (IS_ERR(host->tx_chan)) {
1182 ret = PTR_ERR(host->tx_chan);
1183 if (ret != -EPROBE_DEFER)
1184 pr_warn("Failed to request TX DMA channel.\n");
1185 host->tx_chan = NULL;
1186 return ret;
1187 }
1188
1189 host->rx_chan = dma_request_chan(mmc->parent, "rx");
1190 if (IS_ERR(host->rx_chan)) {
1191 if (host->tx_chan) {
1192 dma_release_channel(host->tx_chan);
1193 host->tx_chan = NULL;
1194 }
1195
1196 ret = PTR_ERR(host->rx_chan);
1197 if (ret != -EPROBE_DEFER)
1198 pr_warn("Failed to request RX DMA channel.\n");
1199 host->rx_chan = NULL;
1200 }
1201
1202 return ret;
1203}
1204
1205static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1206 struct mmc_data *data)
1207{
1208 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
1209}
1210
1211static int sdhci_external_dma_setup(struct sdhci_host *host,
1212 struct mmc_command *cmd)
1213{
1214 int ret, i;
1215c025 1215 enum dma_transfer_direction dir;
18e762e3
CZ		 1216 struct dma_async_tx_descriptor *desc;
1217 struct mmc_data *data = cmd->data;
1218 struct dma_chan *chan;
1219 struct dma_slave_config cfg;
1220 dma_cookie_t cookie;
1221 int sg_cnt;
1222
1223 if (!host->mapbase)
1224 return -EINVAL;
1225
1226 cfg.src_addr = host->mapbase + SDHCI_BUFFER;
1227 cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
1228 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1229 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1230 cfg.src_maxburst = data->blksz / 4;
1231 cfg.dst_maxburst = data->blksz / 4;
1232
1233 /* Sanity check: all the SG entries must be aligned by block size. */
1234 for (i = 0; i < data->sg_len; i++) {
1235 if ((data->sg + i)->length % data->blksz)
1236 return -EINVAL;
1237 }
1238
1239 chan = sdhci_external_dma_channel(host, data);
1240
1241 ret = dmaengine_slave_config(chan, &cfg);
1242 if (ret)
1243 return ret;
1244
1245 sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1246 if (sg_cnt <= 0)
1247 return -EINVAL;
1248
1215c025
CZ		 1249 dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
1250 desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir,
18e762e3
CZ		 1251 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1252 if (!desc)
1253 return -EINVAL;
1254
1255 desc->callback = NULL;
1256 desc->callback_param = NULL;
1257
1258 cookie = dmaengine_submit(desc);
1259 if (dma_submit_error(cookie))
1260 ret = cookie;
1261
1262 return ret;
1263}
1264
1265static void sdhci_external_dma_release(struct sdhci_host *host)
1266{
1267 if (host->tx_chan) {
1268 dma_release_channel(host->tx_chan);
1269 host->tx_chan = NULL;
1270 }
1271
1272 if (host->rx_chan) {
1273 dma_release_channel(host->rx_chan);
1274 host->rx_chan = NULL;
1275 }
1276
1277 sdhci_switch_external_dma(host, false);
1278}
1279
1280static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
1281 struct mmc_command *cmd)
1282{
1283 struct mmc_data *data = cmd->data;
1284
1285 sdhci_initialize_data(host, data);
1286
1287 host->flags |= SDHCI_REQ_USE_DMA;
1288 sdhci_set_transfer_irqs(host);
1289
1290 sdhci_set_block_info(host, data);
1291}
1292
1293static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1294 struct mmc_command *cmd)
1295{
1296 if (!sdhci_external_dma_setup(host, cmd)) {
1297 __sdhci_external_dma_prepare_data(host, cmd);
1298 } else {
1299 sdhci_external_dma_release(host);
1300 pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
1301 mmc_hostname(host->mmc));
1302 sdhci_prepare_data(host, cmd);
1303 }
1304}
1305
1306static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1307 struct mmc_command *cmd)
1308{
1309 struct dma_chan *chan;
1310
1311 if (!cmd->data)
1312 return;
1313
1314 chan = sdhci_external_dma_channel(host, cmd->data);
1315 if (chan)
1316 dma_async_issue_pending(chan);
1317}
1318
1319#else
1320
1321static inline int sdhci_external_dma_init(struct sdhci_host *host)
1322{
1323 return -EOPNOTSUPP;
1324}
1325
1326static inline void sdhci_external_dma_release(struct sdhci_host *host)
1327{
1328}
1329
1330static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1331 struct mmc_command *cmd)
1332{
1333 /* This should never happen */
1334 WARN_ON_ONCE(1);
1335}
1336
1337static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1338 struct mmc_command *cmd)
1339{
1340}
1341
1342static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1343 struct mmc_data *data)
1344{
1345 return NULL;
1346}
1347
1348#endif
1349
1350void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
1351{
1352 host->use_external_dma = en;
1353}
1354EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
1355
0293d501
AH		 1356static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1357 struct mmc_request *mrq)
1358{
20845bef
AH		 1359 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1360 !mrq->cap_cmd_during_tfr;
0293d501
AH		 1361}
1362
ed633033
AH		 1363static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
1364 struct mmc_request *mrq)
1365{
1366 return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1367}
1368
1369static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
1370 struct mmc_request *mrq)
1371{
1372 return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
1373}
1374
427b6514
CZ		 1375static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1376 struct mmc_command *cmd,
1377 u16 *mode)
1378{
1379 bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1380 (cmd->opcode != SD_IO_RW_EXTENDED);
ed633033 1381 bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
427b6514
CZ		 1382 u16 ctrl2;
1383
1384 /*
1385 * In case of Version 4.10 or later, use of 'Auto CMD Auto
1386 * Select' is recommended rather than use of 'Auto CMD12
b3e1ea16
JZ		 1387 * Enable' or 'Auto CMD23 Enable'. We require Version 4 Mode
1388 * here because some controllers (e.g sdhci-of-dwmshc) expect it.
427b6514 1389 */
b3e1ea16
JZ		 1390 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1391 (use_cmd12 || use_cmd23)) {
427b6514
CZ		 1392 *mode |= SDHCI_TRNS_AUTO_SEL;
1393
1394 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1395 if (use_cmd23)
1396 ctrl2 |= SDHCI_CMD23_ENABLE;
1397 else
1398 ctrl2 &= ~SDHCI_CMD23_ENABLE;
1399 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1400
1401 return;
1402 }
1403
1404 /*
1405 * If we are sending CMD23, CMD12 never gets sent
1406 * on successful completion (so no Auto-CMD12).
1407 */
1408 if (use_cmd12)
1409 *mode |= SDHCI_TRNS_AUTO_CMD12;
1410 else if (use_cmd23)
1411 *mode |= SDHCI_TRNS_AUTO_CMD23;
1412}
1413
c7fa9963 1414static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 1415 struct mmc_command *cmd)
c7fa9963 1416{
d3fc5d71 1417 u16 mode = 0;
e89d456f 1418 struct mmc_data *data = cmd->data;
c7fa9963 1419
2b558c13 1420 if (data == NULL) {
9b8ffea6
VW		 1421 if (host->quirks2 &
1422 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
0086fc21 1423 /* must not clear SDHCI_TRANSFER_MODE when tuning */
1424 if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
1425 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
9b8ffea6 1426 } else {
2b558c13 1427 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 1428 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1429 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 1430 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 1431 }
c7fa9963 1432 return;
2b558c13 1433 }
c7fa9963 1434
e538fbe8
PO		 1435 WARN_ON(!host->data);
1436
d3fc5d71
VY		 1437 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1438 mode = SDHCI_TRNS_BLK_CNT_EN;
1439
e89d456f 1440 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 1441 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
427b6514 1442 sdhci_auto_cmd_select(host, cmd, &mode);
ed633033 1443 if (sdhci_auto_cmd23(host, cmd->mrq))
a4c73aba 1444 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
c4512f79 1445 }
8edf6371 1446
c7fa9963
PO		 1447 if (data->flags & MMC_DATA_READ)
1448 mode |= SDHCI_TRNS_READ;
c9fddbc4 1449 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 1450 mode |= SDHCI_TRNS_DMA;
1451
4e4141a5 1452 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 1453}
1454
0cc563ce
AH		 1455static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1456{
1457 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1458 ((mrq->cmd && mrq->cmd->error) ||
1459 (mrq->sbc && mrq->sbc->error) ||
4bf78099 1460 (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
0cc563ce
AH		 1461 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1462}
1463
15db1836 1464static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
4e9f8fe5
AH		 1465{
1466 int i;
1467
1468 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1469 if (host->mrqs_done[i] == mrq) {
1470 WARN_ON(1);
1471 return;
1472 }
1473 }
1474
1475 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1476 if (!host->mrqs_done[i]) {
1477 host->mrqs_done[i] = mrq;
1478 break;
1479 }
1480 }
1481
1482 WARN_ON(i >= SDHCI_MAX_MRQS);
15db1836
FA		 1483}
1484
1485static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1486{
1487 if (host->cmd && host->cmd->mrq == mrq)
1488 host->cmd = NULL;
1489
1490 if (host->data_cmd && host->data_cmd->mrq == mrq)
1491 host->data_cmd = NULL;
1492
845c939e
AH		 1493 if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
1494 host->deferred_cmd = NULL;
1495
15db1836
FA		 1496 if (host->data && host->data->mrq == mrq)
1497 host->data = NULL;
1498
1499 if (sdhci_needs_reset(host, mrq))
1500 host->pending_reset = true;
1501
1502 sdhci_set_mrq_done(host, mrq);
4e9f8fe5 1503
e9a07299
AH		 1504 sdhci_del_timer(host, mrq);
1505
1506 if (!sdhci_has_requests(host))
1507 sdhci_led_deactivate(host);
4e9f8fe5
AH		 1508}
1509
a6d3bdd5
AH		 1510static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1511{
4e9f8fe5 1512 __sdhci_finish_mrq(host, mrq);
2e72ab9b 1513
c07a48c2 1514 queue_work(host->complete_wq, &host->complete_work);
a6d3bdd5
AH		 1515}
1516
845c939e 1517static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
d129bceb 1518{
33a57adb
AH		 1519 struct mmc_command *data_cmd = host->data_cmd;
1520 struct mmc_data *data = host->data;
d129bceb 1521
d129bceb 1522 host->data = NULL;
7c89a3d9 1523 host->data_cmd = NULL;
d129bceb 1524
4bf78099
AH		 1525 /*
1526 * The controller needs a reset of internal state machines upon error
1527 * conditions.
1528 */
1529 if (data->error) {
1530 if (!host->cmd || host->cmd == data_cmd)
1531 sdhci_do_reset(host, SDHCI_RESET_CMD);
1532 sdhci_do_reset(host, SDHCI_RESET_DATA);
1533 }
1534
add8913d
RK		 1535 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1536 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1537 sdhci_adma_table_post(host, data);
d129bceb
PO		 1538
1539 /*
c9b74c5b
PO		 1540 * The specification states that the block count register must
1541 * be updated, but it does not specify at what point in the
1542 * data flow. That makes the register entirely useless to read
1543 * back so we have to assume that nothing made it to the card
1544 * in the event of an error.
d129bceb 1545 */
c9b74c5b
PO		 1546 if (data->error)
1547 data->bytes_xfered = 0;
d129bceb 1548 else
c9b74c5b 1549 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 1550
e89d456f
AW		 1551 /*
1552 * Need to send CMD12 if -
fdbbe6cf 1553 * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
e89d456f
AW		 1554 * b) error in multiblock transfer
1555 */
1556 if (data->stop &&
fdbbe6cf
YL		 1557 ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
1558 data->error)) {
20845bef
AH		 1559 /*
1560 * 'cap_cmd_during_tfr' request must not use the command line
1561 * after mmc_command_done() has been called. It is upper layer's
1562 * responsibility to send the stop command if required.
1563 */
1564 if (data->mrq->cap_cmd_during_tfr) {
19d2f695 1565 __sdhci_finish_mrq(host, data->mrq);
20845bef
AH		 1566 } else {
1567 /* Avoid triggering warning in sdhci_send_command() */
1568 host->cmd = NULL;
845c939e
AH		 1569 if (!sdhci_send_command(host, data->stop)) {
1570 if (sw_data_timeout) {
1571 /*
1572 * This is anyway a sw data timeout, so
1573 * give up now.
1574 */
1575 data->stop->error = -EIO;
1576 __sdhci_finish_mrq(host, data->mrq);
1577 } else {
1578 WARN_ON(host->deferred_cmd);
1579 host->deferred_cmd = data->stop;
1580 }
1581 }
20845bef 1582 }
a6d3bdd5 1583 } else {
19d2f695 1584 __sdhci_finish_mrq(host, data->mrq);
a6d3bdd5 1585 }
d129bceb
PO		 1586}
1587
845c939e
AH		 1588static void sdhci_finish_data(struct sdhci_host *host)
1589{
1590 __sdhci_finish_data(host, false);
1591}
1592
1593static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 1594{
1595 int flags;
fd2208d7 1596 u32 mask;
7cb2c76f 1597 unsigned long timeout;
d129bceb
PO		 1598
1599 WARN_ON(host->cmd);
1600
96776200
RK		 1601 /* Initially, a command has no error */
1602 cmd->error = 0;
1603
fc605f1d
AH		 1604 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1605 cmd->opcode == MMC_STOP_TRANSMISSION)
1606 cmd->flags |= MMC_RSP_BUSY;
1607
fd2208d7 1608 mask = SDHCI_CMD_INHIBIT;
56a590dc 1609 if (sdhci_data_line_cmd(cmd))
fd2208d7
PO		 1610 mask |= SDHCI_DATA_INHIBIT;
1611
1612 /* We shouldn't wait for data inihibit for stop commands, even
1613 though they might use busy signaling */
a4c73aba 1614 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
fd2208d7
PO		 1615 mask &= ~SDHCI_DATA_INHIBIT;
1616
845c939e
AH		 1617 if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
1618 return false;
d129bceb 1619
d129bceb 1620 host->cmd = cmd;
15db1836 1621 host->data_timeout = 0;
56a590dc 1622 if (sdhci_data_line_cmd(cmd)) {
7c89a3d9
AH		 1623 WARN_ON(host->data_cmd);
1624 host->data_cmd = cmd;
15db1836 1625 sdhci_set_timeout(host, cmd);
7c89a3d9 1626 }
d129bceb 1627
18e762e3
CZ		 1628 if (cmd->data) {
1629 if (host->use_external_dma)
1630 sdhci_external_dma_prepare_data(host, cmd);
1631 else
1632 sdhci_prepare_data(host, cmd);
1633 }
d129bceb 1634
4e4141a5 1635 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1636
e89d456f 1637 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1638
d129bceb 1639 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
845c939e
AH		 1640 WARN_ONCE(1, "Unsupported response type!\n");
1641 /*
1642 * This does not happen in practice because 136-bit response
1643 * commands never have busy waiting, so rather than complicate
1644 * the error path, just remove busy waiting and continue.
1645 */
1646 cmd->flags &= ~MMC_RSP_BUSY;
d129bceb
PO		 1647 }
1648
1649 if (!(cmd->flags & MMC_RSP_PRESENT))
1650 flags = SDHCI_CMD_RESP_NONE;
1651 else if (cmd->flags & MMC_RSP_136)
1652 flags = SDHCI_CMD_RESP_LONG;
1653 else if (cmd->flags & MMC_RSP_BUSY)
1654 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1655 else
1656 flags = SDHCI_CMD_RESP_SHORT;
1657
1658 if (cmd->flags & MMC_RSP_CRC)
1659 flags |= SDHCI_CMD_CRC;
1660 if (cmd->flags & MMC_RSP_OPCODE)
1661 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1662
1663 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1664 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1665 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1666 flags |= SDHCI_CMD_DATA;
1667
fc1fa1b7
KVA		 1668 timeout = jiffies;
1669 if (host->data_timeout)
1670 timeout += nsecs_to_jiffies(host->data_timeout);
1671 else if (!cmd->data && cmd->busy_timeout > 9000)
1672 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1673 else
1674 timeout += 10 * HZ;
1675 sdhci_mod_timer(host, cmd->mrq, timeout);
1676
18e762e3
CZ		 1677 if (host->use_external_dma)
1678 sdhci_external_dma_pre_transfer(host, cmd);
1679
4e4141a5 1680 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
845c939e
AH		 1681
1682 return true;
d129bceb
PO		 1683}
1684
e872f1e2
AH		 1685static bool sdhci_present_error(struct sdhci_host *host,
1686 struct mmc_command *cmd, bool present)
1687{
1688 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1689 cmd->error = -ENOMEDIUM;
1690 return true;
1691 }
1692
1693 return false;
1694}
1695
845c939e
AH		 1696static bool sdhci_send_command_retry(struct sdhci_host *host,
1697 struct mmc_command *cmd,
1698 unsigned long flags)
1699 __releases(host->lock)
1700 __acquires(host->lock)
1701{
1702 struct mmc_command *deferred_cmd = host->deferred_cmd;
1703 int timeout = 10; /* Approx. 10 ms */
1704 bool present;
1705
1706 while (!sdhci_send_command(host, cmd)) {
1707 if (!timeout--) {
1708 pr_err("%s: Controller never released inhibit bit(s).\n",
1709 mmc_hostname(host->mmc));
1710 sdhci_dumpregs(host);
1711 cmd->error = -EIO;
1712 return false;
1713 }
1714
1715 spin_unlock_irqrestore(&host->lock, flags);
1716
1717 usleep_range(1000, 1250);
1718
1719 present = host->mmc->ops->get_cd(host->mmc);
1720
1721 spin_lock_irqsave(&host->lock, flags);
1722
1723 /* A deferred command might disappear, handle that */
1724 if (cmd == deferred_cmd && cmd != host->deferred_cmd)
1725 return true;
1726
1727 if (sdhci_present_error(host, cmd, present))
1728 return false;
1729 }
1730
1731 if (cmd == host->deferred_cmd)
1732 host->deferred_cmd = NULL;
1733
1734 return true;
1735}
1736
4a5fc119
AH		 1737static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1738{
1739 int i, reg;
1740
1741 for (i = 0; i < 4; i++) {
1742 reg = SDHCI_RESPONSE + (3 - i) * 4;
1743 cmd->resp[i] = sdhci_readl(host, reg);
1744 }
1745
1284c248
KVA		 1746 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1747 return;
1748
4a5fc119
AH		 1749 /* CRC is stripped so we need to do some shifting */
1750 for (i = 0; i < 4; i++) {
1751 cmd->resp[i] <<= 8;
1752 if (i != 3)
1753 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1754 }
1755}
1756
d129bceb
PO		 1757static void sdhci_finish_command(struct sdhci_host *host)
1758{
e0a5640a 1759 struct mmc_command *cmd = host->cmd;
d129bceb 1760
e0a5640a
AH		 1761 host->cmd = NULL;
1762
1763 if (cmd->flags & MMC_RSP_PRESENT) {
1764 if (cmd->flags & MMC_RSP_136) {
4a5fc119 1765 sdhci_read_rsp_136(host, cmd);
d129bceb 1766 } else {
e0a5640a 1767 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1768 }
1769 }
1770
20845bef
AH		 1771 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1772 mmc_command_done(host->mmc, cmd->mrq);
1773
6bde8681
AH		 1774 /*
1775 * The host can send and interrupt when the busy state has
1776 * ended, allowing us to wait without wasting CPU cycles.
1777 * The busy signal uses DAT0 so this is similar to waiting
1778 * for data to complete.
1779 *
1780 * Note: The 1.0 specification is a bit ambiguous about this
1781 * feature so there might be some problems with older
1782 * controllers.
1783 */
e0a5640a
AH		 1784 if (cmd->flags & MMC_RSP_BUSY) {
1785 if (cmd->data) {
6bde8681
AH		 1786 DBG("Cannot wait for busy signal when also doing a data transfer");
1787 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
ea968023
AH		 1788 cmd == host->data_cmd) {
1789 /* Command complete before busy is ended */
6bde8681
AH		 1790 return;
1791 }
1792 }
1793
e89d456f 1794 /* Finished CMD23, now send actual command. */
a4c73aba 1795 if (cmd == cmd->mrq->sbc) {
845c939e
AH		 1796 if (!sdhci_send_command(host, cmd->mrq->cmd)) {
1797 WARN_ON(host->deferred_cmd);
1798 host->deferred_cmd = cmd->mrq->cmd;
1799 }
e89d456f 1800 } else {
e538fbe8 1801
e89d456f
AW		 1802 /* Processed actual command. */
1803 if (host->data && host->data_early)
1804 sdhci_finish_data(host);
d129bceb 1805
e0a5640a 1806 if (!cmd->data)
19d2f695 1807 __sdhci_finish_mrq(host, cmd->mrq);
e89d456f 1808 }
d129bceb
PO		 1809}
1810
52983382
KL		 1811static u16 sdhci_get_preset_value(struct sdhci_host *host)
1812{
d975f121 1813 u16 preset = 0;
52983382 1814
d975f121
RK		 1815 switch (host->timing) {
1816 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1817 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1818 break;
d975f121 1819 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1820 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1821 break;
d975f121 1822 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1823 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1824 break;
d975f121
RK		 1825 case MMC_TIMING_UHS_SDR104:
1826 case MMC_TIMING_MMC_HS200:
52983382
KL		 1827 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1828 break;
d975f121 1829 case MMC_TIMING_UHS_DDR50:
0dafa60e 1830 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1831 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1832 break;
e9fb05d5
AH		 1833 case MMC_TIMING_MMC_HS400:
1834 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1835 break;
52983382
KL		 1836 default:
1837 pr_warn("%s: Invalid UHS-I mode selected\n",
1838 mmc_hostname(host->mmc));
1839 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1840 break;
1841 }
1842 return preset;
1843}
1844
fb9ee047
LD		 1845u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1846 unsigned int *actual_clock)
d129bceb 1847{
c3ed3877 1848 int div = 0; /* Initialized for compiler warning */
df16219f 1849 int real_div = div, clk_mul = 1;
c3ed3877 1850 u16 clk = 0;
5497159c 1851 bool switch_base_clk = false;
d129bceb 1852
85105c53 1853 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1854 if (host->preset_enabled) {
52983382
KL		 1855 u16 pre_val;
1856
1857 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1858 pre_val = sdhci_get_preset_value(host);
fa091010 1859 div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
52983382 1860 if (host->clk_mul &&
fa091010 1861 (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
52983382
KL		 1862 clk = SDHCI_PROG_CLOCK_MODE;
1863 real_div = div + 1;
1864 clk_mul = host->clk_mul;
1865 } else {
1866 real_div = max_t(int, 1, div << 1);
1867 }
1868 goto clock_set;
1869 }
1870
c3ed3877
AN		 1871 /*
1872 * Check if the Host Controller supports Programmable Clock
1873 * Mode.
1874 */
1875 if (host->clk_mul) {
52983382
KL		 1876 for (div = 1; div <= 1024; div++) {
1877 if ((host->max_clk * host->clk_mul / div)
1878 <= clock)
1879 break;
1880 }
5497159c 1881 if ((host->max_clk * host->clk_mul / div) <= clock) {
1882 /*
1883 * Set Programmable Clock Mode in the Clock
1884 * Control register.
1885 */
1886 clk = SDHCI_PROG_CLOCK_MODE;
1887 real_div = div;
1888 clk_mul = host->clk_mul;
1889 div--;
1890 } else {
1891 /*
1892 * Divisor can be too small to reach clock
1893 * speed requirement. Then use the base clock.
1894 */
1895 switch_base_clk = true;
1896 }
1897 }
1898
1899 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1900 /* Version 3.00 divisors must be a multiple of 2. */
1901 if (host->max_clk <= clock)
1902 div = 1;
1903 else {
1904 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1905 div += 2) {
1906 if ((host->max_clk / div) <= clock)
1907 break;
1908 }
85105c53 1909 }
df16219f 1910 real_div = div;
c3ed3877 1911 div >>= 1;
d1955c3a
SG		 1912 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1913 && !div && host->max_clk <= 25000000)
1914 div = 1;
85105c53
ZG		 1915 }
1916 } else {
1917 /* Version 2.00 divisors must be a power of 2. */
0397526d 1918 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1919 if ((host->max_clk / div) <= clock)
1920 break;
1921 }
df16219f 1922 real_div = div;
c3ed3877 1923 div >>= 1;
d129bceb 1924 }
d129bceb 1925
52983382 1926clock_set:
03d6f5ff 1927 if (real_div)
fb9ee047 1928 *actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1929 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1930 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1931 << SDHCI_DIVIDER_HI_SHIFT;
fb9ee047
LD		 1932
1933 return clk;
1934}
1935EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1936
fec79673 1937void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
fb9ee047 1938{
5a436cc0 1939 ktime_t timeout;
fb9ee047 1940
d129bceb 1941 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1942 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1943
4a9e0d1a
BC		 1944 /* Wait max 150 ms */
1945 timeout = ktime_add_ms(ktime_get(), 150);
b704441e
AD		 1946 while (1) {
1947 bool timedout = ktime_after(ktime_get(), timeout);
1948
1949 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1950 if (clk & SDHCI_CLOCK_INT_STABLE)
1951 break;
1952 if (timedout) {
2e4456f0
MV		 1953 pr_err("%s: Internal clock never stabilised.\n",
1954 mmc_hostname(host->mmc));
d129bceb
PO		 1955 sdhci_dumpregs(host);
1956 return;
1957 }
5a436cc0 1958 udelay(10);
7cb2c76f 1959 }
d129bceb 1960
1beabbdb
BC		 1961 if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
1962 clk |= SDHCI_CLOCK_PLL_EN;
1963 clk &= ~SDHCI_CLOCK_INT_STABLE;
1964 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1965
1966 /* Wait max 150 ms */
1967 timeout = ktime_add_ms(ktime_get(), 150);
1968 while (1) {
1969 bool timedout = ktime_after(ktime_get(), timeout);
1970
1971 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1972 if (clk & SDHCI_CLOCK_INT_STABLE)
1973 break;
1974 if (timedout) {
1975 pr_err("%s: PLL clock never stabilised.\n",
1976 mmc_hostname(host->mmc));
1977 sdhci_dumpregs(host);
1978 return;
1979 }
1980 udelay(10);
1981 }
1982 }
1983
d129bceb 1984 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1985 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1986}
fec79673
RH		 1987EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1988
1989void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1990{
1991 u16 clk;
1992
1993 host->mmc->actual_clock = 0;
1994
1995 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1996
1997 if (clock == 0)
1998 return;
1999
2000 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
2001 sdhci_enable_clk(host, clk);
2002}
1771059c 2003EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 2004
1dceb041
AH		 2005static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
2006 unsigned short vdd)
146ad66e 2007{
3a48edc4 2008 struct mmc_host *mmc = host->mmc;
1dceb041 2009
1dceb041 2010 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1dceb041
AH		 2011
2012 if (mode != MMC_POWER_OFF)
2013 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
2014 else
2015 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2016}
2017
606d3131
AH		 2018void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
2019 unsigned short vdd)
1dceb041 2020{
8364248a 2021 u8 pwr = 0;
146ad66e 2022
24fbb3ca
RK		 2023 if (mode != MMC_POWER_OFF) {
2024 switch (1 << vdd) {
ae628903 2025 case MMC_VDD_165_195:
2a609abe
AS		 2026 /*
2027 * Without a regulator, SDHCI does not support 2.0v
2028 * so we only get here if the driver deliberately
2029 * added the 2.0v range to ocr_avail. Map it to 1.8v
2030 * for the purpose of turning on the power.
2031 */
2032 case MMC_VDD_20_21:
ae628903
PO		 2033 pwr = SDHCI_POWER_180;
2034 break;
2035 case MMC_VDD_29_30:
2036 case MMC_VDD_30_31:
2037 pwr = SDHCI_POWER_300;
2038 break;
2039 case MMC_VDD_32_33:
2040 case MMC_VDD_33_34:
2041 pwr = SDHCI_POWER_330;
2042 break;
2043 default:
9d5de93f
AH		 2044 WARN(1, "%s: Invalid vdd %#x\n",
2045 mmc_hostname(host->mmc), vdd);
2046 break;
ae628903
PO		 2047 }
2048 }
2049
2050 if (host->pwr == pwr)
e921a8b6 2051 return;
146ad66e 2052
ae628903
PO		 2053 host->pwr = pwr;
2054
2055 if (pwr == 0) {
4e4141a5 2056 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 2057 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2058 sdhci_runtime_pm_bus_off(host);
e921a8b6
RK		 2059 } else {
2060 /*
2061 * Spec says that we should clear the power reg before setting
2062 * a new value. Some controllers don't seem to like this though.
2063 */
2064 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
2065 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 2066
e921a8b6
RK		 2067 /*
2068 * At least the Marvell CaFe chip gets confused if we set the
2069 * voltage and set turn on power at the same time, so set the
2070 * voltage first.
2071 */
2072 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
2073 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 2074
e921a8b6 2075 pwr |= SDHCI_POWER_ON;
146ad66e 2076
e921a8b6 2077 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 2078
e921a8b6
RK		 2079 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2080 sdhci_runtime_pm_bus_on(host);
f0710a55 2081
e921a8b6
RK		 2082 /*
2083 * Some controllers need an extra 10ms delay of 10ms before
2084 * they can apply clock after applying power
2085 */
2086 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
2087 mdelay(10);
2088 }
1dceb041 2089}
606d3131 2090EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
918f4cbd 2091
606d3131
AH		 2092void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
2093 unsigned short vdd)
1dceb041 2094{
606d3131
AH		 2095 if (IS_ERR(host->mmc->supply.vmmc))
2096 sdhci_set_power_noreg(host, mode, vdd);
1dceb041 2097 else
606d3131 2098 sdhci_set_power_reg(host, mode, vdd);
146ad66e 2099}
606d3131 2100EXPORT_SYMBOL_GPL(sdhci_set_power);
146ad66e 2101
6c92ae1e
NSJ		 2102/*
2103 * Some controllers need to configure a valid bus voltage on their power
2104 * register regardless of whether an external regulator is taking care of power
2105 * supply. This helper function takes care of it if set as the controller's
2106 * sdhci_ops.set_power callback.
2107 */
2108void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
2109 unsigned char mode,
2110 unsigned short vdd)
2111{
2112 if (!IS_ERR(host->mmc->supply.vmmc)) {
2113 struct mmc_host *mmc = host->mmc;
2114
2115 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2116 }
2117 sdhci_set_power_noreg(host, mode, vdd);
2118}
2119EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
2120
d129bceb
PO		 2121/*****************************************************************************\
2122 * *
2123 * MMC callbacks *
2124 * *
2125\*****************************************************************************/
2126
d462c1b4 2127void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
d129bceb 2128{
e872f1e2
AH		 2129 struct sdhci_host *host = mmc_priv(mmc);
2130 struct mmc_command *cmd;
d129bceb 2131 unsigned long flags;
e872f1e2 2132 bool present;
d129bceb 2133
04e079cf 2134 /* Firstly check card presence */
8d28b7a7 2135 present = mmc->ops->get_cd(mmc);
2836766a 2136
d129bceb
PO		 2137 spin_lock_irqsave(&host->lock, flags);
2138
061d17a6 2139 sdhci_led_activate(host);
e89d456f 2140
e872f1e2
AH		 2141 if (sdhci_present_error(host, mrq->cmd, present))
2142 goto out_finish;
2143
2144 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2145
845c939e
AH		 2146 if (!sdhci_send_command_retry(host, cmd, flags))
2147 goto out_finish;
e872f1e2
AH		 2148
2149 spin_unlock_irqrestore(&host->lock, flags);
2150
2151 return;
d129bceb 2152
e872f1e2
AH		 2153out_finish:
2154 sdhci_finish_mrq(host, mrq);
d129bceb
PO		 2155 spin_unlock_irqrestore(&host->lock, flags);
2156}
d462c1b4 2157EXPORT_SYMBOL_GPL(sdhci_request);
d129bceb 2158
48ef8a2a
BW		 2159int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq)
2160{
2161 struct sdhci_host *host = mmc_priv(mmc);
2162 struct mmc_command *cmd;
2163 unsigned long flags;
2164 int ret = 0;
2165
2166 spin_lock_irqsave(&host->lock, flags);
2167
2168 if (sdhci_present_error(host, mrq->cmd, true)) {
2169 sdhci_finish_mrq(host, mrq);
2170 goto out_finish;
2171 }
2172
2173 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2174
2175 /*
2176 * The HSQ may send a command in interrupt context without polling
2177 * the busy signaling, which means we should return BUSY if controller
2178 * has not released inhibit bits to allow HSQ trying to send request
2179 * again in non-atomic context. So we should not finish this request
2180 * here.
2181 */
2182 if (!sdhci_send_command(host, cmd))
2183 ret = -EBUSY;
2184 else
2185 sdhci_led_activate(host);
2186
2187out_finish:
2188 spin_unlock_irqrestore(&host->lock, flags);
2189 return ret;
2190}
2191EXPORT_SYMBOL_GPL(sdhci_request_atomic);
2192
2317f56c
RK		 2193void sdhci_set_bus_width(struct sdhci_host *host, int width)
2194{
2195 u8 ctrl;
2196
2197 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2198 if (width == MMC_BUS_WIDTH_8) {
2199 ctrl &= ~SDHCI_CTRL_4BITBUS;
98f94ea6 2200 ctrl |= SDHCI_CTRL_8BITBUS;
2317f56c 2201 } else {
98f94ea6 2202 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
2317f56c
RK		 2203 ctrl &= ~SDHCI_CTRL_8BITBUS;
2204 if (width == MMC_BUS_WIDTH_4)
2205 ctrl |= SDHCI_CTRL_4BITBUS;
2206 else
2207 ctrl &= ~SDHCI_CTRL_4BITBUS;
2208 }
2209 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2210}
2211EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
2212
96d7b78c
RK		 2213void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
2214{
2215 u16 ctrl_2;
2216
2217 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2218 /* Select Bus Speed Mode for host */
2219 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
2220 if ((timing == MMC_TIMING_MMC_HS200) ||
2221 (timing == MMC_TIMING_UHS_SDR104))
2222 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
2223 else if (timing == MMC_TIMING_UHS_SDR12)
2224 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
07bcc411 2225 else if (timing == MMC_TIMING_UHS_SDR25)
96d7b78c
RK		 2226 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
2227 else if (timing == MMC_TIMING_UHS_SDR50)
2228 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
2229 else if ((timing == MMC_TIMING_UHS_DDR50) ||
2230 (timing == MMC_TIMING_MMC_DDR52))
2231 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 2232 else if (timing == MMC_TIMING_MMC_HS400)
2233 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 2234 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2235}
2236EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
2237
6a6d4ceb 2238void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
d129bceb 2239{
ded97e0b 2240 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2241 u8 ctrl;
2242
84ec048b
AH		 2243 if (ios->power_mode == MMC_POWER_UNDEFINED)
2244 return;
2245
ceb6143b 2246 if (host->flags & SDHCI_DEVICE_DEAD) {
3a48edc4
TK		 2247 if (!IS_ERR(mmc->supply.vmmc) &&
2248 ios->power_mode == MMC_POWER_OFF)
4e743f1f 2249 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 2250 return;
2251 }
1e72859e 2252
d129bceb
PO		 2253 /*
2254 * Reset the chip on each power off.
2255 * Should clear out any weird states.
2256 */
2257 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 2258 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 2259 sdhci_reinit(host);
d129bceb
PO		 2260 }
2261
52983382 2262 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 2263 (ios->power_mode == MMC_POWER_UP) &&
2264 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 2265 sdhci_enable_preset_value(host, false);
2266
373073ef 2267 if (!ios->clock || ios->clock != host->clock) {
1771059c 2268 host->ops->set_clock(host, ios->clock);
373073ef 2269 host->clock = ios->clock;
03d6f5ff
AD		 2270
2271 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
2272 host->clock) {
2273 host->timeout_clk = host->mmc->actual_clock ?
2274 host->mmc->actual_clock / 1000 :
2275 host->clock / 1000;
2276 host->mmc->max_busy_timeout =
2277 host->ops->get_max_timeout_count ?
2278 host->ops->get_max_timeout_count(host) :
2279 1 << 27;
2280 host->mmc->max_busy_timeout /= host->timeout_clk;
2281 }
373073ef 2282 }
d129bceb 2283
606d3131
AH		 2284 if (host->ops->set_power)
2285 host->ops->set_power(host, ios->power_mode, ios->vdd);
2286 else
2287 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 2288
643a81ff
PR		 2289 if (host->ops->platform_send_init_74_clocks)
2290 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2291
2317f56c 2292 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 2293
15ec4461 2294 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 2295
501639bf 2296 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
2297 if (ios->timing == MMC_TIMING_SD_HS ||
2298 ios->timing == MMC_TIMING_MMC_HS ||
2299 ios->timing == MMC_TIMING_MMC_HS400 ||
2300 ios->timing == MMC_TIMING_MMC_HS200 ||
2301 ios->timing == MMC_TIMING_MMC_DDR52 ||
2302 ios->timing == MMC_TIMING_UHS_SDR50 ||
2303 ios->timing == MMC_TIMING_UHS_SDR104 ||
2304 ios->timing == MMC_TIMING_UHS_DDR50 ||
2305 ios->timing == MMC_TIMING_UHS_SDR25)
2306 ctrl |= SDHCI_CTRL_HISPD;
2307 else
2308 ctrl &= ~SDHCI_CTRL_HISPD;
2309 }
cd9277c0 2310
d6d50a15 2311 if (host->version >= SDHCI_SPEC_300) {
49c468fc 2312 u16 clk, ctrl_2;
49c468fc 2313
da91a8f9 2314 if (!host->preset_enabled) {
758535c4 2315 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 2316 /*
2317 * We only need to set Driver Strength if the
2318 * preset value enable is not set.
2319 */
da91a8f9 2320 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 2321 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
2322 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
2323 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 2324 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
2325 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 2326 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
2327 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 2328 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
2329 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
2330 else {
2e4456f0
MV		 2331 pr_warn("%s: invalid driver type, default to driver type B\n",
2332 mmc_hostname(mmc));
43e943a0
PG		 2333 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2334 }
d6d50a15
AN		 2335
2336 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 2337 } else {
2338 /*
2339 * According to SDHC Spec v3.00, if the Preset Value
2340 * Enable in the Host Control 2 register is set, we
2341 * need to reset SD Clock Enable before changing High
2342 * Speed Enable to avoid generating clock gliches.
2343 */
758535c4
AN		 2344
2345 /* Reset SD Clock Enable */
2346 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2347 clk &= ~SDHCI_CLOCK_CARD_EN;
2348 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2349
2350 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2351
2352 /* Re-enable SD Clock */
1771059c 2353 host->ops->set_clock(host, host->clock);
d6d50a15 2354 }
49c468fc 2355
49c468fc
AN		 2356 /* Reset SD Clock Enable */
2357 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2358 clk &= ~SDHCI_CLOCK_CARD_EN;
2359 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2360
96d7b78c 2361 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 2362 host->timing = ios->timing;
49c468fc 2363
52983382
KL		 2364 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2365 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
2366 (ios->timing == MMC_TIMING_UHS_SDR25) ||
2367 (ios->timing == MMC_TIMING_UHS_SDR50) ||
2368 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 2369 (ios->timing == MMC_TIMING_UHS_DDR50) ||
2370 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 2371 u16 preset;
2372
2373 sdhci_enable_preset_value(host, true);
2374 preset = sdhci_get_preset_value(host);
fa091010
MY		 2375 ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
2376 preset);
52983382
KL		 2377 }
2378
49c468fc 2379 /* Re-enable SD Clock */
1771059c 2380 host->ops->set_clock(host, host->clock);
758535c4
AN		 2381 } else
2382 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 2383
b8352260
LD		 2384 /*
2385 * Some (ENE) controllers go apeshit on some ios operation,
2386 * signalling timeout and CRC errors even on CMD0. Resetting
2387 * it on each ios seems to solve the problem.
2388 */
c63705e1 2389 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 2390 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
d129bceb 2391}
6a6d4ceb 2392EXPORT_SYMBOL_GPL(sdhci_set_ios);
d129bceb 2393
ded97e0b 2394static int sdhci_get_cd(struct mmc_host *mmc)
66fd8ad5
AH		 2395{
2396 struct sdhci_host *host = mmc_priv(mmc);
ded97e0b 2397 int gpio_cd = mmc_gpio_get_cd(mmc);
94144a46
KL		 2398
2399 if (host->flags & SDHCI_DEVICE_DEAD)
2400 return 0;
2401
88af5655 2402 /* If nonremovable, assume that the card is always present. */
860951c5 2403 if (!mmc_card_is_removable(host->mmc))
94144a46
KL		 2404 return 1;
2405
88af5655
II		 2406 /*
2407 * Try slot gpio detect, if defined it take precedence
2408 * over build in controller functionality
2409 */
287980e4 2410 if (gpio_cd >= 0)
94144a46
KL		 2411 return !!gpio_cd;
2412
88af5655
II		 2413 /* If polling, assume that the card is always present. */
2414 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2415 return 1;
2416
94144a46
KL		 2417 /* Host native card detect */
2418 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2419}
2420
66fd8ad5 2421static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 2422{
d129bceb 2423 unsigned long flags;
2dfb579c 2424 int is_readonly;
d129bceb 2425
d129bceb
PO		 2426 spin_lock_irqsave(&host->lock, flags);
2427
1e72859e 2428 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 2429 is_readonly = 0;
2430 else if (host->ops->get_ro)
2431 is_readonly = host->ops->get_ro(host);
6d5cd068
TP		 2432 else if (mmc_can_gpio_ro(host->mmc))
2433 is_readonly = mmc_gpio_get_ro(host->mmc);
1e72859e 2434 else
2dfb579c
WS		 2435 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2436 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 2437
2438 spin_unlock_irqrestore(&host->lock, flags);
2439
2dfb579c
WS		 2440 /* This quirk needs to be replaced by a callback-function later */
2441 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2442 !is_readonly : is_readonly;
d129bceb
PO		 2443}
2444
82b0e23a
TI		 2445#define SAMPLE_COUNT 5
2446
ded97e0b 2447static int sdhci_get_ro(struct mmc_host *mmc)
82b0e23a 2448{
ded97e0b 2449 struct sdhci_host *host = mmc_priv(mmc);
82b0e23a
TI		 2450 int i, ro_count;
2451
82b0e23a 2452 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 2453 return sdhci_check_ro(host);
82b0e23a
TI		 2454
2455 ro_count = 0;
2456 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 2457 if (sdhci_check_ro(host)) {
82b0e23a
TI		 2458 if (++ro_count > SAMPLE_COUNT / 2)
2459 return 1;
2460 }
2461 msleep(30);
2462 }
2463 return 0;
2464}
2465
20758b66
AH		 2466static void sdhci_hw_reset(struct mmc_host *mmc)
2467{
2468 struct sdhci_host *host = mmc_priv(mmc);
2469
2470 if (host->ops && host->ops->hw_reset)
2471 host->ops->hw_reset(host);
2472}
2473
66fd8ad5
AH		 2474static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2475{
be138554 2476 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 2477 if (enable)
b537f94c 2478 host->ier |= SDHCI_INT_CARD_INT;
ef104333 2479 else
b537f94c
RK		 2480 host->ier &= ~SDHCI_INT_CARD_INT;
2481
2482 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2483 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333 2484 }
66fd8ad5
AH		 2485}
2486
2f05b6ab 2487void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
66fd8ad5
AH		 2488{
2489 struct sdhci_host *host = mmc_priv(mmc);
2490 unsigned long flags;
f75979b7 2491
923713b3
HG		 2492 if (enable)
2493 pm_runtime_get_noresume(host->mmc->parent);
2494
66fd8ad5
AH		 2495 spin_lock_irqsave(&host->lock, flags);
2496 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 2497 spin_unlock_irqrestore(&host->lock, flags);
923713b3
HG		 2498
2499 if (!enable)
2500 pm_runtime_put_noidle(host->mmc->parent);
f75979b7 2501}
2f05b6ab 2502EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
f75979b7 2503
89f3c365
AH		 2504static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
2505{
2506 struct sdhci_host *host = mmc_priv(mmc);
2507 unsigned long flags;
2508
2509 spin_lock_irqsave(&host->lock, flags);
a84ad324 2510 sdhci_enable_sdio_irq_nolock(host, true);
89f3c365
AH		 2511 spin_unlock_irqrestore(&host->lock, flags);
2512}
2513
c376ea9e
HZ		 2514int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2515 struct mmc_ios *ios)
f2119df6 2516{
ded97e0b 2517 struct sdhci_host *host = mmc_priv(mmc);
20b92a30 2518 u16 ctrl;
6231f3de 2519 int ret;
f2119df6 2520
20b92a30
KL		 2521 /*
2522 * Signal Voltage Switching is only applicable for Host Controllers
2523 * v3.00 and above.
2524 */
2525 if (host->version < SDHCI_SPEC_300)
2526 return 0;
6231f3de 2527
f2119df6 2528 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 2529
21f5998f 2530 switch (ios->signal_voltage) {
20b92a30 2531 case MMC_SIGNAL_VOLTAGE_330:
8cb851a4
AH		 2532 if (!(host->flags & SDHCI_SIGNALING_330))
2533 return -EINVAL;
20b92a30
KL		 2534 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2535 ctrl &= ~SDHCI_CTRL_VDD_180;
2536 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 2537
3a48edc4 2538 if (!IS_ERR(mmc->supply.vqmmc)) {
761daa36 2539 ret = mmc_regulator_set_vqmmc(mmc, ios);
9cbe0fc8 2540 if (ret < 0) {
6606110d
JP		 2541 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2542 mmc_hostname(mmc));
20b92a30
KL		 2543 return -EIO;
2544 }
2545 }
2546 /* Wait for 5ms */
2547 usleep_range(5000, 5500);
f2119df6 2548
20b92a30
KL		 2549 /* 3.3V regulator output should be stable within 5 ms */
2550 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2551 if (!(ctrl & SDHCI_CTRL_VDD_180))
2552 return 0;
6231f3de 2553
b0b19ce6 2554 pr_warn("%s: 3.3V regulator output did not become stable\n",
6606110d 2555 mmc_hostname(mmc));
20b92a30
KL		 2556
2557 return -EAGAIN;
2558 case MMC_SIGNAL_VOLTAGE_180:
8cb851a4
AH		 2559 if (!(host->flags & SDHCI_SIGNALING_180))
2560 return -EINVAL;
3a48edc4 2561 if (!IS_ERR(mmc->supply.vqmmc)) {
761daa36 2562 ret = mmc_regulator_set_vqmmc(mmc, ios);
9cbe0fc8 2563 if (ret < 0) {
6606110d
JP		 2564 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2565 mmc_hostname(mmc));
20b92a30
KL		 2566 return -EIO;
2567 }
2568 }
6231f3de 2569
6231f3de
PR		 2570 /*
2571 * Enable 1.8V Signal Enable in the Host Control2
2572 * register
2573 */
20b92a30
KL		 2574 ctrl |= SDHCI_CTRL_VDD_180;
2575 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 2576
9d967a61
VY		 2577 /* Some controller need to do more when switching */
2578 if (host->ops->voltage_switch)
2579 host->ops->voltage_switch(host);
2580
20b92a30
KL		 2581 /* 1.8V regulator output should be stable within 5 ms */
2582 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2583 if (ctrl & SDHCI_CTRL_VDD_180)
2584 return 0;
f2119df6 2585
b0b19ce6 2586 pr_warn("%s: 1.8V regulator output did not become stable\n",
6606110d 2587 mmc_hostname(mmc));
f2119df6 2588
20b92a30
KL		 2589 return -EAGAIN;
2590 case MMC_SIGNAL_VOLTAGE_120:
8cb851a4
AH		 2591 if (!(host->flags & SDHCI_SIGNALING_120))
2592 return -EINVAL;
3a48edc4 2593 if (!IS_ERR(mmc->supply.vqmmc)) {
761daa36 2594 ret = mmc_regulator_set_vqmmc(mmc, ios);
9cbe0fc8 2595 if (ret < 0) {
6606110d
JP		 2596 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2597 mmc_hostname(mmc));
20b92a30 2598 return -EIO;
f2119df6
AN		 2599 }
2600 }
6231f3de 2601 return 0;
20b92a30 2602 default:
f2119df6
AN		 2603 /* No signal voltage switch required */
2604 return 0;
20b92a30 2605 }
f2119df6 2606}
c376ea9e 2607EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
f2119df6 2608
20b92a30
KL		 2609static int sdhci_card_busy(struct mmc_host *mmc)
2610{
2611 struct sdhci_host *host = mmc_priv(mmc);
2612 u32 present_state;
2613
e613cc47 2614 /* Check whether DAT[0] is 0 */
20b92a30 2615 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
20b92a30 2616
e613cc47 2617 return !(present_state & SDHCI_DATA_0_LVL_MASK);
20b92a30
KL		 2618}
2619
b5540ce1
AH		 2620static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2621{
2622 struct sdhci_host *host = mmc_priv(mmc);
2623 unsigned long flags;
2624
2625 spin_lock_irqsave(&host->lock, flags);
2626 host->flags |= SDHCI_HS400_TUNING;
2627 spin_unlock_irqrestore(&host->lock, flags);
2628
2629 return 0;
2630}
2631
6663c419 2632void sdhci_start_tuning(struct sdhci_host *host)
da4bc4f2
AH		 2633{
2634 u16 ctrl;
2635
2636 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2637 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2638 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2639 ctrl |= SDHCI_CTRL_TUNED_CLK;
2640 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2641
2642 /*
2643 * As per the Host Controller spec v3.00, tuning command
2644 * generates Buffer Read Ready interrupt, so enable that.
2645 *
2646 * Note: The spec clearly says that when tuning sequence
2647 * is being performed, the controller does not generate
2648 * interrupts other than Buffer Read Ready interrupt. But
2649 * to make sure we don't hit a controller bug, we _only_
2650 * enable Buffer Read Ready interrupt here.
2651 */
2652 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2653 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2654}
6663c419 2655EXPORT_SYMBOL_GPL(sdhci_start_tuning);
da4bc4f2 2656
6663c419 2657void sdhci_end_tuning(struct sdhci_host *host)
da4bc4f2
AH		 2658{
2659 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2660 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2661}
6663c419 2662EXPORT_SYMBOL_GPL(sdhci_end_tuning);
da4bc4f2 2663
6663c419 2664void sdhci_reset_tuning(struct sdhci_host *host)
da4bc4f2
AH		 2665{
2666 u16 ctrl;
2667
2668 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2669 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2670 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2671 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2672}
6663c419 2673EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
da4bc4f2 2674
7353788c 2675void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
da4bc4f2
AH		 2676{
2677 sdhci_reset_tuning(host);
2678
2679 sdhci_do_reset(host, SDHCI_RESET_CMD);
2680 sdhci_do_reset(host, SDHCI_RESET_DATA);
2681
2682 sdhci_end_tuning(host);
2683
da4bc4f2 2684 mmc_abort_tuning(host->mmc, opcode);
da4bc4f2 2685}
7353788c 2686EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
da4bc4f2
AH		 2687
2688/*
2689 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2690 * tuning command does not have a data payload (or rather the hardware does it
2691 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2692 * interrupt setup is different to other commands and there is no timeout
2693 * interrupt so special handling is needed.
2694 */
6663c419 2695void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
da4bc4f2
AH		 2696{
2697 struct mmc_host *mmc = host->mmc;
c7836d15
MY		 2698 struct mmc_command cmd = {};
2699 struct mmc_request mrq = {};
2a85ef25 2700 unsigned long flags;
c846a00f 2701 u32 b = host->sdma_boundary;
2a85ef25
AH		 2702
2703 spin_lock_irqsave(&host->lock, flags);
da4bc4f2
AH		 2704
2705 cmd.opcode = opcode;
2706 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2707 cmd.mrq = &mrq;
2708
2709 mrq.cmd = &cmd;
2710 /*
2711 * In response to CMD19, the card sends 64 bytes of tuning
2712 * block to the Host Controller. So we set the block size
2713 * to 64 here.
2714 */
85336109
AH		 2715 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2716 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
c846a00f 2717 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
85336109 2718 else
c846a00f 2719 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
da4bc4f2
AH		 2720
2721 /*
2722 * The tuning block is sent by the card to the host controller.
2723 * So we set the TRNS_READ bit in the Transfer Mode register.
2724 * This also takes care of setting DMA Enable and Multi Block
2725 * Select in the same register to 0.
2726 */
2727 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2728
845c939e
AH		 2729 if (!sdhci_send_command_retry(host, &cmd, flags)) {
2730 spin_unlock_irqrestore(&host->lock, flags);
2731 host->tuning_done = 0;
2732 return;
2733 }
da4bc4f2
AH		 2734
2735 host->cmd = NULL;
2736
2737 sdhci_del_timer(host, &mrq);
2738
2739 host->tuning_done = 0;
2740
2741 spin_unlock_irqrestore(&host->lock, flags);
2742
2743 /* Wait for Buffer Read Ready interrupt */
2744 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2745 msecs_to_jiffies(50));
2746
da4bc4f2 2747}
6663c419 2748EXPORT_SYMBOL_GPL(sdhci_send_tuning);
da4bc4f2 2749
7d8bb1f4 2750static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
6b11e70b
AH		 2751{
2752 int i;
2753
2754 /*
2755 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
1d8cd065 2756 * of loops reaches tuning loop count.
6b11e70b 2757 */
1d8cd065 2758 for (i = 0; i < host->tuning_loop_count; i++) {
6b11e70b
AH		 2759 u16 ctrl;
2760
2a85ef25 2761 sdhci_send_tuning(host, opcode);
6b11e70b
AH		 2762
2763 if (!host->tuning_done) {
811ba676
FA		 2764 pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2765 mmc_hostname(host->mmc));
2a85ef25 2766 sdhci_abort_tuning(host, opcode);
7d8bb1f4 2767 return -ETIMEDOUT;
6b11e70b
AH		 2768 }
2769
2b06e159
BC		 2770 /* Spec does not require a delay between tuning cycles */
2771 if (host->tuning_delay > 0)
2772 mdelay(host->tuning_delay);
2773
6b11e70b
AH		 2774 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2775 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2776 if (ctrl & SDHCI_CTRL_TUNED_CLK)
7d8bb1f4 2777 return 0; /* Success! */
6b11e70b
AH		 2778 break;
2779 }
2780
6b11e70b
AH		 2781 }
2782
2783 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2784 mmc_hostname(host->mmc));
2785 sdhci_reset_tuning(host);
7d8bb1f4 2786 return -EAGAIN;
6b11e70b
AH		 2787}
2788
85a882c2 2789int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 2790{
4b6f37d3 2791 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 2792 int err = 0;
38e40bf5 2793 unsigned int tuning_count = 0;
b5540ce1 2794 bool hs400_tuning;
b513ea25 2795
b5540ce1 2796 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
b5540ce1 2797
38e40bf5
AH		 2798 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2799 tuning_count = host->tuning_count;
2800
b513ea25 2801 /*
9faac7b9
WY		 2802 * The Host Controller needs tuning in case of SDR104 and DDR50
2803 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2804 * the Capabilities register.
069c9f14
G		 2805 * If the Host Controller supports the HS200 mode then the
2806 * tuning function has to be executed.
b513ea25 2807 */
4b6f37d3 2808 switch (host->timing) {
b5540ce1 2809 /* HS400 tuning is done in HS200 mode */
e9fb05d5 2810 case MMC_TIMING_MMC_HS400:
b5540ce1 2811 err = -EINVAL;
2a85ef25 2812 goto out;
b5540ce1 2813
4b6f37d3 2814 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 2815 /*
2816 * Periodic re-tuning for HS400 is not expected to be needed, so
2817 * disable it here.
2818 */
2819 if (hs400_tuning)
2820 tuning_count = 0;
2821 break;
2822
4b6f37d3 2823 case MMC_TIMING_UHS_SDR104:
9faac7b9 2824 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 2825 break;
2826
2827 case MMC_TIMING_UHS_SDR50:
4228b213 2828 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
4b6f37d3 2829 break;
df561f66 2830 fallthrough;
4b6f37d3
RK		 2831
2832 default:
2a85ef25 2833 goto out;
b513ea25
AN		 2834 }
2835
45251812 2836 if (host->ops->platform_execute_tuning) {
8a8fa879 2837 err = host->ops->platform_execute_tuning(host, opcode);
2a85ef25 2838 goto out;
45251812
DA		 2839 }
2840
6b11e70b 2841 host->mmc->retune_period = tuning_count;
b513ea25 2842
83b600b8
AH		 2843 if (host->tuning_delay < 0)
2844 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2845
6b11e70b 2846 sdhci_start_tuning(host);
da4bc4f2 2847
7d8bb1f4 2848 host->tuning_err = __sdhci_execute_tuning(host, opcode);
cf2b5eea 2849
da4bc4f2 2850 sdhci_end_tuning(host);
2a85ef25 2851out:
8a8fa879 2852 host->flags &= ~SDHCI_HS400_TUNING;
6b11e70b 2853
b513ea25
AN		 2854 return err;
2855}
85a882c2 2856EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
b513ea25 2857
52983382 2858static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2859{
4d55c5a1
AN		 2860 /* Host Controller v3.00 defines preset value registers */
2861 if (host->version < SDHCI_SPEC_300)
2862 return;
2863
4d55c5a1
AN		 2864 /*
2865 * We only enable or disable Preset Value if they are not already
2866 * enabled or disabled respectively. Otherwise, we bail out.
2867 */
da91a8f9
RK		 2868 if (host->preset_enabled != enable) {
2869 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2870
2871 if (enable)
2872 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2873 else
2874 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2875
4d55c5a1 2876 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2877
2878 if (enable)
2879 host->flags |= SDHCI_PV_ENABLED;
2880 else
2881 host->flags &= ~SDHCI_PV_ENABLED;
2882
2883 host->preset_enabled = enable;
4d55c5a1 2884 }
66fd8ad5
AH		 2885}
2886
348487cb
HC		 2887static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2888 int err)
2889{
2890 struct sdhci_host *host = mmc_priv(mmc);
2891 struct mmc_data *data = mrq->data;
2892
f48f039c 2893 if (data->host_cookie != COOKIE_UNMAPPED)
771a3dc2 2894 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
feeef096 2895 mmc_get_dma_dir(data));
771a3dc2
RK		 2896
2897 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2898}
2899
d3c6aac3 2900static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
348487cb
HC		 2901{
2902 struct sdhci_host *host = mmc_priv(mmc);
2903
d31911b9 2904 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb 2905
bd9b9027
LW		 2906 /*
2907 * No pre-mapping in the pre hook if we're using the bounce buffer,
2908 * for that we would need two bounce buffers since one buffer is
2909 * in flight when this is getting called.
2910 */
2911 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
94538e51 2912 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
348487cb
HC		 2913}
2914
5d0d11c5
AH		 2915static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2916{
2917 if (host->data_cmd) {
2918 host->data_cmd->error = err;
2919 sdhci_finish_mrq(host, host->data_cmd->mrq);
2920 }
2921
2922 if (host->cmd) {
2923 host->cmd->error = err;
2924 sdhci_finish_mrq(host, host->cmd->mrq);
2925 }
2926}
2927
71e69211 2928static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2929{
71e69211 2930 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2931 unsigned long flags;
2836766a 2932 int present;
d129bceb 2933
722e1280
CD		 2934 /* First check if client has provided their own card event */
2935 if (host->ops->card_event)
2936 host->ops->card_event(host);
2937
d3940f27 2938 present = mmc->ops->get_cd(mmc);
2836766a 2939
d129bceb
PO		 2940 spin_lock_irqsave(&host->lock, flags);
2941
5d0d11c5
AH		 2942 /* Check sdhci_has_requests() first in case we are runtime suspended */
2943 if (sdhci_has_requests(host) && !present) {
a3c76eb9 2944 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2945 mmc_hostname(host->mmc));
a3c76eb9 2946 pr_err("%s: Resetting controller.\n",
66fd8ad5 2947 mmc_hostname(host->mmc));
d129bceb 2948
03231f9b
RK		 2949 sdhci_do_reset(host, SDHCI_RESET_CMD);
2950 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2951
5d0d11c5 2952 sdhci_error_out_mrqs(host, -ENOMEDIUM);
d129bceb
PO		 2953 }
2954
2955 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2956}
2957
2958static const struct mmc_host_ops sdhci_ops = {
2959 .request = sdhci_request,
348487cb
HC		 2960 .post_req = sdhci_post_req,
2961 .pre_req = sdhci_pre_req,
71e69211 2962 .set_ios = sdhci_set_ios,
94144a46 2963 .get_cd = sdhci_get_cd,
71e69211
GL		 2964 .get_ro = sdhci_get_ro,
2965 .hw_reset = sdhci_hw_reset,
2966 .enable_sdio_irq = sdhci_enable_sdio_irq,
89f3c365 2967 .ack_sdio_irq = sdhci_ack_sdio_irq,
71e69211 2968 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2969 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2970 .execute_tuning = sdhci_execute_tuning,
71e69211 2971 .card_event = sdhci_card_event,
20b92a30 2972 .card_busy = sdhci_card_busy,
71e69211
GL		 2973};
2974
2975/*****************************************************************************\
2976 * *
c07a48c2 2977 * Request done *
71e69211
GL		 2978 * *
2979\*****************************************************************************/
2980
4e9f8fe5 2981static bool sdhci_request_done(struct sdhci_host *host)
d129bceb 2982{
d129bceb
PO		 2983 unsigned long flags;
2984 struct mmc_request *mrq;
4e9f8fe5 2985 int i;
d129bceb 2986
66fd8ad5
AH		 2987 spin_lock_irqsave(&host->lock, flags);
2988
4e9f8fe5
AH		 2989 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2990 mrq = host->mrqs_done[i];
6ebebeab 2991 if (mrq)
4e9f8fe5 2992 break;
66fd8ad5 2993 }
d129bceb 2994
4e9f8fe5
AH		 2995 if (!mrq) {
2996 spin_unlock_irqrestore(&host->lock, flags);
2997 return true;
2998 }
d129bceb 2999
9fc0e1a7
P		 3000 /*
3001 * The controller needs a reset of internal state machines
3002 * upon error conditions.
3003 */
3004 if (sdhci_needs_reset(host, mrq)) {
3005 /*
3006 * Do not finish until command and data lines are available for
3007 * reset. Note there can only be one other mrq, so it cannot
3008 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
3009 * would both be null.
3010 */
3011 if (host->cmd || host->data_cmd) {
3012 spin_unlock_irqrestore(&host->lock, flags);
3013 return true;
3014 }
3015
3016 /* Some controllers need this kick or reset won't work here */
3017 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3018 /* This is to force an update */
3019 host->ops->set_clock(host, host->clock);
3020
3021 /*
3022 * Spec says we should do both at the same time, but Ricoh
3023 * controllers do not like that.
3024 */
3025 sdhci_do_reset(host, SDHCI_RESET_CMD);
3026 sdhci_do_reset(host, SDHCI_RESET_DATA);
3027
3028 host->pending_reset = false;
3029 }
3030
054cedff
RK		 3031 /*
3032 * Always unmap the data buffers if they were mapped by
3033 * sdhci_prepare_data() whenever we finish with a request.
3034 * This avoids leaking DMA mappings on error.
3035 */
3036 if (host->flags & SDHCI_REQ_USE_DMA) {
3037 struct mmc_data *data = mrq->data;
3038
18e762e3
CZ		 3039 if (host->use_external_dma && data &&
3040 (mrq->cmd->error || data->error)) {
3041 struct dma_chan *chan = sdhci_external_dma_channel(host, data);
3042
3043 host->mrqs_done[i] = NULL;
3044 spin_unlock_irqrestore(&host->lock, flags);
3045 dmaengine_terminate_sync(chan);
3046 spin_lock_irqsave(&host->lock, flags);
3047 sdhci_set_mrq_done(host, mrq);
3048 }
3049
054cedff 3050 if (data && data->host_cookie == COOKIE_MAPPED) {
bd9b9027
LW		 3051 if (host->bounce_buffer) {
3052 /*
3053 * On reads, copy the bounced data into the
3054 * sglist
3055 */
3056 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
3057 unsigned int length = data->bytes_xfered;
3058
3059 if (length > host->bounce_buffer_size) {
3060 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
3061 mmc_hostname(host->mmc),
3062 host->bounce_buffer_size,
3063 data->bytes_xfered);
3064 /* Cap it down and continue */
3065 length = host->bounce_buffer_size;
3066 }
3067 dma_sync_single_for_cpu(
3068 host->mmc->parent,
3069 host->bounce_addr,
3070 host->bounce_buffer_size,
3071 DMA_FROM_DEVICE);
3072 sg_copy_from_buffer(data->sg,
3073 data->sg_len,
3074 host->bounce_buffer,
3075 length);
3076 } else {
3077 /* No copying, just switch ownership */
3078 dma_sync_single_for_cpu(
3079 host->mmc->parent,
3080 host->bounce_addr,
3081 host->bounce_buffer_size,
3082 mmc_get_dma_dir(data));
3083 }
3084 } else {
3085 /* Unmap the raw data */
3086 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
3087 data->sg_len,
3088 mmc_get_dma_dir(data));
3089 }
054cedff
RK		 3090 data->host_cookie = COOKIE_UNMAPPED;
3091 }
3092 }
3093
6ebebeab
AH		 3094 host->mrqs_done[i] = NULL;
3095
d129bceb
PO		 3096 spin_unlock_irqrestore(&host->lock, flags);
3097
1774b002
BW		 3098 if (host->ops->request_done)
3099 host->ops->request_done(host, mrq);
3100 else
3101 mmc_request_done(host->mmc, mrq);
4e9f8fe5
AH		 3102
3103 return false;
3104}
3105
c07a48c2 3106static void sdhci_complete_work(struct work_struct *work)
4e9f8fe5 3107{
c07a48c2
AH		 3108 struct sdhci_host *host = container_of(work, struct sdhci_host,
3109 complete_work);
4e9f8fe5
AH		 3110
3111 while (!sdhci_request_done(host))
3112 ;
d129bceb
PO		 3113}
3114
2ee4f620 3115static void sdhci_timeout_timer(struct timer_list *t)
d129bceb
PO		 3116{
3117 struct sdhci_host *host;
3118 unsigned long flags;
3119
2ee4f620 3120 host = from_timer(host, t, timer);
d129bceb
PO		 3121
3122 spin_lock_irqsave(&host->lock, flags);
3123
d7422fb4
AH		 3124 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
3125 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
3126 mmc_hostname(host->mmc));
3127 sdhci_dumpregs(host);
3128
3129 host->cmd->error = -ETIMEDOUT;
3130 sdhci_finish_mrq(host, host->cmd->mrq);
3131 }
3132
d7422fb4
AH		 3133 spin_unlock_irqrestore(&host->lock, flags);
3134}
3135
2ee4f620 3136static void sdhci_timeout_data_timer(struct timer_list *t)
d7422fb4
AH		 3137{
3138 struct sdhci_host *host;
3139 unsigned long flags;
3140
2ee4f620 3141 host = from_timer(host, t, data_timer);
d7422fb4
AH		 3142
3143 spin_lock_irqsave(&host->lock, flags);
3144
3145 if (host->data || host->data_cmd ||
3146 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2e4456f0
MV		 3147 pr_err("%s: Timeout waiting for hardware interrupt.\n",
3148 mmc_hostname(host->mmc));
d129bceb
PO		 3149 sdhci_dumpregs(host);
3150
3151 if (host->data) {
17b0429d 3152 host->data->error = -ETIMEDOUT;
845c939e 3153 __sdhci_finish_data(host, true);
c07a48c2 3154 queue_work(host->complete_wq, &host->complete_work);
d7422fb4
AH		 3155 } else if (host->data_cmd) {
3156 host->data_cmd->error = -ETIMEDOUT;
3157 sdhci_finish_mrq(host, host->data_cmd->mrq);
d129bceb 3158 } else {
d7422fb4
AH		 3159 host->cmd->error = -ETIMEDOUT;
3160 sdhci_finish_mrq(host, host->cmd->mrq);
d129bceb
PO		 3161 }
3162 }
3163
3164 spin_unlock_irqrestore(&host->lock, flags);
3165}
3166
3167/*****************************************************************************\
3168 * *
3169 * Interrupt handling *
3170 * *
3171\*****************************************************************************/
3172
4bf78099 3173static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
d129bceb 3174{
af849c86
AH		 3175 /* Handle auto-CMD12 error */
3176 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
3177 struct mmc_request *mrq = host->data_cmd->mrq;
3178 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3179 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3180 SDHCI_INT_DATA_TIMEOUT :
3181 SDHCI_INT_DATA_CRC;
3182
3183 /* Treat auto-CMD12 error the same as data error */
3184 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
3185 *intmask_p |= data_err_bit;
3186 return;
3187 }
3188 }
3189
d129bceb 3190 if (!host->cmd) {
ed1563de
AH		 3191 /*
3192 * SDHCI recovers from errors by resetting the cmd and data
3193 * circuits. Until that is done, there very well might be more
3194 * interrupts, so ignore them in that case.
3195 */
3196 if (host->pending_reset)
3197 return;
2e4456f0
MV		 3198 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
3199 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 3200 sdhci_dumpregs(host);
3201 return;
3202 }
3203
ec014cba
RK		 3204 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
3205 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
3206 if (intmask & SDHCI_INT_TIMEOUT)
3207 host->cmd->error = -ETIMEDOUT;
3208 else
3209 host->cmd->error = -EILSEQ;
43b58b36 3210
4bf78099 3211 /* Treat data command CRC error the same as data CRC error */
71fcbda0
RK		 3212 if (host->cmd->data &&
3213 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
3214 SDHCI_INT_CRC) {
3215 host->cmd = NULL;
4bf78099 3216 *intmask_p |= SDHCI_INT_DATA_CRC;
71fcbda0
RK		 3217 return;
3218 }
3219
19d2f695 3220 __sdhci_finish_mrq(host, host->cmd->mrq);
e809517f
PO		 3221 return;
3222 }
3223
af849c86
AH		 3224 /* Handle auto-CMD23 error */
3225 if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
3226 struct mmc_request *mrq = host->cmd->mrq;
3227 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3228 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3229 -ETIMEDOUT :
3230 -EILSEQ;
3231
3232 if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
3233 mrq->sbc->error = err;
19d2f695 3234 __sdhci_finish_mrq(host, mrq);
af849c86
AH		 3235 return;
3236 }
3237 }
3238
e809517f 3239 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 3240 sdhci_finish_command(host);
d129bceb
PO		 3241}
3242
08621b18 3243static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0 3244{
1c3d5f6d 3245 void *desc = host->adma_table;
d1c536e3 3246 dma_addr_t dma = host->adma_addr;
6882a8c0
BD		 3247
3248 sdhci_dumpregs(host);
3249
3250 while (true) {
e57a5f61
AH		 3251 struct sdhci_adma2_64_desc *dma_desc = desc;
3252
3253 if (host->flags & SDHCI_USE_64_BIT_DMA)
d1c536e3
RK		 3254 SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
3255 (unsigned long long)dma,
3256 le32_to_cpu(dma_desc->addr_hi),
e57a5f61
AH		 3257 le32_to_cpu(dma_desc->addr_lo),
3258 le16_to_cpu(dma_desc->len),
3259 le16_to_cpu(dma_desc->cmd));
3260 else
d1c536e3
RK		 3261 SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
3262 (unsigned long long)dma,
3263 le32_to_cpu(dma_desc->addr_lo),
e57a5f61
AH		 3264 le16_to_cpu(dma_desc->len),
3265 le16_to_cpu(dma_desc->cmd));
6882a8c0 3266
76fe379a 3267 desc += host->desc_sz;
d1c536e3 3268 dma += host->desc_sz;
6882a8c0 3269
0545230f 3270 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 3271 break;
3272 }
3273}
6882a8c0 3274
d129bceb
PO		 3275static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3276{
069c9f14 3277 u32 command;
d129bceb 3278
b513ea25
AN		 3279 /* CMD19 generates _only_ Buffer Read Ready interrupt */
3280 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 3281 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
3282 if (command == MMC_SEND_TUNING_BLOCK ||
3283 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 3284 host->tuning_done = 1;
3285 wake_up(&host->buf_ready_int);
3286 return;
3287 }
3288 }
3289
d129bceb 3290 if (!host->data) {
7c89a3d9
AH		 3291 struct mmc_command *data_cmd = host->data_cmd;
3292
d129bceb 3293 /*
e809517f
PO		 3294 * The "data complete" interrupt is also used to
3295 * indicate that a busy state has ended. See comment
3296 * above in sdhci_cmd_irq().
d129bceb 3297 */
7c89a3d9 3298 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8 3299 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
69b962a6 3300 host->data_cmd = NULL;
7c89a3d9 3301 data_cmd->error = -ETIMEDOUT;
19d2f695 3302 __sdhci_finish_mrq(host, data_cmd->mrq);
c5abd5e8
MC		 3303 return;
3304 }
e809517f 3305 if (intmask & SDHCI_INT_DATA_END) {
69b962a6 3306 host->data_cmd = NULL;
e99783a4
CM		 3307 /*
3308 * Some cards handle busy-end interrupt
3309 * before the command completed, so make
3310 * sure we do things in the proper order.
3311 */
ea968023
AH		 3312 if (host->cmd == data_cmd)
3313 return;
3314
19d2f695 3315 __sdhci_finish_mrq(host, data_cmd->mrq);
e809517f
PO		 3316 return;
3317 }
3318 }
d129bceb 3319
ed1563de
AH		 3320 /*
3321 * SDHCI recovers from errors by resetting the cmd and data
3322 * circuits. Until that is done, there very well might be more
3323 * interrupts, so ignore them in that case.
3324 */
3325 if (host->pending_reset)
3326 return;
3327
2e4456f0
MV		 3328 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
3329 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 3330 sdhci_dumpregs(host);
3331
3332 return;
3333 }
3334
3335 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 3336 host->data->error = -ETIMEDOUT;
22113efd
AL		 3337 else if (intmask & SDHCI_INT_DATA_END_BIT)
3338 host->data->error = -EILSEQ;
3339 else if ((intmask & SDHCI_INT_DATA_CRC) &&
3340 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
3341 != MMC_BUS_TEST_R)
17b0429d 3342 host->data->error = -EILSEQ;
6882a8c0 3343 else if (intmask & SDHCI_INT_ADMA_ERROR) {
d1c536e3
RK		 3344 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
3345 intmask);
08621b18 3346 sdhci_adma_show_error(host);
2134a922 3347 host->data->error = -EIO;
a4071fbb
HZ		 3348 if (host->ops->adma_workaround)
3349 host->ops->adma_workaround(host, intmask);
6882a8c0 3350 }
d129bceb 3351
17b0429d 3352 if (host->data->error)
d129bceb
PO		 3353 sdhci_finish_data(host);
3354 else {
a406f5a3 3355 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 3356 sdhci_transfer_pio(host);
3357
6ba736a1
PO		 3358 /*
3359 * We currently don't do anything fancy with DMA
3360 * boundaries, but as we can't disable the feature
3361 * we need to at least restart the transfer.
f6a03cbf
MV		 3362 *
3363 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3364 * should return a valid address to continue from, but as
3365 * some controllers are faulty, don't trust them.
6ba736a1 3366 */
f6a03cbf 3367 if (intmask & SDHCI_INT_DMA_END) {
917a0c52 3368 dma_addr_t dmastart, dmanow;
bd9b9027
LW		 3369
3370 dmastart = sdhci_sdma_address(host);
f6a03cbf
MV		 3371 dmanow = dmastart + host->data->bytes_xfered;
3372 /*
3373 * Force update to the next DMA block boundary.
3374 */
3375 dmanow = (dmanow &
917a0c52 3376 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
f6a03cbf
MV		 3377 SDHCI_DEFAULT_BOUNDARY_SIZE;
3378 host->data->bytes_xfered = dmanow - dmastart;
917a0c52
CZ		 3379 DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
3380 &dmastart, host->data->bytes_xfered, &dmanow);
3381 sdhci_set_sdma_addr(host, dmanow);
f6a03cbf 3382 }
6ba736a1 3383
e538fbe8 3384 if (intmask & SDHCI_INT_DATA_END) {
7c89a3d9 3385 if (host->cmd == host->data_cmd) {
e538fbe8
PO		 3386 /*
3387 * Data managed to finish before the
3388 * command completed. Make sure we do
3389 * things in the proper order.
3390 */
3391 host->data_early = 1;
3392 } else {
3393 sdhci_finish_data(host);
3394 }
3395 }
d129bceb
PO		 3396 }
3397}
3398
19d2f695
AH		 3399static inline bool sdhci_defer_done(struct sdhci_host *host,
3400 struct mmc_request *mrq)
3401{
3402 struct mmc_data *data = mrq->data;
3403
4730831c 3404 return host->pending_reset || host->always_defer_done ||
19d2f695
AH		 3405 ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3406 data->host_cookie == COOKIE_MAPPED);
3407}
3408
7d12e780 3409static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 3410{
19d2f695 3411 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
781e989c 3412 irqreturn_t result = IRQ_NONE;
66fd8ad5 3413 struct sdhci_host *host = dev_id;
41005003 3414 u32 intmask, mask, unexpected = 0;
781e989c 3415 int max_loops = 16;
19d2f695 3416 int i;
d129bceb
PO		 3417
3418 spin_lock(&host->lock);
3419
af5d2b7b 3420 if (host->runtime_suspended) {
66fd8ad5 3421 spin_unlock(&host->lock);
655bca76 3422 return IRQ_NONE;
66fd8ad5
AH		 3423 }
3424
4e4141a5 3425 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 3426 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 3427 result = IRQ_NONE;
3428 goto out;
3429 }
3430
41005003 3431 do {
f12e39db
AH		 3432 DBG("IRQ status 0x%08x\n", intmask);
3433
3434 if (host->ops->irq) {
3435 intmask = host->ops->irq(host, intmask);
3436 if (!intmask)
3437 goto cont;
3438 }
3439
41005003
RK		 3440 /* Clear selected interrupts. */
3441 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3442 SDHCI_INT_BUS_POWER);
3443 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 3444
41005003
RK		 3445 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3446 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3447 SDHCI_CARD_PRESENT;
d129bceb 3448
41005003
RK		 3449 /*
3450 * There is a observation on i.mx esdhc. INSERT
3451 * bit will be immediately set again when it gets
3452 * cleared, if a card is inserted. We have to mask
3453 * the irq to prevent interrupt storm which will
3454 * freeze the system. And the REMOVE gets the
3455 * same situation.
3456 *
3457 * More testing are needed here to ensure it works
3458 * for other platforms though.
3459 */
b537f94c
RK		 3460 host->ier &= ~(SDHCI_INT_CARD_INSERT |
3461 SDHCI_INT_CARD_REMOVE);
3462 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3463 SDHCI_INT_CARD_INSERT;
3464 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3465 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 3466
3467 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3468 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 3469
3470 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3471 SDHCI_INT_CARD_REMOVE);
3472 result = IRQ_WAKE_THREAD;
41005003 3473 }
d129bceb 3474
41005003 3475 if (intmask & SDHCI_INT_CMD_MASK)
4bf78099 3476 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
964f9ce2 3477
41005003
RK		 3478 if (intmask & SDHCI_INT_DATA_MASK)
3479 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 3480
41005003
RK		 3481 if (intmask & SDHCI_INT_BUS_POWER)
3482 pr_err("%s: Card is consuming too much power!\n",
3483 mmc_hostname(host->mmc));
3192a28f 3484
f37b20eb
DA		 3485 if (intmask & SDHCI_INT_RETUNE)
3486 mmc_retune_needed(host->mmc);
3487
161e6d44
GKB		 3488 if ((intmask & SDHCI_INT_CARD_INT) &&
3489 (host->ier & SDHCI_INT_CARD_INT)) {
781e989c 3490 sdhci_enable_sdio_irq_nolock(host, false);
89f3c365 3491 sdio_signal_irq(host->mmc);
781e989c 3492 }
f75979b7 3493
41005003
RK		 3494 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3495 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3496 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
f37b20eb 3497 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
f75979b7 3498
41005003
RK		 3499 if (intmask) {
3500 unexpected |= intmask;
3501 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3502 }
f12e39db 3503cont:
781e989c
RK		 3504 if (result == IRQ_NONE)
3505 result = IRQ_HANDLED;
d129bceb 3506
41005003 3507 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 3508 } while (intmask && --max_loops);
19d2f695
AH		 3509
3510 /* Determine if mrqs can be completed immediately */
3511 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3512 struct mmc_request *mrq = host->mrqs_done[i];
3513
3514 if (!mrq)
3515 continue;
3516
3517 if (sdhci_defer_done(host, mrq)) {
c07a48c2 3518 result = IRQ_WAKE_THREAD;
19d2f695
AH		 3519 } else {
3520 mrqs_done[i] = mrq;
3521 host->mrqs_done[i] = NULL;
3522 }
3523 }
d129bceb 3524out:
845c939e
AH		 3525 if (host->deferred_cmd)
3526 result = IRQ_WAKE_THREAD;
3527
d129bceb
PO		 3528 spin_unlock(&host->lock);
3529
19d2f695
AH		 3530 /* Process mrqs ready for immediate completion */
3531 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1774b002
BW		 3532 if (!mrqs_done[i])
3533 continue;
3534
3535 if (host->ops->request_done)
3536 host->ops->request_done(host, mrqs_done[i]);
3537 else
19d2f695
AH		 3538 mmc_request_done(host->mmc, mrqs_done[i]);
3539 }
3540
6379b237
AS		 3541 if (unexpected) {
3542 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3543 mmc_hostname(host->mmc), unexpected);
3544 sdhci_dumpregs(host);
3545 }
f75979b7 3546
d129bceb
PO		 3547 return result;
3548}
3549
781e989c
RK		 3550static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
3551{
3552 struct sdhci_host *host = dev_id;
845c939e 3553 struct mmc_command *cmd;
781e989c
RK		 3554 unsigned long flags;
3555 u32 isr;
3556
c07a48c2
AH		 3557 while (!sdhci_request_done(host))
3558 ;
3559
781e989c 3560 spin_lock_irqsave(&host->lock, flags);
845c939e 3561
781e989c
RK		 3562 isr = host->thread_isr;
3563 host->thread_isr = 0;
845c939e
AH		 3564
3565 cmd = host->deferred_cmd;
3566 if (cmd && !sdhci_send_command_retry(host, cmd, flags))
3567 sdhci_finish_mrq(host, cmd->mrq);
3568
781e989c
RK		 3569 spin_unlock_irqrestore(&host->lock, flags);
3570
3560db8e 3571 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d3940f27
AH		 3572 struct mmc_host *mmc = host->mmc;
3573
3574 mmc->ops->card_event(mmc);
3575 mmc_detect_change(mmc, msecs_to_jiffies(200));
3560db8e
RK		 3576 }
3577
c07a48c2 3578 return IRQ_HANDLED;
781e989c
RK		 3579}
3580
d129bceb
PO		 3581/*****************************************************************************\
3582 * *
3583 * Suspend/resume *
3584 * *
3585\*****************************************************************************/
3586
3587#ifdef CONFIG_PM
9c316b38
AH		 3588
3589static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3590{
3591 return mmc_card_is_removable(host->mmc) &&
3592 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3593 !mmc_can_gpio_cd(host->mmc);
3594}
3595
84d62605
LD		 3596/*
3597 * To enable wakeup events, the corresponding events have to be enabled in
3598 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3599 * Table' in the SD Host Controller Standard Specification.
3600 * It is useless to restore SDHCI_INT_ENABLE state in
3601 * sdhci_disable_irq_wakeups() since it will be set by
3602 * sdhci_enable_card_detection() or sdhci_init().
3603 */
58e79b60 3604static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
ad080d79 3605{
81b14543
AH		 3606 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3607 SDHCI_WAKE_ON_INT;
3608 u32 irq_val = 0;
3609 u8 wake_val = 0;
ad080d79 3610 u8 val;
ad080d79 3611
9c316b38 3612 if (sdhci_cd_irq_can_wakeup(host)) {
81b14543
AH		 3613 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3614 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
84d62605 3615 }
81b14543 3616
d5d568fa
AH		 3617 if (mmc_card_wake_sdio_irq(host->mmc)) {
3618 wake_val |= SDHCI_WAKE_ON_INT;
3619 irq_val |= SDHCI_INT_CARD_INT;
3620 }
3621
3622 if (!irq_val)
3623 return false;
81b14543
AH		 3624
3625 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3626 val &= ~mask;
3627 val |= wake_val;
ad080d79 3628 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
81b14543 3629
84d62605 3630 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
58e79b60
AH		 3631
3632 host->irq_wake_enabled = !enable_irq_wake(host->irq);
3633
3634 return host->irq_wake_enabled;
ad080d79 3635}
ad080d79 3636
0b10f478 3637static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 3638{
3639 u8 val;
3640 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3641 | SDHCI_WAKE_ON_INT;
3642
3643 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3644 val &= ~mask;
3645 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
58e79b60
AH		 3646
3647 disable_irq_wake(host->irq);
3648
3649 host->irq_wake_enabled = false;
ad080d79 3650}
d129bceb 3651
29495aa0 3652int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 3653{
7260cf5e
AV		 3654 sdhci_disable_card_detection(host);
3655
66c39dfc 3656 mmc_retune_timer_stop(host->mmc);
cf2b5eea 3657
58e79b60
AH		 3658 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3659 !sdhci_enable_irq_wakeups(host)) {
b537f94c
RK		 3660 host->ier = 0;
3661 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3662 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79 3663 free_irq(host->irq, host);
ad080d79 3664 }
58e79b60 3665
4ee14ec6 3666 return 0;
d129bceb
PO		 3667}
3668
b8c86fc5 3669EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 3670
b8c86fc5
PO		 3671int sdhci_resume_host(struct sdhci_host *host)
3672{
d3940f27 3673 struct mmc_host *mmc = host->mmc;
4ee14ec6 3674 int ret = 0;
d129bceb 3675
a13abc7b 3676 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 3677 if (host->ops->enable_dma)
3678 host->ops->enable_dma(host);
3679 }
d129bceb 3680
6308d290
AH		 3681 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3682 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3683 /* Card keeps power but host controller does not */
3684 sdhci_init(host, 0);
3685 host->pwr = 0;
3686 host->clock = 0;
d3940f27 3687 mmc->ops->set_ios(mmc, &mmc->ios);
6308d290
AH		 3688 } else {
3689 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
6308d290 3690 }
b8c86fc5 3691
58e79b60
AH		 3692 if (host->irq_wake_enabled) {
3693 sdhci_disable_irq_wakeups(host);
3694 } else {
14a7b416
HC		 3695 ret = request_threaded_irq(host->irq, sdhci_irq,
3696 sdhci_thread_irq, IRQF_SHARED,
3697 mmc_hostname(host->mmc), host);
3698 if (ret)
3699 return ret;
14a7b416
HC		 3700 }
3701
7260cf5e
AV		 3702 sdhci_enable_card_detection(host);
3703
2f4cbb3d 3704 return ret;
d129bceb
PO		 3705}
3706
b8c86fc5 3707EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5 3708
66fd8ad5
AH		 3709int sdhci_runtime_suspend_host(struct sdhci_host *host)
3710{
3711 unsigned long flags;
66fd8ad5 3712
66c39dfc 3713 mmc_retune_timer_stop(host->mmc);
66fd8ad5
AH		 3714
3715 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 3716 host->ier &= SDHCI_INT_CARD_INT;
3717 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3718 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 3719 spin_unlock_irqrestore(&host->lock, flags);
3720
781e989c 3721 synchronize_hardirq(host->irq);
66fd8ad5
AH		 3722
3723 spin_lock_irqsave(&host->lock, flags);
3724 host->runtime_suspended = true;
3725 spin_unlock_irqrestore(&host->lock, flags);
3726
8a125bad 3727 return 0;
66fd8ad5
AH		 3728}
3729EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3730
c6303c5d 3731int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
66fd8ad5 3732{
d3940f27 3733 struct mmc_host *mmc = host->mmc;
66fd8ad5 3734 unsigned long flags;
8a125bad 3735 int host_flags = host->flags;
66fd8ad5
AH		 3736
3737 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3738 if (host->ops->enable_dma)
3739 host->ops->enable_dma(host);
3740 }
3741
c6303c5d 3742 sdhci_init(host, soft_reset);
66fd8ad5 3743
70bc85ad
ZW		 3744 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3745 mmc->ios.power_mode != MMC_POWER_OFF) {
84ec048b
AH		 3746 /* Force clock and power re-program */
3747 host->pwr = 0;
3748 host->clock = 0;
3749 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3750 mmc->ops->set_ios(mmc, &mmc->ios);
66fd8ad5 3751
84ec048b
AH		 3752 if ((host_flags & SDHCI_PV_ENABLED) &&
3753 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3754 spin_lock_irqsave(&host->lock, flags);
3755 sdhci_enable_preset_value(host, true);
3756 spin_unlock_irqrestore(&host->lock, flags);
3757 }
66fd8ad5 3758
84ec048b
AH		 3759 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3760 mmc->ops->hs400_enhanced_strobe)
3761 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3762 }
086b0ddb 3763
66fd8ad5
AH		 3764 spin_lock_irqsave(&host->lock, flags);
3765
3766 host->runtime_suspended = false;
3767
3768 /* Enable SDIO IRQ */
0e62614b 3769 if (sdio_irq_claimed(mmc))
66fd8ad5
AH		 3770 sdhci_enable_sdio_irq_nolock(host, true);
3771
3772 /* Enable Card Detection */
3773 sdhci_enable_card_detection(host);
3774
3775 spin_unlock_irqrestore(&host->lock, flags);
3776
8a125bad 3777 return 0;
66fd8ad5
AH		 3778}
3779EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3780
162d6f98 3781#endif /* CONFIG_PM */
66fd8ad5 3782
f12e39db
AH		 3783/*****************************************************************************\
3784 * *
3785 * Command Queue Engine (CQE) helpers *
3786 * *
3787\*****************************************************************************/
3788
3789void sdhci_cqe_enable(struct mmc_host *mmc)
3790{
3791 struct sdhci_host *host = mmc_priv(mmc);
3792 unsigned long flags;
3793 u8 ctrl;
3794
3795 spin_lock_irqsave(&host->lock, flags);
3796
3797 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3798 ctrl &= ~SDHCI_CTRL_DMA_MASK;
4c4faff6
SK		 3799 /*
3800 * Host from V4.10 supports ADMA3 DMA type.
3801 * ADMA3 performs integrated descriptor which is more suitable
3802 * for cmd queuing to fetch both command and transfer descriptors.
3803 */
3804 if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3805 ctrl |= SDHCI_CTRL_ADMA3;
3806 else if (host->flags & SDHCI_USE_64_BIT_DMA)
f12e39db
AH		 3807 ctrl |= SDHCI_CTRL_ADMA64;
3808 else
3809 ctrl |= SDHCI_CTRL_ADMA32;
3810 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3811
c846a00f 3812 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
f12e39db
AH		 3813 SDHCI_BLOCK_SIZE);
3814
3815 /* Set maximum timeout */
401059df 3816 sdhci_set_timeout(host, NULL);
f12e39db
AH		 3817
3818 host->ier = host->cqe_ier;
3819
3820 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3821 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3822
3823 host->cqe_on = true;
3824
3825 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3826 mmc_hostname(mmc), host->ier,
3827 sdhci_readl(host, SDHCI_INT_STATUS));
3828
f12e39db
AH		 3829 spin_unlock_irqrestore(&host->lock, flags);
3830}
3831EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3832
3833void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3834{
3835 struct sdhci_host *host = mmc_priv(mmc);
3836 unsigned long flags;
3837
3838 spin_lock_irqsave(&host->lock, flags);
3839
3840 sdhci_set_default_irqs(host);
3841
3842 host->cqe_on = false;
3843
3844 if (recovery) {
3845 sdhci_do_reset(host, SDHCI_RESET_CMD);
3846 sdhci_do_reset(host, SDHCI_RESET_DATA);
3847 }
3848
3849 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3850 mmc_hostname(mmc), host->ier,
3851 sdhci_readl(host, SDHCI_INT_STATUS));
3852
f12e39db
AH		 3853 spin_unlock_irqrestore(&host->lock, flags);
3854}
3855EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3856
3857bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3858 int *data_error)
3859{
3860 u32 mask;
3861
3862 if (!host->cqe_on)
3863 return false;
3864
3865 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3866 *cmd_error = -EILSEQ;
3867 else if (intmask & SDHCI_INT_TIMEOUT)
3868 *cmd_error = -ETIMEDOUT;
3869 else
3870 *cmd_error = 0;
3871
3872 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3873 *data_error = -EILSEQ;
3874 else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3875 *data_error = -ETIMEDOUT;
3876 else if (intmask & SDHCI_INT_ADMA_ERROR)
3877 *data_error = -EIO;
3878 else
3879 *data_error = 0;
3880
3881 /* Clear selected interrupts. */
3882 mask = intmask & host->cqe_ier;
3883 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3884
3885 if (intmask & SDHCI_INT_BUS_POWER)
3886 pr_err("%s: Card is consuming too much power!\n",
3887 mmc_hostname(host->mmc));
3888
3889 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3890 if (intmask) {
3891 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3892 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3893 mmc_hostname(host->mmc), intmask);
3894 sdhci_dumpregs(host);
3895 }
3896
3897 return true;
3898}
3899EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3900
d129bceb
PO		 3901/*****************************************************************************\
3902 * *
b8c86fc5 3903 * Device allocation/registration *
d129bceb
PO		 3904 * *
3905\*****************************************************************************/
3906
b8c86fc5
PO		 3907struct sdhci_host *sdhci_alloc_host(struct device *dev,
3908 size_t priv_size)
d129bceb 3909{
d129bceb
PO		 3910 struct mmc_host *mmc;
3911 struct sdhci_host *host;
3912
b8c86fc5 3913 WARN_ON(dev == NULL);
d129bceb 3914
b8c86fc5 3915 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 3916 if (!mmc)
b8c86fc5 3917 return ERR_PTR(-ENOMEM);
d129bceb
PO		 3918
3919 host = mmc_priv(mmc);
3920 host->mmc = mmc;
bf60e592
AH		 3921 host->mmc_host_ops = sdhci_ops;
3922 mmc->ops = &host->mmc_host_ops;
d129bceb 3923
8cb851a4
AH		 3924 host->flags = SDHCI_SIGNALING_330;
3925
f12e39db
AH		 3926 host->cqe_ier = SDHCI_CQE_INT_MASK;
3927 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3928
83b600b8 3929 host->tuning_delay = -1;
1d8cd065 3930 host->tuning_loop_count = MAX_TUNING_LOOP;
83b600b8 3931
c846a00f
SK		 3932 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3933
e93be38a
JZ		 3934 /*
3935 * The DMA table descriptor count is calculated as the maximum
3936 * number of segments times 2, to allow for an alignment
3937 * descriptor for each segment, plus 1 for a nop end descriptor.
3938 */
3939 host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
3940
b8c86fc5
PO		 3941 return host;
3942}
8a4da143 3943
b8c86fc5 3944EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 3945
7b91369b
AC		 3946static int sdhci_set_dma_mask(struct sdhci_host *host)
3947{
3948 struct mmc_host *mmc = host->mmc;
3949 struct device *dev = mmc_dev(mmc);
3950 int ret = -EINVAL;
3951
3952 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3953 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3954
3955 /* Try 64-bit mask if hardware is capable of it */
3956 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3957 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3958 if (ret) {
3959 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3960 mmc_hostname(mmc));
3961 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3962 }
3963 }
3964
3965 /* 32-bit mask as default & fallback */
3966 if (ret) {
3967 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3968 if (ret)
3969 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3970 mmc_hostname(mmc));
3971 }
3972
3973 return ret;
3974}
3975
8784edc8
MY		 3976void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
3977 const u32 *caps, const u32 *caps1)
6132a3bf
AH		 3978{
3979 u16 v;
92e0c44b
ZB		 3980 u64 dt_caps_mask = 0;
3981 u64 dt_caps = 0;
6132a3bf
AH		 3982
3983 if (host->read_caps)
3984 return;
3985
3986 host->read_caps = true;
3987
3988 if (debug_quirks)
3989 host->quirks = debug_quirks;
3990
3991 if (debug_quirks2)
3992 host->quirks2 = debug_quirks2;
3993
3994 sdhci_do_reset(host, SDHCI_RESET_ALL);
3995
b3f80b43
CZ		 3996 if (host->v4_mode)
3997 sdhci_do_enable_v4_mode(host);
3998
cb80a7e9
JL		 3999 device_property_read_u64(mmc_dev(host->mmc),
4000 "sdhci-caps-mask", &dt_caps_mask);
4001 device_property_read_u64(mmc_dev(host->mmc),
4002 "sdhci-caps", &dt_caps);
92e0c44b 4003
6132a3bf
AH		 4004 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
4005 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
4006
4007 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
4008 return;
4009
92e0c44b
ZB		 4010 if (caps) {
4011 host->caps = *caps;
4012 } else {
4013 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
4014 host->caps &= ~lower_32_bits(dt_caps_mask);
4015 host->caps |= lower_32_bits(dt_caps);
4016 }
6132a3bf
AH		 4017
4018 if (host->version < SDHCI_SPEC_300)
4019 return;
4020
92e0c44b
ZB		 4021 if (caps1) {
4022 host->caps1 = *caps1;
4023 } else {
4024 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
4025 host->caps1 &= ~upper_32_bits(dt_caps_mask);
4026 host->caps1 |= upper_32_bits(dt_caps);
4027 }
6132a3bf
AH		 4028}
4029EXPORT_SYMBOL_GPL(__sdhci_read_caps);
4030
a68dd9a0 4031static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
bd9b9027
LW		 4032{
4033 struct mmc_host *mmc = host->mmc;
4034 unsigned int max_blocks;
4035 unsigned int bounce_size;
4036 int ret;
4037
4038 /*
4039 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
4040 * has diminishing returns, this is probably because SD/MMC
4041 * cards are usually optimized to handle this size of requests.
4042 */
4043 bounce_size = SZ_64K;
4044 /*
4045 * Adjust downwards to maximum request size if this is less
4046 * than our segment size, else hammer down the maximum
4047 * request size to the maximum buffer size.
4048 */
4049 if (mmc->max_req_size < bounce_size)
4050 bounce_size = mmc->max_req_size;
4051 max_blocks = bounce_size / 512;
4052
4053 /*
4054 * When we just support one segment, we can get significant
4055 * speedups by the help of a bounce buffer to group scattered
4056 * reads/writes together.
4057 */
4058 host->bounce_buffer = devm_kmalloc(mmc->parent,
4059 bounce_size,
4060 GFP_KERNEL);
4061 if (!host->bounce_buffer) {
4062 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
4063 mmc_hostname(mmc),
4064 bounce_size);
4065 /*
4066 * Exiting with zero here makes sure we proceed with
4067 * mmc->max_segs == 1.
4068 */
a68dd9a0 4069 return;
bd9b9027
LW		 4070 }
4071
4072 host->bounce_addr = dma_map_single(mmc->parent,
4073 host->bounce_buffer,
4074 bounce_size,
4075 DMA_BIDIRECTIONAL);
4076 ret = dma_mapping_error(mmc->parent, host->bounce_addr);
4077 if (ret)
4078 /* Again fall back to max_segs == 1 */
a68dd9a0 4079 return;
bd9b9027
LW		 4080 host->bounce_buffer_size = bounce_size;
4081
4082 /* Lie about this since we're bouncing */
4083 mmc->max_segs = max_blocks;
4084 mmc->max_seg_size = bounce_size;
4085 mmc->max_req_size = bounce_size;
4086
4087 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
4088 mmc_hostname(mmc), max_blocks, bounce_size);
bd9b9027
LW		 4089}
4090
685e444b
CZ		 4091static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
4092{
4093 /*
4094 * According to SD Host Controller spec v4.10, bit[27] added from
4095 * version 4.10 in Capabilities Register is used as 64-bit System
4096 * Address support for V4 mode.
4097 */
4098 if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
4099 return host->caps & SDHCI_CAN_64BIT_V4;
4100
4101 return host->caps & SDHCI_CAN_64BIT;
4102}
4103
52f5336d 4104int sdhci_setup_host(struct sdhci_host *host)
b8c86fc5
PO		 4105{
4106 struct mmc_host *mmc;
f2119df6
AN		 4107 u32 max_current_caps;
4108 unsigned int ocr_avail;
f5fa92e5 4109 unsigned int override_timeout_clk;
59241757 4110 u32 max_clk;
907be2a6 4111 int ret = 0;
0fcb031e 4112 bool enable_vqmmc = false;
d129bceb 4113
b8c86fc5
PO		 4114 WARN_ON(host == NULL);
4115 if (host == NULL)
4116 return -EINVAL;
d129bceb 4117
b8c86fc5 4118 mmc = host->mmc;
d129bceb 4119
efba142b
JH		 4120 /*
4121 * If there are external regulators, get them. Note this must be done
4122 * early before resetting the host and reading the capabilities so that
4123 * the host can take the appropriate action if regulators are not
4124 * available.
4125 */
0fcb031e
VV		 4126 if (!mmc->supply.vqmmc) {
4127 ret = mmc_regulator_get_supply(mmc);
4128 if (ret)
4129 return ret;
4130 enable_vqmmc = true;
4131 }
efba142b 4132
06ebc601
SL		 4133 DBG("Version: 0x%08x | Present: 0x%08x\n",
4134 sdhci_readw(host, SDHCI_HOST_VERSION),
4135 sdhci_readl(host, SDHCI_PRESENT_STATE));
4136 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
4137 sdhci_readl(host, SDHCI_CAPABILITIES),
4138 sdhci_readl(host, SDHCI_CAPABILITIES_1));
4139
6132a3bf 4140 sdhci_read_caps(host);
d129bceb 4141
f5fa92e5
AH		 4142 override_timeout_clk = host->timeout_clk;
4143
18da1990 4144 if (host->version > SDHCI_SPEC_420) {
2e4456f0
MV		 4145 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
4146 mmc_hostname(mmc), host->version);
4a965505
PO		 4147 }
4148
b8c86fc5 4149 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 4150 host->flags |= SDHCI_USE_SDMA;
28da3589 4151 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
a13abc7b 4152 DBG("Controller doesn't have SDMA capability\n");
67435274 4153 else
a13abc7b 4154 host->flags |= SDHCI_USE_SDMA;
d129bceb 4155
b8c86fc5 4156 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 4157 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 4158 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 4159 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 4160 }
4161
f2119df6 4162 if ((host->version >= SDHCI_SPEC_200) &&
28da3589 4163 (host->caps & SDHCI_CAN_DO_ADMA2))
a13abc7b 4164 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 4165
4166 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
4167 (host->flags & SDHCI_USE_ADMA)) {
4168 DBG("Disabling ADMA as it is marked broken\n");
4169 host->flags &= ~SDHCI_USE_ADMA;
4170 }
4171
685e444b 4172 if (sdhci_can_64bit_dma(host))
e57a5f61
AH		 4173 host->flags |= SDHCI_USE_64_BIT_DMA;
4174
18e762e3
CZ		 4175 if (host->use_external_dma) {
4176 ret = sdhci_external_dma_init(host);
4177 if (ret == -EPROBE_DEFER)
4178 goto unreg;
4179 /*
4180 * Fall back to use the DMA/PIO integrated in standard SDHCI
4181 * instead of external DMA devices.
4182 */
4183 else if (ret)
4184 sdhci_switch_external_dma(host, false);
4185 /* Disable internal DMA sources */
4186 else
4187 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4188 }
4189
a13abc7b 4190 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
4ee7dde4
AH		 4191 if (host->ops->set_dma_mask)
4192 ret = host->ops->set_dma_mask(host);
4193 else
4194 ret = sdhci_set_dma_mask(host);
7b91369b
AC		 4195
4196 if (!ret && host->ops->enable_dma)
4197 ret = host->ops->enable_dma(host);
4198
4199 if (ret) {
4200 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
4201 mmc_hostname(mmc));
4202 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4203
4204 ret = 0;
d129bceb
PO		 4205 }
4206 }
4207
917a0c52
CZ		 4208 /* SDMA does not support 64-bit DMA if v4 mode not set */
4209 if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
e57a5f61
AH		 4210 host->flags &= ~SDHCI_USE_SDMA;
4211
2134a922 4212 if (host->flags & SDHCI_USE_ADMA) {
e66e61cb
RK		 4213 dma_addr_t dma;
4214 void *buf;
4215
a663f64b
VB		 4216 if (!(host->flags & SDHCI_USE_64_BIT_DMA))
4217 host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
4218 else if (!host->alloc_desc_sz)
4219 host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
4220
4221 host->desc_sz = host->alloc_desc_sz;
4222 host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
e66e61cb 4223
04a5ae6f 4224 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
685e444b
CZ		 4225 /*
4226 * Use zalloc to zero the reserved high 32-bits of 128-bit
4227 * descriptors so that they never need to be written.
4228 */
750afb08
LC		 4229 buf = dma_alloc_coherent(mmc_dev(mmc),
4230 host->align_buffer_sz + host->adma_table_sz,
4231 &dma, GFP_KERNEL);
e66e61cb 4232 if (!buf) {
6606110d 4233 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 4234 mmc_hostname(mmc));
4235 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 4236 } else if ((dma + host->align_buffer_sz) &
4237 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 4238 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
4239 mmc_hostname(mmc));
d1e49f77 4240 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 4241 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4242 host->adma_table_sz, buf, dma);
4243 } else {
4244 host->align_buffer = buf;
4245 host->align_addr = dma;
edd63fcc 4246
e66e61cb
RK		 4247 host->adma_table = buf + host->align_buffer_sz;
4248 host->adma_addr = dma + host->align_buffer_sz;
4249 }
2134a922
PO		 4250 }
4251
7659150c
PO		 4252 /*
4253 * If we use DMA, then it's up to the caller to set the DMA
4254 * mask, but PIO does not need the hw shim so we set a new
4255 * mask here in that case.
4256 */
a13abc7b 4257 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 4258 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 4259 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 4260 }
d129bceb 4261
c4687d5f 4262 if (host->version >= SDHCI_SPEC_300)
a8e809ec 4263 host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
c4687d5f 4264 else
a8e809ec 4265 host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
c4687d5f 4266
4240ff0a 4267 host->max_clk *= 1000000;
f27f47ef
AV		 4268 if (host->max_clk == 0 || host->quirks &
4269 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 4270 if (!host->ops->get_max_clock) {
2e4456f0
MV		 4271 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
4272 mmc_hostname(mmc));
eb5c20de
AH		 4273 ret = -ENODEV;
4274 goto undma;
4240ff0a
BD		 4275 }
4276 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 4277 }
d129bceb 4278
c3ed3877
AN		 4279 /*
4280 * In case of Host Controller v3.00, find out whether clock
4281 * multiplier is supported.
4282 */
a8e809ec 4283 host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
c3ed3877
AN		 4284
4285 /*
4286 * In case the value in Clock Multiplier is 0, then programmable
4287 * clock mode is not supported, otherwise the actual clock
4288 * multiplier is one more than the value of Clock Multiplier
4289 * in the Capabilities Register.
4290 */
4291 if (host->clk_mul)
4292 host->clk_mul += 1;
4293
d129bceb
PO		 4294 /*
4295 * Set host parameters.
4296 */
59241757
DA		 4297 max_clk = host->max_clk;
4298
ce5f036b 4299 if (host->ops->get_min_clock)
a9e58f25 4300 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877 4301 else if (host->version >= SDHCI_SPEC_300) {
2a187d03 4302 if (host->clk_mul)
59241757 4303 max_clk = host->max_clk * host->clk_mul;
2a187d03
MM		 4304 /*
4305 * Divided Clock Mode minimum clock rate is always less than
4306 * Programmable Clock Mode minimum clock rate.
4307 */
4308 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
c3ed3877 4309 } else
0397526d 4310 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 4311
d310ae49 4312 if (!mmc->f_max || mmc->f_max > max_clk)
59241757
DA		 4313 mmc->f_max = max_clk;
4314
28aab053 4315 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a8e809ec 4316 host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
8cc35289
SL		 4317
4318 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
4319 host->timeout_clk *= 1000;
4320
28aab053 4321 if (host->timeout_clk == 0) {
8cc35289 4322 if (!host->ops->get_timeout_clock) {
28aab053
AD		 4323 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
4324 mmc_hostname(mmc));
eb5c20de
AH		 4325 ret = -ENODEV;
4326 goto undma;
28aab053 4327 }
272308ca 4328
8cc35289
SL		 4329 host->timeout_clk =
4330 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
4331 1000);
4332 }
272308ca 4333
99513624
AH		 4334 if (override_timeout_clk)
4335 host->timeout_clk = override_timeout_clk;
4336
28aab053 4337 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 4338 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 4339 mmc->max_busy_timeout /= host->timeout_clk;
4340 }
58d1246d 4341
a999fd93
AH		 4342 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
4343 !host->ops->get_max_timeout_count)
4344 mmc->max_busy_timeout = 0;
4345
1be64c79 4346 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23;
781e989c 4347 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 4348
4349 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4350 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 4351
7ed71a9d
CZ		 4352 /*
4353 * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
4354 * For v4 mode, SDMA may use Auto-CMD23 as well.
4355 */
4f3d3e9b 4356 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 4357 ((host->flags & SDHCI_USE_ADMA) ||
7ed71a9d 4358 !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
3bfa6f03 4359 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371 4360 host->flags |= SDHCI_AUTO_CMD23;
f421865d 4361 DBG("Auto-CMD23 available\n");
8edf6371 4362 } else {
f421865d 4363 DBG("Auto-CMD23 unavailable\n");
8edf6371
AW		 4364 }
4365
15ec4461
PR		 4366 /*
4367 * A controller may support 8-bit width, but the board itself
4368 * might not have the pins brought out. Boards that support
4369 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
4370 * their platform code before calling sdhci_add_host(), and we
4371 * won't assume 8-bit width for hosts without that CAP.
4372 */
5fe23c7f 4373 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 4374 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 4375
63ef5d8c
JH		 4376 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4377 mmc->caps &= ~MMC_CAP_CMD23;
4378
28da3589 4379 if (host->caps & SDHCI_CAN_DO_HISPD)
a29e7e18 4380 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 4381
176d1ed4 4382 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
860951c5 4383 mmc_card_is_removable(mmc) &&
287980e4 4384 mmc_gpio_get_cd(host->mmc) < 0)
68d1fb7e
AV		 4385 mmc->caps |= MMC_CAP_NEEDS_POLL;
4386
3a48edc4 4387 if (!IS_ERR(mmc->supply.vqmmc)) {
0fcb031e
VV		 4388 if (enable_vqmmc) {
4389 ret = regulator_enable(mmc->supply.vqmmc);
0fcb031e
VV		 4390 host->sdhci_core_to_disable_vqmmc = !ret;
4391 }
1b5190c2
SA		 4392
4393 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 4394 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
4395 1950000))
28da3589
AH		 4396 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
4397 SDHCI_SUPPORT_SDR50 |
4398 SDHCI_SUPPORT_DDR50);
1b5190c2
SA		 4399
4400 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
4401 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
4402 3600000))
4403 host->flags &= ~SDHCI_SIGNALING_330;
4404
a3361aba
CB		 4405 if (ret) {
4406 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
4407 mmc_hostname(mmc), ret);
4bb74313 4408 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 4409 }
3debc24f 4410
8363c374 4411 }
6231f3de 4412
28da3589
AH		 4413 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
4414 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4415 SDHCI_SUPPORT_DDR50);
c16bc9a7
KVA		 4416 /*
4417 * The SDHCI controller in a SoC might support HS200/HS400
4418 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
4419 * but if the board is modeled such that the IO lines are not
4420 * connected to 1.8v then HS200/HS400 cannot be supported.
4421 * Disable HS200/HS400 if the board does not have 1.8v connected
4422 * to the IO lines. (Applicable for other modes in 1.8v)
4423 */
4424 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
4425 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
28da3589 4426 }
6a66180a 4427
4188bba0 4428 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
28da3589
AH		 4429 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4430 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 4431 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4432
4433 /* SDR104 supports also implies SDR50 support */
28da3589 4434 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
f2119df6 4435 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 4436 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
4437 * field can be promoted to support HS200.
4438 */
549c0b18 4439 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 4440 mmc->caps2 |= MMC_CAP2_HS200;
28da3589 4441 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
f2119df6 4442 mmc->caps |= MMC_CAP_UHS_SDR50;
28da3589 4443 }
f2119df6 4444
e9fb05d5 4445 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
28da3589 4446 (host->caps1 & SDHCI_SUPPORT_HS400))
e9fb05d5
AH		 4447 mmc->caps2 |= MMC_CAP2_HS400;
4448
549c0b18
AH		 4449 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
4450 (IS_ERR(mmc->supply.vqmmc) ||
4451 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
4452 1300000)))
4453 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
4454
28da3589
AH		 4455 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4456 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 4457 mmc->caps |= MMC_CAP_UHS_DDR50;
4458
069c9f14 4459 /* Does the host need tuning for SDR50? */
28da3589 4460 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
b513ea25
AN		 4461 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4462
d6d50a15 4463 /* Driver Type(s) (A, C, D) supported by the host */
28da3589 4464 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
d6d50a15 4465 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
28da3589 4466 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
d6d50a15 4467 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
28da3589 4468 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
d6d50a15
AN		 4469 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4470
cf2b5eea 4471 /* Initial value for re-tuning timer count */
a8e809ec
MY		 4472 host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
4473 host->caps1);
cf2b5eea
AN		 4474
4475 /*
4476 * In case Re-tuning Timer is not disabled, the actual value of
4477 * re-tuning timer will be 2 ^ (n - 1).
4478 */
4479 if (host->tuning_count)
4480 host->tuning_count = 1 << (host->tuning_count - 1);
4481
4482 /* Re-tuning mode supported by the Host Controller */
a8e809ec 4483 host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
cf2b5eea 4484
8f230f45 4485 ocr_avail = 0;
bad37e1a 4486
f2119df6
AN		 4487 /*
4488 * According to SD Host Controller spec v3.00, if the Host System
4489 * can afford more than 150mA, Host Driver should set XPC to 1. Also
4490 * the value is meaningful only if Voltage Support in the Capabilities
4491 * register is set. The actual current value is 4 times the register
4492 * value.
4493 */
4494 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 4495 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 4496 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 4497 if (curr > 0) {
4498
4499 /* convert to SDHCI_MAX_CURRENT format */
4500 curr = curr/1000; /* convert to mA */
4501 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4502
4503 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4504 max_current_caps =
804a65b3
MY		 4505 FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) |
4506 FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) |
4507 FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
bad37e1a
PR		 4508 }
4509 }
f2119df6 4510
28da3589 4511 if (host->caps & SDHCI_CAN_VDD_330) {
8f230f45 4512 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 4513
804a65b3
MY		 4514 mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
4515 max_current_caps) *
4516 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 4517 }
28da3589 4518 if (host->caps & SDHCI_CAN_VDD_300) {
8f230f45 4519 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 4520
804a65b3
MY		 4521 mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
4522 max_current_caps) *
4523 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 4524 }
28da3589 4525 if (host->caps & SDHCI_CAN_VDD_180) {
8f230f45
TI		 4526 ocr_avail |= MMC_VDD_165_195;
4527
804a65b3
MY		 4528 mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
4529 max_current_caps) *
4530 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 4531 }
4532
5fd26c7e
UH		 4533 /* If OCR set by host, use it instead. */
4534 if (host->ocr_mask)
4535 ocr_avail = host->ocr_mask;
4536
4537 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 4538 if (mmc->ocr_avail)
52221610 4539 ocr_avail = mmc->ocr_avail;
3a48edc4 4540
8f230f45
TI		 4541 mmc->ocr_avail = ocr_avail;
4542 mmc->ocr_avail_sdio = ocr_avail;
4543 if (host->ocr_avail_sdio)
4544 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4545 mmc->ocr_avail_sd = ocr_avail;
4546 if (host->ocr_avail_sd)
4547 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4548 else /* normal SD controllers don't support 1.8V */
4549 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4550 mmc->ocr_avail_mmc = ocr_avail;
4551 if (host->ocr_avail_mmc)
4552 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 4553
4554 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 4555 pr_err("%s: Hardware doesn't report any support voltages.\n",
4556 mmc_hostname(mmc));
eb5c20de
AH		 4557 ret = -ENODEV;
4558 goto unreg;
146ad66e
PO		 4559 }
4560
8cb851a4
AH		 4561 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
4562 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
4563 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
4564 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
4565 host->flags |= SDHCI_SIGNALING_180;
4566
4567 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
4568 host->flags |= SDHCI_SIGNALING_120;
4569
d129bceb
PO		 4570 spin_lock_init(&host->lock);
4571
250dcd11
UH		 4572 /*
4573 * Maximum number of sectors in one transfer. Limited by SDMA boundary
4574 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
4575 * is less anyway.
4576 */
4577 mmc->max_req_size = 524288;
4578
d129bceb 4579 /*
2134a922
PO		 4580 * Maximum number of segments. Depends on if the hardware
4581 * can do scatter/gather or not.
d129bceb 4582 */
250dcd11 4583 if (host->flags & SDHCI_USE_ADMA) {
4fb213f8 4584 mmc->max_segs = SDHCI_MAX_SEGS;
250dcd11 4585 } else if (host->flags & SDHCI_USE_SDMA) {
a36274e0 4586 mmc->max_segs = 1;
250dcd11
UH		 4587 if (swiotlb_max_segment()) {
4588 unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
4589 IO_TLB_SEGSIZE;
4590 mmc->max_req_size = min(mmc->max_req_size,
4591 max_req_size);
4592 }
4593 } else { /* PIO */
4fb213f8 4594 mmc->max_segs = SDHCI_MAX_SEGS;
250dcd11 4595 }
d129bceb
PO		 4596
4597 /*
4598 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 4599 * of bytes. When doing hardware scatter/gather, each entry cannot
4600 * be larger than 64 KiB though.
d129bceb 4601 */
30652aa3
OJ		 4602 if (host->flags & SDHCI_USE_ADMA) {
4603 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
4604 mmc->max_seg_size = 65535;
4605 else
4606 mmc->max_seg_size = 65536;
4607 } else {
2134a922 4608 mmc->max_seg_size = mmc->max_req_size;
30652aa3 4609 }
d129bceb 4610
fe4a3c7a
PO		 4611 /*
4612 * Maximum block size. This varies from controller to controller and
4613 * is specified in the capabilities register.
4614 */
0633f654
AV		 4615 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4616 mmc->max_blk_size = 2;
4617 } else {
28da3589 4618 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 4619 SDHCI_MAX_BLOCK_SHIFT;
4620 if (mmc->max_blk_size >= 3) {
6606110d
JP		 4621 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4622 mmc_hostname(mmc));
0633f654
AV		 4623 mmc->max_blk_size = 0;
4624 }
4625 }
4626
4627 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 4628
55db890a
PO		 4629 /*
4630 * Maximum block count.
4631 */
1388eefd 4632 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 4633
a68dd9a0 4634 if (mmc->max_segs == 1)
bd9b9027 4635 /* This may alter mmc->*_blk_* parameters */
a68dd9a0 4636 sdhci_allocate_bounce_buffer(host);
bd9b9027 4637
52f5336d
AH		 4638 return 0;
4639
4640unreg:
0fcb031e 4641 if (host->sdhci_core_to_disable_vqmmc)
52f5336d
AH		 4642 regulator_disable(mmc->supply.vqmmc);
4643undma:
4644 if (host->align_buffer)
4645 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4646 host->adma_table_sz, host->align_buffer,
4647 host->align_addr);
4648 host->adma_table = NULL;
4649 host->align_buffer = NULL;
4650
4651 return ret;
4652}
4653EXPORT_SYMBOL_GPL(sdhci_setup_host);
4654
4180ffa8
AH		 4655void sdhci_cleanup_host(struct sdhci_host *host)
4656{
4657 struct mmc_host *mmc = host->mmc;
4658
0fcb031e 4659 if (host->sdhci_core_to_disable_vqmmc)
4180ffa8
AH		 4660 regulator_disable(mmc->supply.vqmmc);
4661
4662 if (host->align_buffer)
4663 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4664 host->adma_table_sz, host->align_buffer,
4665 host->align_addr);
18e762e3
CZ		 4666
4667 if (host->use_external_dma)
4668 sdhci_external_dma_release(host);
4669
4180ffa8
AH		 4670 host->adma_table = NULL;
4671 host->align_buffer = NULL;
4672}
4673EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4674
52f5336d
AH		 4675int __sdhci_add_host(struct sdhci_host *host)
4676{
c07a48c2 4677 unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
52f5336d
AH		 4678 struct mmc_host *mmc = host->mmc;
4679 int ret;
4680
2b17b8d7
AH		 4681 if ((mmc->caps2 & MMC_CAP2_CQE) &&
4682 (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
4683 mmc->caps2 &= ~MMC_CAP2_CQE;
4684 mmc->cqe_ops = NULL;
4685 }
4686
c07a48c2
AH		 4687 host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4688 if (!host->complete_wq)
4689 return -ENOMEM;
4690
4691 INIT_WORK(&host->complete_work, sdhci_complete_work);
d129bceb 4692
2ee4f620
KC		 4693 timer_setup(&host->timer, sdhci_timeout_timer, 0);
4694 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
d129bceb 4695
250fb7b4 4696 init_waitqueue_head(&host->buf_ready_int);
b513ea25 4697
2af502ca
SG		 4698 sdhci_init(host, 0);
4699
781e989c
RK		 4700 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4701 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 4702 if (ret) {
4703 pr_err("%s: Failed to request IRQ %d: %d\n",
4704 mmc_hostname(mmc), host->irq, ret);
c07a48c2 4705 goto unwq;
0fc81ee3 4706 }
d129bceb 4707
061d17a6 4708 ret = sdhci_led_register(host);
0fc81ee3
MB		 4709 if (ret) {
4710 pr_err("%s: Failed to register LED device: %d\n",
4711 mmc_hostname(mmc), ret);
eb5c20de 4712 goto unirq;
0fc81ee3 4713 }
2f730fec 4714
eb5c20de
AH		 4715 ret = mmc_add_host(mmc);
4716 if (ret)
4717 goto unled;
d129bceb 4718
a3c76eb9 4719 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 4720 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
18e762e3 4721 host->use_external_dma ? "External DMA" :
e57a5f61
AH		 4722 (host->flags & SDHCI_USE_ADMA) ?
4723 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 4724 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 4725
7260cf5e
AV		 4726 sdhci_enable_card_detection(host);
4727
d129bceb
PO		 4728 return 0;
4729
eb5c20de 4730unled:
061d17a6 4731 sdhci_led_unregister(host);
eb5c20de 4732unirq:
03231f9b 4733 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 4734 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4735 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec 4736 free_irq(host->irq, host);
c07a48c2
AH		 4737unwq:
4738 destroy_workqueue(host->complete_wq);
52f5336d 4739
d129bceb
PO		 4740 return ret;
4741}
52f5336d
AH		 4742EXPORT_SYMBOL_GPL(__sdhci_add_host);
4743
4744int sdhci_add_host(struct sdhci_host *host)
4745{
4746 int ret;
4747
4748 ret = sdhci_setup_host(host);
4749 if (ret)
4750 return ret;
d129bceb 4751
4180ffa8
AH		 4752 ret = __sdhci_add_host(host);
4753 if (ret)
4754 goto cleanup;
4755
4756 return 0;
4757
4758cleanup:
4759 sdhci_cleanup_host(host);
4760
4761 return ret;
52f5336d 4762}
b8c86fc5 4763EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 4764
1e72859e 4765void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 4766{
3a48edc4 4767 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 4768 unsigned long flags;
4769
4770 if (dead) {
4771 spin_lock_irqsave(&host->lock, flags);
4772
4773 host->flags |= SDHCI_DEVICE_DEAD;
4774
5d0d11c5 4775 if (sdhci_has_requests(host)) {
a3c76eb9 4776 pr_err("%s: Controller removed during "
4e743f1f 4777 " transfer!\n", mmc_hostname(mmc));
5d0d11c5 4778 sdhci_error_out_mrqs(host, -ENOMEDIUM);
1e72859e
PO		 4779 }
4780
4781 spin_unlock_irqrestore(&host->lock, flags);
4782 }
4783
7260cf5e
AV		 4784 sdhci_disable_card_detection(host);
4785
4e743f1f 4786 mmc_remove_host(mmc);
d129bceb 4787
061d17a6 4788 sdhci_led_unregister(host);
2f730fec 4789
1e72859e 4790 if (!dead)
03231f9b 4791 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 4792
b537f94c
RK		 4793 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4794 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 4795 free_irq(host->irq, host);
4796
4797 del_timer_sync(&host->timer);
d7422fb4 4798 del_timer_sync(&host->data_timer);
d129bceb 4799
c07a48c2 4800 destroy_workqueue(host->complete_wq);
2134a922 4801
0fcb031e 4802 if (host->sdhci_core_to_disable_vqmmc)
3a48edc4 4803 regulator_disable(mmc->supply.vqmmc);
6231f3de 4804
edd63fcc 4805 if (host->align_buffer)
e66e61cb
RK		 4806 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4807 host->adma_table_sz, host->align_buffer,
4808 host->align_addr);
2134a922 4809
18e762e3
CZ		 4810 if (host->use_external_dma)
4811 sdhci_external_dma_release(host);
4812
4efaa6fb 4813 host->adma_table = NULL;
2134a922 4814 host->align_buffer = NULL;
d129bceb
PO		 4815}
4816
b8c86fc5 4817EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 4818
b8c86fc5 4819void sdhci_free_host(struct sdhci_host *host)
d129bceb 4820{
b8c86fc5 4821 mmc_free_host(host->mmc);
d129bceb
PO		 4822}
4823
b8c86fc5 4824EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 4825
4826/*****************************************************************************\
4827 * *
4828 * Driver init/exit *
4829 * *
4830\*****************************************************************************/
4831
4832static int __init sdhci_drv_init(void)
4833{
a3c76eb9 4834 pr_info(DRIVER_NAME
52fbf9c9 4835 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 4836 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 4837
b8c86fc5 4838 return 0;
d129bceb
PO		 4839}
4840
4841static void __exit sdhci_drv_exit(void)
4842{
d129bceb
PO		 4843}
4844
4845module_init(sdhci_drv_init);
4846module_exit(sdhci_drv_exit);
4847
df673b22 4848module_param(debug_quirks, uint, 0444);
66fd8ad5 4849module_param(debug_quirks2, uint, 0444);
67435274 4850
32710e8f 4851MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 4852MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 4853MODULE_LICENSE("GPL");
67435274 4854
df673b22 4855MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 4856MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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