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d129bceb | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver |
d129bceb | 3 | * |
1978fda8 GC |
4 | * Header file for Host Controller registers and I/O accessors. |
5 | * | |
b69c9058 | 6 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
d129bceb PO |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
9 | * it under the terms of the GNU General Public License as published by |
10 | * the Free Software Foundation; either version 2 of the License, or (at | |
11 | * your option) any later version. | |
d129bceb | 12 | */ |
1978fda8 GC |
13 | #ifndef __SDHCI_HW_H |
14 | #define __SDHCI_HW_H | |
d129bceb | 15 | |
0c7ad106 | 16 | #include <linux/scatterlist.h> |
4e4141a5 AV |
17 | #include <linux/compiler.h> |
18 | #include <linux/types.h> | |
19 | #include <linux/io.h> | |
210583f4 | 20 | #include <linux/leds.h> |
b8789ec4 | 21 | #include <linux/interrupt.h> |
0c7ad106 | 22 | |
83f13cc9 | 23 | #include <linux/mmc/host.h> |
1978fda8 | 24 | |
d129bceb PO |
25 | /* |
26 | * Controller registers | |
27 | */ | |
28 | ||
29 | #define SDHCI_DMA_ADDRESS 0x00 | |
8edf6371 | 30 | #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS |
d129bceb PO |
31 | |
32 | #define SDHCI_BLOCK_SIZE 0x04 | |
bab76961 | 33 | #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) |
d129bceb PO |
34 | |
35 | #define SDHCI_BLOCK_COUNT 0x06 | |
36 | ||
37 | #define SDHCI_ARGUMENT 0x08 | |
38 | ||
39 | #define SDHCI_TRANSFER_MODE 0x0C | |
40 | #define SDHCI_TRNS_DMA 0x01 | |
41 | #define SDHCI_TRNS_BLK_CNT_EN 0x02 | |
e89d456f | 42 | #define SDHCI_TRNS_AUTO_CMD12 0x04 |
8edf6371 | 43 | #define SDHCI_TRNS_AUTO_CMD23 0x08 |
d129bceb PO |
44 | #define SDHCI_TRNS_READ 0x10 |
45 | #define SDHCI_TRNS_MULTI 0x20 | |
46 | ||
47 | #define SDHCI_COMMAND 0x0E | |
48 | #define SDHCI_CMD_RESP_MASK 0x03 | |
49 | #define SDHCI_CMD_CRC 0x08 | |
50 | #define SDHCI_CMD_INDEX 0x10 | |
51 | #define SDHCI_CMD_DATA 0x20 | |
574e3f56 | 52 | #define SDHCI_CMD_ABORTCMD 0xC0 |
d129bceb PO |
53 | |
54 | #define SDHCI_CMD_RESP_NONE 0x00 | |
55 | #define SDHCI_CMD_RESP_LONG 0x01 | |
56 | #define SDHCI_CMD_RESP_SHORT 0x02 | |
57 | #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 | |
58 | ||
59 | #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) | |
22113efd | 60 | #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) |
d129bceb PO |
61 | |
62 | #define SDHCI_RESPONSE 0x10 | |
63 | ||
64 | #define SDHCI_BUFFER 0x20 | |
65 | ||
66 | #define SDHCI_PRESENT_STATE 0x24 | |
67 | #define SDHCI_CMD_INHIBIT 0x00000001 | |
68 | #define SDHCI_DATA_INHIBIT 0x00000002 | |
69 | #define SDHCI_DOING_WRITE 0x00000100 | |
70 | #define SDHCI_DOING_READ 0x00000200 | |
71 | #define SDHCI_SPACE_AVAILABLE 0x00000400 | |
72 | #define SDHCI_DATA_AVAILABLE 0x00000800 | |
73 | #define SDHCI_CARD_PRESENT 0x00010000 | |
74 | #define SDHCI_WRITE_PROTECT 0x00080000 | |
f2119df6 AN |
75 | #define SDHCI_DATA_LVL_MASK 0x00F00000 |
76 | #define SDHCI_DATA_LVL_SHIFT 20 | |
7756a96d | 77 | #define SDHCI_DATA_0_LVL_MASK 0x00100000 |
b0921d5c | 78 | #define SDHCI_CMD_LVL 0x01000000 |
d129bceb | 79 | |
d6d50a15 | 80 | #define SDHCI_HOST_CONTROL 0x28 |
d129bceb PO |
81 | #define SDHCI_CTRL_LED 0x01 |
82 | #define SDHCI_CTRL_4BITBUS 0x02 | |
077df884 | 83 | #define SDHCI_CTRL_HISPD 0x04 |
2134a922 PO |
84 | #define SDHCI_CTRL_DMA_MASK 0x18 |
85 | #define SDHCI_CTRL_SDMA 0x00 | |
86 | #define SDHCI_CTRL_ADMA1 0x08 | |
87 | #define SDHCI_CTRL_ADMA32 0x10 | |
88 | #define SDHCI_CTRL_ADMA64 0x18 | |
15ec4461 | 89 | #define SDHCI_CTRL_8BITBUS 0x20 |
3794c542 ZB |
90 | #define SDHCI_CTRL_CDTEST_INS 0x40 |
91 | #define SDHCI_CTRL_CDTEST_EN 0x80 | |
d129bceb PO |
92 | |
93 | #define SDHCI_POWER_CONTROL 0x29 | |
146ad66e PO |
94 | #define SDHCI_POWER_ON 0x01 |
95 | #define SDHCI_POWER_180 0x0A | |
96 | #define SDHCI_POWER_300 0x0C | |
97 | #define SDHCI_POWER_330 0x0E | |
d129bceb PO |
98 | |
99 | #define SDHCI_BLOCK_GAP_CONTROL 0x2A | |
100 | ||
2df3b71b | 101 | #define SDHCI_WAKE_UP_CONTROL 0x2B |
5f619704 DD |
102 | #define SDHCI_WAKE_ON_INT 0x01 |
103 | #define SDHCI_WAKE_ON_INSERT 0x02 | |
104 | #define SDHCI_WAKE_ON_REMOVE 0x04 | |
d129bceb PO |
105 | |
106 | #define SDHCI_CLOCK_CONTROL 0x2C | |
107 | #define SDHCI_DIVIDER_SHIFT 8 | |
85105c53 ZG |
108 | #define SDHCI_DIVIDER_HI_SHIFT 6 |
109 | #define SDHCI_DIV_MASK 0xFF | |
110 | #define SDHCI_DIV_MASK_LEN 8 | |
111 | #define SDHCI_DIV_HI_MASK 0x300 | |
c3ed3877 | 112 | #define SDHCI_PROG_CLOCK_MODE 0x0020 |
d129bceb PO |
113 | #define SDHCI_CLOCK_CARD_EN 0x0004 |
114 | #define SDHCI_CLOCK_INT_STABLE 0x0002 | |
115 | #define SDHCI_CLOCK_INT_EN 0x0001 | |
116 | ||
117 | #define SDHCI_TIMEOUT_CONTROL 0x2E | |
118 | ||
119 | #define SDHCI_SOFTWARE_RESET 0x2F | |
120 | #define SDHCI_RESET_ALL 0x01 | |
121 | #define SDHCI_RESET_CMD 0x02 | |
122 | #define SDHCI_RESET_DATA 0x04 | |
123 | ||
124 | #define SDHCI_INT_STATUS 0x30 | |
125 | #define SDHCI_INT_ENABLE 0x34 | |
126 | #define SDHCI_SIGNAL_ENABLE 0x38 | |
127 | #define SDHCI_INT_RESPONSE 0x00000001 | |
128 | #define SDHCI_INT_DATA_END 0x00000002 | |
a4071fbb | 129 | #define SDHCI_INT_BLK_GAP 0x00000004 |
d129bceb | 130 | #define SDHCI_INT_DMA_END 0x00000008 |
a406f5a3 PO |
131 | #define SDHCI_INT_SPACE_AVAIL 0x00000010 |
132 | #define SDHCI_INT_DATA_AVAIL 0x00000020 | |
d129bceb PO |
133 | #define SDHCI_INT_CARD_INSERT 0x00000040 |
134 | #define SDHCI_INT_CARD_REMOVE 0x00000080 | |
135 | #define SDHCI_INT_CARD_INT 0x00000100 | |
f37b20eb | 136 | #define SDHCI_INT_RETUNE 0x00001000 |
f12e39db | 137 | #define SDHCI_INT_CQE 0x00004000 |
964f9ce2 | 138 | #define SDHCI_INT_ERROR 0x00008000 |
d129bceb PO |
139 | #define SDHCI_INT_TIMEOUT 0x00010000 |
140 | #define SDHCI_INT_CRC 0x00020000 | |
141 | #define SDHCI_INT_END_BIT 0x00040000 | |
142 | #define SDHCI_INT_INDEX 0x00080000 | |
143 | #define SDHCI_INT_DATA_TIMEOUT 0x00100000 | |
144 | #define SDHCI_INT_DATA_CRC 0x00200000 | |
145 | #define SDHCI_INT_DATA_END_BIT 0x00400000 | |
146 | #define SDHCI_INT_BUS_POWER 0x00800000 | |
147 | #define SDHCI_INT_ACMD12ERR 0x01000000 | |
2134a922 | 148 | #define SDHCI_INT_ADMA_ERROR 0x02000000 |
d129bceb PO |
149 | |
150 | #define SDHCI_INT_NORMAL_MASK 0x00007FFF | |
151 | #define SDHCI_INT_ERROR_MASK 0xFFFF8000 | |
152 | ||
153 | #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ | |
154 | SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) | |
155 | #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ | |
a406f5a3 | 156 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ |
d129bceb | 157 | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ |
a4071fbb HZ |
158 | SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ |
159 | SDHCI_INT_BLK_GAP) | |
7260cf5e | 160 | #define SDHCI_INT_ALL_MASK ((unsigned int)-1) |
d129bceb | 161 | |
f12e39db AH |
162 | #define SDHCI_CQE_INT_ERR_MASK ( \ |
163 | SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \ | |
164 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \ | |
165 | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT) | |
166 | ||
167 | #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE) | |
168 | ||
d129bceb PO |
169 | #define SDHCI_ACMD12_ERR 0x3C |
170 | ||
f2119df6 | 171 | #define SDHCI_HOST_CONTROL2 0x3E |
49c468fc AN |
172 | #define SDHCI_CTRL_UHS_MASK 0x0007 |
173 | #define SDHCI_CTRL_UHS_SDR12 0x0000 | |
174 | #define SDHCI_CTRL_UHS_SDR25 0x0001 | |
175 | #define SDHCI_CTRL_UHS_SDR50 0x0002 | |
176 | #define SDHCI_CTRL_UHS_SDR104 0x0003 | |
177 | #define SDHCI_CTRL_UHS_DDR50 0x0004 | |
e9fb05d5 | 178 | #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ |
f2119df6 | 179 | #define SDHCI_CTRL_VDD_180 0x0008 |
d6d50a15 AN |
180 | #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 |
181 | #define SDHCI_CTRL_DRV_TYPE_B 0x0000 | |
182 | #define SDHCI_CTRL_DRV_TYPE_A 0x0010 | |
183 | #define SDHCI_CTRL_DRV_TYPE_C 0x0020 | |
184 | #define SDHCI_CTRL_DRV_TYPE_D 0x0030 | |
b513ea25 AN |
185 | #define SDHCI_CTRL_EXEC_TUNING 0x0040 |
186 | #define SDHCI_CTRL_TUNED_CLK 0x0080 | |
d6d50a15 | 187 | #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 |
d129bceb PO |
188 | |
189 | #define SDHCI_CAPABILITIES 0x40 | |
1c8cde92 PO |
190 | #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F |
191 | #define SDHCI_TIMEOUT_CLK_SHIFT 0 | |
192 | #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 | |
d129bceb | 193 | #define SDHCI_CLOCK_BASE_MASK 0x00003F00 |
c4687d5f | 194 | #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 |
d129bceb | 195 | #define SDHCI_CLOCK_BASE_SHIFT 8 |
1d676e02 PO |
196 | #define SDHCI_MAX_BLOCK_MASK 0x00030000 |
197 | #define SDHCI_MAX_BLOCK_SHIFT 16 | |
15ec4461 | 198 | #define SDHCI_CAN_DO_8BIT 0x00040000 |
2134a922 PO |
199 | #define SDHCI_CAN_DO_ADMA2 0x00080000 |
200 | #define SDHCI_CAN_DO_ADMA1 0x00100000 | |
077df884 | 201 | #define SDHCI_CAN_DO_HISPD 0x00200000 |
a13abc7b | 202 | #define SDHCI_CAN_DO_SDMA 0x00400000 |
e71d4b81 | 203 | #define SDHCI_CAN_DO_SUSPEND 0x00800000 |
146ad66e PO |
204 | #define SDHCI_CAN_VDD_330 0x01000000 |
205 | #define SDHCI_CAN_VDD_300 0x02000000 | |
206 | #define SDHCI_CAN_VDD_180 0x04000000 | |
2134a922 | 207 | #define SDHCI_CAN_64BIT 0x10000000 |
d129bceb | 208 | |
f2119df6 AN |
209 | #define SDHCI_SUPPORT_SDR50 0x00000001 |
210 | #define SDHCI_SUPPORT_SDR104 0x00000002 | |
211 | #define SDHCI_SUPPORT_DDR50 0x00000004 | |
d6d50a15 AN |
212 | #define SDHCI_DRIVER_TYPE_A 0x00000010 |
213 | #define SDHCI_DRIVER_TYPE_C 0x00000020 | |
214 | #define SDHCI_DRIVER_TYPE_D 0x00000040 | |
cf2b5eea AN |
215 | #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 |
216 | #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 | |
217 | #define SDHCI_USE_SDR50_TUNING 0x00002000 | |
218 | #define SDHCI_RETUNING_MODE_MASK 0x0000C000 | |
219 | #define SDHCI_RETUNING_MODE_SHIFT 14 | |
c3ed3877 AN |
220 | #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 |
221 | #define SDHCI_CLOCK_MUL_SHIFT 16 | |
e9fb05d5 | 222 | #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ |
f2119df6 | 223 | |
e8120ad1 | 224 | #define SDHCI_CAPABILITIES_1 0x44 |
d129bceb | 225 | |
f2119df6 | 226 | #define SDHCI_MAX_CURRENT 0x48 |
bad37e1a | 227 | #define SDHCI_MAX_CURRENT_LIMIT 0xFF |
f2119df6 AN |
228 | #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF |
229 | #define SDHCI_MAX_CURRENT_330_SHIFT 0 | |
230 | #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 | |
231 | #define SDHCI_MAX_CURRENT_300_SHIFT 8 | |
232 | #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 | |
233 | #define SDHCI_MAX_CURRENT_180_SHIFT 16 | |
234 | #define SDHCI_MAX_CURRENT_MULTIPLIER 4 | |
d129bceb PO |
235 | |
236 | /* 4C-4F reserved for more max current */ | |
237 | ||
2134a922 PO |
238 | #define SDHCI_SET_ACMD12_ERROR 0x50 |
239 | #define SDHCI_SET_INT_ERROR 0x52 | |
240 | ||
241 | #define SDHCI_ADMA_ERROR 0x54 | |
242 | ||
243 | /* 55-57 reserved */ | |
244 | ||
245 | #define SDHCI_ADMA_ADDRESS 0x58 | |
e57a5f61 | 246 | #define SDHCI_ADMA_ADDRESS_HI 0x5C |
2134a922 PO |
247 | |
248 | /* 60-FB reserved */ | |
d129bceb | 249 | |
52983382 KL |
250 | #define SDHCI_PRESET_FOR_SDR12 0x66 |
251 | #define SDHCI_PRESET_FOR_SDR25 0x68 | |
252 | #define SDHCI_PRESET_FOR_SDR50 0x6A | |
253 | #define SDHCI_PRESET_FOR_SDR104 0x6C | |
254 | #define SDHCI_PRESET_FOR_DDR50 0x6E | |
e9fb05d5 | 255 | #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ |
52983382 KL |
256 | #define SDHCI_PRESET_DRV_MASK 0xC000 |
257 | #define SDHCI_PRESET_DRV_SHIFT 14 | |
258 | #define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400 | |
259 | #define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10 | |
260 | #define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF | |
261 | #define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 | |
262 | ||
d129bceb PO |
263 | #define SDHCI_SLOT_INT_STATUS 0xFC |
264 | ||
265 | #define SDHCI_HOST_VERSION 0xFE | |
4a965505 PO |
266 | #define SDHCI_VENDOR_VER_MASK 0xFF00 |
267 | #define SDHCI_VENDOR_VER_SHIFT 8 | |
268 | #define SDHCI_SPEC_VER_MASK 0x00FF | |
269 | #define SDHCI_SPEC_VER_SHIFT 0 | |
2134a922 PO |
270 | #define SDHCI_SPEC_100 0 |
271 | #define SDHCI_SPEC_200 1 | |
85105c53 | 272 | #define SDHCI_SPEC_300 2 |
d129bceb | 273 | |
0397526d ZG |
274 | /* |
275 | * End of controller registers. | |
276 | */ | |
277 | ||
278 | #define SDHCI_MAX_DIV_SPEC_200 256 | |
279 | #define SDHCI_MAX_DIV_SPEC_300 2046 | |
280 | ||
f6a03cbf MV |
281 | /* |
282 | * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. | |
283 | */ | |
284 | #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) | |
285 | #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) | |
286 | ||
739d46dc AH |
287 | /* ADMA2 32-bit DMA descriptor size */ |
288 | #define SDHCI_ADMA2_32_DESC_SZ 8 | |
289 | ||
0545230f AH |
290 | /* ADMA2 32-bit descriptor */ |
291 | struct sdhci_adma2_32_desc { | |
292 | __le16 cmd; | |
293 | __le16 len; | |
294 | __le32 addr; | |
04a5ae6f AH |
295 | } __packed __aligned(4); |
296 | ||
297 | /* ADMA2 data alignment */ | |
298 | #define SDHCI_ADMA2_ALIGN 4 | |
299 | #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) | |
300 | ||
301 | /* | |
302 | * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte | |
303 | * alignment for the descriptor table even in 32-bit DMA mode. Memory | |
304 | * allocation is at least 8 byte aligned anyway, so just stipulate 8 always. | |
305 | */ | |
306 | #define SDHCI_ADMA2_DESC_ALIGN 8 | |
0545230f | 307 | |
e57a5f61 AH |
308 | /* ADMA2 64-bit DMA descriptor size */ |
309 | #define SDHCI_ADMA2_64_DESC_SZ 12 | |
310 | ||
e57a5f61 AH |
311 | /* |
312 | * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte | |
313 | * aligned. | |
314 | */ | |
315 | struct sdhci_adma2_64_desc { | |
316 | __le16 cmd; | |
317 | __le16 len; | |
318 | __le32 addr_lo; | |
319 | __le32 addr_hi; | |
320 | } __packed __aligned(4); | |
321 | ||
739d46dc AH |
322 | #define ADMA2_TRAN_VALID 0x21 |
323 | #define ADMA2_NOP_END_VALID 0x3 | |
324 | #define ADMA2_END 0x2 | |
325 | ||
4fb213f8 AH |
326 | /* |
327 | * Maximum segments assuming a 512KiB maximum requisition size and a minimum | |
328 | * 4KiB page size. | |
329 | */ | |
330 | #define SDHCI_MAX_SEGS 128 | |
331 | ||
4e9f8fe5 AH |
332 | /* Allow for a a command request and a data request at the same time */ |
333 | #define SDHCI_MAX_MRQS 2 | |
334 | ||
d31911b9 HC |
335 | enum sdhci_cookie { |
336 | COOKIE_UNMAPPED, | |
94538e51 RK |
337 | COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ |
338 | COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ | |
83f13cc9 UH |
339 | }; |
340 | ||
341 | struct sdhci_host { | |
342 | /* Data set by hardware interface driver */ | |
343 | const char *hw_name; /* Hardware bus name */ | |
344 | ||
345 | unsigned int quirks; /* Deviations from spec. */ | |
346 | ||
347 | /* Controller doesn't honor resets unless we touch the clock register */ | |
348 | #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) | |
349 | /* Controller has bad caps bits, but really supports DMA */ | |
350 | #define SDHCI_QUIRK_FORCE_DMA (1<<1) | |
351 | /* Controller doesn't like to be reset when there is no card inserted. */ | |
352 | #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) | |
353 | /* Controller doesn't like clearing the power reg before a change */ | |
354 | #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) | |
355 | /* Controller has flaky internal state so reset it on each ios change */ | |
356 | #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) | |
357 | /* Controller has an unusable DMA engine */ | |
358 | #define SDHCI_QUIRK_BROKEN_DMA (1<<5) | |
359 | /* Controller has an unusable ADMA engine */ | |
360 | #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) | |
361 | /* Controller can only DMA from 32-bit aligned addresses */ | |
362 | #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) | |
363 | /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ | |
364 | #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) | |
365 | /* Controller can only ADMA chunks that are a multiple of 32 bits */ | |
366 | #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) | |
367 | /* Controller needs to be reset after each request to stay stable */ | |
368 | #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) | |
369 | /* Controller needs voltage and power writes to happen separately */ | |
370 | #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) | |
371 | /* Controller provides an incorrect timeout value for transfers */ | |
372 | #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) | |
373 | /* Controller has an issue with buffer bits for small transfers */ | |
374 | #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) | |
375 | /* Controller does not provide transfer-complete interrupt when not busy */ | |
376 | #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) | |
377 | /* Controller has unreliable card detection */ | |
378 | #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) | |
379 | /* Controller reports inverted write-protect state */ | |
380 | #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) | |
381 | /* Controller does not like fast PIO transfers */ | |
382 | #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) | |
383 | /* Controller has to be forced to use block size of 2048 bytes */ | |
384 | #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) | |
385 | /* Controller cannot do multi-block transfers */ | |
386 | #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) | |
387 | /* Controller can only handle 1-bit data transfers */ | |
388 | #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) | |
389 | /* Controller needs 10ms delay between applying power and clock */ | |
390 | #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) | |
391 | /* Controller uses SDCLK instead of TMCLK for data timeouts */ | |
392 | #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) | |
393 | /* Controller reports wrong base clock capability */ | |
394 | #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) | |
395 | /* Controller cannot support End Attribute in NOP ADMA descriptor */ | |
396 | #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) | |
397 | /* Controller is missing device caps. Use caps provided by host */ | |
398 | #define SDHCI_QUIRK_MISSING_CAPS (1<<27) | |
399 | /* Controller uses Auto CMD12 command to stop the transfer */ | |
400 | #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) | |
401 | /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ | |
402 | #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) | |
403 | /* Controller treats ADMA descriptors with length 0000h incorrectly */ | |
404 | #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) | |
405 | /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ | |
406 | #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) | |
407 | ||
408 | unsigned int quirks2; /* More deviations from spec. */ | |
409 | ||
410 | #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) | |
411 | #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) | |
412 | /* The system physically doesn't support 1.8v, even if the host does */ | |
413 | #define SDHCI_QUIRK2_NO_1_8_V (1<<2) | |
414 | #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) | |
415 | #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) | |
416 | /* Controller has a non-standard host control register */ | |
417 | #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) | |
418 | /* Controller does not support HS200 */ | |
419 | #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) | |
420 | /* Controller does not support DDR50 */ | |
421 | #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) | |
422 | /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ | |
423 | #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) | |
424 | /* Controller does not support 64-bit DMA */ | |
425 | #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) | |
426 | /* need clear transfer mode register before send cmd */ | |
427 | #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) | |
428 | /* Capability register bit-63 indicates HS400 support */ | |
429 | #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) | |
430 | /* forced tuned clock */ | |
431 | #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) | |
432 | /* disable the block count for single block transactions */ | |
433 | #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) | |
434 | /* Controller broken with using ACMD23 */ | |
435 | #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) | |
d1955c3a SG |
436 | /* Broken Clock divider zero in controller */ |
437 | #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) | |
1284c248 KVA |
438 | /* Controller has CRC in 136 bit Command Response */ |
439 | #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) | |
83f13cc9 UH |
440 | |
441 | int irq; /* Device IRQ */ | |
442 | void __iomem *ioaddr; /* Mapped address */ | |
443 | ||
444 | const struct sdhci_ops *ops; /* Low level hw interface */ | |
445 | ||
446 | /* Internal data */ | |
447 | struct mmc_host *mmc; /* MMC structure */ | |
bf60e592 | 448 | struct mmc_host_ops mmc_host_ops; /* MMC host ops */ |
83f13cc9 UH |
449 | u64 dma_mask; /* custom DMA mask */ |
450 | ||
74479c5d | 451 | #if IS_ENABLED(CONFIG_LEDS_CLASS) |
83f13cc9 UH |
452 | struct led_classdev led; /* LED control */ |
453 | char led_name[32]; | |
454 | #endif | |
455 | ||
456 | spinlock_t lock; /* Mutex */ | |
457 | ||
458 | int flags; /* Host attributes */ | |
459 | #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ | |
460 | #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ | |
461 | #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ | |
462 | #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ | |
463 | #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ | |
83f13cc9 UH |
464 | #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ |
465 | #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ | |
466 | #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ | |
467 | #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ | |
83f13cc9 UH |
468 | #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ |
469 | #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ | |
8cb851a4 AH |
470 | #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ |
471 | #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ | |
472 | #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ | |
83f13cc9 UH |
473 | |
474 | unsigned int version; /* SDHCI spec. version */ | |
475 | ||
476 | unsigned int max_clk; /* Max possible freq (MHz) */ | |
477 | unsigned int timeout_clk; /* Timeout freq (KHz) */ | |
478 | unsigned int clk_mul; /* Clock Muliplier value */ | |
479 | ||
480 | unsigned int clock; /* Current clock (MHz) */ | |
481 | u8 pwr; /* Current voltage */ | |
482 | ||
483 | bool runtime_suspended; /* Host is runtime suspended */ | |
484 | bool bus_on; /* Bus power prevents runtime suspend */ | |
485 | bool preset_enabled; /* Preset is enabled */ | |
ed1563de | 486 | bool pending_reset; /* Cmd/data reset is pending */ |
58e79b60 | 487 | bool irq_wake_enabled; /* IRQ wakeup is enabled */ |
83f13cc9 | 488 | |
4e9f8fe5 | 489 | struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ |
83f13cc9 | 490 | struct mmc_command *cmd; /* Current command */ |
7c89a3d9 | 491 | struct mmc_command *data_cmd; /* Current data command */ |
83f13cc9 UH |
492 | struct mmc_data *data; /* Current data request */ |
493 | unsigned int data_early:1; /* Data finished before cmd */ | |
83f13cc9 UH |
494 | |
495 | struct sg_mapping_iter sg_miter; /* SG state for PIO */ | |
496 | unsigned int blocks; /* remaining PIO blocks */ | |
497 | ||
498 | int sg_count; /* Mapped sg entries */ | |
499 | ||
500 | void *adma_table; /* ADMA descriptor table */ | |
501 | void *align_buffer; /* Bounce buffer */ | |
502 | ||
503 | size_t adma_table_sz; /* ADMA descriptor table size */ | |
504 | size_t align_buffer_sz; /* Bounce buffer size */ | |
505 | ||
506 | dma_addr_t adma_addr; /* Mapped ADMA descr. table */ | |
507 | dma_addr_t align_addr; /* Mapped bounce buffer */ | |
508 | ||
509 | unsigned int desc_sz; /* ADMA descriptor size */ | |
83f13cc9 UH |
510 | |
511 | struct tasklet_struct finish_tasklet; /* Tasklet structures */ | |
512 | ||
513 | struct timer_list timer; /* Timer for timeouts */ | |
d7422fb4 | 514 | struct timer_list data_timer; /* Timer for data timeouts */ |
83f13cc9 | 515 | |
28da3589 AH |
516 | u32 caps; /* CAPABILITY_0 */ |
517 | u32 caps1; /* CAPABILITY_1 */ | |
6132a3bf | 518 | bool read_caps; /* Capability flags have been read */ |
83f13cc9 UH |
519 | |
520 | unsigned int ocr_avail_sdio; /* OCR bit masks */ | |
521 | unsigned int ocr_avail_sd; | |
522 | unsigned int ocr_avail_mmc; | |
523 | u32 ocr_mask; /* available voltages */ | |
524 | ||
525 | unsigned timing; /* Current timing */ | |
526 | ||
527 | u32 thread_isr; | |
528 | ||
529 | /* cached registers */ | |
530 | u32 ier; | |
531 | ||
f12e39db AH |
532 | bool cqe_on; /* CQE is operating */ |
533 | u32 cqe_ier; /* CQE interrupt mask */ | |
534 | u32 cqe_err_ier; /* CQE error interrupt mask */ | |
535 | ||
83f13cc9 UH |
536 | wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ |
537 | unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ | |
538 | ||
539 | unsigned int tuning_count; /* Timer count for re-tuning */ | |
540 | unsigned int tuning_mode; /* Re-tuning mode supported by host */ | |
541 | #define SDHCI_TUNING_MODE_1 0 | |
f37b20eb DA |
542 | #define SDHCI_TUNING_MODE_2 1 |
543 | #define SDHCI_TUNING_MODE_3 2 | |
83b600b8 AH |
544 | /* Delay (ms) between tuning commands */ |
545 | int tuning_delay; | |
83f13cc9 | 546 | |
c846a00f SK |
547 | /* Host SDMA buffer boundary. */ |
548 | u32 sdma_boundary; | |
549 | ||
83f13cc9 UH |
550 | unsigned long private[0] ____cacheline_aligned; |
551 | }; | |
552 | ||
b8c86fc5 | 553 | struct sdhci_ops { |
4e4141a5 | 554 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
dc297c92 MF |
555 | u32 (*read_l)(struct sdhci_host *host, int reg); |
556 | u16 (*read_w)(struct sdhci_host *host, int reg); | |
557 | u8 (*read_b)(struct sdhci_host *host, int reg); | |
558 | void (*write_l)(struct sdhci_host *host, u32 val, int reg); | |
559 | void (*write_w)(struct sdhci_host *host, u16 val, int reg); | |
560 | void (*write_b)(struct sdhci_host *host, u8 val, int reg); | |
4e4141a5 AV |
561 | #endif |
562 | ||
8114634c | 563 | void (*set_clock)(struct sdhci_host *host, unsigned int clock); |
1dceb041 AH |
564 | void (*set_power)(struct sdhci_host *host, unsigned char mode, |
565 | unsigned short vdd); | |
8114634c | 566 | |
f12e39db AH |
567 | u32 (*irq)(struct sdhci_host *host, u32 intmask); |
568 | ||
b8c86fc5 | 569 | int (*enable_dma)(struct sdhci_host *host); |
4240ff0a | 570 | unsigned int (*get_max_clock)(struct sdhci_host *host); |
a9e58f25 | 571 | unsigned int (*get_min_clock)(struct sdhci_host *host); |
8cc35289 | 572 | /* get_timeout_clock should return clk rate in unit of Hz */ |
4240ff0a | 573 | unsigned int (*get_timeout_clock)(struct sdhci_host *host); |
a6ff5aeb | 574 | unsigned int (*get_max_timeout_count)(struct sdhci_host *host); |
b45e668a AD |
575 | void (*set_timeout)(struct sdhci_host *host, |
576 | struct mmc_command *cmd); | |
2317f56c | 577 | void (*set_bus_width)(struct sdhci_host *host, int width); |
643a81ff PR |
578 | void (*platform_send_init_74_clocks)(struct sdhci_host *host, |
579 | u8 power_mode); | |
2dfb579c | 580 | unsigned int (*get_ro)(struct sdhci_host *host); |
03231f9b | 581 | void (*reset)(struct sdhci_host *host, u8 mask); |
45251812 | 582 | int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); |
13e64501 | 583 | void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); |
20758b66 | 584 | void (*hw_reset)(struct sdhci_host *host); |
a4071fbb | 585 | void (*adma_workaround)(struct sdhci_host *host, u32 intmask); |
722e1280 | 586 | void (*card_event)(struct sdhci_host *host); |
9d967a61 | 587 | void (*voltage_switch)(struct sdhci_host *host); |
d129bceb | 588 | }; |
b8c86fc5 | 589 | |
4e4141a5 AV |
590 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
591 | ||
592 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) | |
593 | { | |
dc297c92 MF |
594 | if (unlikely(host->ops->write_l)) |
595 | host->ops->write_l(host, val, reg); | |
4e4141a5 AV |
596 | else |
597 | writel(val, host->ioaddr + reg); | |
598 | } | |
599 | ||
600 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) | |
601 | { | |
dc297c92 MF |
602 | if (unlikely(host->ops->write_w)) |
603 | host->ops->write_w(host, val, reg); | |
4e4141a5 AV |
604 | else |
605 | writew(val, host->ioaddr + reg); | |
606 | } | |
607 | ||
608 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) | |
609 | { | |
dc297c92 MF |
610 | if (unlikely(host->ops->write_b)) |
611 | host->ops->write_b(host, val, reg); | |
4e4141a5 AV |
612 | else |
613 | writeb(val, host->ioaddr + reg); | |
614 | } | |
615 | ||
616 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) | |
617 | { | |
dc297c92 MF |
618 | if (unlikely(host->ops->read_l)) |
619 | return host->ops->read_l(host, reg); | |
4e4141a5 AV |
620 | else |
621 | return readl(host->ioaddr + reg); | |
622 | } | |
623 | ||
624 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) | |
625 | { | |
dc297c92 MF |
626 | if (unlikely(host->ops->read_w)) |
627 | return host->ops->read_w(host, reg); | |
4e4141a5 AV |
628 | else |
629 | return readw(host->ioaddr + reg); | |
630 | } | |
631 | ||
632 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) | |
633 | { | |
dc297c92 MF |
634 | if (unlikely(host->ops->read_b)) |
635 | return host->ops->read_b(host, reg); | |
4e4141a5 AV |
636 | else |
637 | return readb(host->ioaddr + reg); | |
638 | } | |
639 | ||
640 | #else | |
641 | ||
642 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) | |
643 | { | |
644 | writel(val, host->ioaddr + reg); | |
645 | } | |
646 | ||
647 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) | |
648 | { | |
649 | writew(val, host->ioaddr + reg); | |
650 | } | |
651 | ||
652 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) | |
653 | { | |
654 | writeb(val, host->ioaddr + reg); | |
655 | } | |
656 | ||
657 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) | |
658 | { | |
659 | return readl(host->ioaddr + reg); | |
660 | } | |
661 | ||
662 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) | |
663 | { | |
664 | return readw(host->ioaddr + reg); | |
665 | } | |
666 | ||
667 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) | |
668 | { | |
669 | return readb(host->ioaddr + reg); | |
670 | } | |
671 | ||
672 | #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ | |
b8c86fc5 | 673 | |
15becf68 AH |
674 | struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size); |
675 | void sdhci_free_host(struct sdhci_host *host); | |
b8c86fc5 PO |
676 | |
677 | static inline void *sdhci_priv(struct sdhci_host *host) | |
678 | { | |
178b0fa0 | 679 | return host->private; |
b8c86fc5 PO |
680 | } |
681 | ||
15becf68 AH |
682 | void sdhci_card_detect(struct sdhci_host *host); |
683 | void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, | |
684 | u32 *caps1); | |
685 | int sdhci_setup_host(struct sdhci_host *host); | |
4180ffa8 | 686 | void sdhci_cleanup_host(struct sdhci_host *host); |
15becf68 AH |
687 | int __sdhci_add_host(struct sdhci_host *host); |
688 | int sdhci_add_host(struct sdhci_host *host); | |
689 | void sdhci_remove_host(struct sdhci_host *host, int dead); | |
690 | void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); | |
b8c86fc5 | 691 | |
6132a3bf AH |
692 | static inline void sdhci_read_caps(struct sdhci_host *host) |
693 | { | |
694 | __sdhci_read_caps(host, NULL, NULL, NULL); | |
695 | } | |
696 | ||
be138554 RK |
697 | static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) |
698 | { | |
699 | return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); | |
700 | } | |
701 | ||
fb9ee047 LD |
702 | u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, |
703 | unsigned int *actual_clock); | |
1771059c | 704 | void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); |
fec79673 | 705 | void sdhci_enable_clk(struct sdhci_host *host, u16 clk); |
1dceb041 AH |
706 | void sdhci_set_power(struct sdhci_host *host, unsigned char mode, |
707 | unsigned short vdd); | |
606d3131 AH |
708 | void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, |
709 | unsigned short vdd); | |
2317f56c | 710 | void sdhci_set_bus_width(struct sdhci_host *host, int width); |
03231f9b | 711 | void sdhci_reset(struct sdhci_host *host, u8 mask); |
96d7b78c | 712 | void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); |
85a882c2 | 713 | int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); |
6a6d4ceb | 714 | void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); |
c376ea9e HZ |
715 | int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, |
716 | struct mmc_ios *ios); | |
2f05b6ab | 717 | void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); |
2317f56c | 718 | |
b8c86fc5 | 719 | #ifdef CONFIG_PM |
15becf68 AH |
720 | int sdhci_suspend_host(struct sdhci_host *host); |
721 | int sdhci_resume_host(struct sdhci_host *host); | |
15becf68 AH |
722 | int sdhci_runtime_suspend_host(struct sdhci_host *host); |
723 | int sdhci_runtime_resume_host(struct sdhci_host *host); | |
66fd8ad5 AH |
724 | #endif |
725 | ||
f12e39db AH |
726 | void sdhci_cqe_enable(struct mmc_host *mmc); |
727 | void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery); | |
728 | bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, | |
729 | int *data_error); | |
730 | ||
d2898172 AH |
731 | void sdhci_dumpregs(struct sdhci_host *host); |
732 | ||
1978fda8 | 733 | #endif /* __SDHCI_HW_H */ |