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d129bceb | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver |
d129bceb | 3 | * |
1978fda8 GC |
4 | * Header file for Host Controller registers and I/O accessors. |
5 | * | |
b69c9058 | 6 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
d129bceb PO |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
9 | * it under the terms of the GNU General Public License as published by |
10 | * the Free Software Foundation; either version 2 of the License, or (at | |
11 | * your option) any later version. | |
d129bceb | 12 | */ |
1978fda8 GC |
13 | #ifndef __SDHCI_HW_H |
14 | #define __SDHCI_HW_H | |
d129bceb | 15 | |
0c7ad106 | 16 | #include <linux/scatterlist.h> |
4e4141a5 AV |
17 | #include <linux/compiler.h> |
18 | #include <linux/types.h> | |
19 | #include <linux/io.h> | |
0c7ad106 | 20 | |
83f13cc9 | 21 | #include <linux/mmc/host.h> |
1978fda8 | 22 | |
d129bceb PO |
23 | /* |
24 | * Controller registers | |
25 | */ | |
26 | ||
27 | #define SDHCI_DMA_ADDRESS 0x00 | |
8edf6371 | 28 | #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS |
d129bceb PO |
29 | |
30 | #define SDHCI_BLOCK_SIZE 0x04 | |
bab76961 | 31 | #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) |
d129bceb PO |
32 | |
33 | #define SDHCI_BLOCK_COUNT 0x06 | |
34 | ||
35 | #define SDHCI_ARGUMENT 0x08 | |
36 | ||
37 | #define SDHCI_TRANSFER_MODE 0x0C | |
38 | #define SDHCI_TRNS_DMA 0x01 | |
39 | #define SDHCI_TRNS_BLK_CNT_EN 0x02 | |
e89d456f | 40 | #define SDHCI_TRNS_AUTO_CMD12 0x04 |
8edf6371 | 41 | #define SDHCI_TRNS_AUTO_CMD23 0x08 |
d129bceb PO |
42 | #define SDHCI_TRNS_READ 0x10 |
43 | #define SDHCI_TRNS_MULTI 0x20 | |
44 | ||
45 | #define SDHCI_COMMAND 0x0E | |
46 | #define SDHCI_CMD_RESP_MASK 0x03 | |
47 | #define SDHCI_CMD_CRC 0x08 | |
48 | #define SDHCI_CMD_INDEX 0x10 | |
49 | #define SDHCI_CMD_DATA 0x20 | |
574e3f56 | 50 | #define SDHCI_CMD_ABORTCMD 0xC0 |
d129bceb PO |
51 | |
52 | #define SDHCI_CMD_RESP_NONE 0x00 | |
53 | #define SDHCI_CMD_RESP_LONG 0x01 | |
54 | #define SDHCI_CMD_RESP_SHORT 0x02 | |
55 | #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 | |
56 | ||
57 | #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) | |
22113efd | 58 | #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) |
d129bceb PO |
59 | |
60 | #define SDHCI_RESPONSE 0x10 | |
61 | ||
62 | #define SDHCI_BUFFER 0x20 | |
63 | ||
64 | #define SDHCI_PRESENT_STATE 0x24 | |
65 | #define SDHCI_CMD_INHIBIT 0x00000001 | |
66 | #define SDHCI_DATA_INHIBIT 0x00000002 | |
67 | #define SDHCI_DOING_WRITE 0x00000100 | |
68 | #define SDHCI_DOING_READ 0x00000200 | |
69 | #define SDHCI_SPACE_AVAILABLE 0x00000400 | |
70 | #define SDHCI_DATA_AVAILABLE 0x00000800 | |
71 | #define SDHCI_CARD_PRESENT 0x00010000 | |
72 | #define SDHCI_WRITE_PROTECT 0x00080000 | |
f2119df6 AN |
73 | #define SDHCI_DATA_LVL_MASK 0x00F00000 |
74 | #define SDHCI_DATA_LVL_SHIFT 20 | |
7756a96d | 75 | #define SDHCI_DATA_0_LVL_MASK 0x00100000 |
d129bceb | 76 | |
d6d50a15 | 77 | #define SDHCI_HOST_CONTROL 0x28 |
d129bceb PO |
78 | #define SDHCI_CTRL_LED 0x01 |
79 | #define SDHCI_CTRL_4BITBUS 0x02 | |
077df884 | 80 | #define SDHCI_CTRL_HISPD 0x04 |
2134a922 PO |
81 | #define SDHCI_CTRL_DMA_MASK 0x18 |
82 | #define SDHCI_CTRL_SDMA 0x00 | |
83 | #define SDHCI_CTRL_ADMA1 0x08 | |
84 | #define SDHCI_CTRL_ADMA32 0x10 | |
85 | #define SDHCI_CTRL_ADMA64 0x18 | |
15ec4461 | 86 | #define SDHCI_CTRL_8BITBUS 0x20 |
d129bceb PO |
87 | |
88 | #define SDHCI_POWER_CONTROL 0x29 | |
146ad66e PO |
89 | #define SDHCI_POWER_ON 0x01 |
90 | #define SDHCI_POWER_180 0x0A | |
91 | #define SDHCI_POWER_300 0x0C | |
92 | #define SDHCI_POWER_330 0x0E | |
d129bceb PO |
93 | |
94 | #define SDHCI_BLOCK_GAP_CONTROL 0x2A | |
95 | ||
2df3b71b | 96 | #define SDHCI_WAKE_UP_CONTROL 0x2B |
5f619704 DD |
97 | #define SDHCI_WAKE_ON_INT 0x01 |
98 | #define SDHCI_WAKE_ON_INSERT 0x02 | |
99 | #define SDHCI_WAKE_ON_REMOVE 0x04 | |
d129bceb PO |
100 | |
101 | #define SDHCI_CLOCK_CONTROL 0x2C | |
102 | #define SDHCI_DIVIDER_SHIFT 8 | |
85105c53 ZG |
103 | #define SDHCI_DIVIDER_HI_SHIFT 6 |
104 | #define SDHCI_DIV_MASK 0xFF | |
105 | #define SDHCI_DIV_MASK_LEN 8 | |
106 | #define SDHCI_DIV_HI_MASK 0x300 | |
c3ed3877 | 107 | #define SDHCI_PROG_CLOCK_MODE 0x0020 |
d129bceb PO |
108 | #define SDHCI_CLOCK_CARD_EN 0x0004 |
109 | #define SDHCI_CLOCK_INT_STABLE 0x0002 | |
110 | #define SDHCI_CLOCK_INT_EN 0x0001 | |
111 | ||
112 | #define SDHCI_TIMEOUT_CONTROL 0x2E | |
113 | ||
114 | #define SDHCI_SOFTWARE_RESET 0x2F | |
115 | #define SDHCI_RESET_ALL 0x01 | |
116 | #define SDHCI_RESET_CMD 0x02 | |
117 | #define SDHCI_RESET_DATA 0x04 | |
118 | ||
119 | #define SDHCI_INT_STATUS 0x30 | |
120 | #define SDHCI_INT_ENABLE 0x34 | |
121 | #define SDHCI_SIGNAL_ENABLE 0x38 | |
122 | #define SDHCI_INT_RESPONSE 0x00000001 | |
123 | #define SDHCI_INT_DATA_END 0x00000002 | |
a4071fbb | 124 | #define SDHCI_INT_BLK_GAP 0x00000004 |
d129bceb | 125 | #define SDHCI_INT_DMA_END 0x00000008 |
a406f5a3 PO |
126 | #define SDHCI_INT_SPACE_AVAIL 0x00000010 |
127 | #define SDHCI_INT_DATA_AVAIL 0x00000020 | |
d129bceb PO |
128 | #define SDHCI_INT_CARD_INSERT 0x00000040 |
129 | #define SDHCI_INT_CARD_REMOVE 0x00000080 | |
130 | #define SDHCI_INT_CARD_INT 0x00000100 | |
964f9ce2 | 131 | #define SDHCI_INT_ERROR 0x00008000 |
d129bceb PO |
132 | #define SDHCI_INT_TIMEOUT 0x00010000 |
133 | #define SDHCI_INT_CRC 0x00020000 | |
134 | #define SDHCI_INT_END_BIT 0x00040000 | |
135 | #define SDHCI_INT_INDEX 0x00080000 | |
136 | #define SDHCI_INT_DATA_TIMEOUT 0x00100000 | |
137 | #define SDHCI_INT_DATA_CRC 0x00200000 | |
138 | #define SDHCI_INT_DATA_END_BIT 0x00400000 | |
139 | #define SDHCI_INT_BUS_POWER 0x00800000 | |
140 | #define SDHCI_INT_ACMD12ERR 0x01000000 | |
2134a922 | 141 | #define SDHCI_INT_ADMA_ERROR 0x02000000 |
d129bceb PO |
142 | |
143 | #define SDHCI_INT_NORMAL_MASK 0x00007FFF | |
144 | #define SDHCI_INT_ERROR_MASK 0xFFFF8000 | |
145 | ||
146 | #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ | |
147 | SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) | |
148 | #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ | |
a406f5a3 | 149 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ |
d129bceb | 150 | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ |
a4071fbb HZ |
151 | SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ |
152 | SDHCI_INT_BLK_GAP) | |
7260cf5e | 153 | #define SDHCI_INT_ALL_MASK ((unsigned int)-1) |
d129bceb PO |
154 | |
155 | #define SDHCI_ACMD12_ERR 0x3C | |
156 | ||
f2119df6 | 157 | #define SDHCI_HOST_CONTROL2 0x3E |
49c468fc AN |
158 | #define SDHCI_CTRL_UHS_MASK 0x0007 |
159 | #define SDHCI_CTRL_UHS_SDR12 0x0000 | |
160 | #define SDHCI_CTRL_UHS_SDR25 0x0001 | |
161 | #define SDHCI_CTRL_UHS_SDR50 0x0002 | |
162 | #define SDHCI_CTRL_UHS_SDR104 0x0003 | |
163 | #define SDHCI_CTRL_UHS_DDR50 0x0004 | |
e9fb05d5 | 164 | #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ |
f2119df6 | 165 | #define SDHCI_CTRL_VDD_180 0x0008 |
d6d50a15 AN |
166 | #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 |
167 | #define SDHCI_CTRL_DRV_TYPE_B 0x0000 | |
168 | #define SDHCI_CTRL_DRV_TYPE_A 0x0010 | |
169 | #define SDHCI_CTRL_DRV_TYPE_C 0x0020 | |
170 | #define SDHCI_CTRL_DRV_TYPE_D 0x0030 | |
b513ea25 AN |
171 | #define SDHCI_CTRL_EXEC_TUNING 0x0040 |
172 | #define SDHCI_CTRL_TUNED_CLK 0x0080 | |
d6d50a15 | 173 | #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 |
d129bceb PO |
174 | |
175 | #define SDHCI_CAPABILITIES 0x40 | |
1c8cde92 PO |
176 | #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F |
177 | #define SDHCI_TIMEOUT_CLK_SHIFT 0 | |
178 | #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 | |
d129bceb | 179 | #define SDHCI_CLOCK_BASE_MASK 0x00003F00 |
c4687d5f | 180 | #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 |
d129bceb | 181 | #define SDHCI_CLOCK_BASE_SHIFT 8 |
1d676e02 PO |
182 | #define SDHCI_MAX_BLOCK_MASK 0x00030000 |
183 | #define SDHCI_MAX_BLOCK_SHIFT 16 | |
15ec4461 | 184 | #define SDHCI_CAN_DO_8BIT 0x00040000 |
2134a922 PO |
185 | #define SDHCI_CAN_DO_ADMA2 0x00080000 |
186 | #define SDHCI_CAN_DO_ADMA1 0x00100000 | |
077df884 | 187 | #define SDHCI_CAN_DO_HISPD 0x00200000 |
a13abc7b | 188 | #define SDHCI_CAN_DO_SDMA 0x00400000 |
146ad66e PO |
189 | #define SDHCI_CAN_VDD_330 0x01000000 |
190 | #define SDHCI_CAN_VDD_300 0x02000000 | |
191 | #define SDHCI_CAN_VDD_180 0x04000000 | |
2134a922 | 192 | #define SDHCI_CAN_64BIT 0x10000000 |
d129bceb | 193 | |
f2119df6 AN |
194 | #define SDHCI_SUPPORT_SDR50 0x00000001 |
195 | #define SDHCI_SUPPORT_SDR104 0x00000002 | |
196 | #define SDHCI_SUPPORT_DDR50 0x00000004 | |
d6d50a15 AN |
197 | #define SDHCI_DRIVER_TYPE_A 0x00000010 |
198 | #define SDHCI_DRIVER_TYPE_C 0x00000020 | |
199 | #define SDHCI_DRIVER_TYPE_D 0x00000040 | |
cf2b5eea AN |
200 | #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 |
201 | #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 | |
202 | #define SDHCI_USE_SDR50_TUNING 0x00002000 | |
203 | #define SDHCI_RETUNING_MODE_MASK 0x0000C000 | |
204 | #define SDHCI_RETUNING_MODE_SHIFT 14 | |
c3ed3877 AN |
205 | #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 |
206 | #define SDHCI_CLOCK_MUL_SHIFT 16 | |
e9fb05d5 | 207 | #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ |
f2119df6 | 208 | |
e8120ad1 | 209 | #define SDHCI_CAPABILITIES_1 0x44 |
d129bceb | 210 | |
f2119df6 | 211 | #define SDHCI_MAX_CURRENT 0x48 |
bad37e1a | 212 | #define SDHCI_MAX_CURRENT_LIMIT 0xFF |
f2119df6 AN |
213 | #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF |
214 | #define SDHCI_MAX_CURRENT_330_SHIFT 0 | |
215 | #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 | |
216 | #define SDHCI_MAX_CURRENT_300_SHIFT 8 | |
217 | #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 | |
218 | #define SDHCI_MAX_CURRENT_180_SHIFT 16 | |
219 | #define SDHCI_MAX_CURRENT_MULTIPLIER 4 | |
d129bceb PO |
220 | |
221 | /* 4C-4F reserved for more max current */ | |
222 | ||
2134a922 PO |
223 | #define SDHCI_SET_ACMD12_ERROR 0x50 |
224 | #define SDHCI_SET_INT_ERROR 0x52 | |
225 | ||
226 | #define SDHCI_ADMA_ERROR 0x54 | |
227 | ||
228 | /* 55-57 reserved */ | |
229 | ||
230 | #define SDHCI_ADMA_ADDRESS 0x58 | |
e57a5f61 | 231 | #define SDHCI_ADMA_ADDRESS_HI 0x5C |
2134a922 PO |
232 | |
233 | /* 60-FB reserved */ | |
d129bceb | 234 | |
52983382 KL |
235 | #define SDHCI_PRESET_FOR_SDR12 0x66 |
236 | #define SDHCI_PRESET_FOR_SDR25 0x68 | |
237 | #define SDHCI_PRESET_FOR_SDR50 0x6A | |
238 | #define SDHCI_PRESET_FOR_SDR104 0x6C | |
239 | #define SDHCI_PRESET_FOR_DDR50 0x6E | |
e9fb05d5 | 240 | #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ |
52983382 KL |
241 | #define SDHCI_PRESET_DRV_MASK 0xC000 |
242 | #define SDHCI_PRESET_DRV_SHIFT 14 | |
243 | #define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400 | |
244 | #define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10 | |
245 | #define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF | |
246 | #define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 | |
247 | ||
d129bceb PO |
248 | #define SDHCI_SLOT_INT_STATUS 0xFC |
249 | ||
250 | #define SDHCI_HOST_VERSION 0xFE | |
4a965505 PO |
251 | #define SDHCI_VENDOR_VER_MASK 0xFF00 |
252 | #define SDHCI_VENDOR_VER_SHIFT 8 | |
253 | #define SDHCI_SPEC_VER_MASK 0x00FF | |
254 | #define SDHCI_SPEC_VER_SHIFT 0 | |
2134a922 PO |
255 | #define SDHCI_SPEC_100 0 |
256 | #define SDHCI_SPEC_200 1 | |
85105c53 | 257 | #define SDHCI_SPEC_300 2 |
d129bceb | 258 | |
0397526d ZG |
259 | /* |
260 | * End of controller registers. | |
261 | */ | |
262 | ||
263 | #define SDHCI_MAX_DIV_SPEC_200 256 | |
264 | #define SDHCI_MAX_DIV_SPEC_300 2046 | |
265 | ||
f6a03cbf MV |
266 | /* |
267 | * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. | |
268 | */ | |
269 | #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) | |
270 | #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) | |
271 | ||
739d46dc AH |
272 | /* ADMA2 32-bit DMA descriptor size */ |
273 | #define SDHCI_ADMA2_32_DESC_SZ 8 | |
274 | ||
275 | /* ADMA2 32-bit DMA alignment */ | |
276 | #define SDHCI_ADMA2_32_ALIGN 4 | |
277 | ||
0545230f AH |
278 | /* ADMA2 32-bit descriptor */ |
279 | struct sdhci_adma2_32_desc { | |
280 | __le16 cmd; | |
281 | __le16 len; | |
282 | __le32 addr; | |
283 | } __packed __aligned(SDHCI_ADMA2_32_ALIGN); | |
284 | ||
e57a5f61 AH |
285 | /* ADMA2 64-bit DMA descriptor size */ |
286 | #define SDHCI_ADMA2_64_DESC_SZ 12 | |
287 | ||
288 | /* ADMA2 64-bit DMA alignment */ | |
289 | #define SDHCI_ADMA2_64_ALIGN 8 | |
290 | ||
291 | /* | |
292 | * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte | |
293 | * aligned. | |
294 | */ | |
295 | struct sdhci_adma2_64_desc { | |
296 | __le16 cmd; | |
297 | __le16 len; | |
298 | __le32 addr_lo; | |
299 | __le32 addr_hi; | |
300 | } __packed __aligned(4); | |
301 | ||
739d46dc AH |
302 | #define ADMA2_TRAN_VALID 0x21 |
303 | #define ADMA2_NOP_END_VALID 0x3 | |
304 | #define ADMA2_END 0x2 | |
305 | ||
4fb213f8 AH |
306 | /* |
307 | * Maximum segments assuming a 512KiB maximum requisition size and a minimum | |
308 | * 4KiB page size. | |
309 | */ | |
310 | #define SDHCI_MAX_SEGS 128 | |
311 | ||
d31911b9 HC |
312 | enum sdhci_cookie { |
313 | COOKIE_UNMAPPED, | |
314 | COOKIE_MAPPED, | |
315 | COOKIE_GIVEN, | |
83f13cc9 UH |
316 | }; |
317 | ||
318 | struct sdhci_host { | |
319 | /* Data set by hardware interface driver */ | |
320 | const char *hw_name; /* Hardware bus name */ | |
321 | ||
322 | unsigned int quirks; /* Deviations from spec. */ | |
323 | ||
324 | /* Controller doesn't honor resets unless we touch the clock register */ | |
325 | #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) | |
326 | /* Controller has bad caps bits, but really supports DMA */ | |
327 | #define SDHCI_QUIRK_FORCE_DMA (1<<1) | |
328 | /* Controller doesn't like to be reset when there is no card inserted. */ | |
329 | #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) | |
330 | /* Controller doesn't like clearing the power reg before a change */ | |
331 | #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) | |
332 | /* Controller has flaky internal state so reset it on each ios change */ | |
333 | #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) | |
334 | /* Controller has an unusable DMA engine */ | |
335 | #define SDHCI_QUIRK_BROKEN_DMA (1<<5) | |
336 | /* Controller has an unusable ADMA engine */ | |
337 | #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) | |
338 | /* Controller can only DMA from 32-bit aligned addresses */ | |
339 | #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) | |
340 | /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ | |
341 | #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) | |
342 | /* Controller can only ADMA chunks that are a multiple of 32 bits */ | |
343 | #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) | |
344 | /* Controller needs to be reset after each request to stay stable */ | |
345 | #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) | |
346 | /* Controller needs voltage and power writes to happen separately */ | |
347 | #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) | |
348 | /* Controller provides an incorrect timeout value for transfers */ | |
349 | #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) | |
350 | /* Controller has an issue with buffer bits for small transfers */ | |
351 | #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) | |
352 | /* Controller does not provide transfer-complete interrupt when not busy */ | |
353 | #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) | |
354 | /* Controller has unreliable card detection */ | |
355 | #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) | |
356 | /* Controller reports inverted write-protect state */ | |
357 | #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) | |
358 | /* Controller does not like fast PIO transfers */ | |
359 | #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) | |
360 | /* Controller has to be forced to use block size of 2048 bytes */ | |
361 | #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) | |
362 | /* Controller cannot do multi-block transfers */ | |
363 | #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) | |
364 | /* Controller can only handle 1-bit data transfers */ | |
365 | #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) | |
366 | /* Controller needs 10ms delay between applying power and clock */ | |
367 | #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) | |
368 | /* Controller uses SDCLK instead of TMCLK for data timeouts */ | |
369 | #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) | |
370 | /* Controller reports wrong base clock capability */ | |
371 | #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) | |
372 | /* Controller cannot support End Attribute in NOP ADMA descriptor */ | |
373 | #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) | |
374 | /* Controller is missing device caps. Use caps provided by host */ | |
375 | #define SDHCI_QUIRK_MISSING_CAPS (1<<27) | |
376 | /* Controller uses Auto CMD12 command to stop the transfer */ | |
377 | #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) | |
378 | /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ | |
379 | #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) | |
380 | /* Controller treats ADMA descriptors with length 0000h incorrectly */ | |
381 | #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) | |
382 | /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ | |
383 | #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) | |
384 | ||
385 | unsigned int quirks2; /* More deviations from spec. */ | |
386 | ||
387 | #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) | |
388 | #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) | |
389 | /* The system physically doesn't support 1.8v, even if the host does */ | |
390 | #define SDHCI_QUIRK2_NO_1_8_V (1<<2) | |
391 | #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) | |
392 | #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) | |
393 | /* Controller has a non-standard host control register */ | |
394 | #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) | |
395 | /* Controller does not support HS200 */ | |
396 | #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) | |
397 | /* Controller does not support DDR50 */ | |
398 | #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) | |
399 | /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ | |
400 | #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) | |
401 | /* Controller does not support 64-bit DMA */ | |
402 | #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) | |
403 | /* need clear transfer mode register before send cmd */ | |
404 | #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) | |
405 | /* Capability register bit-63 indicates HS400 support */ | |
406 | #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) | |
407 | /* forced tuned clock */ | |
408 | #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) | |
409 | /* disable the block count for single block transactions */ | |
410 | #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) | |
411 | /* Controller broken with using ACMD23 */ | |
412 | #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) | |
d1955c3a SG |
413 | /* Broken Clock divider zero in controller */ |
414 | #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) | |
af951761 | 415 | /* |
416 | * When internal clock is disabled, a delay is needed before modifying the | |
417 | * SD clock frequency or enabling back the internal clock. | |
418 | */ | |
419 | #define SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST (1<<16) | |
83f13cc9 UH |
420 | |
421 | int irq; /* Device IRQ */ | |
422 | void __iomem *ioaddr; /* Mapped address */ | |
423 | ||
424 | const struct sdhci_ops *ops; /* Low level hw interface */ | |
425 | ||
426 | /* Internal data */ | |
427 | struct mmc_host *mmc; /* MMC structure */ | |
428 | u64 dma_mask; /* custom DMA mask */ | |
429 | ||
430 | #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) | |
431 | struct led_classdev led; /* LED control */ | |
432 | char led_name[32]; | |
433 | #endif | |
434 | ||
435 | spinlock_t lock; /* Mutex */ | |
436 | ||
437 | int flags; /* Host attributes */ | |
438 | #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ | |
439 | #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ | |
440 | #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ | |
441 | #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ | |
442 | #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ | |
83f13cc9 UH |
443 | #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ |
444 | #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ | |
445 | #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ | |
446 | #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ | |
447 | #define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */ | |
83f13cc9 UH |
448 | #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ |
449 | #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ | |
450 | ||
451 | unsigned int version; /* SDHCI spec. version */ | |
452 | ||
453 | unsigned int max_clk; /* Max possible freq (MHz) */ | |
454 | unsigned int timeout_clk; /* Timeout freq (KHz) */ | |
455 | unsigned int clk_mul; /* Clock Muliplier value */ | |
456 | ||
457 | unsigned int clock; /* Current clock (MHz) */ | |
458 | u8 pwr; /* Current voltage */ | |
459 | ||
460 | bool runtime_suspended; /* Host is runtime suspended */ | |
461 | bool bus_on; /* Bus power prevents runtime suspend */ | |
462 | bool preset_enabled; /* Preset is enabled */ | |
463 | ||
464 | struct mmc_request *mrq; /* Current request */ | |
465 | struct mmc_command *cmd; /* Current command */ | |
466 | struct mmc_data *data; /* Current data request */ | |
467 | unsigned int data_early:1; /* Data finished before cmd */ | |
468 | unsigned int busy_handle:1; /* Handling the order of Busy-end */ | |
469 | ||
470 | struct sg_mapping_iter sg_miter; /* SG state for PIO */ | |
471 | unsigned int blocks; /* remaining PIO blocks */ | |
472 | ||
473 | int sg_count; /* Mapped sg entries */ | |
474 | ||
475 | void *adma_table; /* ADMA descriptor table */ | |
476 | void *align_buffer; /* Bounce buffer */ | |
477 | ||
478 | size_t adma_table_sz; /* ADMA descriptor table size */ | |
479 | size_t align_buffer_sz; /* Bounce buffer size */ | |
480 | ||
481 | dma_addr_t adma_addr; /* Mapped ADMA descr. table */ | |
482 | dma_addr_t align_addr; /* Mapped bounce buffer */ | |
483 | ||
484 | unsigned int desc_sz; /* ADMA descriptor size */ | |
485 | unsigned int align_sz; /* ADMA alignment */ | |
486 | unsigned int align_mask; /* ADMA alignment mask */ | |
487 | ||
488 | struct tasklet_struct finish_tasklet; /* Tasklet structures */ | |
489 | ||
490 | struct timer_list timer; /* Timer for timeouts */ | |
491 | ||
492 | u32 caps; /* Alternative CAPABILITY_0 */ | |
493 | u32 caps1; /* Alternative CAPABILITY_1 */ | |
494 | ||
495 | unsigned int ocr_avail_sdio; /* OCR bit masks */ | |
496 | unsigned int ocr_avail_sd; | |
497 | unsigned int ocr_avail_mmc; | |
498 | u32 ocr_mask; /* available voltages */ | |
499 | ||
500 | unsigned timing; /* Current timing */ | |
501 | ||
502 | u32 thread_isr; | |
503 | ||
504 | /* cached registers */ | |
505 | u32 ier; | |
506 | ||
507 | wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ | |
508 | unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ | |
509 | ||
510 | unsigned int tuning_count; /* Timer count for re-tuning */ | |
511 | unsigned int tuning_mode; /* Re-tuning mode supported by host */ | |
512 | #define SDHCI_TUNING_MODE_1 0 | |
83f13cc9 | 513 | |
83f13cc9 UH |
514 | unsigned long private[0] ____cacheline_aligned; |
515 | }; | |
516 | ||
b8c86fc5 | 517 | struct sdhci_ops { |
4e4141a5 | 518 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
dc297c92 MF |
519 | u32 (*read_l)(struct sdhci_host *host, int reg); |
520 | u16 (*read_w)(struct sdhci_host *host, int reg); | |
521 | u8 (*read_b)(struct sdhci_host *host, int reg); | |
522 | void (*write_l)(struct sdhci_host *host, u32 val, int reg); | |
523 | void (*write_w)(struct sdhci_host *host, u16 val, int reg); | |
524 | void (*write_b)(struct sdhci_host *host, u8 val, int reg); | |
4e4141a5 AV |
525 | #endif |
526 | ||
8114634c AV |
527 | void (*set_clock)(struct sdhci_host *host, unsigned int clock); |
528 | ||
b8c86fc5 | 529 | int (*enable_dma)(struct sdhci_host *host); |
4240ff0a | 530 | unsigned int (*get_max_clock)(struct sdhci_host *host); |
a9e58f25 | 531 | unsigned int (*get_min_clock)(struct sdhci_host *host); |
4240ff0a | 532 | unsigned int (*get_timeout_clock)(struct sdhci_host *host); |
a6ff5aeb | 533 | unsigned int (*get_max_timeout_count)(struct sdhci_host *host); |
b45e668a AD |
534 | void (*set_timeout)(struct sdhci_host *host, |
535 | struct mmc_command *cmd); | |
2317f56c | 536 | void (*set_bus_width)(struct sdhci_host *host, int width); |
643a81ff PR |
537 | void (*platform_send_init_74_clocks)(struct sdhci_host *host, |
538 | u8 power_mode); | |
2dfb579c | 539 | unsigned int (*get_ro)(struct sdhci_host *host); |
03231f9b | 540 | void (*reset)(struct sdhci_host *host, u8 mask); |
45251812 | 541 | int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); |
13e64501 | 542 | void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); |
20758b66 | 543 | void (*hw_reset)(struct sdhci_host *host); |
a4071fbb | 544 | void (*adma_workaround)(struct sdhci_host *host, u32 intmask); |
63ef5d8c | 545 | void (*platform_init)(struct sdhci_host *host); |
722e1280 | 546 | void (*card_event)(struct sdhci_host *host); |
9d967a61 | 547 | void (*voltage_switch)(struct sdhci_host *host); |
cb849648 AH |
548 | int (*select_drive_strength)(struct sdhci_host *host, |
549 | struct mmc_card *card, | |
550 | unsigned int max_dtr, int host_drv, | |
551 | int card_drv, int *drv_type); | |
d129bceb | 552 | }; |
b8c86fc5 | 553 | |
4e4141a5 AV |
554 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
555 | ||
556 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) | |
557 | { | |
dc297c92 MF |
558 | if (unlikely(host->ops->write_l)) |
559 | host->ops->write_l(host, val, reg); | |
4e4141a5 AV |
560 | else |
561 | writel(val, host->ioaddr + reg); | |
562 | } | |
563 | ||
564 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) | |
565 | { | |
dc297c92 MF |
566 | if (unlikely(host->ops->write_w)) |
567 | host->ops->write_w(host, val, reg); | |
4e4141a5 AV |
568 | else |
569 | writew(val, host->ioaddr + reg); | |
570 | } | |
571 | ||
572 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) | |
573 | { | |
dc297c92 MF |
574 | if (unlikely(host->ops->write_b)) |
575 | host->ops->write_b(host, val, reg); | |
4e4141a5 AV |
576 | else |
577 | writeb(val, host->ioaddr + reg); | |
578 | } | |
579 | ||
580 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) | |
581 | { | |
dc297c92 MF |
582 | if (unlikely(host->ops->read_l)) |
583 | return host->ops->read_l(host, reg); | |
4e4141a5 AV |
584 | else |
585 | return readl(host->ioaddr + reg); | |
586 | } | |
587 | ||
588 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) | |
589 | { | |
dc297c92 MF |
590 | if (unlikely(host->ops->read_w)) |
591 | return host->ops->read_w(host, reg); | |
4e4141a5 AV |
592 | else |
593 | return readw(host->ioaddr + reg); | |
594 | } | |
595 | ||
596 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) | |
597 | { | |
dc297c92 MF |
598 | if (unlikely(host->ops->read_b)) |
599 | return host->ops->read_b(host, reg); | |
4e4141a5 AV |
600 | else |
601 | return readb(host->ioaddr + reg); | |
602 | } | |
603 | ||
604 | #else | |
605 | ||
606 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) | |
607 | { | |
608 | writel(val, host->ioaddr + reg); | |
609 | } | |
610 | ||
611 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) | |
612 | { | |
613 | writew(val, host->ioaddr + reg); | |
614 | } | |
615 | ||
616 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) | |
617 | { | |
618 | writeb(val, host->ioaddr + reg); | |
619 | } | |
620 | ||
621 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) | |
622 | { | |
623 | return readl(host->ioaddr + reg); | |
624 | } | |
625 | ||
626 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) | |
627 | { | |
628 | return readw(host->ioaddr + reg); | |
629 | } | |
630 | ||
631 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) | |
632 | { | |
633 | return readb(host->ioaddr + reg); | |
634 | } | |
635 | ||
636 | #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ | |
b8c86fc5 PO |
637 | |
638 | extern struct sdhci_host *sdhci_alloc_host(struct device *dev, | |
639 | size_t priv_size); | |
640 | extern void sdhci_free_host(struct sdhci_host *host); | |
641 | ||
642 | static inline void *sdhci_priv(struct sdhci_host *host) | |
643 | { | |
644 | return (void *)host->private; | |
645 | } | |
646 | ||
17866e14 | 647 | extern void sdhci_card_detect(struct sdhci_host *host); |
b8c86fc5 | 648 | extern int sdhci_add_host(struct sdhci_host *host); |
1e72859e | 649 | extern void sdhci_remove_host(struct sdhci_host *host, int dead); |
c0e55129 DA |
650 | extern void sdhci_send_command(struct sdhci_host *host, |
651 | struct mmc_command *cmd); | |
b8c86fc5 | 652 | |
be138554 RK |
653 | static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) |
654 | { | |
655 | return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); | |
656 | } | |
657 | ||
1771059c | 658 | void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); |
2317f56c | 659 | void sdhci_set_bus_width(struct sdhci_host *host, int width); |
03231f9b | 660 | void sdhci_reset(struct sdhci_host *host, u8 mask); |
96d7b78c | 661 | void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); |
2317f56c | 662 | |
b8c86fc5 | 663 | #ifdef CONFIG_PM |
29495aa0 | 664 | extern int sdhci_suspend_host(struct sdhci_host *host); |
b8c86fc5 | 665 | extern int sdhci_resume_host(struct sdhci_host *host); |
5f619704 | 666 | extern void sdhci_enable_irq_wakeups(struct sdhci_host *host); |
66fd8ad5 AH |
667 | extern int sdhci_runtime_suspend_host(struct sdhci_host *host); |
668 | extern int sdhci_runtime_resume_host(struct sdhci_host *host); | |
669 | #endif | |
670 | ||
1978fda8 | 671 | #endif /* __SDHCI_HW_H */ |