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Commit | Line | Data |
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fdc50a94 YG |
1 | /* |
2 | * MMCIF eMMC driver. | |
3 | * | |
4 | * Copyright (C) 2010 Renesas Solutions Corp. | |
5 | * Yusuke Goda <yusuke.goda.sx@renesas.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License. | |
10 | * | |
11 | * | |
12 | * TODO | |
13 | * 1. DMA | |
14 | * 2. Power management | |
15 | * 3. Handle MMC errors better | |
16 | * | |
17 | */ | |
18 | ||
f985da17 GL |
19 | /* |
20 | * The MMCIF driver is now processing MMC requests asynchronously, according | |
21 | * to the Linux MMC API requirement. | |
22 | * | |
23 | * The MMCIF driver processes MMC requests in up to 3 stages: command, optional | |
24 | * data, and optional stop. To achieve asynchronous processing each of these | |
25 | * stages is split into two halves: a top and a bottom half. The top half | |
26 | * initialises the hardware, installs a timeout handler to handle completion | |
27 | * timeouts, and returns. In case of the command stage this immediately returns | |
28 | * control to the caller, leaving all further processing to run asynchronously. | |
29 | * All further request processing is performed by the bottom halves. | |
30 | * | |
31 | * The bottom half further consists of a "hard" IRQ handler, an IRQ handler | |
32 | * thread, a DMA completion callback, if DMA is used, a timeout work, and | |
33 | * request- and stage-specific handler methods. | |
34 | * | |
35 | * Each bottom half run begins with either a hardware interrupt, a DMA callback | |
36 | * invocation, or a timeout work run. In case of an error or a successful | |
37 | * processing completion, the MMC core is informed and the request processing is | |
38 | * finished. In case processing has to continue, i.e., if data has to be read | |
39 | * from or written to the card, or if a stop command has to be sent, the next | |
40 | * top half is called, which performs the necessary hardware handling and | |
41 | * reschedules the timeout work. This returns the driver state machine into the | |
42 | * bottom half waiting state. | |
43 | */ | |
44 | ||
86df1745 | 45 | #include <linux/bitops.h> |
aa0787a9 GL |
46 | #include <linux/clk.h> |
47 | #include <linux/completion.h> | |
e47bf32a | 48 | #include <linux/delay.h> |
fdc50a94 | 49 | #include <linux/dma-mapping.h> |
a782d688 | 50 | #include <linux/dmaengine.h> |
fdc50a94 YG |
51 | #include <linux/mmc/card.h> |
52 | #include <linux/mmc/core.h> | |
e47bf32a | 53 | #include <linux/mmc/host.h> |
fdc50a94 YG |
54 | #include <linux/mmc/mmc.h> |
55 | #include <linux/mmc/sdio.h> | |
fdc50a94 | 56 | #include <linux/mmc/sh_mmcif.h> |
e480606a | 57 | #include <linux/mmc/slot-gpio.h> |
bf68a812 | 58 | #include <linux/mod_devicetable.h> |
a782d688 | 59 | #include <linux/pagemap.h> |
e47bf32a | 60 | #include <linux/platform_device.h> |
efe6a8ad | 61 | #include <linux/pm_qos.h> |
faca6648 | 62 | #include <linux/pm_runtime.h> |
3b0beafc | 63 | #include <linux/spinlock.h> |
88b47679 | 64 | #include <linux/module.h> |
fdc50a94 YG |
65 | |
66 | #define DRIVER_NAME "sh_mmcif" | |
67 | #define DRIVER_VERSION "2010-04-28" | |
68 | ||
fdc50a94 YG |
69 | /* CE_CMD_SET */ |
70 | #define CMD_MASK 0x3f000000 | |
71 | #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) | |
72 | #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ | |
73 | #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ | |
74 | #define CMD_SET_RBSY (1 << 21) /* R1b */ | |
75 | #define CMD_SET_CCSEN (1 << 20) | |
76 | #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ | |
77 | #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ | |
78 | #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ | |
79 | #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ | |
80 | #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ | |
81 | #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ | |
82 | #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ | |
83 | #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ | |
84 | #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ | |
85 | #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ | |
86 | #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ | |
87 | #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ | |
88 | #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ | |
89 | #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ | |
90 | #define CMD_SET_CCSH (1 << 5) | |
555061f9 | 91 | #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ |
fdc50a94 YG |
92 | #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ |
93 | #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ | |
94 | #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ | |
95 | ||
96 | /* CE_CMD_CTRL */ | |
97 | #define CMD_CTRL_BREAK (1 << 0) | |
98 | ||
99 | /* CE_BLOCK_SET */ | |
100 | #define BLOCK_SIZE_MASK 0x0000ffff | |
101 | ||
fdc50a94 YG |
102 | /* CE_INT */ |
103 | #define INT_CCSDE (1 << 29) | |
104 | #define INT_CMD12DRE (1 << 26) | |
105 | #define INT_CMD12RBE (1 << 25) | |
106 | #define INT_CMD12CRE (1 << 24) | |
107 | #define INT_DTRANE (1 << 23) | |
108 | #define INT_BUFRE (1 << 22) | |
109 | #define INT_BUFWEN (1 << 21) | |
110 | #define INT_BUFREN (1 << 20) | |
111 | #define INT_CCSRCV (1 << 19) | |
112 | #define INT_RBSYE (1 << 17) | |
113 | #define INT_CRSPE (1 << 16) | |
114 | #define INT_CMDVIO (1 << 15) | |
115 | #define INT_BUFVIO (1 << 14) | |
116 | #define INT_WDATERR (1 << 11) | |
117 | #define INT_RDATERR (1 << 10) | |
118 | #define INT_RIDXERR (1 << 9) | |
119 | #define INT_RSPERR (1 << 8) | |
120 | #define INT_CCSTO (1 << 5) | |
121 | #define INT_CRCSTO (1 << 4) | |
122 | #define INT_WDATTO (1 << 3) | |
123 | #define INT_RDATTO (1 << 2) | |
124 | #define INT_RBSYTO (1 << 1) | |
125 | #define INT_RSPTO (1 << 0) | |
126 | #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ | |
127 | INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ | |
128 | INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ | |
129 | INT_RDATTO | INT_RBSYTO | INT_RSPTO) | |
130 | ||
131 | /* CE_INT_MASK */ | |
132 | #define MASK_ALL 0x00000000 | |
133 | #define MASK_MCCSDE (1 << 29) | |
134 | #define MASK_MCMD12DRE (1 << 26) | |
135 | #define MASK_MCMD12RBE (1 << 25) | |
136 | #define MASK_MCMD12CRE (1 << 24) | |
137 | #define MASK_MDTRANE (1 << 23) | |
138 | #define MASK_MBUFRE (1 << 22) | |
139 | #define MASK_MBUFWEN (1 << 21) | |
140 | #define MASK_MBUFREN (1 << 20) | |
141 | #define MASK_MCCSRCV (1 << 19) | |
142 | #define MASK_MRBSYE (1 << 17) | |
143 | #define MASK_MCRSPE (1 << 16) | |
144 | #define MASK_MCMDVIO (1 << 15) | |
145 | #define MASK_MBUFVIO (1 << 14) | |
146 | #define MASK_MWDATERR (1 << 11) | |
147 | #define MASK_MRDATERR (1 << 10) | |
148 | #define MASK_MRIDXERR (1 << 9) | |
149 | #define MASK_MRSPERR (1 << 8) | |
150 | #define MASK_MCCSTO (1 << 5) | |
151 | #define MASK_MCRCSTO (1 << 4) | |
152 | #define MASK_MWDATTO (1 << 3) | |
153 | #define MASK_MRDATTO (1 << 2) | |
154 | #define MASK_MRBSYTO (1 << 1) | |
155 | #define MASK_MRSPTO (1 << 0) | |
156 | ||
ee4b8887 GL |
157 | #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ |
158 | MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ | |
159 | MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \ | |
160 | MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) | |
161 | ||
fdc50a94 YG |
162 | /* CE_HOST_STS1 */ |
163 | #define STS1_CMDSEQ (1 << 31) | |
164 | ||
165 | /* CE_HOST_STS2 */ | |
166 | #define STS2_CRCSTE (1 << 31) | |
167 | #define STS2_CRC16E (1 << 30) | |
168 | #define STS2_AC12CRCE (1 << 29) | |
169 | #define STS2_RSPCRC7E (1 << 28) | |
170 | #define STS2_CRCSTEBE (1 << 27) | |
171 | #define STS2_RDATEBE (1 << 26) | |
172 | #define STS2_AC12REBE (1 << 25) | |
173 | #define STS2_RSPEBE (1 << 24) | |
174 | #define STS2_AC12IDXE (1 << 23) | |
175 | #define STS2_RSPIDXE (1 << 22) | |
176 | #define STS2_CCSTO (1 << 15) | |
177 | #define STS2_RDATTO (1 << 14) | |
178 | #define STS2_DATBSYTO (1 << 13) | |
179 | #define STS2_CRCSTTO (1 << 12) | |
180 | #define STS2_AC12BSYTO (1 << 11) | |
181 | #define STS2_RSPBSYTO (1 << 10) | |
182 | #define STS2_AC12RSPTO (1 << 9) | |
183 | #define STS2_RSPTO (1 << 8) | |
184 | #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ | |
185 | STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) | |
186 | #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ | |
187 | STS2_DATBSYTO | STS2_CRCSTTO | \ | |
188 | STS2_AC12BSYTO | STS2_RSPBSYTO | \ | |
189 | STS2_AC12RSPTO | STS2_RSPTO) | |
190 | ||
fdc50a94 YG |
191 | #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ |
192 | #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ | |
193 | #define CLKDEV_INIT 400000 /* 400 KHz */ | |
194 | ||
3b0beafc GL |
195 | enum mmcif_state { |
196 | STATE_IDLE, | |
197 | STATE_REQUEST, | |
198 | STATE_IOS, | |
199 | }; | |
200 | ||
f985da17 GL |
201 | enum mmcif_wait_for { |
202 | MMCIF_WAIT_FOR_REQUEST, | |
203 | MMCIF_WAIT_FOR_CMD, | |
204 | MMCIF_WAIT_FOR_MREAD, | |
205 | MMCIF_WAIT_FOR_MWRITE, | |
206 | MMCIF_WAIT_FOR_READ, | |
207 | MMCIF_WAIT_FOR_WRITE, | |
208 | MMCIF_WAIT_FOR_READ_END, | |
209 | MMCIF_WAIT_FOR_WRITE_END, | |
210 | MMCIF_WAIT_FOR_STOP, | |
211 | }; | |
212 | ||
fdc50a94 YG |
213 | struct sh_mmcif_host { |
214 | struct mmc_host *mmc; | |
f985da17 | 215 | struct mmc_request *mrq; |
fdc50a94 YG |
216 | struct platform_device *pd; |
217 | struct clk *hclk; | |
218 | unsigned int clk; | |
219 | int bus_width; | |
555061f9 | 220 | unsigned char timing; |
aa0787a9 | 221 | bool sd_error; |
f985da17 | 222 | bool dying; |
fdc50a94 YG |
223 | long timeout; |
224 | void __iomem *addr; | |
f985da17 | 225 | u32 *pio_ptr; |
ee4b8887 | 226 | spinlock_t lock; /* protect sh_mmcif_host::state */ |
3b0beafc | 227 | enum mmcif_state state; |
f985da17 GL |
228 | enum mmcif_wait_for wait_for; |
229 | struct delayed_work timeout_work; | |
230 | size_t blocksize; | |
231 | int sg_idx; | |
232 | int sg_blkidx; | |
faca6648 | 233 | bool power; |
c9b0cef2 | 234 | bool card_present; |
fdc50a94 | 235 | |
a782d688 GL |
236 | /* DMA support */ |
237 | struct dma_chan *chan_rx; | |
238 | struct dma_chan *chan_tx; | |
239 | struct completion dma_complete; | |
f38f94c6 | 240 | bool dma_active; |
a782d688 | 241 | }; |
fdc50a94 YG |
242 | |
243 | static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, | |
244 | unsigned int reg, u32 val) | |
245 | { | |
487d9fc5 | 246 | writel(val | readl(host->addr + reg), host->addr + reg); |
fdc50a94 YG |
247 | } |
248 | ||
249 | static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, | |
250 | unsigned int reg, u32 val) | |
251 | { | |
487d9fc5 | 252 | writel(~val & readl(host->addr + reg), host->addr + reg); |
fdc50a94 YG |
253 | } |
254 | ||
a782d688 GL |
255 | static void mmcif_dma_complete(void *arg) |
256 | { | |
257 | struct sh_mmcif_host *host = arg; | |
69983404 GL |
258 | struct mmc_data *data = host->mrq->data; |
259 | ||
a782d688 GL |
260 | dev_dbg(&host->pd->dev, "Command completed\n"); |
261 | ||
69983404 | 262 | if (WARN(!data, "%s: NULL data in DMA completion!\n", |
a782d688 GL |
263 | dev_name(&host->pd->dev))) |
264 | return; | |
265 | ||
69983404 | 266 | if (data->flags & MMC_DATA_READ) |
1ed828db | 267 | dma_unmap_sg(host->chan_rx->device->dev, |
69983404 | 268 | data->sg, data->sg_len, |
a782d688 GL |
269 | DMA_FROM_DEVICE); |
270 | else | |
1ed828db | 271 | dma_unmap_sg(host->chan_tx->device->dev, |
69983404 | 272 | data->sg, data->sg_len, |
a782d688 GL |
273 | DMA_TO_DEVICE); |
274 | ||
275 | complete(&host->dma_complete); | |
276 | } | |
277 | ||
278 | static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) | |
279 | { | |
69983404 GL |
280 | struct mmc_data *data = host->mrq->data; |
281 | struct scatterlist *sg = data->sg; | |
a782d688 GL |
282 | struct dma_async_tx_descriptor *desc = NULL; |
283 | struct dma_chan *chan = host->chan_rx; | |
284 | dma_cookie_t cookie = -EINVAL; | |
285 | int ret; | |
286 | ||
69983404 | 287 | ret = dma_map_sg(chan->device->dev, sg, data->sg_len, |
1ed828db | 288 | DMA_FROM_DEVICE); |
a782d688 | 289 | if (ret > 0) { |
f38f94c6 | 290 | host->dma_active = true; |
16052827 | 291 | desc = dmaengine_prep_slave_sg(chan, sg, ret, |
05f5799c | 292 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
a782d688 GL |
293 | } |
294 | ||
295 | if (desc) { | |
296 | desc->callback = mmcif_dma_complete; | |
297 | desc->callback_param = host; | |
a5ece7d2 LW |
298 | cookie = dmaengine_submit(desc); |
299 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); | |
300 | dma_async_issue_pending(chan); | |
a782d688 GL |
301 | } |
302 | dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", | |
69983404 | 303 | __func__, data->sg_len, ret, cookie); |
a782d688 GL |
304 | |
305 | if (!desc) { | |
306 | /* DMA failed, fall back to PIO */ | |
307 | if (ret >= 0) | |
308 | ret = -EIO; | |
309 | host->chan_rx = NULL; | |
f38f94c6 | 310 | host->dma_active = false; |
a782d688 GL |
311 | dma_release_channel(chan); |
312 | /* Free the Tx channel too */ | |
313 | chan = host->chan_tx; | |
314 | if (chan) { | |
315 | host->chan_tx = NULL; | |
316 | dma_release_channel(chan); | |
317 | } | |
318 | dev_warn(&host->pd->dev, | |
319 | "DMA failed: %d, falling back to PIO\n", ret); | |
320 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
321 | } | |
322 | ||
323 | dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, | |
69983404 | 324 | desc, cookie, data->sg_len); |
a782d688 GL |
325 | } |
326 | ||
327 | static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) | |
328 | { | |
69983404 GL |
329 | struct mmc_data *data = host->mrq->data; |
330 | struct scatterlist *sg = data->sg; | |
a782d688 GL |
331 | struct dma_async_tx_descriptor *desc = NULL; |
332 | struct dma_chan *chan = host->chan_tx; | |
333 | dma_cookie_t cookie = -EINVAL; | |
334 | int ret; | |
335 | ||
69983404 | 336 | ret = dma_map_sg(chan->device->dev, sg, data->sg_len, |
1ed828db | 337 | DMA_TO_DEVICE); |
a782d688 | 338 | if (ret > 0) { |
f38f94c6 | 339 | host->dma_active = true; |
16052827 | 340 | desc = dmaengine_prep_slave_sg(chan, sg, ret, |
05f5799c | 341 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
a782d688 GL |
342 | } |
343 | ||
344 | if (desc) { | |
345 | desc->callback = mmcif_dma_complete; | |
346 | desc->callback_param = host; | |
a5ece7d2 LW |
347 | cookie = dmaengine_submit(desc); |
348 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); | |
349 | dma_async_issue_pending(chan); | |
a782d688 GL |
350 | } |
351 | dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", | |
69983404 | 352 | __func__, data->sg_len, ret, cookie); |
a782d688 GL |
353 | |
354 | if (!desc) { | |
355 | /* DMA failed, fall back to PIO */ | |
356 | if (ret >= 0) | |
357 | ret = -EIO; | |
358 | host->chan_tx = NULL; | |
f38f94c6 | 359 | host->dma_active = false; |
a782d688 GL |
360 | dma_release_channel(chan); |
361 | /* Free the Rx channel too */ | |
362 | chan = host->chan_rx; | |
363 | if (chan) { | |
364 | host->chan_rx = NULL; | |
365 | dma_release_channel(chan); | |
366 | } | |
367 | dev_warn(&host->pd->dev, | |
368 | "DMA failed: %d, falling back to PIO\n", ret); | |
369 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
370 | } | |
371 | ||
372 | dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__, | |
373 | desc, cookie); | |
374 | } | |
375 | ||
a782d688 GL |
376 | static void sh_mmcif_request_dma(struct sh_mmcif_host *host, |
377 | struct sh_mmcif_plat_data *pdata) | |
378 | { | |
0e79f9ae GL |
379 | struct resource *res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); |
380 | struct dma_slave_config cfg; | |
381 | dma_cap_mask_t mask; | |
382 | int ret; | |
a782d688 | 383 | |
f38f94c6 | 384 | host->dma_active = false; |
a782d688 | 385 | |
bf68a812 GL |
386 | if (!pdata) |
387 | return; | |
388 | ||
0e79f9ae GL |
389 | if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0) |
390 | return; | |
a782d688 | 391 | |
0e79f9ae GL |
392 | /* We can only either use DMA for both Tx and Rx or not use it at all */ |
393 | dma_cap_zero(mask); | |
394 | dma_cap_set(DMA_SLAVE, mask); | |
a782d688 | 395 | |
0e79f9ae GL |
396 | host->chan_tx = dma_request_channel(mask, shdma_chan_filter, |
397 | (void *)pdata->slave_id_tx); | |
398 | dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__, | |
399 | host->chan_tx); | |
a782d688 | 400 | |
0e79f9ae GL |
401 | if (!host->chan_tx) |
402 | return; | |
a782d688 | 403 | |
0e79f9ae GL |
404 | cfg.slave_id = pdata->slave_id_tx; |
405 | cfg.direction = DMA_MEM_TO_DEV; | |
406 | cfg.dst_addr = res->start + MMCIF_CE_DATA; | |
407 | cfg.src_addr = 0; | |
408 | ret = dmaengine_slave_config(host->chan_tx, &cfg); | |
409 | if (ret < 0) | |
410 | goto ecfgtx; | |
411 | ||
412 | host->chan_rx = dma_request_channel(mask, shdma_chan_filter, | |
413 | (void *)pdata->slave_id_rx); | |
414 | dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__, | |
415 | host->chan_rx); | |
416 | ||
417 | if (!host->chan_rx) | |
418 | goto erqrx; | |
419 | ||
420 | cfg.slave_id = pdata->slave_id_rx; | |
421 | cfg.direction = DMA_DEV_TO_MEM; | |
422 | cfg.dst_addr = 0; | |
423 | cfg.src_addr = res->start + MMCIF_CE_DATA; | |
424 | ret = dmaengine_slave_config(host->chan_rx, &cfg); | |
425 | if (ret < 0) | |
426 | goto ecfgrx; | |
427 | ||
428 | init_completion(&host->dma_complete); | |
429 | ||
430 | return; | |
431 | ||
432 | ecfgrx: | |
433 | dma_release_channel(host->chan_rx); | |
434 | host->chan_rx = NULL; | |
435 | erqrx: | |
436 | ecfgtx: | |
437 | dma_release_channel(host->chan_tx); | |
438 | host->chan_tx = NULL; | |
a782d688 GL |
439 | } |
440 | ||
441 | static void sh_mmcif_release_dma(struct sh_mmcif_host *host) | |
442 | { | |
443 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
444 | /* Descriptors are freed automatically */ | |
445 | if (host->chan_tx) { | |
446 | struct dma_chan *chan = host->chan_tx; | |
447 | host->chan_tx = NULL; | |
448 | dma_release_channel(chan); | |
449 | } | |
450 | if (host->chan_rx) { | |
451 | struct dma_chan *chan = host->chan_rx; | |
452 | host->chan_rx = NULL; | |
453 | dma_release_channel(chan); | |
454 | } | |
455 | ||
f38f94c6 | 456 | host->dma_active = false; |
a782d688 | 457 | } |
fdc50a94 YG |
458 | |
459 | static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) | |
460 | { | |
461 | struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; | |
bf68a812 | 462 | bool sup_pclk = p ? p->sup_pclk : false; |
fdc50a94 YG |
463 | |
464 | sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); | |
465 | sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); | |
466 | ||
467 | if (!clk) | |
468 | return; | |
bf68a812 | 469 | if (sup_pclk && clk == host->clk) |
fdc50a94 YG |
470 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); |
471 | else | |
472 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & | |
f9388257 SH |
473 | ((fls(DIV_ROUND_UP(host->clk, |
474 | clk) - 1) - 1) << 16)); | |
fdc50a94 YG |
475 | |
476 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); | |
477 | } | |
478 | ||
479 | static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) | |
480 | { | |
481 | u32 tmp; | |
482 | ||
487d9fc5 | 483 | tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); |
fdc50a94 | 484 | |
487d9fc5 MD |
485 | sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); |
486 | sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); | |
fdc50a94 YG |
487 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | |
488 | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); | |
489 | /* byte swap on */ | |
490 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); | |
491 | } | |
492 | ||
493 | static int sh_mmcif_error_manage(struct sh_mmcif_host *host) | |
494 | { | |
495 | u32 state1, state2; | |
ee4b8887 | 496 | int ret, timeout; |
fdc50a94 | 497 | |
aa0787a9 | 498 | host->sd_error = false; |
fdc50a94 | 499 | |
487d9fc5 MD |
500 | state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); |
501 | state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); | |
e47bf32a GL |
502 | dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); |
503 | dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); | |
fdc50a94 YG |
504 | |
505 | if (state1 & STS1_CMDSEQ) { | |
506 | sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); | |
507 | sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); | |
ee4b8887 | 508 | for (timeout = 10000000; timeout; timeout--) { |
487d9fc5 | 509 | if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) |
ee4b8887 | 510 | & STS1_CMDSEQ)) |
fdc50a94 YG |
511 | break; |
512 | mdelay(1); | |
513 | } | |
ee4b8887 GL |
514 | if (!timeout) { |
515 | dev_err(&host->pd->dev, | |
516 | "Forced end of command sequence timeout err\n"); | |
517 | return -EIO; | |
518 | } | |
fdc50a94 | 519 | sh_mmcif_sync_reset(host); |
e47bf32a | 520 | dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); |
fdc50a94 YG |
521 | return -EIO; |
522 | } | |
523 | ||
524 | if (state2 & STS2_CRC_ERR) { | |
ee4b8887 | 525 | dev_dbg(&host->pd->dev, ": CRC error\n"); |
fdc50a94 YG |
526 | ret = -EIO; |
527 | } else if (state2 & STS2_TIMEOUT_ERR) { | |
ee4b8887 | 528 | dev_dbg(&host->pd->dev, ": Timeout\n"); |
fdc50a94 YG |
529 | ret = -ETIMEDOUT; |
530 | } else { | |
ee4b8887 | 531 | dev_dbg(&host->pd->dev, ": End/Index error\n"); |
fdc50a94 YG |
532 | ret = -EIO; |
533 | } | |
534 | return ret; | |
535 | } | |
536 | ||
f985da17 | 537 | static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) |
fdc50a94 | 538 | { |
f985da17 GL |
539 | struct mmc_data *data = host->mrq->data; |
540 | ||
541 | host->sg_blkidx += host->blocksize; | |
542 | ||
543 | /* data->sg->length must be a multiple of host->blocksize? */ | |
544 | BUG_ON(host->sg_blkidx > data->sg->length); | |
545 | ||
546 | if (host->sg_blkidx == data->sg->length) { | |
547 | host->sg_blkidx = 0; | |
548 | if (++host->sg_idx < data->sg_len) | |
549 | host->pio_ptr = sg_virt(++data->sg); | |
550 | } else { | |
551 | host->pio_ptr = p; | |
552 | } | |
553 | ||
554 | if (host->sg_idx == data->sg_len) | |
555 | return false; | |
556 | ||
557 | return true; | |
558 | } | |
559 | ||
560 | static void sh_mmcif_single_read(struct sh_mmcif_host *host, | |
561 | struct mmc_request *mrq) | |
562 | { | |
563 | host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & | |
564 | BLOCK_SIZE_MASK) + 3; | |
565 | ||
566 | host->wait_for = MMCIF_WAIT_FOR_READ; | |
567 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
fdc50a94 | 568 | |
fdc50a94 YG |
569 | /* buf read enable */ |
570 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); | |
f985da17 GL |
571 | } |
572 | ||
573 | static bool sh_mmcif_read_block(struct sh_mmcif_host *host) | |
574 | { | |
575 | struct mmc_data *data = host->mrq->data; | |
576 | u32 *p = sg_virt(data->sg); | |
577 | int i; | |
578 | ||
579 | if (host->sd_error) { | |
580 | data->error = sh_mmcif_error_manage(host); | |
581 | return false; | |
582 | } | |
583 | ||
584 | for (i = 0; i < host->blocksize / 4; i++) | |
487d9fc5 | 585 | *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); |
fdc50a94 YG |
586 | |
587 | /* buffer read end */ | |
588 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); | |
f985da17 | 589 | host->wait_for = MMCIF_WAIT_FOR_READ_END; |
fdc50a94 | 590 | |
f985da17 | 591 | return true; |
fdc50a94 YG |
592 | } |
593 | ||
f985da17 GL |
594 | static void sh_mmcif_multi_read(struct sh_mmcif_host *host, |
595 | struct mmc_request *mrq) | |
fdc50a94 YG |
596 | { |
597 | struct mmc_data *data = mrq->data; | |
f985da17 GL |
598 | |
599 | if (!data->sg_len || !data->sg->length) | |
600 | return; | |
601 | ||
602 | host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & | |
603 | BLOCK_SIZE_MASK; | |
604 | ||
605 | host->wait_for = MMCIF_WAIT_FOR_MREAD; | |
606 | host->sg_idx = 0; | |
607 | host->sg_blkidx = 0; | |
608 | host->pio_ptr = sg_virt(data->sg); | |
609 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
610 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); | |
611 | } | |
612 | ||
613 | static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) | |
614 | { | |
615 | struct mmc_data *data = host->mrq->data; | |
616 | u32 *p = host->pio_ptr; | |
617 | int i; | |
618 | ||
619 | if (host->sd_error) { | |
620 | data->error = sh_mmcif_error_manage(host); | |
621 | return false; | |
fdc50a94 | 622 | } |
f985da17 GL |
623 | |
624 | BUG_ON(!data->sg->length); | |
625 | ||
626 | for (i = 0; i < host->blocksize / 4; i++) | |
627 | *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); | |
628 | ||
629 | if (!sh_mmcif_next_block(host, p)) | |
630 | return false; | |
631 | ||
632 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
633 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); | |
634 | ||
635 | return true; | |
fdc50a94 YG |
636 | } |
637 | ||
f985da17 | 638 | static void sh_mmcif_single_write(struct sh_mmcif_host *host, |
fdc50a94 YG |
639 | struct mmc_request *mrq) |
640 | { | |
f985da17 GL |
641 | host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & |
642 | BLOCK_SIZE_MASK) + 3; | |
fdc50a94 | 643 | |
f985da17 GL |
644 | host->wait_for = MMCIF_WAIT_FOR_WRITE; |
645 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
fdc50a94 YG |
646 | |
647 | /* buf write enable */ | |
f985da17 GL |
648 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
649 | } | |
650 | ||
651 | static bool sh_mmcif_write_block(struct sh_mmcif_host *host) | |
652 | { | |
653 | struct mmc_data *data = host->mrq->data; | |
654 | u32 *p = sg_virt(data->sg); | |
655 | int i; | |
656 | ||
657 | if (host->sd_error) { | |
658 | data->error = sh_mmcif_error_manage(host); | |
659 | return false; | |
660 | } | |
661 | ||
662 | for (i = 0; i < host->blocksize / 4; i++) | |
487d9fc5 | 663 | sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); |
fdc50a94 YG |
664 | |
665 | /* buffer write end */ | |
666 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); | |
f985da17 | 667 | host->wait_for = MMCIF_WAIT_FOR_WRITE_END; |
fdc50a94 | 668 | |
f985da17 | 669 | return true; |
fdc50a94 YG |
670 | } |
671 | ||
f985da17 GL |
672 | static void sh_mmcif_multi_write(struct sh_mmcif_host *host, |
673 | struct mmc_request *mrq) | |
fdc50a94 YG |
674 | { |
675 | struct mmc_data *data = mrq->data; | |
fdc50a94 | 676 | |
f985da17 GL |
677 | if (!data->sg_len || !data->sg->length) |
678 | return; | |
fdc50a94 | 679 | |
f985da17 GL |
680 | host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & |
681 | BLOCK_SIZE_MASK; | |
fdc50a94 | 682 | |
f985da17 GL |
683 | host->wait_for = MMCIF_WAIT_FOR_MWRITE; |
684 | host->sg_idx = 0; | |
685 | host->sg_blkidx = 0; | |
686 | host->pio_ptr = sg_virt(data->sg); | |
687 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
688 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); | |
689 | } | |
fdc50a94 | 690 | |
f985da17 GL |
691 | static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) |
692 | { | |
693 | struct mmc_data *data = host->mrq->data; | |
694 | u32 *p = host->pio_ptr; | |
695 | int i; | |
696 | ||
697 | if (host->sd_error) { | |
698 | data->error = sh_mmcif_error_manage(host); | |
699 | return false; | |
fdc50a94 | 700 | } |
f985da17 GL |
701 | |
702 | BUG_ON(!data->sg->length); | |
703 | ||
704 | for (i = 0; i < host->blocksize / 4; i++) | |
705 | sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); | |
706 | ||
707 | if (!sh_mmcif_next_block(host, p)) | |
708 | return false; | |
709 | ||
710 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
711 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); | |
712 | ||
713 | return true; | |
fdc50a94 YG |
714 | } |
715 | ||
716 | static void sh_mmcif_get_response(struct sh_mmcif_host *host, | |
717 | struct mmc_command *cmd) | |
718 | { | |
719 | if (cmd->flags & MMC_RSP_136) { | |
487d9fc5 MD |
720 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); |
721 | cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); | |
722 | cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); | |
723 | cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); | |
fdc50a94 | 724 | } else |
487d9fc5 | 725 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); |
fdc50a94 YG |
726 | } |
727 | ||
728 | static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, | |
729 | struct mmc_command *cmd) | |
730 | { | |
487d9fc5 | 731 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); |
fdc50a94 YG |
732 | } |
733 | ||
734 | static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, | |
69983404 | 735 | struct mmc_request *mrq) |
fdc50a94 | 736 | { |
69983404 GL |
737 | struct mmc_data *data = mrq->data; |
738 | struct mmc_command *cmd = mrq->cmd; | |
739 | u32 opc = cmd->opcode; | |
fdc50a94 YG |
740 | u32 tmp = 0; |
741 | ||
742 | /* Response Type check */ | |
743 | switch (mmc_resp_type(cmd)) { | |
744 | case MMC_RSP_NONE: | |
745 | tmp |= CMD_SET_RTYP_NO; | |
746 | break; | |
747 | case MMC_RSP_R1: | |
748 | case MMC_RSP_R1B: | |
749 | case MMC_RSP_R3: | |
750 | tmp |= CMD_SET_RTYP_6B; | |
751 | break; | |
752 | case MMC_RSP_R2: | |
753 | tmp |= CMD_SET_RTYP_17B; | |
754 | break; | |
755 | default: | |
e47bf32a | 756 | dev_err(&host->pd->dev, "Unsupported response type.\n"); |
fdc50a94 YG |
757 | break; |
758 | } | |
759 | switch (opc) { | |
760 | /* RBSY */ | |
761 | case MMC_SWITCH: | |
762 | case MMC_STOP_TRANSMISSION: | |
763 | case MMC_SET_WRITE_PROT: | |
764 | case MMC_CLR_WRITE_PROT: | |
765 | case MMC_ERASE: | |
fdc50a94 YG |
766 | tmp |= CMD_SET_RBSY; |
767 | break; | |
768 | } | |
769 | /* WDAT / DATW */ | |
69983404 | 770 | if (data) { |
fdc50a94 YG |
771 | tmp |= CMD_SET_WDAT; |
772 | switch (host->bus_width) { | |
773 | case MMC_BUS_WIDTH_1: | |
774 | tmp |= CMD_SET_DATW_1; | |
775 | break; | |
776 | case MMC_BUS_WIDTH_4: | |
777 | tmp |= CMD_SET_DATW_4; | |
778 | break; | |
779 | case MMC_BUS_WIDTH_8: | |
780 | tmp |= CMD_SET_DATW_8; | |
781 | break; | |
782 | default: | |
e47bf32a | 783 | dev_err(&host->pd->dev, "Unsupported bus width.\n"); |
fdc50a94 YG |
784 | break; |
785 | } | |
555061f9 TK |
786 | switch (host->timing) { |
787 | case MMC_TIMING_UHS_DDR50: | |
788 | /* | |
789 | * MMC core will only set this timing, if the host | |
790 | * advertises the MMC_CAP_UHS_DDR50 capability. MMCIF | |
791 | * implementations with this capability, e.g. sh73a0, | |
792 | * will have to set it in their platform data. | |
793 | */ | |
794 | tmp |= CMD_SET_DARS; | |
795 | break; | |
796 | } | |
fdc50a94 YG |
797 | } |
798 | /* DWEN */ | |
799 | if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) | |
800 | tmp |= CMD_SET_DWEN; | |
801 | /* CMLTE/CMD12EN */ | |
802 | if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { | |
803 | tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; | |
804 | sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, | |
69983404 | 805 | data->blocks << 16); |
fdc50a94 YG |
806 | } |
807 | /* RIDXC[1:0] check bits */ | |
808 | if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || | |
809 | opc == MMC_SEND_CSD || opc == MMC_SEND_CID) | |
810 | tmp |= CMD_SET_RIDXC_BITS; | |
811 | /* RCRC7C[1:0] check bits */ | |
812 | if (opc == MMC_SEND_OP_COND) | |
813 | tmp |= CMD_SET_CRC7C_BITS; | |
814 | /* RCRC7C[1:0] internal CRC7 */ | |
815 | if (opc == MMC_ALL_SEND_CID || | |
816 | opc == MMC_SEND_CSD || opc == MMC_SEND_CID) | |
817 | tmp |= CMD_SET_CRC7C_INTERNAL; | |
818 | ||
69983404 | 819 | return (opc << 24) | tmp; |
fdc50a94 YG |
820 | } |
821 | ||
e47bf32a | 822 | static int sh_mmcif_data_trans(struct sh_mmcif_host *host, |
f985da17 | 823 | struct mmc_request *mrq, u32 opc) |
fdc50a94 | 824 | { |
fdc50a94 YG |
825 | switch (opc) { |
826 | case MMC_READ_MULTIPLE_BLOCK: | |
f985da17 GL |
827 | sh_mmcif_multi_read(host, mrq); |
828 | return 0; | |
fdc50a94 | 829 | case MMC_WRITE_MULTIPLE_BLOCK: |
f985da17 GL |
830 | sh_mmcif_multi_write(host, mrq); |
831 | return 0; | |
fdc50a94 | 832 | case MMC_WRITE_BLOCK: |
f985da17 GL |
833 | sh_mmcif_single_write(host, mrq); |
834 | return 0; | |
fdc50a94 YG |
835 | case MMC_READ_SINGLE_BLOCK: |
836 | case MMC_SEND_EXT_CSD: | |
f985da17 GL |
837 | sh_mmcif_single_read(host, mrq); |
838 | return 0; | |
fdc50a94 | 839 | default: |
e47bf32a | 840 | dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc); |
ee4b8887 | 841 | return -EINVAL; |
fdc50a94 | 842 | } |
fdc50a94 YG |
843 | } |
844 | ||
845 | static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, | |
ee4b8887 | 846 | struct mmc_request *mrq) |
fdc50a94 | 847 | { |
ee4b8887 | 848 | struct mmc_command *cmd = mrq->cmd; |
f985da17 GL |
849 | u32 opc = cmd->opcode; |
850 | u32 mask; | |
fdc50a94 | 851 | |
fdc50a94 | 852 | switch (opc) { |
ee4b8887 | 853 | /* response busy check */ |
fdc50a94 YG |
854 | case MMC_SWITCH: |
855 | case MMC_STOP_TRANSMISSION: | |
856 | case MMC_SET_WRITE_PROT: | |
857 | case MMC_CLR_WRITE_PROT: | |
858 | case MMC_ERASE: | |
ee4b8887 | 859 | mask = MASK_START_CMD | MASK_MRBSYE; |
fdc50a94 YG |
860 | break; |
861 | default: | |
ee4b8887 | 862 | mask = MASK_START_CMD | MASK_MCRSPE; |
fdc50a94 YG |
863 | break; |
864 | } | |
fdc50a94 | 865 | |
69983404 | 866 | if (mrq->data) { |
487d9fc5 MD |
867 | sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); |
868 | sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, | |
869 | mrq->data->blksz); | |
fdc50a94 | 870 | } |
69983404 | 871 | opc = sh_mmcif_set_cmd(host, mrq); |
fdc50a94 | 872 | |
487d9fc5 MD |
873 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); |
874 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); | |
fdc50a94 | 875 | /* set arg */ |
487d9fc5 | 876 | sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); |
fdc50a94 | 877 | /* set cmd */ |
487d9fc5 | 878 | sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); |
fdc50a94 | 879 | |
f985da17 GL |
880 | host->wait_for = MMCIF_WAIT_FOR_CMD; |
881 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
fdc50a94 YG |
882 | } |
883 | ||
884 | static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, | |
ee4b8887 | 885 | struct mmc_request *mrq) |
fdc50a94 | 886 | { |
69983404 GL |
887 | switch (mrq->cmd->opcode) { |
888 | case MMC_READ_MULTIPLE_BLOCK: | |
fdc50a94 | 889 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); |
69983404 GL |
890 | break; |
891 | case MMC_WRITE_MULTIPLE_BLOCK: | |
fdc50a94 | 892 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); |
69983404 GL |
893 | break; |
894 | default: | |
e47bf32a | 895 | dev_err(&host->pd->dev, "unsupported stop cmd\n"); |
69983404 | 896 | mrq->stop->error = sh_mmcif_error_manage(host); |
fdc50a94 YG |
897 | return; |
898 | } | |
899 | ||
f985da17 GL |
900 | host->wait_for = MMCIF_WAIT_FOR_STOP; |
901 | schedule_delayed_work(&host->timeout_work, host->timeout); | |
fdc50a94 YG |
902 | } |
903 | ||
904 | static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
905 | { | |
906 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
3b0beafc GL |
907 | unsigned long flags; |
908 | ||
909 | spin_lock_irqsave(&host->lock, flags); | |
910 | if (host->state != STATE_IDLE) { | |
911 | spin_unlock_irqrestore(&host->lock, flags); | |
912 | mrq->cmd->error = -EAGAIN; | |
913 | mmc_request_done(mmc, mrq); | |
914 | return; | |
915 | } | |
916 | ||
917 | host->state = STATE_REQUEST; | |
918 | spin_unlock_irqrestore(&host->lock, flags); | |
fdc50a94 YG |
919 | |
920 | switch (mrq->cmd->opcode) { | |
921 | /* MMCIF does not support SD/SDIO command */ | |
7541ca98 LP |
922 | case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */ |
923 | case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ | |
924 | if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR) | |
925 | break; | |
fdc50a94 | 926 | case MMC_APP_CMD: |
92ff0c5b | 927 | case SD_IO_RW_DIRECT: |
3b0beafc | 928 | host->state = STATE_IDLE; |
fdc50a94 YG |
929 | mrq->cmd->error = -ETIMEDOUT; |
930 | mmc_request_done(mmc, mrq); | |
931 | return; | |
fdc50a94 YG |
932 | default: |
933 | break; | |
934 | } | |
f985da17 GL |
935 | |
936 | host->mrq = mrq; | |
fdc50a94 | 937 | |
f985da17 | 938 | sh_mmcif_start_cmd(host, mrq); |
fdc50a94 YG |
939 | } |
940 | ||
a6609267 GL |
941 | static int sh_mmcif_clk_update(struct sh_mmcif_host *host) |
942 | { | |
943 | int ret = clk_enable(host->hclk); | |
944 | ||
945 | if (!ret) { | |
946 | host->clk = clk_get_rate(host->hclk); | |
947 | host->mmc->f_max = host->clk / 2; | |
948 | host->mmc->f_min = host->clk / 512; | |
949 | } | |
950 | ||
951 | return ret; | |
952 | } | |
953 | ||
7d17baa0 GL |
954 | static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) |
955 | { | |
956 | struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; | |
957 | struct mmc_host *mmc = host->mmc; | |
958 | ||
bf68a812 | 959 | if (pd && pd->set_pwr) |
7d17baa0 GL |
960 | pd->set_pwr(host->pd, ios->power_mode != MMC_POWER_OFF); |
961 | if (!IS_ERR(mmc->supply.vmmc)) | |
962 | /* Errors ignored... */ | |
963 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, | |
964 | ios->power_mode ? ios->vdd : 0); | |
965 | } | |
966 | ||
fdc50a94 YG |
967 | static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
968 | { | |
969 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
3b0beafc GL |
970 | unsigned long flags; |
971 | ||
972 | spin_lock_irqsave(&host->lock, flags); | |
973 | if (host->state != STATE_IDLE) { | |
974 | spin_unlock_irqrestore(&host->lock, flags); | |
975 | return; | |
976 | } | |
977 | ||
978 | host->state = STATE_IOS; | |
979 | spin_unlock_irqrestore(&host->lock, flags); | |
fdc50a94 | 980 | |
f5e0cec4 | 981 | if (ios->power_mode == MMC_POWER_UP) { |
c9b0cef2 | 982 | if (!host->card_present) { |
faca6648 GL |
983 | /* See if we also get DMA */ |
984 | sh_mmcif_request_dma(host, host->pd->dev.platform_data); | |
c9b0cef2 | 985 | host->card_present = true; |
faca6648 | 986 | } |
7d17baa0 | 987 | sh_mmcif_set_power(host, ios); |
f5e0cec4 | 988 | } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { |
fdc50a94 YG |
989 | /* clock stop */ |
990 | sh_mmcif_clock_control(host, 0); | |
faca6648 | 991 | if (ios->power_mode == MMC_POWER_OFF) { |
c9b0cef2 | 992 | if (host->card_present) { |
faca6648 | 993 | sh_mmcif_release_dma(host); |
c9b0cef2 | 994 | host->card_present = false; |
faca6648 | 995 | } |
c9b0cef2 GL |
996 | } |
997 | if (host->power) { | |
f8a8ced7 | 998 | pm_runtime_put_sync(&host->pd->dev); |
b289174f | 999 | clk_disable(host->hclk); |
c9b0cef2 | 1000 | host->power = false; |
7d17baa0 GL |
1001 | if (ios->power_mode == MMC_POWER_OFF) |
1002 | sh_mmcif_set_power(host, ios); | |
faca6648 | 1003 | } |
3b0beafc | 1004 | host->state = STATE_IDLE; |
fdc50a94 | 1005 | return; |
fdc50a94 YG |
1006 | } |
1007 | ||
c9b0cef2 GL |
1008 | if (ios->clock) { |
1009 | if (!host->power) { | |
a6609267 | 1010 | sh_mmcif_clk_update(host); |
c9b0cef2 GL |
1011 | pm_runtime_get_sync(&host->pd->dev); |
1012 | host->power = true; | |
1013 | sh_mmcif_sync_reset(host); | |
1014 | } | |
fdc50a94 | 1015 | sh_mmcif_clock_control(host, ios->clock); |
c9b0cef2 | 1016 | } |
fdc50a94 | 1017 | |
555061f9 | 1018 | host->timing = ios->timing; |
fdc50a94 | 1019 | host->bus_width = ios->bus_width; |
3b0beafc | 1020 | host->state = STATE_IDLE; |
fdc50a94 YG |
1021 | } |
1022 | ||
777271d0 AH |
1023 | static int sh_mmcif_get_cd(struct mmc_host *mmc) |
1024 | { | |
1025 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
1026 | struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; | |
e480606a GL |
1027 | int ret = mmc_gpio_get_cd(mmc); |
1028 | ||
1029 | if (ret >= 0) | |
1030 | return ret; | |
777271d0 | 1031 | |
bf68a812 | 1032 | if (!p || !p->get_cd) |
777271d0 AH |
1033 | return -ENOSYS; |
1034 | else | |
1035 | return p->get_cd(host->pd); | |
1036 | } | |
1037 | ||
fdc50a94 YG |
1038 | static struct mmc_host_ops sh_mmcif_ops = { |
1039 | .request = sh_mmcif_request, | |
1040 | .set_ios = sh_mmcif_set_ios, | |
777271d0 | 1041 | .get_cd = sh_mmcif_get_cd, |
fdc50a94 YG |
1042 | }; |
1043 | ||
f985da17 GL |
1044 | static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) |
1045 | { | |
1046 | struct mmc_command *cmd = host->mrq->cmd; | |
69983404 | 1047 | struct mmc_data *data = host->mrq->data; |
f985da17 GL |
1048 | long time; |
1049 | ||
1050 | if (host->sd_error) { | |
1051 | switch (cmd->opcode) { | |
1052 | case MMC_ALL_SEND_CID: | |
1053 | case MMC_SELECT_CARD: | |
1054 | case MMC_APP_CMD: | |
1055 | cmd->error = -ETIMEDOUT; | |
1056 | host->sd_error = false; | |
1057 | break; | |
1058 | default: | |
1059 | cmd->error = sh_mmcif_error_manage(host); | |
1060 | dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n", | |
1061 | cmd->opcode, cmd->error); | |
1062 | break; | |
1063 | } | |
1064 | return false; | |
1065 | } | |
1066 | if (!(cmd->flags & MMC_RSP_PRESENT)) { | |
1067 | cmd->error = 0; | |
1068 | return false; | |
1069 | } | |
1070 | ||
1071 | sh_mmcif_get_response(host, cmd); | |
1072 | ||
69983404 | 1073 | if (!data) |
f985da17 GL |
1074 | return false; |
1075 | ||
69983404 | 1076 | if (data->flags & MMC_DATA_READ) { |
f985da17 GL |
1077 | if (host->chan_rx) |
1078 | sh_mmcif_start_dma_rx(host); | |
1079 | } else { | |
1080 | if (host->chan_tx) | |
1081 | sh_mmcif_start_dma_tx(host); | |
1082 | } | |
1083 | ||
1084 | if (!host->dma_active) { | |
69983404 GL |
1085 | data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); |
1086 | if (!data->error) | |
f985da17 GL |
1087 | return true; |
1088 | return false; | |
1089 | } | |
1090 | ||
1091 | /* Running in the IRQ thread, can sleep */ | |
1092 | time = wait_for_completion_interruptible_timeout(&host->dma_complete, | |
1093 | host->timeout); | |
1094 | if (host->sd_error) { | |
1095 | dev_err(host->mmc->parent, | |
1096 | "Error IRQ while waiting for DMA completion!\n"); | |
1097 | /* Woken up by an error IRQ: abort DMA */ | |
69983404 | 1098 | if (data->flags & MMC_DATA_READ) |
f985da17 GL |
1099 | dmaengine_terminate_all(host->chan_rx); |
1100 | else | |
1101 | dmaengine_terminate_all(host->chan_tx); | |
69983404 | 1102 | data->error = sh_mmcif_error_manage(host); |
f985da17 | 1103 | } else if (!time) { |
69983404 | 1104 | data->error = -ETIMEDOUT; |
f985da17 | 1105 | } else if (time < 0) { |
69983404 | 1106 | data->error = time; |
f985da17 GL |
1107 | } |
1108 | sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, | |
1109 | BUF_ACC_DMAREN | BUF_ACC_DMAWEN); | |
1110 | host->dma_active = false; | |
1111 | ||
69983404 GL |
1112 | if (data->error) |
1113 | data->bytes_xfered = 0; | |
f985da17 GL |
1114 | |
1115 | return false; | |
1116 | } | |
1117 | ||
1118 | static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) | |
1119 | { | |
1120 | struct sh_mmcif_host *host = dev_id; | |
1121 | struct mmc_request *mrq = host->mrq; | |
1122 | ||
1123 | cancel_delayed_work_sync(&host->timeout_work); | |
1124 | ||
1125 | /* | |
1126 | * All handlers return true, if processing continues, and false, if the | |
1127 | * request has to be completed - successfully or not | |
1128 | */ | |
1129 | switch (host->wait_for) { | |
1130 | case MMCIF_WAIT_FOR_REQUEST: | |
1131 | /* We're too late, the timeout has already kicked in */ | |
1132 | return IRQ_HANDLED; | |
1133 | case MMCIF_WAIT_FOR_CMD: | |
1134 | if (sh_mmcif_end_cmd(host)) | |
1135 | /* Wait for data */ | |
1136 | return IRQ_HANDLED; | |
1137 | break; | |
1138 | case MMCIF_WAIT_FOR_MREAD: | |
1139 | if (sh_mmcif_mread_block(host)) | |
1140 | /* Wait for more data */ | |
1141 | return IRQ_HANDLED; | |
1142 | break; | |
1143 | case MMCIF_WAIT_FOR_READ: | |
1144 | if (sh_mmcif_read_block(host)) | |
1145 | /* Wait for data end */ | |
1146 | return IRQ_HANDLED; | |
1147 | break; | |
1148 | case MMCIF_WAIT_FOR_MWRITE: | |
1149 | if (sh_mmcif_mwrite_block(host)) | |
1150 | /* Wait data to write */ | |
1151 | return IRQ_HANDLED; | |
1152 | break; | |
1153 | case MMCIF_WAIT_FOR_WRITE: | |
1154 | if (sh_mmcif_write_block(host)) | |
1155 | /* Wait for data end */ | |
1156 | return IRQ_HANDLED; | |
1157 | break; | |
1158 | case MMCIF_WAIT_FOR_STOP: | |
1159 | if (host->sd_error) { | |
1160 | mrq->stop->error = sh_mmcif_error_manage(host); | |
1161 | break; | |
1162 | } | |
1163 | sh_mmcif_get_cmd12response(host, mrq->stop); | |
1164 | mrq->stop->error = 0; | |
1165 | break; | |
1166 | case MMCIF_WAIT_FOR_READ_END: | |
1167 | case MMCIF_WAIT_FOR_WRITE_END: | |
1168 | if (host->sd_error) | |
91ab252a | 1169 | mrq->data->error = sh_mmcif_error_manage(host); |
f985da17 GL |
1170 | break; |
1171 | default: | |
1172 | BUG(); | |
1173 | } | |
1174 | ||
1175 | if (host->wait_for != MMCIF_WAIT_FOR_STOP) { | |
91ab252a | 1176 | struct mmc_data *data = mrq->data; |
69983404 GL |
1177 | if (!mrq->cmd->error && data && !data->error) |
1178 | data->bytes_xfered = | |
1179 | data->blocks * data->blksz; | |
f985da17 | 1180 | |
69983404 | 1181 | if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { |
f985da17 GL |
1182 | sh_mmcif_stop_cmd(host, mrq); |
1183 | if (!mrq->stop->error) | |
1184 | return IRQ_HANDLED; | |
1185 | } | |
1186 | } | |
1187 | ||
1188 | host->wait_for = MMCIF_WAIT_FOR_REQUEST; | |
1189 | host->state = STATE_IDLE; | |
69983404 | 1190 | host->mrq = NULL; |
f985da17 GL |
1191 | mmc_request_done(host->mmc, mrq); |
1192 | ||
1193 | return IRQ_HANDLED; | |
1194 | } | |
1195 | ||
fdc50a94 YG |
1196 | static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) |
1197 | { | |
1198 | struct sh_mmcif_host *host = dev_id; | |
aa0787a9 | 1199 | u32 state; |
fdc50a94 YG |
1200 | int err = 0; |
1201 | ||
487d9fc5 | 1202 | state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); |
fdc50a94 | 1203 | |
8a8284a9 GL |
1204 | if (state & INT_ERR_STS) { |
1205 | /* error interrupts - process first */ | |
1206 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); | |
1207 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); | |
1208 | err = 1; | |
1209 | } else if (state & INT_RBSYE) { | |
487d9fc5 MD |
1210 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, |
1211 | ~(INT_RBSYE | INT_CRSPE)); | |
fdc50a94 YG |
1212 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE); |
1213 | } else if (state & INT_CRSPE) { | |
487d9fc5 | 1214 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE); |
fdc50a94 YG |
1215 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE); |
1216 | } else if (state & INT_BUFREN) { | |
487d9fc5 | 1217 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN); |
fdc50a94 YG |
1218 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); |
1219 | } else if (state & INT_BUFWEN) { | |
487d9fc5 | 1220 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN); |
fdc50a94 YG |
1221 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
1222 | } else if (state & INT_CMD12DRE) { | |
487d9fc5 | 1223 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, |
fdc50a94 YG |
1224 | ~(INT_CMD12DRE | INT_CMD12RBE | |
1225 | INT_CMD12CRE | INT_BUFRE)); | |
1226 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); | |
1227 | } else if (state & INT_BUFRE) { | |
487d9fc5 | 1228 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE); |
fdc50a94 YG |
1229 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); |
1230 | } else if (state & INT_DTRANE) { | |
7a7eb328 GL |
1231 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, |
1232 | ~(INT_CMD12DRE | INT_CMD12RBE | | |
1233 | INT_CMD12CRE | INT_DTRANE)); | |
fdc50a94 YG |
1234 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); |
1235 | } else if (state & INT_CMD12RBE) { | |
487d9fc5 | 1236 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, |
fdc50a94 YG |
1237 | ~(INT_CMD12RBE | INT_CMD12CRE)); |
1238 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); | |
fdc50a94 | 1239 | } else { |
faca6648 | 1240 | dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state); |
487d9fc5 | 1241 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); |
fdc50a94 YG |
1242 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); |
1243 | err = 1; | |
1244 | } | |
1245 | if (err) { | |
aa0787a9 | 1246 | host->sd_error = true; |
e47bf32a | 1247 | dev_dbg(&host->pd->dev, "int err state = %08x\n", state); |
fdc50a94 | 1248 | } |
f985da17 GL |
1249 | if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { |
1250 | if (!host->dma_active) | |
1251 | return IRQ_WAKE_THREAD; | |
1252 | else if (host->sd_error) | |
1253 | mmcif_dma_complete(host); | |
1254 | } else { | |
aa0787a9 | 1255 | dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); |
f985da17 | 1256 | } |
fdc50a94 YG |
1257 | |
1258 | return IRQ_HANDLED; | |
1259 | } | |
1260 | ||
f985da17 GL |
1261 | static void mmcif_timeout_work(struct work_struct *work) |
1262 | { | |
1263 | struct delayed_work *d = container_of(work, struct delayed_work, work); | |
1264 | struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); | |
1265 | struct mmc_request *mrq = host->mrq; | |
1266 | ||
1267 | if (host->dying) | |
1268 | /* Don't run after mmc_remove_host() */ | |
1269 | return; | |
1270 | ||
1271 | /* | |
1272 | * Handle races with cancel_delayed_work(), unless | |
1273 | * cancel_delayed_work_sync() is used | |
1274 | */ | |
1275 | switch (host->wait_for) { | |
1276 | case MMCIF_WAIT_FOR_CMD: | |
1277 | mrq->cmd->error = sh_mmcif_error_manage(host); | |
1278 | break; | |
1279 | case MMCIF_WAIT_FOR_STOP: | |
1280 | mrq->stop->error = sh_mmcif_error_manage(host); | |
1281 | break; | |
1282 | case MMCIF_WAIT_FOR_MREAD: | |
1283 | case MMCIF_WAIT_FOR_MWRITE: | |
1284 | case MMCIF_WAIT_FOR_READ: | |
1285 | case MMCIF_WAIT_FOR_WRITE: | |
1286 | case MMCIF_WAIT_FOR_READ_END: | |
1287 | case MMCIF_WAIT_FOR_WRITE_END: | |
69983404 | 1288 | mrq->data->error = sh_mmcif_error_manage(host); |
f985da17 GL |
1289 | break; |
1290 | default: | |
1291 | BUG(); | |
1292 | } | |
1293 | ||
1294 | host->state = STATE_IDLE; | |
1295 | host->wait_for = MMCIF_WAIT_FOR_REQUEST; | |
f985da17 GL |
1296 | host->mrq = NULL; |
1297 | mmc_request_done(host->mmc, mrq); | |
1298 | } | |
1299 | ||
7d17baa0 GL |
1300 | static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) |
1301 | { | |
1302 | struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; | |
1303 | struct mmc_host *mmc = host->mmc; | |
1304 | ||
1305 | mmc_regulator_get_supply(mmc); | |
1306 | ||
bf68a812 GL |
1307 | if (!pd) |
1308 | return; | |
1309 | ||
7d17baa0 GL |
1310 | if (!mmc->ocr_avail) |
1311 | mmc->ocr_avail = pd->ocr; | |
1312 | else if (pd->ocr) | |
1313 | dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); | |
1314 | } | |
1315 | ||
c3be1efd | 1316 | static int sh_mmcif_probe(struct platform_device *pdev) |
fdc50a94 YG |
1317 | { |
1318 | int ret = 0, irq[2]; | |
1319 | struct mmc_host *mmc; | |
e47bf32a | 1320 | struct sh_mmcif_host *host; |
e1aae2eb | 1321 | struct sh_mmcif_plat_data *pd = pdev->dev.platform_data; |
fdc50a94 YG |
1322 | struct resource *res; |
1323 | void __iomem *reg; | |
2cd5b3e0 | 1324 | const char *name; |
fdc50a94 YG |
1325 | |
1326 | irq[0] = platform_get_irq(pdev, 0); | |
1327 | irq[1] = platform_get_irq(pdev, 1); | |
2cd5b3e0 | 1328 | if (irq[0] < 0) { |
e47bf32a | 1329 | dev_err(&pdev->dev, "Get irq error\n"); |
fdc50a94 YG |
1330 | return -ENXIO; |
1331 | } | |
1332 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1333 | if (!res) { | |
1334 | dev_err(&pdev->dev, "platform_get_resource error.\n"); | |
1335 | return -ENXIO; | |
1336 | } | |
1337 | reg = ioremap(res->start, resource_size(res)); | |
1338 | if (!reg) { | |
1339 | dev_err(&pdev->dev, "ioremap error.\n"); | |
1340 | return -ENOMEM; | |
1341 | } | |
e1aae2eb | 1342 | |
fdc50a94 YG |
1343 | mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); |
1344 | if (!mmc) { | |
1345 | ret = -ENOMEM; | |
e1aae2eb | 1346 | goto ealloch; |
fdc50a94 YG |
1347 | } |
1348 | host = mmc_priv(mmc); | |
1349 | host->mmc = mmc; | |
1350 | host->addr = reg; | |
1351 | host->timeout = 1000; | |
1352 | ||
fdc50a94 YG |
1353 | host->pd = pdev; |
1354 | ||
3b0beafc | 1355 | spin_lock_init(&host->lock); |
fdc50a94 YG |
1356 | |
1357 | mmc->ops = &sh_mmcif_ops; | |
7d17baa0 GL |
1358 | sh_mmcif_init_ocr(host); |
1359 | ||
fdc50a94 | 1360 | mmc->caps = MMC_CAP_MMC_HIGHSPEED; |
bf68a812 | 1361 | if (pd && pd->caps) |
fdc50a94 | 1362 | mmc->caps |= pd->caps; |
a782d688 | 1363 | mmc->max_segs = 32; |
fdc50a94 | 1364 | mmc->max_blk_size = 512; |
a782d688 GL |
1365 | mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; |
1366 | mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; | |
fdc50a94 YG |
1367 | mmc->max_seg_size = mmc->max_req_size; |
1368 | ||
fdc50a94 | 1369 | platform_set_drvdata(pdev, host); |
a782d688 | 1370 | |
faca6648 GL |
1371 | pm_runtime_enable(&pdev->dev); |
1372 | host->power = false; | |
1373 | ||
047a9ce7 | 1374 | host->hclk = clk_get(&pdev->dev, NULL); |
b289174f GL |
1375 | if (IS_ERR(host->hclk)) { |
1376 | ret = PTR_ERR(host->hclk); | |
047a9ce7 | 1377 | dev_err(&pdev->dev, "cannot get clock: %d\n", ret); |
b289174f GL |
1378 | goto eclkget; |
1379 | } | |
a6609267 GL |
1380 | ret = sh_mmcif_clk_update(host); |
1381 | if (ret < 0) | |
1382 | goto eclkupdate; | |
b289174f | 1383 | |
faca6648 GL |
1384 | ret = pm_runtime_resume(&pdev->dev); |
1385 | if (ret < 0) | |
e1aae2eb | 1386 | goto eresume; |
a782d688 | 1387 | |
5ba85d95 | 1388 | INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work); |
fdc50a94 | 1389 | |
b289174f | 1390 | sh_mmcif_sync_reset(host); |
3b0beafc GL |
1391 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
1392 | ||
2cd5b3e0 SK |
1393 | name = irq[1] < 0 ? dev_name(&pdev->dev) : "sh_mmc:error"; |
1394 | ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, name, host); | |
fdc50a94 | 1395 | if (ret) { |
2cd5b3e0 | 1396 | dev_err(&pdev->dev, "request_irq error (%s)\n", name); |
e1aae2eb | 1397 | goto ereqirq0; |
fdc50a94 | 1398 | } |
2cd5b3e0 SK |
1399 | if (irq[1] >= 0) { |
1400 | ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, | |
1401 | 0, "sh_mmc:int", host); | |
1402 | if (ret) { | |
1403 | dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n"); | |
1404 | goto ereqirq1; | |
1405 | } | |
fdc50a94 YG |
1406 | } |
1407 | ||
e480606a GL |
1408 | if (pd && pd->use_cd_gpio) { |
1409 | ret = mmc_gpio_request_cd(mmc, pd->cd_gpio); | |
1410 | if (ret < 0) | |
1411 | goto erqcd; | |
1412 | } | |
1413 | ||
b289174f | 1414 | clk_disable(host->hclk); |
5ba85d95 GL |
1415 | ret = mmc_add_host(mmc); |
1416 | if (ret < 0) | |
e1aae2eb | 1417 | goto emmcaddh; |
fdc50a94 | 1418 | |
efe6a8ad RW |
1419 | dev_pm_qos_expose_latency_limit(&pdev->dev, 100); |
1420 | ||
e47bf32a GL |
1421 | dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION); |
1422 | dev_dbg(&pdev->dev, "chip ver H'%04x\n", | |
487d9fc5 | 1423 | sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff); |
fdc50a94 YG |
1424 | return ret; |
1425 | ||
e1aae2eb | 1426 | emmcaddh: |
e480606a | 1427 | erqcd: |
2cd5b3e0 SK |
1428 | if (irq[1] >= 0) |
1429 | free_irq(irq[1], host); | |
e1aae2eb | 1430 | ereqirq1: |
5ba85d95 | 1431 | free_irq(irq[0], host); |
e1aae2eb | 1432 | ereqirq0: |
faca6648 | 1433 | pm_runtime_suspend(&pdev->dev); |
e1aae2eb | 1434 | eresume: |
fdc50a94 | 1435 | clk_disable(host->hclk); |
a6609267 | 1436 | eclkupdate: |
b289174f | 1437 | clk_put(host->hclk); |
e1aae2eb | 1438 | eclkget: |
b289174f | 1439 | pm_runtime_disable(&pdev->dev); |
fdc50a94 | 1440 | mmc_free_host(mmc); |
e1aae2eb GL |
1441 | ealloch: |
1442 | iounmap(reg); | |
fdc50a94 YG |
1443 | return ret; |
1444 | } | |
1445 | ||
6e0ee714 | 1446 | static int sh_mmcif_remove(struct platform_device *pdev) |
fdc50a94 YG |
1447 | { |
1448 | struct sh_mmcif_host *host = platform_get_drvdata(pdev); | |
1449 | int irq[2]; | |
1450 | ||
f985da17 | 1451 | host->dying = true; |
b289174f | 1452 | clk_enable(host->hclk); |
faca6648 | 1453 | pm_runtime_get_sync(&pdev->dev); |
fdc50a94 | 1454 | |
efe6a8ad RW |
1455 | dev_pm_qos_hide_latency_limit(&pdev->dev); |
1456 | ||
faca6648 | 1457 | mmc_remove_host(host->mmc); |
3b0beafc GL |
1458 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
1459 | ||
f985da17 GL |
1460 | /* |
1461 | * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the | |
1462 | * mmc_remove_host() call above. But swapping order doesn't help either | |
1463 | * (a query on the linux-mmc mailing list didn't bring any replies). | |
1464 | */ | |
1465 | cancel_delayed_work_sync(&host->timeout_work); | |
1466 | ||
fdc50a94 YG |
1467 | if (host->addr) |
1468 | iounmap(host->addr); | |
1469 | ||
aa0787a9 GL |
1470 | irq[0] = platform_get_irq(pdev, 0); |
1471 | irq[1] = platform_get_irq(pdev, 1); | |
fdc50a94 YG |
1472 | |
1473 | free_irq(irq[0], host); | |
2cd5b3e0 SK |
1474 | if (irq[1] >= 0) |
1475 | free_irq(irq[1], host); | |
fdc50a94 | 1476 | |
aa0787a9 GL |
1477 | platform_set_drvdata(pdev, NULL); |
1478 | ||
a0d28ba0 | 1479 | clk_disable(host->hclk); |
fdc50a94 | 1480 | mmc_free_host(host->mmc); |
faca6648 GL |
1481 | pm_runtime_put_sync(&pdev->dev); |
1482 | pm_runtime_disable(&pdev->dev); | |
fdc50a94 YG |
1483 | |
1484 | return 0; | |
1485 | } | |
1486 | ||
faca6648 GL |
1487 | #ifdef CONFIG_PM |
1488 | static int sh_mmcif_suspend(struct device *dev) | |
1489 | { | |
b289174f | 1490 | struct sh_mmcif_host *host = dev_get_drvdata(dev); |
faca6648 GL |
1491 | int ret = mmc_suspend_host(host->mmc); |
1492 | ||
b289174f | 1493 | if (!ret) |
faca6648 | 1494 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
faca6648 GL |
1495 | |
1496 | return ret; | |
1497 | } | |
1498 | ||
1499 | static int sh_mmcif_resume(struct device *dev) | |
1500 | { | |
b289174f | 1501 | struct sh_mmcif_host *host = dev_get_drvdata(dev); |
faca6648 GL |
1502 | |
1503 | return mmc_resume_host(host->mmc); | |
1504 | } | |
1505 | #else | |
1506 | #define sh_mmcif_suspend NULL | |
1507 | #define sh_mmcif_resume NULL | |
1508 | #endif /* CONFIG_PM */ | |
1509 | ||
bf68a812 GL |
1510 | static const struct of_device_id mmcif_of_match[] = { |
1511 | { .compatible = "renesas,sh-mmcif" }, | |
1512 | { } | |
1513 | }; | |
1514 | MODULE_DEVICE_TABLE(of, mmcif_of_match); | |
1515 | ||
faca6648 GL |
1516 | static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { |
1517 | .suspend = sh_mmcif_suspend, | |
1518 | .resume = sh_mmcif_resume, | |
1519 | }; | |
1520 | ||
fdc50a94 YG |
1521 | static struct platform_driver sh_mmcif_driver = { |
1522 | .probe = sh_mmcif_probe, | |
1523 | .remove = sh_mmcif_remove, | |
1524 | .driver = { | |
1525 | .name = DRIVER_NAME, | |
faca6648 | 1526 | .pm = &sh_mmcif_dev_pm_ops, |
bf68a812 GL |
1527 | .owner = THIS_MODULE, |
1528 | .of_match_table = mmcif_of_match, | |
fdc50a94 YG |
1529 | }, |
1530 | }; | |
1531 | ||
d1f81a64 | 1532 | module_platform_driver(sh_mmcif_driver); |
fdc50a94 YG |
1533 | |
1534 | MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); | |
1535 | MODULE_LICENSE("GPL"); | |
aa0787a9 | 1536 | MODULE_ALIAS("platform:" DRIVER_NAME); |
fdc50a94 | 1537 | MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); |