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Commit | Line | Data |
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fdc50a94 YG |
1 | /* |
2 | * MMCIF eMMC driver. | |
3 | * | |
4 | * Copyright (C) 2010 Renesas Solutions Corp. | |
5 | * Yusuke Goda <yusuke.goda.sx@renesas.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License. | |
10 | * | |
11 | * | |
12 | * TODO | |
13 | * 1. DMA | |
14 | * 2. Power management | |
15 | * 3. Handle MMC errors better | |
16 | * | |
17 | */ | |
18 | ||
aa0787a9 GL |
19 | #include <linux/clk.h> |
20 | #include <linux/completion.h> | |
e47bf32a | 21 | #include <linux/delay.h> |
fdc50a94 | 22 | #include <linux/dma-mapping.h> |
fdc50a94 YG |
23 | #include <linux/mmc/card.h> |
24 | #include <linux/mmc/core.h> | |
e47bf32a | 25 | #include <linux/mmc/host.h> |
fdc50a94 YG |
26 | #include <linux/mmc/mmc.h> |
27 | #include <linux/mmc/sdio.h> | |
fdc50a94 | 28 | #include <linux/mmc/sh_mmcif.h> |
e47bf32a | 29 | #include <linux/platform_device.h> |
fdc50a94 YG |
30 | |
31 | #define DRIVER_NAME "sh_mmcif" | |
32 | #define DRIVER_VERSION "2010-04-28" | |
33 | ||
fdc50a94 YG |
34 | /* CE_CMD_SET */ |
35 | #define CMD_MASK 0x3f000000 | |
36 | #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) | |
37 | #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ | |
38 | #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ | |
39 | #define CMD_SET_RBSY (1 << 21) /* R1b */ | |
40 | #define CMD_SET_CCSEN (1 << 20) | |
41 | #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ | |
42 | #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ | |
43 | #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ | |
44 | #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ | |
45 | #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ | |
46 | #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ | |
47 | #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ | |
48 | #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ | |
49 | #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ | |
50 | #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ | |
51 | #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ | |
52 | #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ | |
53 | #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ | |
54 | #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ | |
55 | #define CMD_SET_CCSH (1 << 5) | |
56 | #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ | |
57 | #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ | |
58 | #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ | |
59 | ||
60 | /* CE_CMD_CTRL */ | |
61 | #define CMD_CTRL_BREAK (1 << 0) | |
62 | ||
63 | /* CE_BLOCK_SET */ | |
64 | #define BLOCK_SIZE_MASK 0x0000ffff | |
65 | ||
fdc50a94 YG |
66 | /* CE_INT */ |
67 | #define INT_CCSDE (1 << 29) | |
68 | #define INT_CMD12DRE (1 << 26) | |
69 | #define INT_CMD12RBE (1 << 25) | |
70 | #define INT_CMD12CRE (1 << 24) | |
71 | #define INT_DTRANE (1 << 23) | |
72 | #define INT_BUFRE (1 << 22) | |
73 | #define INT_BUFWEN (1 << 21) | |
74 | #define INT_BUFREN (1 << 20) | |
75 | #define INT_CCSRCV (1 << 19) | |
76 | #define INT_RBSYE (1 << 17) | |
77 | #define INT_CRSPE (1 << 16) | |
78 | #define INT_CMDVIO (1 << 15) | |
79 | #define INT_BUFVIO (1 << 14) | |
80 | #define INT_WDATERR (1 << 11) | |
81 | #define INT_RDATERR (1 << 10) | |
82 | #define INT_RIDXERR (1 << 9) | |
83 | #define INT_RSPERR (1 << 8) | |
84 | #define INT_CCSTO (1 << 5) | |
85 | #define INT_CRCSTO (1 << 4) | |
86 | #define INT_WDATTO (1 << 3) | |
87 | #define INT_RDATTO (1 << 2) | |
88 | #define INT_RBSYTO (1 << 1) | |
89 | #define INT_RSPTO (1 << 0) | |
90 | #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ | |
91 | INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ | |
92 | INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ | |
93 | INT_RDATTO | INT_RBSYTO | INT_RSPTO) | |
94 | ||
95 | /* CE_INT_MASK */ | |
96 | #define MASK_ALL 0x00000000 | |
97 | #define MASK_MCCSDE (1 << 29) | |
98 | #define MASK_MCMD12DRE (1 << 26) | |
99 | #define MASK_MCMD12RBE (1 << 25) | |
100 | #define MASK_MCMD12CRE (1 << 24) | |
101 | #define MASK_MDTRANE (1 << 23) | |
102 | #define MASK_MBUFRE (1 << 22) | |
103 | #define MASK_MBUFWEN (1 << 21) | |
104 | #define MASK_MBUFREN (1 << 20) | |
105 | #define MASK_MCCSRCV (1 << 19) | |
106 | #define MASK_MRBSYE (1 << 17) | |
107 | #define MASK_MCRSPE (1 << 16) | |
108 | #define MASK_MCMDVIO (1 << 15) | |
109 | #define MASK_MBUFVIO (1 << 14) | |
110 | #define MASK_MWDATERR (1 << 11) | |
111 | #define MASK_MRDATERR (1 << 10) | |
112 | #define MASK_MRIDXERR (1 << 9) | |
113 | #define MASK_MRSPERR (1 << 8) | |
114 | #define MASK_MCCSTO (1 << 5) | |
115 | #define MASK_MCRCSTO (1 << 4) | |
116 | #define MASK_MWDATTO (1 << 3) | |
117 | #define MASK_MRDATTO (1 << 2) | |
118 | #define MASK_MRBSYTO (1 << 1) | |
119 | #define MASK_MRSPTO (1 << 0) | |
120 | ||
121 | /* CE_HOST_STS1 */ | |
122 | #define STS1_CMDSEQ (1 << 31) | |
123 | ||
124 | /* CE_HOST_STS2 */ | |
125 | #define STS2_CRCSTE (1 << 31) | |
126 | #define STS2_CRC16E (1 << 30) | |
127 | #define STS2_AC12CRCE (1 << 29) | |
128 | #define STS2_RSPCRC7E (1 << 28) | |
129 | #define STS2_CRCSTEBE (1 << 27) | |
130 | #define STS2_RDATEBE (1 << 26) | |
131 | #define STS2_AC12REBE (1 << 25) | |
132 | #define STS2_RSPEBE (1 << 24) | |
133 | #define STS2_AC12IDXE (1 << 23) | |
134 | #define STS2_RSPIDXE (1 << 22) | |
135 | #define STS2_CCSTO (1 << 15) | |
136 | #define STS2_RDATTO (1 << 14) | |
137 | #define STS2_DATBSYTO (1 << 13) | |
138 | #define STS2_CRCSTTO (1 << 12) | |
139 | #define STS2_AC12BSYTO (1 << 11) | |
140 | #define STS2_RSPBSYTO (1 << 10) | |
141 | #define STS2_AC12RSPTO (1 << 9) | |
142 | #define STS2_RSPTO (1 << 8) | |
143 | #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ | |
144 | STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) | |
145 | #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ | |
146 | STS2_DATBSYTO | STS2_CRCSTTO | \ | |
147 | STS2_AC12BSYTO | STS2_RSPBSYTO | \ | |
148 | STS2_AC12RSPTO | STS2_RSPTO) | |
149 | ||
fdc50a94 YG |
150 | #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ |
151 | #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ | |
152 | #define CLKDEV_INIT 400000 /* 400 KHz */ | |
153 | ||
154 | struct sh_mmcif_host { | |
155 | struct mmc_host *mmc; | |
156 | struct mmc_data *data; | |
fdc50a94 YG |
157 | struct platform_device *pd; |
158 | struct clk *hclk; | |
159 | unsigned int clk; | |
160 | int bus_width; | |
aa0787a9 | 161 | bool sd_error; |
fdc50a94 YG |
162 | long timeout; |
163 | void __iomem *addr; | |
aa0787a9 | 164 | struct completion intr_wait; |
fdc50a94 YG |
165 | }; |
166 | ||
fdc50a94 YG |
167 | |
168 | static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, | |
169 | unsigned int reg, u32 val) | |
170 | { | |
487d9fc5 | 171 | writel(val | readl(host->addr + reg), host->addr + reg); |
fdc50a94 YG |
172 | } |
173 | ||
174 | static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, | |
175 | unsigned int reg, u32 val) | |
176 | { | |
487d9fc5 | 177 | writel(~val & readl(host->addr + reg), host->addr + reg); |
fdc50a94 YG |
178 | } |
179 | ||
180 | ||
181 | static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) | |
182 | { | |
183 | struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; | |
184 | ||
185 | sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); | |
186 | sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); | |
187 | ||
188 | if (!clk) | |
189 | return; | |
190 | if (p->sup_pclk && clk == host->clk) | |
191 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); | |
192 | else | |
193 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & | |
194 | (ilog2(__rounddown_pow_of_two(host->clk / clk)) << 16)); | |
195 | ||
196 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); | |
197 | } | |
198 | ||
199 | static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) | |
200 | { | |
201 | u32 tmp; | |
202 | ||
487d9fc5 | 203 | tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); |
fdc50a94 | 204 | |
487d9fc5 MD |
205 | sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); |
206 | sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); | |
fdc50a94 YG |
207 | sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | |
208 | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); | |
209 | /* byte swap on */ | |
210 | sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); | |
211 | } | |
212 | ||
213 | static int sh_mmcif_error_manage(struct sh_mmcif_host *host) | |
214 | { | |
215 | u32 state1, state2; | |
216 | int ret, timeout = 10000000; | |
217 | ||
aa0787a9 | 218 | host->sd_error = false; |
fdc50a94 | 219 | |
487d9fc5 MD |
220 | state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); |
221 | state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); | |
e47bf32a GL |
222 | dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); |
223 | dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); | |
fdc50a94 YG |
224 | |
225 | if (state1 & STS1_CMDSEQ) { | |
226 | sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); | |
227 | sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); | |
228 | while (1) { | |
229 | timeout--; | |
230 | if (timeout < 0) { | |
e47bf32a GL |
231 | dev_err(&host->pd->dev, |
232 | "Forceed end of command sequence timeout err\n"); | |
fdc50a94 YG |
233 | return -EIO; |
234 | } | |
487d9fc5 | 235 | if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) |
fdc50a94 YG |
236 | & STS1_CMDSEQ)) |
237 | break; | |
238 | mdelay(1); | |
239 | } | |
240 | sh_mmcif_sync_reset(host); | |
e47bf32a | 241 | dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); |
fdc50a94 YG |
242 | return -EIO; |
243 | } | |
244 | ||
245 | if (state2 & STS2_CRC_ERR) { | |
e47bf32a | 246 | dev_dbg(&host->pd->dev, ": Happened CRC error\n"); |
fdc50a94 YG |
247 | ret = -EIO; |
248 | } else if (state2 & STS2_TIMEOUT_ERR) { | |
e47bf32a | 249 | dev_dbg(&host->pd->dev, ": Happened Timeout error\n"); |
fdc50a94 YG |
250 | ret = -ETIMEDOUT; |
251 | } else { | |
e47bf32a | 252 | dev_dbg(&host->pd->dev, ": Happened End/Index error\n"); |
fdc50a94 YG |
253 | ret = -EIO; |
254 | } | |
255 | return ret; | |
256 | } | |
257 | ||
258 | static int sh_mmcif_single_read(struct sh_mmcif_host *host, | |
259 | struct mmc_request *mrq) | |
260 | { | |
261 | struct mmc_data *data = mrq->data; | |
262 | long time; | |
263 | u32 blocksize, i, *p = sg_virt(data->sg); | |
264 | ||
fdc50a94 YG |
265 | /* buf read enable */ |
266 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); | |
aa0787a9 GL |
267 | time = wait_for_completion_interruptible_timeout(&host->intr_wait, |
268 | host->timeout); | |
269 | if (time <= 0 || host->sd_error) | |
fdc50a94 YG |
270 | return sh_mmcif_error_manage(host); |
271 | ||
fdc50a94 | 272 | blocksize = (BLOCK_SIZE_MASK & |
487d9fc5 | 273 | sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3; |
fdc50a94 | 274 | for (i = 0; i < blocksize / 4; i++) |
487d9fc5 | 275 | *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); |
fdc50a94 YG |
276 | |
277 | /* buffer read end */ | |
278 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); | |
aa0787a9 GL |
279 | time = wait_for_completion_interruptible_timeout(&host->intr_wait, |
280 | host->timeout); | |
281 | if (time <= 0 || host->sd_error) | |
fdc50a94 YG |
282 | return sh_mmcif_error_manage(host); |
283 | ||
fdc50a94 YG |
284 | return 0; |
285 | } | |
286 | ||
287 | static int sh_mmcif_multi_read(struct sh_mmcif_host *host, | |
288 | struct mmc_request *mrq) | |
289 | { | |
290 | struct mmc_data *data = mrq->data; | |
291 | long time; | |
292 | u32 blocksize, i, j, sec, *p; | |
293 | ||
487d9fc5 MD |
294 | blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr, |
295 | MMCIF_CE_BLOCK_SET); | |
fdc50a94 YG |
296 | for (j = 0; j < data->sg_len; j++) { |
297 | p = sg_virt(data->sg); | |
fdc50a94 YG |
298 | for (sec = 0; sec < data->sg->length / blocksize; sec++) { |
299 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); | |
300 | /* buf read enable */ | |
aa0787a9 GL |
301 | time = wait_for_completion_interruptible_timeout(&host->intr_wait, |
302 | host->timeout); | |
fdc50a94 | 303 | |
aa0787a9 | 304 | if (time <= 0 || host->sd_error) |
fdc50a94 YG |
305 | return sh_mmcif_error_manage(host); |
306 | ||
fdc50a94 | 307 | for (i = 0; i < blocksize / 4; i++) |
487d9fc5 MD |
308 | *p++ = sh_mmcif_readl(host->addr, |
309 | MMCIF_CE_DATA); | |
fdc50a94 YG |
310 | } |
311 | if (j < data->sg_len - 1) | |
312 | data->sg++; | |
313 | } | |
314 | return 0; | |
315 | } | |
316 | ||
317 | static int sh_mmcif_single_write(struct sh_mmcif_host *host, | |
318 | struct mmc_request *mrq) | |
319 | { | |
320 | struct mmc_data *data = mrq->data; | |
321 | long time; | |
322 | u32 blocksize, i, *p = sg_virt(data->sg); | |
323 | ||
fdc50a94 YG |
324 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
325 | ||
326 | /* buf write enable */ | |
aa0787a9 GL |
327 | time = wait_for_completion_interruptible_timeout(&host->intr_wait, |
328 | host->timeout); | |
329 | if (time <= 0 || host->sd_error) | |
fdc50a94 YG |
330 | return sh_mmcif_error_manage(host); |
331 | ||
fdc50a94 | 332 | blocksize = (BLOCK_SIZE_MASK & |
487d9fc5 | 333 | sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3; |
fdc50a94 | 334 | for (i = 0; i < blocksize / 4; i++) |
487d9fc5 | 335 | sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); |
fdc50a94 YG |
336 | |
337 | /* buffer write end */ | |
338 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); | |
339 | ||
aa0787a9 GL |
340 | time = wait_for_completion_interruptible_timeout(&host->intr_wait, |
341 | host->timeout); | |
342 | if (time <= 0 || host->sd_error) | |
fdc50a94 YG |
343 | return sh_mmcif_error_manage(host); |
344 | ||
fdc50a94 YG |
345 | return 0; |
346 | } | |
347 | ||
348 | static int sh_mmcif_multi_write(struct sh_mmcif_host *host, | |
349 | struct mmc_request *mrq) | |
350 | { | |
351 | struct mmc_data *data = mrq->data; | |
352 | long time; | |
353 | u32 i, sec, j, blocksize, *p; | |
354 | ||
487d9fc5 MD |
355 | blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr, |
356 | MMCIF_CE_BLOCK_SET); | |
fdc50a94 YG |
357 | |
358 | for (j = 0; j < data->sg_len; j++) { | |
359 | p = sg_virt(data->sg); | |
fdc50a94 YG |
360 | for (sec = 0; sec < data->sg->length / blocksize; sec++) { |
361 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); | |
362 | /* buf write enable*/ | |
aa0787a9 GL |
363 | time = wait_for_completion_interruptible_timeout(&host->intr_wait, |
364 | host->timeout); | |
fdc50a94 | 365 | |
aa0787a9 | 366 | if (time <= 0 || host->sd_error) |
fdc50a94 YG |
367 | return sh_mmcif_error_manage(host); |
368 | ||
fdc50a94 | 369 | for (i = 0; i < blocksize / 4; i++) |
487d9fc5 MD |
370 | sh_mmcif_writel(host->addr, |
371 | MMCIF_CE_DATA, *p++); | |
fdc50a94 YG |
372 | } |
373 | if (j < data->sg_len - 1) | |
374 | data->sg++; | |
375 | } | |
376 | return 0; | |
377 | } | |
378 | ||
379 | static void sh_mmcif_get_response(struct sh_mmcif_host *host, | |
380 | struct mmc_command *cmd) | |
381 | { | |
382 | if (cmd->flags & MMC_RSP_136) { | |
487d9fc5 MD |
383 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); |
384 | cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); | |
385 | cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); | |
386 | cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); | |
fdc50a94 | 387 | } else |
487d9fc5 | 388 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); |
fdc50a94 YG |
389 | } |
390 | ||
391 | static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, | |
392 | struct mmc_command *cmd) | |
393 | { | |
487d9fc5 | 394 | cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); |
fdc50a94 YG |
395 | } |
396 | ||
397 | static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, | |
398 | struct mmc_request *mrq, struct mmc_command *cmd, u32 opc) | |
399 | { | |
400 | u32 tmp = 0; | |
401 | ||
402 | /* Response Type check */ | |
403 | switch (mmc_resp_type(cmd)) { | |
404 | case MMC_RSP_NONE: | |
405 | tmp |= CMD_SET_RTYP_NO; | |
406 | break; | |
407 | case MMC_RSP_R1: | |
408 | case MMC_RSP_R1B: | |
409 | case MMC_RSP_R3: | |
410 | tmp |= CMD_SET_RTYP_6B; | |
411 | break; | |
412 | case MMC_RSP_R2: | |
413 | tmp |= CMD_SET_RTYP_17B; | |
414 | break; | |
415 | default: | |
e47bf32a | 416 | dev_err(&host->pd->dev, "Unsupported response type.\n"); |
fdc50a94 YG |
417 | break; |
418 | } | |
419 | switch (opc) { | |
420 | /* RBSY */ | |
421 | case MMC_SWITCH: | |
422 | case MMC_STOP_TRANSMISSION: | |
423 | case MMC_SET_WRITE_PROT: | |
424 | case MMC_CLR_WRITE_PROT: | |
425 | case MMC_ERASE: | |
426 | case MMC_GEN_CMD: | |
427 | tmp |= CMD_SET_RBSY; | |
428 | break; | |
429 | } | |
430 | /* WDAT / DATW */ | |
431 | if (host->data) { | |
432 | tmp |= CMD_SET_WDAT; | |
433 | switch (host->bus_width) { | |
434 | case MMC_BUS_WIDTH_1: | |
435 | tmp |= CMD_SET_DATW_1; | |
436 | break; | |
437 | case MMC_BUS_WIDTH_4: | |
438 | tmp |= CMD_SET_DATW_4; | |
439 | break; | |
440 | case MMC_BUS_WIDTH_8: | |
441 | tmp |= CMD_SET_DATW_8; | |
442 | break; | |
443 | default: | |
e47bf32a | 444 | dev_err(&host->pd->dev, "Unsupported bus width.\n"); |
fdc50a94 YG |
445 | break; |
446 | } | |
447 | } | |
448 | /* DWEN */ | |
449 | if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) | |
450 | tmp |= CMD_SET_DWEN; | |
451 | /* CMLTE/CMD12EN */ | |
452 | if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { | |
453 | tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; | |
454 | sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, | |
455 | mrq->data->blocks << 16); | |
456 | } | |
457 | /* RIDXC[1:0] check bits */ | |
458 | if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || | |
459 | opc == MMC_SEND_CSD || opc == MMC_SEND_CID) | |
460 | tmp |= CMD_SET_RIDXC_BITS; | |
461 | /* RCRC7C[1:0] check bits */ | |
462 | if (opc == MMC_SEND_OP_COND) | |
463 | tmp |= CMD_SET_CRC7C_BITS; | |
464 | /* RCRC7C[1:0] internal CRC7 */ | |
465 | if (opc == MMC_ALL_SEND_CID || | |
466 | opc == MMC_SEND_CSD || opc == MMC_SEND_CID) | |
467 | tmp |= CMD_SET_CRC7C_INTERNAL; | |
468 | ||
469 | return opc = ((opc << 24) | tmp); | |
470 | } | |
471 | ||
e47bf32a | 472 | static int sh_mmcif_data_trans(struct sh_mmcif_host *host, |
fdc50a94 YG |
473 | struct mmc_request *mrq, u32 opc) |
474 | { | |
e47bf32a | 475 | int ret; |
fdc50a94 YG |
476 | |
477 | switch (opc) { | |
478 | case MMC_READ_MULTIPLE_BLOCK: | |
479 | ret = sh_mmcif_multi_read(host, mrq); | |
480 | break; | |
481 | case MMC_WRITE_MULTIPLE_BLOCK: | |
482 | ret = sh_mmcif_multi_write(host, mrq); | |
483 | break; | |
484 | case MMC_WRITE_BLOCK: | |
485 | ret = sh_mmcif_single_write(host, mrq); | |
486 | break; | |
487 | case MMC_READ_SINGLE_BLOCK: | |
488 | case MMC_SEND_EXT_CSD: | |
489 | ret = sh_mmcif_single_read(host, mrq); | |
490 | break; | |
491 | default: | |
e47bf32a | 492 | dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc); |
fdc50a94 YG |
493 | ret = -EINVAL; |
494 | break; | |
495 | } | |
496 | return ret; | |
497 | } | |
498 | ||
499 | static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, | |
500 | struct mmc_request *mrq, struct mmc_command *cmd) | |
501 | { | |
502 | long time; | |
503 | int ret = 0, mask = 0; | |
504 | u32 opc = cmd->opcode; | |
505 | ||
fdc50a94 YG |
506 | switch (opc) { |
507 | /* respons busy check */ | |
508 | case MMC_SWITCH: | |
509 | case MMC_STOP_TRANSMISSION: | |
510 | case MMC_SET_WRITE_PROT: | |
511 | case MMC_CLR_WRITE_PROT: | |
512 | case MMC_ERASE: | |
513 | case MMC_GEN_CMD: | |
514 | mask = MASK_MRBSYE; | |
515 | break; | |
516 | default: | |
517 | mask = MASK_MCRSPE; | |
518 | break; | |
519 | } | |
520 | mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | | |
521 | MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | | |
522 | MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | | |
523 | MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO; | |
524 | ||
525 | if (host->data) { | |
487d9fc5 MD |
526 | sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); |
527 | sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, | |
528 | mrq->data->blksz); | |
fdc50a94 YG |
529 | } |
530 | opc = sh_mmcif_set_cmd(host, mrq, cmd, opc); | |
531 | ||
487d9fc5 MD |
532 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); |
533 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); | |
fdc50a94 | 534 | /* set arg */ |
487d9fc5 | 535 | sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); |
fdc50a94 | 536 | /* set cmd */ |
487d9fc5 | 537 | sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); |
fdc50a94 | 538 | |
aa0787a9 GL |
539 | time = wait_for_completion_interruptible_timeout(&host->intr_wait, |
540 | host->timeout); | |
541 | if (time <= 0) { | |
fdc50a94 YG |
542 | cmd->error = sh_mmcif_error_manage(host); |
543 | return; | |
544 | } | |
545 | if (host->sd_error) { | |
546 | switch (cmd->opcode) { | |
547 | case MMC_ALL_SEND_CID: | |
548 | case MMC_SELECT_CARD: | |
549 | case MMC_APP_CMD: | |
550 | cmd->error = -ETIMEDOUT; | |
551 | break; | |
552 | default: | |
e47bf32a GL |
553 | dev_dbg(&host->pd->dev, "Cmd(d'%d) err\n", |
554 | cmd->opcode); | |
fdc50a94 YG |
555 | cmd->error = sh_mmcif_error_manage(host); |
556 | break; | |
557 | } | |
aa0787a9 | 558 | host->sd_error = false; |
fdc50a94 YG |
559 | return; |
560 | } | |
561 | if (!(cmd->flags & MMC_RSP_PRESENT)) { | |
e47bf32a | 562 | cmd->error = 0; |
fdc50a94 YG |
563 | return; |
564 | } | |
aa0787a9 | 565 | sh_mmcif_get_response(host, cmd); |
fdc50a94 YG |
566 | if (host->data) { |
567 | ret = sh_mmcif_data_trans(host, mrq, cmd->opcode); | |
568 | if (ret < 0) | |
569 | mrq->data->bytes_xfered = 0; | |
570 | else | |
571 | mrq->data->bytes_xfered = | |
572 | mrq->data->blocks * mrq->data->blksz; | |
573 | } | |
574 | cmd->error = ret; | |
575 | } | |
576 | ||
577 | static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, | |
578 | struct mmc_request *mrq, struct mmc_command *cmd) | |
579 | { | |
580 | long time; | |
581 | ||
582 | if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK) | |
583 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); | |
584 | else if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) | |
585 | sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); | |
586 | else { | |
e47bf32a | 587 | dev_err(&host->pd->dev, "unsupported stop cmd\n"); |
fdc50a94 YG |
588 | cmd->error = sh_mmcif_error_manage(host); |
589 | return; | |
590 | } | |
591 | ||
aa0787a9 GL |
592 | time = wait_for_completion_interruptible_timeout(&host->intr_wait, |
593 | host->timeout); | |
594 | if (time <= 0 || host->sd_error) { | |
fdc50a94 YG |
595 | cmd->error = sh_mmcif_error_manage(host); |
596 | return; | |
597 | } | |
598 | sh_mmcif_get_cmd12response(host, cmd); | |
fdc50a94 YG |
599 | cmd->error = 0; |
600 | } | |
601 | ||
602 | static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
603 | { | |
604 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
605 | ||
606 | switch (mrq->cmd->opcode) { | |
607 | /* MMCIF does not support SD/SDIO command */ | |
608 | case SD_IO_SEND_OP_COND: | |
609 | case MMC_APP_CMD: | |
610 | mrq->cmd->error = -ETIMEDOUT; | |
611 | mmc_request_done(mmc, mrq); | |
612 | return; | |
613 | case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ | |
614 | if (!mrq->data) { | |
615 | /* send_if_cond cmd (not support) */ | |
616 | mrq->cmd->error = -ETIMEDOUT; | |
617 | mmc_request_done(mmc, mrq); | |
618 | return; | |
619 | } | |
620 | break; | |
621 | default: | |
622 | break; | |
623 | } | |
624 | host->data = mrq->data; | |
625 | sh_mmcif_start_cmd(host, mrq, mrq->cmd); | |
626 | host->data = NULL; | |
627 | ||
628 | if (mrq->cmd->error != 0) { | |
629 | mmc_request_done(mmc, mrq); | |
630 | return; | |
631 | } | |
632 | if (mrq->stop) | |
633 | sh_mmcif_stop_cmd(host, mrq, mrq->stop); | |
634 | mmc_request_done(mmc, mrq); | |
635 | } | |
636 | ||
637 | static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
638 | { | |
639 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
640 | struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; | |
641 | ||
642 | if (ios->power_mode == MMC_POWER_OFF) { | |
643 | /* clock stop */ | |
644 | sh_mmcif_clock_control(host, 0); | |
645 | if (p->down_pwr) | |
646 | p->down_pwr(host->pd); | |
647 | return; | |
648 | } else if (ios->power_mode == MMC_POWER_UP) { | |
649 | if (p->set_pwr) | |
650 | p->set_pwr(host->pd, ios->power_mode); | |
651 | } | |
652 | ||
653 | if (ios->clock) | |
654 | sh_mmcif_clock_control(host, ios->clock); | |
655 | ||
656 | host->bus_width = ios->bus_width; | |
657 | } | |
658 | ||
777271d0 AH |
659 | static int sh_mmcif_get_cd(struct mmc_host *mmc) |
660 | { | |
661 | struct sh_mmcif_host *host = mmc_priv(mmc); | |
662 | struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; | |
663 | ||
664 | if (!p->get_cd) | |
665 | return -ENOSYS; | |
666 | else | |
667 | return p->get_cd(host->pd); | |
668 | } | |
669 | ||
fdc50a94 YG |
670 | static struct mmc_host_ops sh_mmcif_ops = { |
671 | .request = sh_mmcif_request, | |
672 | .set_ios = sh_mmcif_set_ios, | |
777271d0 | 673 | .get_cd = sh_mmcif_get_cd, |
fdc50a94 YG |
674 | }; |
675 | ||
676 | static void sh_mmcif_detect(struct mmc_host *mmc) | |
677 | { | |
678 | mmc_detect_change(mmc, 0); | |
679 | } | |
680 | ||
681 | static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) | |
682 | { | |
683 | struct sh_mmcif_host *host = dev_id; | |
aa0787a9 | 684 | u32 state; |
fdc50a94 YG |
685 | int err = 0; |
686 | ||
487d9fc5 | 687 | state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); |
fdc50a94 YG |
688 | |
689 | if (state & INT_RBSYE) { | |
487d9fc5 MD |
690 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, |
691 | ~(INT_RBSYE | INT_CRSPE)); | |
fdc50a94 YG |
692 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE); |
693 | } else if (state & INT_CRSPE) { | |
487d9fc5 | 694 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE); |
fdc50a94 YG |
695 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE); |
696 | } else if (state & INT_BUFREN) { | |
487d9fc5 | 697 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN); |
fdc50a94 YG |
698 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); |
699 | } else if (state & INT_BUFWEN) { | |
487d9fc5 | 700 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN); |
fdc50a94 YG |
701 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); |
702 | } else if (state & INT_CMD12DRE) { | |
487d9fc5 | 703 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, |
fdc50a94 YG |
704 | ~(INT_CMD12DRE | INT_CMD12RBE | |
705 | INT_CMD12CRE | INT_BUFRE)); | |
706 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); | |
707 | } else if (state & INT_BUFRE) { | |
487d9fc5 | 708 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE); |
fdc50a94 YG |
709 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); |
710 | } else if (state & INT_DTRANE) { | |
487d9fc5 | 711 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE); |
fdc50a94 YG |
712 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); |
713 | } else if (state & INT_CMD12RBE) { | |
487d9fc5 | 714 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, |
fdc50a94 YG |
715 | ~(INT_CMD12RBE | INT_CMD12CRE)); |
716 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); | |
717 | } else if (state & INT_ERR_STS) { | |
718 | /* err interrupts */ | |
487d9fc5 | 719 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); |
fdc50a94 YG |
720 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); |
721 | err = 1; | |
722 | } else { | |
e47bf32a | 723 | dev_dbg(&host->pd->dev, "Not support int\n"); |
487d9fc5 | 724 | sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); |
fdc50a94 YG |
725 | sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); |
726 | err = 1; | |
727 | } | |
728 | if (err) { | |
aa0787a9 | 729 | host->sd_error = true; |
e47bf32a | 730 | dev_dbg(&host->pd->dev, "int err state = %08x\n", state); |
fdc50a94 | 731 | } |
aa0787a9 GL |
732 | if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) |
733 | complete(&host->intr_wait); | |
734 | else | |
735 | dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); | |
fdc50a94 YG |
736 | |
737 | return IRQ_HANDLED; | |
738 | } | |
739 | ||
740 | static int __devinit sh_mmcif_probe(struct platform_device *pdev) | |
741 | { | |
742 | int ret = 0, irq[2]; | |
743 | struct mmc_host *mmc; | |
e47bf32a GL |
744 | struct sh_mmcif_host *host; |
745 | struct sh_mmcif_plat_data *pd; | |
fdc50a94 YG |
746 | struct resource *res; |
747 | void __iomem *reg; | |
748 | char clk_name[8]; | |
749 | ||
750 | irq[0] = platform_get_irq(pdev, 0); | |
751 | irq[1] = platform_get_irq(pdev, 1); | |
752 | if (irq[0] < 0 || irq[1] < 0) { | |
e47bf32a | 753 | dev_err(&pdev->dev, "Get irq error\n"); |
fdc50a94 YG |
754 | return -ENXIO; |
755 | } | |
756 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
757 | if (!res) { | |
758 | dev_err(&pdev->dev, "platform_get_resource error.\n"); | |
759 | return -ENXIO; | |
760 | } | |
761 | reg = ioremap(res->start, resource_size(res)); | |
762 | if (!reg) { | |
763 | dev_err(&pdev->dev, "ioremap error.\n"); | |
764 | return -ENOMEM; | |
765 | } | |
e47bf32a | 766 | pd = pdev->dev.platform_data; |
fdc50a94 YG |
767 | if (!pd) { |
768 | dev_err(&pdev->dev, "sh_mmcif plat data error.\n"); | |
769 | ret = -ENXIO; | |
770 | goto clean_up; | |
771 | } | |
772 | mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); | |
773 | if (!mmc) { | |
774 | ret = -ENOMEM; | |
775 | goto clean_up; | |
776 | } | |
777 | host = mmc_priv(mmc); | |
778 | host->mmc = mmc; | |
779 | host->addr = reg; | |
780 | host->timeout = 1000; | |
781 | ||
782 | snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id); | |
783 | host->hclk = clk_get(&pdev->dev, clk_name); | |
784 | if (IS_ERR(host->hclk)) { | |
785 | dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name); | |
786 | ret = PTR_ERR(host->hclk); | |
787 | goto clean_up1; | |
788 | } | |
789 | clk_enable(host->hclk); | |
790 | host->clk = clk_get_rate(host->hclk); | |
791 | host->pd = pdev; | |
792 | ||
aa0787a9 | 793 | init_completion(&host->intr_wait); |
fdc50a94 YG |
794 | |
795 | mmc->ops = &sh_mmcif_ops; | |
796 | mmc->f_max = host->clk; | |
797 | /* close to 400KHz */ | |
798 | if (mmc->f_max < 51200000) | |
799 | mmc->f_min = mmc->f_max / 128; | |
800 | else if (mmc->f_max < 102400000) | |
801 | mmc->f_min = mmc->f_max / 256; | |
802 | else | |
803 | mmc->f_min = mmc->f_max / 512; | |
804 | if (pd->ocr) | |
805 | mmc->ocr_avail = pd->ocr; | |
806 | mmc->caps = MMC_CAP_MMC_HIGHSPEED; | |
807 | if (pd->caps) | |
808 | mmc->caps |= pd->caps; | |
a36274e0 | 809 | mmc->max_segs = 128; |
fdc50a94 YG |
810 | mmc->max_blk_size = 512; |
811 | mmc->max_blk_count = 65535; | |
812 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
813 | mmc->max_seg_size = mmc->max_req_size; | |
814 | ||
815 | sh_mmcif_sync_reset(host); | |
816 | platform_set_drvdata(pdev, host); | |
817 | mmc_add_host(mmc); | |
818 | ||
819 | ret = request_irq(irq[0], sh_mmcif_intr, 0, "sh_mmc:error", host); | |
820 | if (ret) { | |
e47bf32a | 821 | dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n"); |
fdc50a94 YG |
822 | goto clean_up2; |
823 | } | |
824 | ret = request_irq(irq[1], sh_mmcif_intr, 0, "sh_mmc:int", host); | |
825 | if (ret) { | |
826 | free_irq(irq[0], host); | |
e47bf32a | 827 | dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n"); |
fdc50a94 YG |
828 | goto clean_up2; |
829 | } | |
830 | ||
487d9fc5 | 831 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
fdc50a94 YG |
832 | sh_mmcif_detect(host->mmc); |
833 | ||
e47bf32a GL |
834 | dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION); |
835 | dev_dbg(&pdev->dev, "chip ver H'%04x\n", | |
487d9fc5 | 836 | sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff); |
fdc50a94 YG |
837 | return ret; |
838 | ||
839 | clean_up2: | |
840 | clk_disable(host->hclk); | |
841 | clean_up1: | |
842 | mmc_free_host(mmc); | |
843 | clean_up: | |
844 | if (reg) | |
845 | iounmap(reg); | |
846 | return ret; | |
847 | } | |
848 | ||
849 | static int __devexit sh_mmcif_remove(struct platform_device *pdev) | |
850 | { | |
851 | struct sh_mmcif_host *host = platform_get_drvdata(pdev); | |
852 | int irq[2]; | |
853 | ||
aa0787a9 | 854 | mmc_remove_host(host->mmc); |
fdc50a94 YG |
855 | |
856 | if (host->addr) | |
857 | iounmap(host->addr); | |
858 | ||
aa0787a9 GL |
859 | sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); |
860 | ||
861 | irq[0] = platform_get_irq(pdev, 0); | |
862 | irq[1] = platform_get_irq(pdev, 1); | |
fdc50a94 YG |
863 | |
864 | free_irq(irq[0], host); | |
865 | free_irq(irq[1], host); | |
866 | ||
aa0787a9 GL |
867 | platform_set_drvdata(pdev, NULL); |
868 | ||
fdc50a94 YG |
869 | clk_disable(host->hclk); |
870 | mmc_free_host(host->mmc); | |
871 | ||
872 | return 0; | |
873 | } | |
874 | ||
875 | static struct platform_driver sh_mmcif_driver = { | |
876 | .probe = sh_mmcif_probe, | |
877 | .remove = sh_mmcif_remove, | |
878 | .driver = { | |
879 | .name = DRIVER_NAME, | |
880 | }, | |
881 | }; | |
882 | ||
883 | static int __init sh_mmcif_init(void) | |
884 | { | |
885 | return platform_driver_register(&sh_mmcif_driver); | |
886 | } | |
887 | ||
888 | static void __exit sh_mmcif_exit(void) | |
889 | { | |
890 | platform_driver_unregister(&sh_mmcif_driver); | |
891 | } | |
892 | ||
893 | module_init(sh_mmcif_init); | |
894 | module_exit(sh_mmcif_exit); | |
895 | ||
896 | ||
897 | MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); | |
898 | MODULE_LICENSE("GPL"); | |
aa0787a9 | 899 | MODULE_ALIAS("platform:" DRIVER_NAME); |
fdc50a94 | 900 | MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); |