[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / tmio_mmc.h

/*
 * Driver for the MMC / SD / SDIO cell found in:
 *
 * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
 *
 * Copyright (C) 2015-17 Renesas Electronics Corporation
 * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
 * Copyright (C) 2007 Ian Molton
 * Copyright (C) 2004 Ian Molton
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#ifndef TMIO_MMC_H
#define TMIO_MMC_H

#include <linux/dmaengine.h>
#include <linux/highmem.h>
#include <linux/mutex.h>
#include <linux/pagemap.h>
#include <linux/scatterlist.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>

#define CTL_SD_CMD 0x00
#define CTL_ARG_REG 0x04
#define CTL_STOP_INTERNAL_ACTION 0x08
#define CTL_XFER_BLK_COUNT 0xa
#define CTL_RESPONSE 0x0c
/* driver merges STATUS and following STATUS2 */
#define CTL_STATUS 0x1c
/* driver merges IRQ_MASK and following IRQ_MASK2 */
#define CTL_IRQ_MASK 0x20
#define CTL_SD_CARD_CLK_CTL 0x24
#define CTL_SD_XFER_LEN 0x26
#define CTL_SD_MEM_CARD_OPT 0x28
#define CTL_SD_ERROR_DETAIL_STATUS 0x2c
#define CTL_SD_DATA_PORT 0x30
#define CTL_TRANSACTION_CTL 0x34
#define CTL_SDIO_STATUS 0x36
#define CTL_SDIO_IRQ_MASK 0x38
#define CTL_DMA_ENABLE 0xd8
#define CTL_RESET_SD 0xe0
#define CTL_VERSION 0xe2
#define CTL_SDIO_REGS 0x100
#define CTL_CLK_AND_WAIT_CTL 0x138
#define CTL_RESET_SDIO 0x1e0

/* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */
#define TMIO_STOP_STP		BIT(0)
#define TMIO_STOP_SEC		BIT(8)

/* Definitions for values the CTL_STATUS register can take */
#define TMIO_STAT_CMDRESPEND    BIT(0)
#define TMIO_STAT_DATAEND       BIT(2)
#define TMIO_STAT_CARD_REMOVE   BIT(3)
#define TMIO_STAT_CARD_INSERT   BIT(4)
#define TMIO_STAT_SIGSTATE      BIT(5)
#define TMIO_STAT_WRPROTECT     BIT(7)
#define TMIO_STAT_CARD_REMOVE_A BIT(8)
#define TMIO_STAT_CARD_INSERT_A BIT(9)
#define TMIO_STAT_SIGSTATE_A    BIT(10)

/* These belong technically to CTL_STATUS2, but the driver merges them */
#define TMIO_STAT_CMD_IDX_ERR   BIT(16)
#define TMIO_STAT_CRCFAIL       BIT(17)
#define TMIO_STAT_STOPBIT_ERR   BIT(18)
#define TMIO_STAT_DATATIMEOUT   BIT(19)
#define TMIO_STAT_RXOVERFLOW    BIT(20)
#define TMIO_STAT_TXUNDERRUN    BIT(21)
#define TMIO_STAT_CMDTIMEOUT    BIT(22)
#define TMIO_STAT_DAT0		BIT(23)	/* only known on R-Car so far */
#define TMIO_STAT_RXRDY         BIT(24)
#define TMIO_STAT_TXRQ          BIT(25)
#define TMIO_STAT_ILL_FUNC      BIT(29) /* only when !TMIO_MMC_HAS_IDLE_WAIT */
#define TMIO_STAT_SCLKDIVEN     BIT(29) /* only when TMIO_MMC_HAS_IDLE_WAIT */
#define TMIO_STAT_CMD_BUSY      BIT(30)
#define TMIO_STAT_ILL_ACCESS    BIT(31)

/* Definitions for values the CTL_SD_CARD_CLK_CTL register can take */
#define	CLK_CTL_DIV_MASK	0xff
#define	CLK_CTL_SCLKEN		BIT(8)

/* Definitions for values the CTL_SD_MEM_CARD_OPT register can take */
#define CARD_OPT_WIDTH8		BIT(13)
#define CARD_OPT_WIDTH		BIT(15)

/* Definitions for values the CTL_SDIO_STATUS register can take */
#define TMIO_SDIO_STAT_IOIRQ	0x0001
#define TMIO_SDIO_STAT_EXPUB52	0x4000
#define TMIO_SDIO_STAT_EXWT	0x8000
#define TMIO_SDIO_MASK_ALL	0xc007

#define TMIO_SDIO_SETBITS_MASK	0x0006

/* Definitions for values the CTL_DMA_ENABLE register can take */
#define DMA_ENABLE_DMASDRW	BIT(1)

/* Define some IRQ masks */
/* This is the mask used at reset by the chip */
#define TMIO_MASK_ALL           0x837f031d
#define TMIO_MASK_READOP  (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND)
#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND)
#define TMIO_MASK_CMD     (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \
		TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
#define TMIO_MASK_IRQ     (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)

struct tmio_mmc_data;
struct tmio_mmc_host;

struct tmio_mmc_dma {
	enum dma_slave_buswidth dma_buswidth;
	bool (*filter)(struct dma_chan *chan, void *arg);
	void (*enable)(struct tmio_mmc_host *host, bool enable);
};

struct tmio_mmc_dma_ops {
	void (*start)(struct tmio_mmc_host *host, struct mmc_data *data);
	void (*enable)(struct tmio_mmc_host *host, bool enable);
	void (*request)(struct tmio_mmc_host *host,
			struct tmio_mmc_data *pdata);
	void (*release)(struct tmio_mmc_host *host);
	void (*abort)(struct tmio_mmc_host *host);
	void (*dataend)(struct tmio_mmc_host *host);
};

struct tmio_mmc_host {
	void __iomem *ctl;
	struct mmc_command      *cmd;
	struct mmc_request      *mrq;
	struct mmc_data         *data;
	struct mmc_host         *mmc;

	/* Callbacks for clock / power control */
	void (*set_pwr)(struct platform_device *host, int state);
	void (*set_clk_div)(struct platform_device *host, int state);

	/* pio related stuff */
	struct scatterlist      *sg_ptr;
	struct scatterlist      *sg_orig;
	unsigned int            sg_len;
	unsigned int            sg_off;
	unsigned long		bus_shift;

	struct platform_device *pdev;
	struct tmio_mmc_data *pdata;
	struct tmio_mmc_dma	*dma;

	/* DMA support */
	bool			force_pio;
	struct dma_chan		*chan_rx;
	struct dma_chan		*chan_tx;
	struct completion	dma_dataend;
	struct tasklet_struct	dma_complete;
	struct tasklet_struct	dma_issue;
	struct scatterlist	bounce_sg;
	u8			*bounce_buf;

	/* Track lost interrupts */
	struct delayed_work	delayed_reset_work;
	struct work_struct	done;

	/* Cache */
	u32			sdcard_irq_mask;
	u32			sdio_irq_mask;
	unsigned int		clk_cache;

	spinlock_t		lock;		/* protect host private data */
	unsigned long		last_req_ts;
	struct mutex		ios_lock;	/* protect set_ios() context */
	bool			native_hotplug;
	bool			sdio_irq_enabled;
	u32			scc_tappos;

	/* Mandatory callback */
	int (*clk_enable)(struct tmio_mmc_host *host);

	/* Optional callbacks */
	unsigned int (*clk_update)(struct tmio_mmc_host *host,
				   unsigned int new_clock);
	void (*clk_disable)(struct tmio_mmc_host *host);
	int (*multi_io_quirk)(struct mmc_card *card,
			      unsigned int direction, int blk_size);
	int (*card_busy)(struct mmc_host *mmc);
	int (*start_signal_voltage_switch)(struct mmc_host *mmc,
					   struct mmc_ios *ios);
	int (*write16_hook)(struct tmio_mmc_host *host, int addr);
	void (*hw_reset)(struct tmio_mmc_host *host);
	void (*prepare_tuning)(struct tmio_mmc_host *host, unsigned long tap);
	bool (*check_scc_error)(struct tmio_mmc_host *host);

	/*
	 * Mandatory callback for tuning to occur which is optional for SDR50
	 * and mandatory for SDR104.
	 */
	unsigned int (*init_tuning)(struct tmio_mmc_host *host);
	int (*select_tuning)(struct tmio_mmc_host *host);

	/* Tuning values: 1 for success, 0 for failure */
	DECLARE_BITMAP(taps, BITS_PER_BYTE * sizeof(long));
	unsigned int tap_num;

	const struct tmio_mmc_dma_ops *dma_ops;
};

struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev);
void tmio_mmc_host_free(struct tmio_mmc_host *host);
int tmio_mmc_host_probe(struct tmio_mmc_host *host,
			struct tmio_mmc_data *pdata,
			const struct tmio_mmc_dma_ops *dma_ops);
void tmio_mmc_host_remove(struct tmio_mmc_host *host);
void tmio_mmc_do_data_irq(struct tmio_mmc_host *host);

void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
irqreturn_t tmio_mmc_irq(int irq, void *devid);

static inline char *tmio_mmc_kmap_atomic(struct scatterlist *sg,
					 unsigned long *flags)
{
	local_irq_save(*flags);
	return kmap_atomic(sg_page(sg)) + sg->offset;
}

static inline void tmio_mmc_kunmap_atomic(struct scatterlist *sg,
					  unsigned long *flags, void *virt)
{
	kunmap_atomic(virt - sg->offset);
	local_irq_restore(*flags);
}

#ifdef CONFIG_PM
int tmio_mmc_host_runtime_suspend(struct device *dev);
int tmio_mmc_host_runtime_resume(struct device *dev);
#endif

static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
{
	return readw(host->ctl + (addr << host->bus_shift));
}

static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
				      u16 *buf, int count)
{
	readsw(host->ctl + (addr << host->bus_shift), buf, count);
}

static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host,
					      int addr)
{
	return readw(host->ctl + (addr << host->bus_shift)) |
	       readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
}

static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
				      u32 *buf, int count)
{
	readsl(host->ctl + (addr << host->bus_shift), buf, count);
}

static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
				   u16 val)
{
	/* If there is a hook and it returns non-zero then there
	 * is an error and the write should be skipped
	 */
	if (host->write16_hook && host->write16_hook(host, addr))
		return;
	writew(val, host->ctl + (addr << host->bus_shift));
}

static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
				       u16 *buf, int count)
{
	writesw(host->ctl + (addr << host->bus_shift), buf, count);
}

static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host,
						int addr, u32 val)
{
	writew(val & 0xffff, host->ctl + (addr << host->bus_shift));
	writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
}

static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr,
				       const u32 *buf, int count)
{
	writesl(host->ctl + (addr << host->bus_shift), buf, count);
}

#endif
Commit	Line	Data
b6147490	1	/*
b21f13d8 SH	2	* Driver for the MMC / SD / SDIO cell found in:
	3	*
	4	* TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
b6147490	5	*
87317c4d SH	6	* Copyright (C) 2015-17 Renesas Electronics Corporation
	7	* Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
	8	* Copyright (C) 2016-17 Horms Solutions, Simon Horman
b6147490 GL	9	* Copyright (C) 2007 Ian Molton
	10	* Copyright (C) 2004 Ian Molton
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*
b6147490 GL	16	*/
	17
	18	#ifndef TMIO_MMC_H
	19	#define TMIO_MMC_H
	20
361936ef	21	#include <linux/dmaengine.h>
b6147490	22	#include <linux/highmem.h>
b9269fdd	23	#include <linux/mutex.h>
b6147490	24	#include <linux/pagemap.h>
6c0cbef6	25	#include <linux/scatterlist.h>
e3de2be7	26	#include <linux/spinlock.h>
b8789ec4	27	#include <linux/interrupt.h>
b6147490	28
ac86045e WS	29	#define CTL_SD_CMD 0x00
	30	#define CTL_ARG_REG 0x04
	31	#define CTL_STOP_INTERNAL_ACTION 0x08
	32	#define CTL_XFER_BLK_COUNT 0xa
	33	#define CTL_RESPONSE 0x0c
184adf20	34	/* driver merges STATUS and following STATUS2 */
ac86045e	35	#define CTL_STATUS 0x1c
184adf20	36	/* driver merges IRQ_MASK and following IRQ_MASK2 */
ac86045e WS	37	#define CTL_IRQ_MASK 0x20
	38	#define CTL_SD_CARD_CLK_CTL 0x24
	39	#define CTL_SD_XFER_LEN 0x26
	40	#define CTL_SD_MEM_CARD_OPT 0x28
	41	#define CTL_SD_ERROR_DETAIL_STATUS 0x2c
	42	#define CTL_SD_DATA_PORT 0x30
	43	#define CTL_TRANSACTION_CTL 0x34
	44	#define CTL_SDIO_STATUS 0x36
	45	#define CTL_SDIO_IRQ_MASK 0x38
	46	#define CTL_DMA_ENABLE 0xd8
	47	#define CTL_RESET_SD 0xe0
	48	#define CTL_VERSION 0xe2
	49	#define CTL_SDIO_REGS 0x100
	50	#define CTL_CLK_AND_WAIT_CTL 0x138
	51	#define CTL_RESET_SDIO 0x1e0
	52
9afcbf4a WS	53	/* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */
	54	#define TMIO_STOP_STP BIT(0)
	55	#define TMIO_STOP_SEC BIT(8)
	56
d8acd16c	57	/* Definitions for values the CTL_STATUS register can take */
2cafc5cb WS	58	#define TMIO_STAT_CMDRESPEND BIT(0)
	59	#define TMIO_STAT_DATAEND BIT(2)
	60	#define TMIO_STAT_CARD_REMOVE BIT(3)
	61	#define TMIO_STAT_CARD_INSERT BIT(4)
	62	#define TMIO_STAT_SIGSTATE BIT(5)
	63	#define TMIO_STAT_WRPROTECT BIT(7)
	64	#define TMIO_STAT_CARD_REMOVE_A BIT(8)
	65	#define TMIO_STAT_CARD_INSERT_A BIT(9)
	66	#define TMIO_STAT_SIGSTATE_A BIT(10)
	67
d8acd16c	68	/* These belong technically to CTL_STATUS2, but the driver merges them */
2cafc5cb WS	69	#define TMIO_STAT_CMD_IDX_ERR BIT(16)
	70	#define TMIO_STAT_CRCFAIL BIT(17)
	71	#define TMIO_STAT_STOPBIT_ERR BIT(18)
	72	#define TMIO_STAT_DATATIMEOUT BIT(19)
	73	#define TMIO_STAT_RXOVERFLOW BIT(20)
	74	#define TMIO_STAT_TXUNDERRUN BIT(21)
	75	#define TMIO_STAT_CMDTIMEOUT BIT(22)
83e95351	76	#define TMIO_STAT_DAT0 BIT(23) /* only known on R-Car so far */
2cafc5cb WS	77	#define TMIO_STAT_RXRDY BIT(24)
2cafc5cb WS	78	#define TMIO_STAT_TXRQ BIT(25)
a21553c9 WS	79	#define TMIO_STAT_ILL_FUNC BIT(29) /* only when !TMIO_MMC_HAS_IDLE_WAIT */
a21553c9 WS	80	#define TMIO_STAT_SCLKDIVEN BIT(29) /* only when TMIO_MMC_HAS_IDLE_WAIT */
2cafc5cb WS	81	#define TMIO_STAT_CMD_BUSY BIT(30)
2cafc5cb WS	82	#define TMIO_STAT_ILL_ACCESS BIT(31)
ac86045e	83
c78e1694	84	/* Definitions for values the CTL_SD_CARD_CLK_CTL register can take */
ac86045e WS	85	#define CLK_CTL_DIV_MASK 0xff
	86	#define CLK_CTL_SCLKEN BIT(8)
	87
c78e1694	88	/* Definitions for values the CTL_SD_MEM_CARD_OPT register can take */
0bc0b6e8 WS	89	#define CARD_OPT_WIDTH8 BIT(13)
	90	#define CARD_OPT_WIDTH BIT(15)
	91
d8acd16c	92	/* Definitions for values the CTL_SDIO_STATUS register can take */
cba179ae	93	#define TMIO_SDIO_STAT_IOIRQ 0x0001
b6147490	94	#define TMIO_SDIO_STAT_EXPUB52 0x4000
cba179ae SH	95	#define TMIO_SDIO_STAT_EXWT 0x8000
cba179ae SH	96	#define TMIO_SDIO_MASK_ALL 0xc007
b6147490	97
ee289815 WS	98	#define TMIO_SDIO_SETBITS_MASK 0x0006
ee289815 WS	99
5af02d32 WS	100	/* Definitions for values the CTL_DMA_ENABLE register can take */
	101	#define DMA_ENABLE_DMASDRW BIT(1)
	102
b6147490 GL	103	/* Define some IRQ masks */
	104	/* This is the mask used at reset by the chip */
	105	#define TMIO_MASK_ALL 0x837f031d
	106	#define TMIO_MASK_READOP (TMIO_STAT_RXRDY \| TMIO_STAT_DATAEND)
	107	#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ \| TMIO_STAT_DATAEND)
	108	#define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND \| TMIO_STAT_CMDTIMEOUT \| \
	109	TMIO_STAT_CARD_REMOVE \| TMIO_STAT_CARD_INSERT)
	110	#define TMIO_MASK_IRQ (TMIO_MASK_READOP \| TMIO_MASK_WRITEOP \| TMIO_MASK_CMD)
	111
	112	struct tmio_mmc_data;
5add2aca	113	struct tmio_mmc_host;
b6147490	114
7ecc09ba	115	struct tmio_mmc_dma {
361936ef	116	enum dma_slave_buswidth dma_buswidth;
7ecc09ba	117	bool (filter)(struct dma_chan chan, void *arg);
5add2aca	118	void (enable)(struct tmio_mmc_host host, bool enable);
7ecc09ba KM	119	};
7ecc09ba KM	120
631fa73c SH	121	struct tmio_mmc_dma_ops {
	122	void (start)(struct tmio_mmc_host host, struct mmc_data *data);
	123	void (enable)(struct tmio_mmc_host host, bool enable);
	124	void (request)(struct tmio_mmc_host host,
	125	struct tmio_mmc_data *pdata);
	126	void (release)(struct tmio_mmc_host host);
	127	void (abort)(struct tmio_mmc_host host);
92d0f925	128	void (dataend)(struct tmio_mmc_host host);
631fa73c SH	129	};
631fa73c SH	130
b6147490 GL	131	struct tmio_mmc_host {
b6147490 GL	132	void __iomem *ctl;
b6147490 GL	133	struct mmc_command *cmd;
	134	struct mmc_request *mrq;
	135	struct mmc_data *data;
	136	struct mmc_host *mmc;
b6147490 GL	137
	138	/* Callbacks for clock / power control */
	139	void (set_pwr)(struct platform_device host, int state);
	140	void (set_clk_div)(struct platform_device host, int state);
	141
	142	/* pio related stuff */
	143	struct scatterlist *sg_ptr;
	144	struct scatterlist *sg_orig;
	145	unsigned int sg_len;
	146	unsigned int sg_off;
7445bf9e	147	unsigned long bus_shift;
b6147490 GL	148
	149	struct platform_device *pdev;
	150	struct tmio_mmc_data *pdata;
7ecc09ba	151	struct tmio_mmc_dma *dma;
b6147490 GL	152
	153	/* DMA support */
	154	bool force_pio;
	155	struct dma_chan *chan_rx;
	156	struct dma_chan *chan_tx;
52ad9a8e	157	struct completion dma_dataend;
2a68ea78	158	struct tasklet_struct dma_complete;
b6147490 GL	159	struct tasklet_struct dma_issue;
	160	struct scatterlist bounce_sg;
	161	u8 *bounce_buf;
	162
	163	/* Track lost interrupts */
	164	struct delayed_work delayed_reset_work;
b9269fdd GL	165	struct work_struct done;
b9269fdd GL	166
ae12d250	167	/* Cache */
54680fe7 SH	168	u32 sdcard_irq_mask;
54680fe7 SH	169	u32 sdio_irq_mask;
ae12d250	170	unsigned int clk_cache;
54680fe7	171
b9269fdd	172	spinlock_t lock; /* protect host private data */
b6147490	173	unsigned long last_req_ts;
b9269fdd	174	struct mutex ios_lock; /* protect set_ios() context */
2b1ac5c2	175	bool native_hotplug;
7501c431	176	bool sdio_irq_enabled;
4f119977	177	u32 scc_tappos;
dfe9a229	178
2f87365f	179	/* Mandatory callback */
0ea28210	180	int (clk_enable)(struct tmio_mmc_host host);
2f87365f SH	181
2f87365f SH	182	/* Optional callbacks */
2fb55956 BH	183	unsigned int (clk_update)(struct tmio_mmc_host host,
2fb55956 BH	184	unsigned int new_clock);
0ea28210	185	void (clk_disable)(struct tmio_mmc_host host);
85c02ddd KM	186	int (multi_io_quirk)(struct mmc_card card,
85c02ddd KM	187	unsigned int direction, int blk_size);
6a4679f3	188	int (card_busy)(struct mmc_host mmc);
452e5eef WS	189	int (start_signal_voltage_switch)(struct mmc_host mmc,
452e5eef WS	190	struct mmc_ios *ios);
2f87365f	191	int (write16_hook)(struct tmio_mmc_host host, int addr);
e8f36b5d	192	void (hw_reset)(struct tmio_mmc_host host);
4f119977 AK	193	void (prepare_tuning)(struct tmio_mmc_host host, unsigned long tap);
	194	bool (check_scc_error)(struct tmio_mmc_host host);
	195
	196	/*
	197	* Mandatory callback for tuning to occur which is optional for SDR50
	198	* and mandatory for SDR104.
	199	*/
	200	unsigned int (init_tuning)(struct tmio_mmc_host host);
	201	int (select_tuning)(struct tmio_mmc_host host);
	202
	203	/* Tuning values: 1 for success, 0 for failure */
	204	DECLARE_BITMAP(taps, BITS_PER_BYTE * sizeof(long));
	205	unsigned int tap_num;
631fa73c SH	206
631fa73c SH	207	const struct tmio_mmc_dma_ops *dma_ops;
b6147490 GL	208	};
b6147490 GL	209
94b110af KM	210	struct tmio_mmc_host tmio_mmc_host_alloc(struct platform_device pdev);
	211	void tmio_mmc_host_free(struct tmio_mmc_host *host);
	212	int tmio_mmc_host_probe(struct tmio_mmc_host *host,
631fa73c SH	213	struct tmio_mmc_data *pdata,
631fa73c SH	214	const struct tmio_mmc_dma_ops *dma_ops);
b6147490 GL	215	void tmio_mmc_host_remove(struct tmio_mmc_host *host);
	216	void tmio_mmc_do_data_irq(struct tmio_mmc_host *host);
	217
	218	void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
	219	void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
8e7bfdb3	220	irqreturn_t tmio_mmc_irq(int irq, void *devid);
b6147490 GL	221
	222	static inline char tmio_mmc_kmap_atomic(struct scatterlist sg,
	223	unsigned long *flags)
	224	{
	225	local_irq_save(*flags);
482fce99	226	return kmap_atomic(sg_page(sg)) + sg->offset;
b6147490 GL	227	}
	228
	229	static inline void tmio_mmc_kunmap_atomic(struct scatterlist *sg,
	230	unsigned long flags, void virt)
	231	{
482fce99	232	kunmap_atomic(virt - sg->offset);
b6147490 GL	233	local_irq_restore(*flags);
	234	}
	235
9ade7dbf	236	#ifdef CONFIG_PM
7311bef0 GL	237	int tmio_mmc_host_runtime_suspend(struct device *dev);
7311bef0 GL	238	int tmio_mmc_host_runtime_resume(struct device *dev);
710dec95	239	#endif
7311bef0	240
a11862d3 SH	241	static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
a11862d3 SH	242	{
7445bf9e	243	return readw(host->ctl + (addr << host->bus_shift));
a11862d3 SH	244	}
	245
	246	static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
f2218db8	247	u16 *buf, int count)
a11862d3	248	{
7445bf9e	249	readsw(host->ctl + (addr << host->bus_shift), buf, count);
a11862d3 SH	250	}
a11862d3 SH	251
f2218db8 SH	252	static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host,
f2218db8 SH	253	int addr)
a11862d3	254	{
7445bf9e KM	255	return readw(host->ctl + (addr << host->bus_shift)) \|
7445bf9e KM	256	readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
a11862d3 SH	257	}
a11862d3 SH	258
8185e51f	259	static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
f2218db8	260	u32 *buf, int count)
8185e51f CB	261	{
	262	readsl(host->ctl + (addr << host->bus_shift), buf, count);
	263	}
	264
f2218db8 SH	265	static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
f2218db8 SH	266	u16 val)
a11862d3	267	{
973ed3af SH	268	/* If there is a hook and it returns non-zero then there
	269	* is an error and the write should be skipped
	270	*/
dfe9a229	271	if (host->write16_hook && host->write16_hook(host, addr))
973ed3af	272	return;
7445bf9e	273	writew(val, host->ctl + (addr << host->bus_shift));
a11862d3 SH	274	}
	275
	276	static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
f2218db8	277	u16 *buf, int count)
a11862d3	278	{
7445bf9e	279	writesw(host->ctl + (addr << host->bus_shift), buf, count);
a11862d3 SH	280	}
a11862d3 SH	281
f2218db8 SH	282	static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host,
f2218db8 SH	283	int addr, u32 val)
a11862d3	284	{
7c42dbf3	285	writew(val & 0xffff, host->ctl + (addr << host->bus_shift));
7445bf9e	286	writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
a11862d3 SH	287	}
a11862d3 SH	288
8185e51f	289	static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr,
f2218db8	290	const u32 *buf, int count)
8185e51f CB	291	{
	292	writesl(host->ctl + (addr << host->bus_shift), buf, count);
	293	}
	294
b6147490	295	#endif