[mirror_ubuntu-hirsute-kernel.git] / drivers / mmc / host / tmio_mmc.h

/*
 * linux/drivers/mmc/host/tmio_mmc.h
 *
 * Copyright (C) 2016 Sang Engineering, Wolfram Sang
 * Copyright (C) 2015-16 Renesas Electronics Corporation
 * Copyright (C) 2007 Ian Molton
 * Copyright (C) 2004 Ian Molton
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Driver for the MMC / SD / SDIO cell found in:
 *
 * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
 */

#ifndef TMIO_MMC_H
#define TMIO_MMC_H

#include <linux/dmaengine.h>
#include <linux/highmem.h>
#include <linux/mutex.h>
#include <linux/pagemap.h>
#include <linux/scatterlist.h>
#include <linux/spinlock.h>

#define CTL_SD_CMD 0x00
#define CTL_ARG_REG 0x04
#define CTL_STOP_INTERNAL_ACTION 0x08
#define CTL_XFER_BLK_COUNT 0xa
#define CTL_RESPONSE 0x0c
#define CTL_STATUS 0x1c
#define CTL_STATUS2 0x1e
#define CTL_IRQ_MASK 0x20
#define CTL_SD_CARD_CLK_CTL 0x24
#define CTL_SD_XFER_LEN 0x26
#define CTL_SD_MEM_CARD_OPT 0x28
#define CTL_SD_ERROR_DETAIL_STATUS 0x2c
#define CTL_SD_DATA_PORT 0x30
#define CTL_TRANSACTION_CTL 0x34
#define CTL_SDIO_STATUS 0x36
#define CTL_SDIO_IRQ_MASK 0x38
#define CTL_DMA_ENABLE 0xd8
#define CTL_RESET_SD 0xe0
#define CTL_VERSION 0xe2
#define CTL_SDIO_REGS 0x100
#define CTL_CLK_AND_WAIT_CTL 0x138
#define CTL_RESET_SDIO 0x1e0

/* Definitions for values the CTRL_STATUS register can take. */
#define TMIO_STAT_CMDRESPEND    BIT(0)
#define TMIO_STAT_DATAEND       BIT(2)
#define TMIO_STAT_CARD_REMOVE   BIT(3)
#define TMIO_STAT_CARD_INSERT   BIT(4)
#define TMIO_STAT_SIGSTATE      BIT(5)
#define TMIO_STAT_WRPROTECT     BIT(7)
#define TMIO_STAT_CARD_REMOVE_A BIT(8)
#define TMIO_STAT_CARD_INSERT_A BIT(9)
#define TMIO_STAT_SIGSTATE_A    BIT(10)

/* These belong technically to CTRL_STATUS2, but the driver merges them */
#define TMIO_STAT_CMD_IDX_ERR   BIT(16)
#define TMIO_STAT_CRCFAIL       BIT(17)
#define TMIO_STAT_STOPBIT_ERR   BIT(18)
#define TMIO_STAT_DATATIMEOUT   BIT(19)
#define TMIO_STAT_RXOVERFLOW    BIT(20)
#define TMIO_STAT_TXUNDERRUN    BIT(21)
#define TMIO_STAT_CMDTIMEOUT    BIT(22)
#define TMIO_STAT_RXRDY         BIT(24)
#define TMIO_STAT_TXRQ          BIT(25)
#define TMIO_STAT_ILL_FUNC      BIT(29)
#define TMIO_STAT_CMD_BUSY      BIT(30)
#define TMIO_STAT_ILL_ACCESS    BIT(31)

#define TMIO_STATUS2_DAT0	BIT(7)

#define	CLK_CTL_DIV_MASK	0xff
#define	CLK_CTL_SCLKEN		BIT(8)

#define TMIO_BBS		512		/* Boot block size */

/* Definitions for values the CTRL_SDIO_STATUS register can take. */
#define TMIO_SDIO_STAT_IOIRQ	0x0001
#define TMIO_SDIO_STAT_EXPUB52	0x4000
#define TMIO_SDIO_STAT_EXWT	0x8000
#define TMIO_SDIO_MASK_ALL	0xc007

/* Define some IRQ masks */
/* This is the mask used at reset by the chip */
#define TMIO_MASK_ALL           0x837f031d
#define TMIO_MASK_READOP  (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND)
#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND)
#define TMIO_MASK_CMD     (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \
		TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
#define TMIO_MASK_IRQ     (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)

struct tmio_mmc_data;
struct tmio_mmc_host;

struct tmio_mmc_dma {
	enum dma_slave_buswidth dma_buswidth;
	bool (*filter)(struct dma_chan *chan, void *arg);
	void (*enable)(struct tmio_mmc_host *host, bool enable);
};

struct tmio_mmc_host {
	void __iomem *ctl;
	struct mmc_command      *cmd;
	struct mmc_request      *mrq;
	struct mmc_data         *data;
	struct mmc_host         *mmc;

	/* Callbacks for clock / power control */
	void (*set_pwr)(struct platform_device *host, int state);
	void (*set_clk_div)(struct platform_device *host, int state);

	/* pio related stuff */
	struct scatterlist      *sg_ptr;
	struct scatterlist      *sg_orig;
	unsigned int            sg_len;
	unsigned int            sg_off;
	unsigned long		bus_shift;

	struct platform_device *pdev;
	struct tmio_mmc_data *pdata;
	struct tmio_mmc_dma	*dma;

	/* DMA support */
	bool			force_pio;
	struct dma_chan		*chan_rx;
	struct dma_chan		*chan_tx;
	struct tasklet_struct	dma_complete;
	struct tasklet_struct	dma_issue;
	struct scatterlist	bounce_sg;
	u8			*bounce_buf;

	/* Track lost interrupts */
	struct delayed_work	delayed_reset_work;
	struct work_struct	done;

	/* Cache */
	u32			sdcard_irq_mask;
	u32			sdio_irq_mask;
	unsigned int		clk_cache;

	spinlock_t		lock;		/* protect host private data */
	unsigned long		last_req_ts;
	struct mutex		ios_lock;	/* protect set_ios() context */
	bool			native_hotplug;
	bool			sdio_irq_enabled;

	int (*write16_hook)(struct tmio_mmc_host *host, int addr);
	int (*clk_enable)(struct tmio_mmc_host *host);
	unsigned int (*clk_update)(struct tmio_mmc_host *host,
				   unsigned int new_clock);
	void (*clk_disable)(struct tmio_mmc_host *host);
	int (*multi_io_quirk)(struct mmc_card *card,
			      unsigned int direction, int blk_size);
	int (*start_signal_voltage_switch)(struct mmc_host *mmc,
					   struct mmc_ios *ios);
};

struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev);
void tmio_mmc_host_free(struct tmio_mmc_host *host);
int tmio_mmc_host_probe(struct tmio_mmc_host *host,
			struct tmio_mmc_data *pdata);
void tmio_mmc_host_remove(struct tmio_mmc_host *host);
void tmio_mmc_do_data_irq(struct tmio_mmc_host *host);

void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
irqreturn_t tmio_mmc_irq(int irq, void *devid);

static inline char *tmio_mmc_kmap_atomic(struct scatterlist *sg,
					 unsigned long *flags)
{
	local_irq_save(*flags);
	return kmap_atomic(sg_page(sg)) + sg->offset;
}

static inline void tmio_mmc_kunmap_atomic(struct scatterlist *sg,
					  unsigned long *flags, void *virt)
{
	kunmap_atomic(virt - sg->offset);
	local_irq_restore(*flags);
}

#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
void tmio_mmc_start_dma(struct tmio_mmc_host *host, struct mmc_data *data);
void tmio_mmc_enable_dma(struct tmio_mmc_host *host, bool enable);
void tmio_mmc_request_dma(struct tmio_mmc_host *host, struct tmio_mmc_data *pdata);
void tmio_mmc_release_dma(struct tmio_mmc_host *host);
void tmio_mmc_abort_dma(struct tmio_mmc_host *host);
#else
static inline void tmio_mmc_start_dma(struct tmio_mmc_host *host,
			       struct mmc_data *data)
{
}

static inline void tmio_mmc_enable_dma(struct tmio_mmc_host *host, bool enable)
{
}

static inline void tmio_mmc_request_dma(struct tmio_mmc_host *host,
				 struct tmio_mmc_data *pdata)
{
	host->chan_tx = NULL;
	host->chan_rx = NULL;
}

static inline void tmio_mmc_release_dma(struct tmio_mmc_host *host)
{
}

static inline void tmio_mmc_abort_dma(struct tmio_mmc_host *host)
{
}
#endif

#ifdef CONFIG_PM
int tmio_mmc_host_runtime_suspend(struct device *dev);
int tmio_mmc_host_runtime_resume(struct device *dev);
#endif

static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
{
	return readw(host->ctl + (addr << host->bus_shift));
}

static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
		u16 *buf, int count)
{
	readsw(host->ctl + (addr << host->bus_shift), buf, count);
}

static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host, int addr)
{
	return readw(host->ctl + (addr << host->bus_shift)) |
	       readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
}

static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, u16 val)
{
	/* If there is a hook and it returns non-zero then there
	 * is an error and the write should be skipped
	 */
	if (host->write16_hook && host->write16_hook(host, addr))
		return;
	writew(val, host->ctl + (addr << host->bus_shift));
}

static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
		u16 *buf, int count)
{
	writesw(host->ctl + (addr << host->bus_shift), buf, count);
}

static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host, int addr, u32 val)
{
	writew(val, host->ctl + (addr << host->bus_shift));
	writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
}

#endif
Commit	Line	Data
b6147490 GL	1	/*
	2	* linux/drivers/mmc/host/tmio_mmc.h
	3	*
ac86045e WS	4	* Copyright (C) 2016 Sang Engineering, Wolfram Sang
ac86045e WS	5	* Copyright (C) 2015-16 Renesas Electronics Corporation
b6147490 GL	6	* Copyright (C) 2007 Ian Molton
	7	* Copyright (C) 2004 Ian Molton
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* Driver for the MMC / SD / SDIO cell found in:
	14	*
	15	* TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
	16	*/
	17
	18	#ifndef TMIO_MMC_H
	19	#define TMIO_MMC_H
	20
361936ef	21	#include <linux/dmaengine.h>
b6147490	22	#include <linux/highmem.h>
b9269fdd	23	#include <linux/mutex.h>
b6147490	24	#include <linux/pagemap.h>
6c0cbef6	25	#include <linux/scatterlist.h>
e3de2be7	26	#include <linux/spinlock.h>
b6147490	27
ac86045e WS	28	#define CTL_SD_CMD 0x00
	29	#define CTL_ARG_REG 0x04
	30	#define CTL_STOP_INTERNAL_ACTION 0x08
	31	#define CTL_XFER_BLK_COUNT 0xa
	32	#define CTL_RESPONSE 0x0c
	33	#define CTL_STATUS 0x1c
	34	#define CTL_STATUS2 0x1e
	35	#define CTL_IRQ_MASK 0x20
	36	#define CTL_SD_CARD_CLK_CTL 0x24
	37	#define CTL_SD_XFER_LEN 0x26
	38	#define CTL_SD_MEM_CARD_OPT 0x28
	39	#define CTL_SD_ERROR_DETAIL_STATUS 0x2c
	40	#define CTL_SD_DATA_PORT 0x30
	41	#define CTL_TRANSACTION_CTL 0x34
	42	#define CTL_SDIO_STATUS 0x36
	43	#define CTL_SDIO_IRQ_MASK 0x38
	44	#define CTL_DMA_ENABLE 0xd8
	45	#define CTL_RESET_SD 0xe0
	46	#define CTL_VERSION 0xe2
	47	#define CTL_SDIO_REGS 0x100
	48	#define CTL_CLK_AND_WAIT_CTL 0x138
	49	#define CTL_RESET_SDIO 0x1e0
	50
	51	/* Definitions for values the CTRL_STATUS register can take. */
2cafc5cb WS	52	#define TMIO_STAT_CMDRESPEND BIT(0)
	53	#define TMIO_STAT_DATAEND BIT(2)
	54	#define TMIO_STAT_CARD_REMOVE BIT(3)
	55	#define TMIO_STAT_CARD_INSERT BIT(4)
	56	#define TMIO_STAT_SIGSTATE BIT(5)
	57	#define TMIO_STAT_WRPROTECT BIT(7)
	58	#define TMIO_STAT_CARD_REMOVE_A BIT(8)
	59	#define TMIO_STAT_CARD_INSERT_A BIT(9)
	60	#define TMIO_STAT_SIGSTATE_A BIT(10)
	61
	62	/* These belong technically to CTRL_STATUS2, but the driver merges them */
	63	#define TMIO_STAT_CMD_IDX_ERR BIT(16)
	64	#define TMIO_STAT_CRCFAIL BIT(17)
	65	#define TMIO_STAT_STOPBIT_ERR BIT(18)
	66	#define TMIO_STAT_DATATIMEOUT BIT(19)
	67	#define TMIO_STAT_RXOVERFLOW BIT(20)
	68	#define TMIO_STAT_TXUNDERRUN BIT(21)
	69	#define TMIO_STAT_CMDTIMEOUT BIT(22)
	70	#define TMIO_STAT_RXRDY BIT(24)
	71	#define TMIO_STAT_TXRQ BIT(25)
	72	#define TMIO_STAT_ILL_FUNC BIT(29)
	73	#define TMIO_STAT_CMD_BUSY BIT(30)
	74	#define TMIO_STAT_ILL_ACCESS BIT(31)
ac86045e WS	75
	76	#define TMIO_STATUS2_DAT0 BIT(7)
	77
	78	#define CLK_CTL_DIV_MASK 0xff
	79	#define CLK_CTL_SCLKEN BIT(8)
	80
	81	#define TMIO_BBS 512 /* Boot block size */
	82
b6147490	83	/* Definitions for values the CTRL_SDIO_STATUS register can take. */
cba179ae	84	#define TMIO_SDIO_STAT_IOIRQ 0x0001
b6147490	85	#define TMIO_SDIO_STAT_EXPUB52 0x4000
cba179ae SH	86	#define TMIO_SDIO_STAT_EXWT 0x8000
cba179ae SH	87	#define TMIO_SDIO_MASK_ALL 0xc007
b6147490 GL	88
	89	/* Define some IRQ masks */
	90	/* This is the mask used at reset by the chip */
	91	#define TMIO_MASK_ALL 0x837f031d
	92	#define TMIO_MASK_READOP (TMIO_STAT_RXRDY \| TMIO_STAT_DATAEND)
	93	#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ \| TMIO_STAT_DATAEND)
	94	#define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND \| TMIO_STAT_CMDTIMEOUT \| \
	95	TMIO_STAT_CARD_REMOVE \| TMIO_STAT_CARD_INSERT)
	96	#define TMIO_MASK_IRQ (TMIO_MASK_READOP \| TMIO_MASK_WRITEOP \| TMIO_MASK_CMD)
	97
	98	struct tmio_mmc_data;
5add2aca	99	struct tmio_mmc_host;
b6147490	100
7ecc09ba	101	struct tmio_mmc_dma {
361936ef	102	enum dma_slave_buswidth dma_buswidth;
7ecc09ba	103	bool (filter)(struct dma_chan chan, void *arg);
5add2aca	104	void (enable)(struct tmio_mmc_host host, bool enable);
7ecc09ba KM	105	};
7ecc09ba KM	106
b6147490 GL	107	struct tmio_mmc_host {
b6147490 GL	108	void __iomem *ctl;
b6147490 GL	109	struct mmc_command *cmd;
	110	struct mmc_request *mrq;
	111	struct mmc_data *data;
	112	struct mmc_host *mmc;
b6147490 GL	113
	114	/* Callbacks for clock / power control */
	115	void (set_pwr)(struct platform_device host, int state);
	116	void (set_clk_div)(struct platform_device host, int state);
	117
	118	/* pio related stuff */
	119	struct scatterlist *sg_ptr;
	120	struct scatterlist *sg_orig;
	121	unsigned int sg_len;
	122	unsigned int sg_off;
7445bf9e	123	unsigned long bus_shift;
b6147490 GL	124
	125	struct platform_device *pdev;
	126	struct tmio_mmc_data *pdata;
7ecc09ba	127	struct tmio_mmc_dma *dma;
b6147490 GL	128
	129	/* DMA support */
	130	bool force_pio;
	131	struct dma_chan *chan_rx;
	132	struct dma_chan *chan_tx;
	133	struct tasklet_struct dma_complete;
	134	struct tasklet_struct dma_issue;
	135	struct scatterlist bounce_sg;
	136	u8 *bounce_buf;
	137
	138	/* Track lost interrupts */
	139	struct delayed_work delayed_reset_work;
b9269fdd GL	140	struct work_struct done;
b9269fdd GL	141
ae12d250	142	/* Cache */
54680fe7 SH	143	u32 sdcard_irq_mask;
54680fe7 SH	144	u32 sdio_irq_mask;
ae12d250	145	unsigned int clk_cache;
54680fe7	146
b9269fdd	147	spinlock_t lock; /* protect host private data */
b6147490	148	unsigned long last_req_ts;
b9269fdd	149	struct mutex ios_lock; /* protect set_ios() context */
2b1ac5c2	150	bool native_hotplug;
7501c431	151	bool sdio_irq_enabled;
dfe9a229 KM	152
dfe9a229 KM	153	int (write16_hook)(struct tmio_mmc_host host, int addr);
0ea28210	154	int (clk_enable)(struct tmio_mmc_host host);
2fb55956 BH	155	unsigned int (clk_update)(struct tmio_mmc_host host,
2fb55956 BH	156	unsigned int new_clock);
0ea28210	157	void (clk_disable)(struct tmio_mmc_host host);
85c02ddd KM	158	int (multi_io_quirk)(struct mmc_card card,
85c02ddd KM	159	unsigned int direction, int blk_size);
452e5eef WS	160	int (start_signal_voltage_switch)(struct mmc_host mmc,
452e5eef WS	161	struct mmc_ios *ios);
b6147490 GL	162	};
b6147490 GL	163
94b110af KM	164	struct tmio_mmc_host tmio_mmc_host_alloc(struct platform_device pdev);
	165	void tmio_mmc_host_free(struct tmio_mmc_host *host);
	166	int tmio_mmc_host_probe(struct tmio_mmc_host *host,
b6147490 GL	167	struct tmio_mmc_data *pdata);
	168	void tmio_mmc_host_remove(struct tmio_mmc_host *host);
	169	void tmio_mmc_do_data_irq(struct tmio_mmc_host *host);
	170
	171	void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
	172	void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
8e7bfdb3	173	irqreturn_t tmio_mmc_irq(int irq, void *devid);
b6147490 GL	174
	175	static inline char tmio_mmc_kmap_atomic(struct scatterlist sg,
	176	unsigned long *flags)
	177	{
	178	local_irq_save(*flags);
482fce99	179	return kmap_atomic(sg_page(sg)) + sg->offset;
b6147490 GL	180	}
	181
	182	static inline void tmio_mmc_kunmap_atomic(struct scatterlist *sg,
	183	unsigned long flags, void virt)
	184	{
482fce99	185	kunmap_atomic(virt - sg->offset);
b6147490 GL	186	local_irq_restore(*flags);
	187	}
	188
42051e8a	189	#if defined(CONFIG_MMC_SDHI) \|\| defined(CONFIG_MMC_SDHI_MODULE)
b6147490	190	void tmio_mmc_start_dma(struct tmio_mmc_host host, struct mmc_data data);
162f43e3	191	void tmio_mmc_enable_dma(struct tmio_mmc_host *host, bool enable);
b6147490 GL	192	void tmio_mmc_request_dma(struct tmio_mmc_host host, struct tmio_mmc_data pdata);
b6147490 GL	193	void tmio_mmc_release_dma(struct tmio_mmc_host *host);
e3de2be7	194	void tmio_mmc_abort_dma(struct tmio_mmc_host *host);
b6147490 GL	195	#else
	196	static inline void tmio_mmc_start_dma(struct tmio_mmc_host *host,
	197	struct mmc_data *data)
	198	{
	199	}
	200
162f43e3 GL	201	static inline void tmio_mmc_enable_dma(struct tmio_mmc_host *host, bool enable)
	202	{
	203	}
	204
b6147490 GL	205	static inline void tmio_mmc_request_dma(struct tmio_mmc_host *host,
	206	struct tmio_mmc_data *pdata)
	207	{
	208	host->chan_tx = NULL;
	209	host->chan_rx = NULL;
	210	}
	211
	212	static inline void tmio_mmc_release_dma(struct tmio_mmc_host *host)
	213	{
	214	}
e3de2be7 GL	215
	216	static inline void tmio_mmc_abort_dma(struct tmio_mmc_host *host)
	217	{
	218	}
b6147490 GL	219	#endif
b6147490 GL	220
9ade7dbf	221	#ifdef CONFIG_PM
7311bef0 GL	222	int tmio_mmc_host_runtime_suspend(struct device *dev);
7311bef0 GL	223	int tmio_mmc_host_runtime_resume(struct device *dev);
710dec95	224	#endif
7311bef0	225
a11862d3 SH	226	static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
a11862d3 SH	227	{
7445bf9e	228	return readw(host->ctl + (addr << host->bus_shift));
a11862d3 SH	229	}
	230
	231	static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
	232	u16 *buf, int count)
	233	{
7445bf9e	234	readsw(host->ctl + (addr << host->bus_shift), buf, count);
a11862d3 SH	235	}
a11862d3 SH	236
2c54506b	237	static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host, int addr)
a11862d3	238	{
7445bf9e KM	239	return readw(host->ctl + (addr << host->bus_shift)) \|
7445bf9e KM	240	readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
a11862d3 SH	241	}
	242
	243	static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, u16 val)
	244	{
973ed3af SH	245	/* If there is a hook and it returns non-zero then there
	246	* is an error and the write should be skipped
	247	*/
dfe9a229	248	if (host->write16_hook && host->write16_hook(host, addr))
973ed3af	249	return;
7445bf9e	250	writew(val, host->ctl + (addr << host->bus_shift));
a11862d3 SH	251	}
	252
	253	static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
	254	u16 *buf, int count)
	255	{
7445bf9e	256	writesw(host->ctl + (addr << host->bus_shift), buf, count);
a11862d3 SH	257	}
a11862d3 SH	258
2c54506b	259	static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host, int addr, u32 val)
a11862d3	260	{
7445bf9e KM	261	writew(val, host->ctl + (addr << host->bus_shift));
7445bf9e KM	262	writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
a11862d3 SH	263	}
a11862d3 SH	264
b6147490	265	#endif