[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / tmio_mmc.h

/*
 * Driver for the MMC / SD / SDIO cell found in:
 *
 * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
 *
 * Copyright (C) 2015-17 Renesas Electronics Corporation
 * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
 * Copyright (C) 2007 Ian Molton
 * Copyright (C) 2004 Ian Molton
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#ifndef TMIO_MMC_H
#define TMIO_MMC_H

#include <linux/dmaengine.h>
#include <linux/highmem.h>
#include <linux/mutex.h>
#include <linux/pagemap.h>
#include <linux/scatterlist.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>

#define CTL_SD_CMD 0x00
#define CTL_ARG_REG 0x04
#define CTL_STOP_INTERNAL_ACTION 0x08
#define CTL_XFER_BLK_COUNT 0xa
#define CTL_RESPONSE 0x0c
/* driver merges STATUS and following STATUS2 */
#define CTL_STATUS 0x1c
/* driver merges IRQ_MASK and following IRQ_MASK2 */
#define CTL_IRQ_MASK 0x20
#define CTL_SD_CARD_CLK_CTL 0x24
#define CTL_SD_XFER_LEN 0x26
#define CTL_SD_MEM_CARD_OPT 0x28
#define CTL_SD_ERROR_DETAIL_STATUS 0x2c
#define CTL_SD_DATA_PORT 0x30
#define CTL_TRANSACTION_CTL 0x34
#define CTL_SDIO_STATUS 0x36
#define CTL_SDIO_IRQ_MASK 0x38
#define CTL_DMA_ENABLE 0xd8
#define CTL_RESET_SD 0xe0
#define CTL_VERSION 0xe2
#define CTL_SDIO_REGS 0x100
#define CTL_CLK_AND_WAIT_CTL 0x138
#define CTL_RESET_SDIO 0x1e0

/* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */
#define TMIO_STOP_STP		BIT(0)
#define TMIO_STOP_SEC		BIT(8)

/* Definitions for values the CTL_STATUS register can take */
#define TMIO_STAT_CMDRESPEND    BIT(0)
#define TMIO_STAT_DATAEND       BIT(2)
#define TMIO_STAT_CARD_REMOVE   BIT(3)
#define TMIO_STAT_CARD_INSERT   BIT(4)
#define TMIO_STAT_SIGSTATE      BIT(5)
#define TMIO_STAT_WRPROTECT     BIT(7)
#define TMIO_STAT_CARD_REMOVE_A BIT(8)
#define TMIO_STAT_CARD_INSERT_A BIT(9)
#define TMIO_STAT_SIGSTATE_A    BIT(10)

/* These belong technically to CTL_STATUS2, but the driver merges them */
#define TMIO_STAT_CMD_IDX_ERR   BIT(16)
#define TMIO_STAT_CRCFAIL       BIT(17)
#define TMIO_STAT_STOPBIT_ERR   BIT(18)
#define TMIO_STAT_DATATIMEOUT   BIT(19)
#define TMIO_STAT_RXOVERFLOW    BIT(20)
#define TMIO_STAT_TXUNDERRUN    BIT(21)
#define TMIO_STAT_CMDTIMEOUT    BIT(22)
#define TMIO_STAT_DAT0		BIT(23)	/* only known on R-Car so far */
#define TMIO_STAT_RXRDY         BIT(24)
#define TMIO_STAT_TXRQ          BIT(25)
#define TMIO_STAT_ILL_FUNC      BIT(29) /* only when !TMIO_MMC_HAS_IDLE_WAIT */
#define TMIO_STAT_SCLKDIVEN     BIT(29) /* only when TMIO_MMC_HAS_IDLE_WAIT */
#define TMIO_STAT_CMD_BUSY      BIT(30)
#define TMIO_STAT_ILL_ACCESS    BIT(31)

#define	CLK_CTL_DIV_MASK	0xff
#define	CLK_CTL_SCLKEN		BIT(8)

#define CARD_OPT_WIDTH8		BIT(13)
#define CARD_OPT_WIDTH		BIT(15)

#define TMIO_BBS		512		/* Boot block size */

/* Definitions for values the CTL_SDIO_STATUS register can take */
#define TMIO_SDIO_STAT_IOIRQ	0x0001
#define TMIO_SDIO_STAT_EXPUB52	0x4000
#define TMIO_SDIO_STAT_EXWT	0x8000
#define TMIO_SDIO_MASK_ALL	0xc007

#define TMIO_SDIO_SETBITS_MASK	0x0006

/* Define some IRQ masks */
/* This is the mask used at reset by the chip */
#define TMIO_MASK_ALL           0x837f031d
#define TMIO_MASK_READOP  (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND)
#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND)
#define TMIO_MASK_CMD     (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \
		TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
#define TMIO_MASK_IRQ     (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)

struct tmio_mmc_data;
struct tmio_mmc_host;

struct tmio_mmc_dma {
	enum dma_slave_buswidth dma_buswidth;
	bool (*filter)(struct dma_chan *chan, void *arg);
	void (*enable)(struct tmio_mmc_host *host, bool enable);
};

struct tmio_mmc_dma_ops {
	void (*start)(struct tmio_mmc_host *host, struct mmc_data *data);
	void (*enable)(struct tmio_mmc_host *host, bool enable);
	void (*request)(struct tmio_mmc_host *host,
			struct tmio_mmc_data *pdata);
	void (*release)(struct tmio_mmc_host *host);
	void (*abort)(struct tmio_mmc_host *host);
	void (*dataend)(struct tmio_mmc_host *host);
};

struct tmio_mmc_host {
	void __iomem *ctl;
	struct mmc_command      *cmd;
	struct mmc_request      *mrq;
	struct mmc_data         *data;
	struct mmc_host         *mmc;

	/* Callbacks for clock / power control */
	void (*set_pwr)(struct platform_device *host, int state);
	void (*set_clk_div)(struct platform_device *host, int state);

	/* pio related stuff */
	struct scatterlist      *sg_ptr;
	struct scatterlist      *sg_orig;
	unsigned int            sg_len;
	unsigned int            sg_off;
	unsigned long		bus_shift;

	struct platform_device *pdev;
	struct tmio_mmc_data *pdata;
	struct tmio_mmc_dma	*dma;

	/* DMA support */
	bool			force_pio;
	struct dma_chan		*chan_rx;
	struct dma_chan		*chan_tx;
	struct completion	dma_dataend;
	struct tasklet_struct	dma_issue;
	struct scatterlist	bounce_sg;
	u8			*bounce_buf;

	/* Track lost interrupts */
	struct delayed_work	delayed_reset_work;
	struct work_struct	done;

	/* Cache */
	u32			sdcard_irq_mask;
	u32			sdio_irq_mask;
	unsigned int		clk_cache;

	spinlock_t		lock;		/* protect host private data */
	unsigned long		last_req_ts;
	struct mutex		ios_lock;	/* protect set_ios() context */
	bool			native_hotplug;
	bool			sdio_irq_enabled;
	u32			scc_tappos;

	/* Mandatory callback */
	int (*clk_enable)(struct tmio_mmc_host *host);

	/* Optional callbacks */
	unsigned int (*clk_update)(struct tmio_mmc_host *host,
				   unsigned int new_clock);
	void (*clk_disable)(struct tmio_mmc_host *host);
	int (*multi_io_quirk)(struct mmc_card *card,
			      unsigned int direction, int blk_size);
	int (*card_busy)(struct mmc_host *mmc);
	int (*start_signal_voltage_switch)(struct mmc_host *mmc,
					   struct mmc_ios *ios);
	int (*write16_hook)(struct tmio_mmc_host *host, int addr);
	void (*hw_reset)(struct tmio_mmc_host *host);
	void (*prepare_tuning)(struct tmio_mmc_host *host, unsigned long tap);
	bool (*check_scc_error)(struct tmio_mmc_host *host);

	/*
	 * Mandatory callback for tuning to occur which is optional for SDR50
	 * and mandatory for SDR104.
	 */
	unsigned int (*init_tuning)(struct tmio_mmc_host *host);
	int (*select_tuning)(struct tmio_mmc_host *host);

	/* Tuning values: 1 for success, 0 for failure */
	DECLARE_BITMAP(taps, BITS_PER_BYTE * sizeof(long));
	unsigned int tap_num;

	const struct tmio_mmc_dma_ops *dma_ops;
};

struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev);
void tmio_mmc_host_free(struct tmio_mmc_host *host);
int tmio_mmc_host_probe(struct tmio_mmc_host *host,
			struct tmio_mmc_data *pdata,
			const struct tmio_mmc_dma_ops *dma_ops);
void tmio_mmc_host_remove(struct tmio_mmc_host *host);
void tmio_mmc_do_data_irq(struct tmio_mmc_host *host);

void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
irqreturn_t tmio_mmc_irq(int irq, void *devid);

static inline char *tmio_mmc_kmap_atomic(struct scatterlist *sg,
					 unsigned long *flags)
{
	local_irq_save(*flags);
	return kmap_atomic(sg_page(sg)) + sg->offset;
}

static inline void tmio_mmc_kunmap_atomic(struct scatterlist *sg,
					  unsigned long *flags, void *virt)
{
	kunmap_atomic(virt - sg->offset);
	local_irq_restore(*flags);
}

#ifdef CONFIG_PM
int tmio_mmc_host_runtime_suspend(struct device *dev);
int tmio_mmc_host_runtime_resume(struct device *dev);
#endif

static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
{
	return readw(host->ctl + (addr << host->bus_shift));
}

static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
				      u16 *buf, int count)
{
	readsw(host->ctl + (addr << host->bus_shift), buf, count);
}

static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host,
					      int addr)
{
	return readw(host->ctl + (addr << host->bus_shift)) |
	       readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
}

static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
				      u32 *buf, int count)
{
	readsl(host->ctl + (addr << host->bus_shift), buf, count);
}

static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
				   u16 val)
{
	/* If there is a hook and it returns non-zero then there
	 * is an error and the write should be skipped
	 */
	if (host->write16_hook && host->write16_hook(host, addr))
		return;
	writew(val, host->ctl + (addr << host->bus_shift));
}

static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
				       u16 *buf, int count)
{
	writesw(host->ctl + (addr << host->bus_shift), buf, count);
}

static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host,
						int addr, u32 val)
{
	writew(val & 0xffff, host->ctl + (addr << host->bus_shift));
	writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
}

static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr,
				       const u32 *buf, int count)
{
	writesl(host->ctl + (addr << host->bus_shift), buf, count);
}

#endif
Commit	Line	Data
b6147490	1	/*
b21f13d8 SH	2	* Driver for the MMC / SD / SDIO cell found in:
	3	*
	4	* TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
b6147490	5	*
87317c4d SH	6	* Copyright (C) 2015-17 Renesas Electronics Corporation
	7	* Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
	8	* Copyright (C) 2016-17 Horms Solutions, Simon Horman
b6147490 GL	9	* Copyright (C) 2007 Ian Molton
	10	* Copyright (C) 2004 Ian Molton
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*
b6147490 GL	16	*/
	17
	18	#ifndef TMIO_MMC_H
	19	#define TMIO_MMC_H
	20
361936ef	21	#include <linux/dmaengine.h>
b6147490	22	#include <linux/highmem.h>
b9269fdd	23	#include <linux/mutex.h>
b6147490	24	#include <linux/pagemap.h>
6c0cbef6	25	#include <linux/scatterlist.h>
e3de2be7	26	#include <linux/spinlock.h>
b8789ec4	27	#include <linux/interrupt.h>
b6147490	28
ac86045e WS	29	#define CTL_SD_CMD 0x00
	30	#define CTL_ARG_REG 0x04
	31	#define CTL_STOP_INTERNAL_ACTION 0x08
	32	#define CTL_XFER_BLK_COUNT 0xa
	33	#define CTL_RESPONSE 0x0c
184adf20	34	/* driver merges STATUS and following STATUS2 */
ac86045e	35	#define CTL_STATUS 0x1c
184adf20	36	/* driver merges IRQ_MASK and following IRQ_MASK2 */
ac86045e WS	37	#define CTL_IRQ_MASK 0x20
	38	#define CTL_SD_CARD_CLK_CTL 0x24
	39	#define CTL_SD_XFER_LEN 0x26
	40	#define CTL_SD_MEM_CARD_OPT 0x28
	41	#define CTL_SD_ERROR_DETAIL_STATUS 0x2c
	42	#define CTL_SD_DATA_PORT 0x30
	43	#define CTL_TRANSACTION_CTL 0x34
	44	#define CTL_SDIO_STATUS 0x36
	45	#define CTL_SDIO_IRQ_MASK 0x38
	46	#define CTL_DMA_ENABLE 0xd8
	47	#define CTL_RESET_SD 0xe0
	48	#define CTL_VERSION 0xe2
	49	#define CTL_SDIO_REGS 0x100
	50	#define CTL_CLK_AND_WAIT_CTL 0x138
	51	#define CTL_RESET_SDIO 0x1e0
	52
9afcbf4a WS	53	/* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */
	54	#define TMIO_STOP_STP BIT(0)
	55	#define TMIO_STOP_SEC BIT(8)
	56
d8acd16c	57	/* Definitions for values the CTL_STATUS register can take */
2cafc5cb WS	58	#define TMIO_STAT_CMDRESPEND BIT(0)
	59	#define TMIO_STAT_DATAEND BIT(2)
	60	#define TMIO_STAT_CARD_REMOVE BIT(3)
	61	#define TMIO_STAT_CARD_INSERT BIT(4)
	62	#define TMIO_STAT_SIGSTATE BIT(5)
	63	#define TMIO_STAT_WRPROTECT BIT(7)
	64	#define TMIO_STAT_CARD_REMOVE_A BIT(8)
	65	#define TMIO_STAT_CARD_INSERT_A BIT(9)
	66	#define TMIO_STAT_SIGSTATE_A BIT(10)
	67
d8acd16c	68	/* These belong technically to CTL_STATUS2, but the driver merges them */
2cafc5cb WS	69	#define TMIO_STAT_CMD_IDX_ERR BIT(16)
	70	#define TMIO_STAT_CRCFAIL BIT(17)
	71	#define TMIO_STAT_STOPBIT_ERR BIT(18)
	72	#define TMIO_STAT_DATATIMEOUT BIT(19)
	73	#define TMIO_STAT_RXOVERFLOW BIT(20)
	74	#define TMIO_STAT_TXUNDERRUN BIT(21)
	75	#define TMIO_STAT_CMDTIMEOUT BIT(22)
83e95351	76	#define TMIO_STAT_DAT0 BIT(23) /* only known on R-Car so far */
2cafc5cb WS	77	#define TMIO_STAT_RXRDY BIT(24)
2cafc5cb WS	78	#define TMIO_STAT_TXRQ BIT(25)
a21553c9 WS	79	#define TMIO_STAT_ILL_FUNC BIT(29) /* only when !TMIO_MMC_HAS_IDLE_WAIT */
a21553c9 WS	80	#define TMIO_STAT_SCLKDIVEN BIT(29) /* only when TMIO_MMC_HAS_IDLE_WAIT */
2cafc5cb WS	81	#define TMIO_STAT_CMD_BUSY BIT(30)
2cafc5cb WS	82	#define TMIO_STAT_ILL_ACCESS BIT(31)
ac86045e	83
ac86045e WS	84	#define CLK_CTL_DIV_MASK 0xff
	85	#define CLK_CTL_SCLKEN BIT(8)
	86
0bc0b6e8 WS	87	#define CARD_OPT_WIDTH8 BIT(13)
	88	#define CARD_OPT_WIDTH BIT(15)
	89
ac86045e WS	90	#define TMIO_BBS 512 /* Boot block size */
ac86045e WS	91
d8acd16c	92	/* Definitions for values the CTL_SDIO_STATUS register can take */
cba179ae	93	#define TMIO_SDIO_STAT_IOIRQ 0x0001
b6147490	94	#define TMIO_SDIO_STAT_EXPUB52 0x4000
cba179ae SH	95	#define TMIO_SDIO_STAT_EXWT 0x8000
cba179ae SH	96	#define TMIO_SDIO_MASK_ALL 0xc007
b6147490	97
ee289815 WS	98	#define TMIO_SDIO_SETBITS_MASK 0x0006
ee289815 WS	99
b6147490 GL	100	/* Define some IRQ masks */
	101	/* This is the mask used at reset by the chip */
	102	#define TMIO_MASK_ALL 0x837f031d
	103	#define TMIO_MASK_READOP (TMIO_STAT_RXRDY \| TMIO_STAT_DATAEND)
	104	#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ \| TMIO_STAT_DATAEND)
	105	#define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND \| TMIO_STAT_CMDTIMEOUT \| \
	106	TMIO_STAT_CARD_REMOVE \| TMIO_STAT_CARD_INSERT)
	107	#define TMIO_MASK_IRQ (TMIO_MASK_READOP \| TMIO_MASK_WRITEOP \| TMIO_MASK_CMD)
	108
	109	struct tmio_mmc_data;
5add2aca	110	struct tmio_mmc_host;
b6147490	111
7ecc09ba	112	struct tmio_mmc_dma {
361936ef	113	enum dma_slave_buswidth dma_buswidth;
7ecc09ba	114	bool (filter)(struct dma_chan chan, void *arg);
5add2aca	115	void (enable)(struct tmio_mmc_host host, bool enable);
7ecc09ba KM	116	};
7ecc09ba KM	117
631fa73c SH	118	struct tmio_mmc_dma_ops {
	119	void (start)(struct tmio_mmc_host host, struct mmc_data *data);
	120	void (enable)(struct tmio_mmc_host host, bool enable);
	121	void (request)(struct tmio_mmc_host host,
	122	struct tmio_mmc_data *pdata);
	123	void (release)(struct tmio_mmc_host host);
	124	void (abort)(struct tmio_mmc_host host);
92d0f925	125	void (dataend)(struct tmio_mmc_host host);
631fa73c SH	126	};
631fa73c SH	127
b6147490 GL	128	struct tmio_mmc_host {
b6147490 GL	129	void __iomem *ctl;
b6147490 GL	130	struct mmc_command *cmd;
	131	struct mmc_request *mrq;
	132	struct mmc_data *data;
	133	struct mmc_host *mmc;
b6147490 GL	134
	135	/* Callbacks for clock / power control */
	136	void (set_pwr)(struct platform_device host, int state);
	137	void (set_clk_div)(struct platform_device host, int state);
	138
	139	/* pio related stuff */
	140	struct scatterlist *sg_ptr;
	141	struct scatterlist *sg_orig;
	142	unsigned int sg_len;
	143	unsigned int sg_off;
7445bf9e	144	unsigned long bus_shift;
b6147490 GL	145
	146	struct platform_device *pdev;
	147	struct tmio_mmc_data *pdata;
7ecc09ba	148	struct tmio_mmc_dma *dma;
b6147490 GL	149
	150	/* DMA support */
	151	bool force_pio;
	152	struct dma_chan *chan_rx;
	153	struct dma_chan *chan_tx;
52ad9a8e	154	struct completion dma_dataend;
b6147490 GL	155	struct tasklet_struct dma_issue;
	156	struct scatterlist bounce_sg;
	157	u8 *bounce_buf;
	158
	159	/* Track lost interrupts */
	160	struct delayed_work delayed_reset_work;
b9269fdd GL	161	struct work_struct done;
b9269fdd GL	162
ae12d250	163	/* Cache */
54680fe7 SH	164	u32 sdcard_irq_mask;
54680fe7 SH	165	u32 sdio_irq_mask;
ae12d250	166	unsigned int clk_cache;
54680fe7	167
b9269fdd	168	spinlock_t lock; /* protect host private data */
b6147490	169	unsigned long last_req_ts;
b9269fdd	170	struct mutex ios_lock; /* protect set_ios() context */
2b1ac5c2	171	bool native_hotplug;
7501c431	172	bool sdio_irq_enabled;
4f119977	173	u32 scc_tappos;
dfe9a229	174
2f87365f	175	/* Mandatory callback */
0ea28210	176	int (clk_enable)(struct tmio_mmc_host host);
2f87365f SH	177
2f87365f SH	178	/* Optional callbacks */
2fb55956 BH	179	unsigned int (clk_update)(struct tmio_mmc_host host,
2fb55956 BH	180	unsigned int new_clock);
0ea28210	181	void (clk_disable)(struct tmio_mmc_host host);
85c02ddd KM	182	int (multi_io_quirk)(struct mmc_card card,
85c02ddd KM	183	unsigned int direction, int blk_size);
6a4679f3	184	int (card_busy)(struct mmc_host mmc);
452e5eef WS	185	int (start_signal_voltage_switch)(struct mmc_host mmc,
452e5eef WS	186	struct mmc_ios *ios);
2f87365f	187	int (write16_hook)(struct tmio_mmc_host host, int addr);
e8f36b5d	188	void (hw_reset)(struct tmio_mmc_host host);
4f119977 AK	189	void (prepare_tuning)(struct tmio_mmc_host host, unsigned long tap);
	190	bool (check_scc_error)(struct tmio_mmc_host host);
	191
	192	/*
	193	* Mandatory callback for tuning to occur which is optional for SDR50
	194	* and mandatory for SDR104.
	195	*/
	196	unsigned int (init_tuning)(struct tmio_mmc_host host);
	197	int (select_tuning)(struct tmio_mmc_host host);
	198
	199	/* Tuning values: 1 for success, 0 for failure */
	200	DECLARE_BITMAP(taps, BITS_PER_BYTE * sizeof(long));
	201	unsigned int tap_num;
631fa73c SH	202
631fa73c SH	203	const struct tmio_mmc_dma_ops *dma_ops;
b6147490 GL	204	};
b6147490 GL	205
94b110af KM	206	struct tmio_mmc_host tmio_mmc_host_alloc(struct platform_device pdev);
	207	void tmio_mmc_host_free(struct tmio_mmc_host *host);
	208	int tmio_mmc_host_probe(struct tmio_mmc_host *host,
631fa73c SH	209	struct tmio_mmc_data *pdata,
631fa73c SH	210	const struct tmio_mmc_dma_ops *dma_ops);
b6147490 GL	211	void tmio_mmc_host_remove(struct tmio_mmc_host *host);
	212	void tmio_mmc_do_data_irq(struct tmio_mmc_host *host);
	213
	214	void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
	215	void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
8e7bfdb3	216	irqreturn_t tmio_mmc_irq(int irq, void *devid);
b6147490 GL	217
	218	static inline char tmio_mmc_kmap_atomic(struct scatterlist sg,
	219	unsigned long *flags)
	220	{
	221	local_irq_save(*flags);
482fce99	222	return kmap_atomic(sg_page(sg)) + sg->offset;
b6147490 GL	223	}
	224
	225	static inline void tmio_mmc_kunmap_atomic(struct scatterlist *sg,
	226	unsigned long flags, void virt)
	227	{
482fce99	228	kunmap_atomic(virt - sg->offset);
b6147490 GL	229	local_irq_restore(*flags);
	230	}
	231
9ade7dbf	232	#ifdef CONFIG_PM
7311bef0 GL	233	int tmio_mmc_host_runtime_suspend(struct device *dev);
7311bef0 GL	234	int tmio_mmc_host_runtime_resume(struct device *dev);
710dec95	235	#endif
7311bef0	236
a11862d3 SH	237	static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
a11862d3 SH	238	{
7445bf9e	239	return readw(host->ctl + (addr << host->bus_shift));
a11862d3 SH	240	}
	241
	242	static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
f2218db8	243	u16 *buf, int count)
a11862d3	244	{
7445bf9e	245	readsw(host->ctl + (addr << host->bus_shift), buf, count);
a11862d3 SH	246	}
a11862d3 SH	247
f2218db8 SH	248	static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host,
f2218db8 SH	249	int addr)
a11862d3	250	{
7445bf9e KM	251	return readw(host->ctl + (addr << host->bus_shift)) \|
7445bf9e KM	252	readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
a11862d3 SH	253	}
a11862d3 SH	254
8185e51f	255	static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
f2218db8	256	u32 *buf, int count)
8185e51f CB	257	{
	258	readsl(host->ctl + (addr << host->bus_shift), buf, count);
	259	}
	260
f2218db8 SH	261	static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
f2218db8 SH	262	u16 val)
a11862d3	263	{
973ed3af SH	264	/* If there is a hook and it returns non-zero then there
	265	* is an error and the write should be skipped
	266	*/
dfe9a229	267	if (host->write16_hook && host->write16_hook(host, addr))
973ed3af	268	return;
7445bf9e	269	writew(val, host->ctl + (addr << host->bus_shift));
a11862d3 SH	270	}
	271
	272	static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
f2218db8	273	u16 *buf, int count)
a11862d3	274	{
7445bf9e	275	writesw(host->ctl + (addr << host->bus_shift), buf, count);
a11862d3 SH	276	}
a11862d3 SH	277
f2218db8 SH	278	static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host,
f2218db8 SH	279	int addr, u32 val)
a11862d3	280	{
7c42dbf3	281	writew(val & 0xffff, host->ctl + (addr << host->bus_shift));
7445bf9e	282	writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
a11862d3 SH	283	}
a11862d3 SH	284
8185e51f	285	static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr,
f2218db8	286	const u32 *buf, int count)
8185e51f CB	287	{
	288	writesl(host->ctl + (addr << host->bus_shift), buf, count);
	289	}
	290
b6147490	291	#endif