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b6147490 GL |
1 | /* |
2 | * linux/drivers/mmc/host/tmio_mmc_pio.c | |
3 | * | |
4 | * Copyright (C) 2011 Guennadi Liakhovetski | |
5 | * Copyright (C) 2007 Ian Molton | |
6 | * Copyright (C) 2004 Ian Molton | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Driver for the MMC / SD / SDIO IP found in: | |
13 | * | |
14 | * TC6393XB, TC6391XB, TC6387XB, T7L66XB, ASIC3, SH-Mobile SoCs | |
15 | * | |
16 | * This driver draws mainly on scattered spec sheets, Reverse engineering | |
17 | * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit | |
18 | * support). (Further 4 bit support from a later datasheet). | |
19 | * | |
20 | * TODO: | |
21 | * Investigate using a workqueue for PIO transfers | |
22 | * Eliminate FIXMEs | |
23 | * SDIO support | |
24 | * Better Power management | |
25 | * Handle MMC errors better | |
26 | * double buffer support | |
27 | * | |
28 | */ | |
29 | ||
30 | #include <linux/delay.h> | |
31 | #include <linux/device.h> | |
32 | #include <linux/highmem.h> | |
33 | #include <linux/interrupt.h> | |
34 | #include <linux/io.h> | |
35 | #include <linux/irq.h> | |
36 | #include <linux/mfd/tmio.h> | |
37 | #include <linux/mmc/host.h> | |
0f506a96 | 38 | #include <linux/mmc/mmc.h> |
fd0ea65d | 39 | #include <linux/mmc/slot-gpio.h> |
cba179ae | 40 | #include <linux/mmc/tmio.h> |
b6147490 GL |
41 | #include <linux/module.h> |
42 | #include <linux/pagemap.h> | |
43 | #include <linux/platform_device.h> | |
c419e611 | 44 | #include <linux/pm_qos.h> |
e6ee7182 | 45 | #include <linux/pm_runtime.h> |
619b08d4 | 46 | #include <linux/regulator/consumer.h> |
b8d11962 | 47 | #include <linux/mmc/sdio.h> |
b6147490 | 48 | #include <linux/scatterlist.h> |
b6147490 | 49 | #include <linux/spinlock.h> |
e3de2be7 | 50 | #include <linux/workqueue.h> |
b6147490 GL |
51 | |
52 | #include "tmio_mmc.h" | |
53 | ||
b6147490 GL |
54 | void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i) |
55 | { | |
54680fe7 SH |
56 | host->sdcard_irq_mask &= ~(i & TMIO_MASK_IRQ); |
57 | sd_ctrl_write32(host, CTL_IRQ_MASK, host->sdcard_irq_mask); | |
b6147490 GL |
58 | } |
59 | ||
60 | void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i) | |
61 | { | |
54680fe7 SH |
62 | host->sdcard_irq_mask |= (i & TMIO_MASK_IRQ); |
63 | sd_ctrl_write32(host, CTL_IRQ_MASK, host->sdcard_irq_mask); | |
b6147490 GL |
64 | } |
65 | ||
66 | static void tmio_mmc_ack_mmc_irqs(struct tmio_mmc_host *host, u32 i) | |
67 | { | |
68 | sd_ctrl_write32(host, CTL_STATUS, ~i); | |
69 | } | |
70 | ||
71 | static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data) | |
72 | { | |
73 | host->sg_len = data->sg_len; | |
74 | host->sg_ptr = data->sg; | |
75 | host->sg_orig = data->sg; | |
76 | host->sg_off = 0; | |
77 | } | |
78 | ||
79 | static int tmio_mmc_next_sg(struct tmio_mmc_host *host) | |
80 | { | |
81 | host->sg_ptr = sg_next(host->sg_ptr); | |
82 | host->sg_off = 0; | |
83 | return --host->sg_len; | |
84 | } | |
85 | ||
86 | #ifdef CONFIG_MMC_DEBUG | |
87 | ||
88 | #define STATUS_TO_TEXT(a, status, i) \ | |
89 | do { \ | |
90 | if (status & TMIO_STAT_##a) { \ | |
91 | if (i++) \ | |
92 | printk(" | "); \ | |
93 | printk(#a); \ | |
94 | } \ | |
95 | } while (0) | |
96 | ||
97 | static void pr_debug_status(u32 status) | |
98 | { | |
99 | int i = 0; | |
a3c76eb9 | 100 | pr_debug("status: %08x = ", status); |
b6147490 GL |
101 | STATUS_TO_TEXT(CARD_REMOVE, status, i); |
102 | STATUS_TO_TEXT(CARD_INSERT, status, i); | |
103 | STATUS_TO_TEXT(SIGSTATE, status, i); | |
104 | STATUS_TO_TEXT(WRPROTECT, status, i); | |
105 | STATUS_TO_TEXT(CARD_REMOVE_A, status, i); | |
106 | STATUS_TO_TEXT(CARD_INSERT_A, status, i); | |
107 | STATUS_TO_TEXT(SIGSTATE_A, status, i); | |
108 | STATUS_TO_TEXT(CMD_IDX_ERR, status, i); | |
109 | STATUS_TO_TEXT(STOPBIT_ERR, status, i); | |
110 | STATUS_TO_TEXT(ILL_FUNC, status, i); | |
111 | STATUS_TO_TEXT(CMD_BUSY, status, i); | |
112 | STATUS_TO_TEXT(CMDRESPEND, status, i); | |
113 | STATUS_TO_TEXT(DATAEND, status, i); | |
114 | STATUS_TO_TEXT(CRCFAIL, status, i); | |
115 | STATUS_TO_TEXT(DATATIMEOUT, status, i); | |
116 | STATUS_TO_TEXT(CMDTIMEOUT, status, i); | |
117 | STATUS_TO_TEXT(RXOVERFLOW, status, i); | |
118 | STATUS_TO_TEXT(TXUNDERRUN, status, i); | |
119 | STATUS_TO_TEXT(RXRDY, status, i); | |
120 | STATUS_TO_TEXT(TXRQ, status, i); | |
121 | STATUS_TO_TEXT(ILL_ACCESS, status, i); | |
122 | printk("\n"); | |
123 | } | |
124 | ||
125 | #else | |
126 | #define pr_debug_status(s) do { } while (0) | |
127 | #endif | |
128 | ||
129 | static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) | |
130 | { | |
131 | struct tmio_mmc_host *host = mmc_priv(mmc); | |
132 | ||
7501c431 UH |
133 | if (enable && !host->sdio_irq_enabled) { |
134 | /* Keep device active while SDIO irq is enabled */ | |
135 | pm_runtime_get_sync(mmc_dev(mmc)); | |
136 | host->sdio_irq_enabled = true; | |
137 | ||
54680fe7 SH |
138 | host->sdio_irq_mask = TMIO_SDIO_MASK_ALL & |
139 | ~TMIO_SDIO_STAT_IOIRQ; | |
b6147490 | 140 | sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001); |
54680fe7 | 141 | sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask); |
7501c431 | 142 | } else if (!enable && host->sdio_irq_enabled) { |
54680fe7 SH |
143 | host->sdio_irq_mask = TMIO_SDIO_MASK_ALL; |
144 | sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask); | |
b6147490 | 145 | sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000); |
7501c431 UH |
146 | |
147 | host->sdio_irq_enabled = false; | |
0369483e UH |
148 | pm_runtime_mark_last_busy(mmc_dev(mmc)); |
149 | pm_runtime_put_autosuspend(mmc_dev(mmc)); | |
b6147490 GL |
150 | } |
151 | } | |
152 | ||
ae12d250 UH |
153 | static void tmio_mmc_set_clock(struct tmio_mmc_host *host, |
154 | unsigned int new_clock) | |
b6147490 GL |
155 | { |
156 | u32 clk = 0, clock; | |
157 | ||
158 | if (new_clock) { | |
159 | for (clock = host->mmc->f_min, clk = 0x80000080; | |
160 | new_clock >= (clock<<1); clk >>= 1) | |
161 | clock <<= 1; | |
da29fe2b SU |
162 | |
163 | /* 1/1 clock is option */ | |
164 | if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && | |
165 | ((clk >> 22) & 0x1)) | |
166 | clk |= 0xff; | |
b6147490 GL |
167 | } |
168 | ||
169 | if (host->set_clk_div) | |
170 | host->set_clk_div(host->pdev, (clk>>22) & 1); | |
171 | ||
172 | sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff); | |
619b08d4 | 173 | msleep(10); |
b6147490 GL |
174 | } |
175 | ||
176 | static void tmio_mmc_clk_stop(struct tmio_mmc_host *host) | |
177 | { | |
69d1fe18 | 178 | /* implicit BUG_ON(!res) */ |
5d60e500 | 179 | if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) { |
69d1fe18 GL |
180 | sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000); |
181 | msleep(10); | |
182 | } | |
d9b03421 | 183 | |
b6147490 GL |
184 | sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 & |
185 | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); | |
186 | msleep(10); | |
187 | } | |
188 | ||
189 | static void tmio_mmc_clk_start(struct tmio_mmc_host *host) | |
190 | { | |
b6147490 GL |
191 | sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 | |
192 | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); | |
193 | msleep(10); | |
d9b03421 | 194 | |
69d1fe18 | 195 | /* implicit BUG_ON(!res) */ |
5d60e500 | 196 | if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) { |
69d1fe18 GL |
197 | sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100); |
198 | msleep(10); | |
199 | } | |
b6147490 GL |
200 | } |
201 | ||
202 | static void tmio_mmc_reset(struct tmio_mmc_host *host) | |
203 | { | |
204 | /* FIXME - should we set stop clock reg here */ | |
205 | sd_ctrl_write16(host, CTL_RESET_SD, 0x0000); | |
69d1fe18 | 206 | /* implicit BUG_ON(!res) */ |
5d60e500 | 207 | if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) |
69d1fe18 | 208 | sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000); |
b6147490 GL |
209 | msleep(10); |
210 | sd_ctrl_write16(host, CTL_RESET_SD, 0x0001); | |
5d60e500 | 211 | if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) |
69d1fe18 | 212 | sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001); |
b6147490 GL |
213 | msleep(10); |
214 | } | |
215 | ||
216 | static void tmio_mmc_reset_work(struct work_struct *work) | |
217 | { | |
218 | struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host, | |
219 | delayed_reset_work.work); | |
220 | struct mmc_request *mrq; | |
221 | unsigned long flags; | |
222 | ||
223 | spin_lock_irqsave(&host->lock, flags); | |
224 | mrq = host->mrq; | |
225 | ||
df3ef2d3 GL |
226 | /* |
227 | * is request already finished? Since we use a non-blocking | |
228 | * cancel_delayed_work(), it can happen, that a .set_ios() call preempts | |
229 | * us, so, have to check for IS_ERR(host->mrq) | |
230 | */ | |
231 | if (IS_ERR_OR_NULL(mrq) | |
b6147490 GL |
232 | || time_is_after_jiffies(host->last_req_ts + |
233 | msecs_to_jiffies(2000))) { | |
234 | spin_unlock_irqrestore(&host->lock, flags); | |
235 | return; | |
236 | } | |
237 | ||
238 | dev_warn(&host->pdev->dev, | |
239 | "timeout waiting for hardware interrupt (CMD%u)\n", | |
240 | mrq->cmd->opcode); | |
241 | ||
242 | if (host->data) | |
243 | host->data->error = -ETIMEDOUT; | |
244 | else if (host->cmd) | |
245 | host->cmd->error = -ETIMEDOUT; | |
246 | else | |
247 | mrq->cmd->error = -ETIMEDOUT; | |
248 | ||
249 | host->cmd = NULL; | |
250 | host->data = NULL; | |
b6147490 GL |
251 | host->force_pio = false; |
252 | ||
253 | spin_unlock_irqrestore(&host->lock, flags); | |
254 | ||
255 | tmio_mmc_reset(host); | |
256 | ||
df3ef2d3 GL |
257 | /* Ready for new calls */ |
258 | host->mrq = NULL; | |
259 | ||
e3de2be7 | 260 | tmio_mmc_abort_dma(host); |
b6147490 | 261 | mmc_request_done(host->mmc, mrq); |
0369483e UH |
262 | |
263 | pm_runtime_mark_last_busy(mmc_dev(host->mmc)); | |
264 | pm_runtime_put_autosuspend(mmc_dev(host->mmc)); | |
b6147490 GL |
265 | } |
266 | ||
df3ef2d3 | 267 | /* called with host->lock held, interrupts disabled */ |
b6147490 GL |
268 | static void tmio_mmc_finish_request(struct tmio_mmc_host *host) |
269 | { | |
b9269fdd GL |
270 | struct mmc_request *mrq; |
271 | unsigned long flags; | |
b6147490 | 272 | |
b9269fdd GL |
273 | spin_lock_irqsave(&host->lock, flags); |
274 | ||
275 | mrq = host->mrq; | |
276 | if (IS_ERR_OR_NULL(mrq)) { | |
277 | spin_unlock_irqrestore(&host->lock, flags); | |
b6147490 | 278 | return; |
b9269fdd | 279 | } |
b6147490 | 280 | |
b6147490 GL |
281 | host->cmd = NULL; |
282 | host->data = NULL; | |
283 | host->force_pio = false; | |
284 | ||
285 | cancel_delayed_work(&host->delayed_reset_work); | |
286 | ||
df3ef2d3 | 287 | host->mrq = NULL; |
b9269fdd | 288 | spin_unlock_irqrestore(&host->lock, flags); |
df3ef2d3 | 289 | |
e3de2be7 GL |
290 | if (mrq->cmd->error || (mrq->data && mrq->data->error)) |
291 | tmio_mmc_abort_dma(host); | |
292 | ||
b6147490 | 293 | mmc_request_done(host->mmc, mrq); |
0369483e UH |
294 | |
295 | pm_runtime_mark_last_busy(mmc_dev(host->mmc)); | |
296 | pm_runtime_put_autosuspend(mmc_dev(host->mmc)); | |
b6147490 GL |
297 | } |
298 | ||
b9269fdd GL |
299 | static void tmio_mmc_done_work(struct work_struct *work) |
300 | { | |
301 | struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host, | |
302 | done); | |
303 | tmio_mmc_finish_request(host); | |
304 | } | |
305 | ||
b6147490 GL |
306 | /* These are the bitmasks the tmio chip requires to implement the MMC response |
307 | * types. Note that R1 and R6 are the same in this scheme. */ | |
308 | #define APP_CMD 0x0040 | |
309 | #define RESP_NONE 0x0300 | |
310 | #define RESP_R1 0x0400 | |
311 | #define RESP_R1B 0x0500 | |
312 | #define RESP_R2 0x0600 | |
313 | #define RESP_R3 0x0700 | |
314 | #define DATA_PRESENT 0x0800 | |
315 | #define TRANSFER_READ 0x1000 | |
316 | #define TRANSFER_MULTI 0x2000 | |
317 | #define SECURITY_CMD 0x4000 | |
b8d11962 | 318 | #define NO_CMD12_ISSUE 0x4000 /* TMIO_MMC_HAVE_CMD12_CTRL */ |
b6147490 GL |
319 | |
320 | static int tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd) | |
321 | { | |
322 | struct mmc_data *data = host->data; | |
323 | int c = cmd->opcode; | |
e23cd53c | 324 | u32 irq_mask = TMIO_MASK_CMD; |
b6147490 | 325 | |
0f506a96 GL |
326 | /* CMD12 is handled by hardware */ |
327 | if (cmd->opcode == MMC_STOP_TRANSMISSION && !cmd->arg) { | |
b6147490 GL |
328 | sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001); |
329 | return 0; | |
330 | } | |
331 | ||
332 | switch (mmc_resp_type(cmd)) { | |
333 | case MMC_RSP_NONE: c |= RESP_NONE; break; | |
334 | case MMC_RSP_R1: c |= RESP_R1; break; | |
335 | case MMC_RSP_R1B: c |= RESP_R1B; break; | |
336 | case MMC_RSP_R2: c |= RESP_R2; break; | |
337 | case MMC_RSP_R3: c |= RESP_R3; break; | |
338 | default: | |
339 | pr_debug("Unknown response type %d\n", mmc_resp_type(cmd)); | |
340 | return -EINVAL; | |
341 | } | |
342 | ||
343 | host->cmd = cmd; | |
344 | ||
345 | /* FIXME - this seems to be ok commented out but the spec suggest this bit | |
346 | * should be set when issuing app commands. | |
347 | * if(cmd->flags & MMC_FLAG_ACMD) | |
348 | * c |= APP_CMD; | |
349 | */ | |
350 | if (data) { | |
351 | c |= DATA_PRESENT; | |
352 | if (data->blocks > 1) { | |
353 | sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100); | |
354 | c |= TRANSFER_MULTI; | |
b8d11962 SU |
355 | |
356 | /* | |
357 | * Disable auto CMD12 at IO_RW_EXTENDED when | |
358 | * multiple block transfer | |
359 | */ | |
360 | if ((host->pdata->flags & TMIO_MMC_HAVE_CMD12_CTRL) && | |
361 | (cmd->opcode == SD_IO_RW_EXTENDED)) | |
362 | c |= NO_CMD12_ISSUE; | |
b6147490 GL |
363 | } |
364 | if (data->flags & MMC_DATA_READ) | |
365 | c |= TRANSFER_READ; | |
366 | } | |
367 | ||
e23cd53c GL |
368 | if (!host->native_hotplug) |
369 | irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT); | |
370 | tmio_mmc_enable_mmc_irqs(host, irq_mask); | |
b6147490 GL |
371 | |
372 | /* Fire off the command */ | |
373 | sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg); | |
374 | sd_ctrl_write16(host, CTL_SD_CMD, c); | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
b9bd7ff8 KM |
379 | static void tmio_mmc_transfer_data(struct tmio_mmc_host *host, |
380 | unsigned short *buf, | |
381 | unsigned int count) | |
382 | { | |
383 | int is_read = host->data->flags & MMC_DATA_READ; | |
384 | u8 *buf8; | |
385 | ||
386 | /* | |
387 | * Transfer the data | |
388 | */ | |
389 | if (is_read) | |
390 | sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1); | |
391 | else | |
392 | sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1); | |
393 | ||
394 | /* if count was even number */ | |
395 | if (!(count & 0x1)) | |
396 | return; | |
397 | ||
398 | /* if count was odd number */ | |
399 | buf8 = (u8 *)(buf + (count >> 1)); | |
400 | ||
401 | /* | |
402 | * FIXME | |
403 | * | |
404 | * driver and this function are assuming that | |
405 | * it is used as little endian | |
406 | */ | |
407 | if (is_read) | |
408 | *buf8 = sd_ctrl_read16(host, CTL_SD_DATA_PORT) & 0xff; | |
409 | else | |
410 | sd_ctrl_write16(host, CTL_SD_DATA_PORT, *buf8); | |
411 | } | |
412 | ||
b6147490 GL |
413 | /* |
414 | * This chip always returns (at least?) as much data as you ask for. | |
415 | * I'm unsure what happens if you ask for less than a block. This should be | |
25985edc | 416 | * looked into to ensure that a funny length read doesn't hose the controller. |
b6147490 GL |
417 | */ |
418 | static void tmio_mmc_pio_irq(struct tmio_mmc_host *host) | |
419 | { | |
420 | struct mmc_data *data = host->data; | |
421 | void *sg_virt; | |
422 | unsigned short *buf; | |
423 | unsigned int count; | |
424 | unsigned long flags; | |
425 | ||
426 | if ((host->chan_tx || host->chan_rx) && !host->force_pio) { | |
427 | pr_err("PIO IRQ in DMA mode!\n"); | |
428 | return; | |
429 | } else if (!data) { | |
430 | pr_debug("Spurious PIO IRQ\n"); | |
431 | return; | |
432 | } | |
433 | ||
434 | sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags); | |
435 | buf = (unsigned short *)(sg_virt + host->sg_off); | |
436 | ||
437 | count = host->sg_ptr->length - host->sg_off; | |
438 | if (count > data->blksz) | |
439 | count = data->blksz; | |
440 | ||
441 | pr_debug("count: %08x offset: %08x flags %08x\n", | |
442 | count, host->sg_off, data->flags); | |
443 | ||
444 | /* Transfer the data */ | |
b9bd7ff8 | 445 | tmio_mmc_transfer_data(host, buf, count); |
b6147490 GL |
446 | |
447 | host->sg_off += count; | |
448 | ||
449 | tmio_mmc_kunmap_atomic(host->sg_ptr, &flags, sg_virt); | |
450 | ||
451 | if (host->sg_off == host->sg_ptr->length) | |
452 | tmio_mmc_next_sg(host); | |
453 | ||
454 | return; | |
455 | } | |
456 | ||
457 | static void tmio_mmc_check_bounce_buffer(struct tmio_mmc_host *host) | |
458 | { | |
459 | if (host->sg_ptr == &host->bounce_sg) { | |
460 | unsigned long flags; | |
461 | void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags); | |
462 | memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length); | |
463 | tmio_mmc_kunmap_atomic(host->sg_orig, &flags, sg_vaddr); | |
464 | } | |
465 | } | |
466 | ||
467 | /* needs to be called with host->lock held */ | |
468 | void tmio_mmc_do_data_irq(struct tmio_mmc_host *host) | |
469 | { | |
470 | struct mmc_data *data = host->data; | |
471 | struct mmc_command *stop; | |
472 | ||
473 | host->data = NULL; | |
474 | ||
475 | if (!data) { | |
476 | dev_warn(&host->pdev->dev, "Spurious data end IRQ\n"); | |
477 | return; | |
478 | } | |
479 | stop = data->stop; | |
480 | ||
481 | /* FIXME - return correct transfer count on errors */ | |
482 | if (!data->error) | |
483 | data->bytes_xfered = data->blocks * data->blksz; | |
484 | else | |
485 | data->bytes_xfered = 0; | |
486 | ||
487 | pr_debug("Completed data request\n"); | |
488 | ||
489 | /* | |
490 | * FIXME: other drivers allow an optional stop command of any given type | |
491 | * which we dont do, as the chip can auto generate them. | |
492 | * Perhaps we can be smarter about when to use auto CMD12 and | |
493 | * only issue the auto request when we know this is the desired | |
494 | * stop command, allowing fallback to the stop command the | |
495 | * upper layers expect. For now, we do what works. | |
496 | */ | |
497 | ||
498 | if (data->flags & MMC_DATA_READ) { | |
499 | if (host->chan_rx && !host->force_pio) | |
500 | tmio_mmc_check_bounce_buffer(host); | |
501 | dev_dbg(&host->pdev->dev, "Complete Rx request %p\n", | |
502 | host->mrq); | |
503 | } else { | |
504 | dev_dbg(&host->pdev->dev, "Complete Tx request %p\n", | |
505 | host->mrq); | |
506 | } | |
507 | ||
508 | if (stop) { | |
0f506a96 | 509 | if (stop->opcode == MMC_STOP_TRANSMISSION && !stop->arg) |
b6147490 GL |
510 | sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000); |
511 | else | |
512 | BUG(); | |
513 | } | |
514 | ||
b9269fdd | 515 | schedule_work(&host->done); |
b6147490 GL |
516 | } |
517 | ||
518 | static void tmio_mmc_data_irq(struct tmio_mmc_host *host) | |
519 | { | |
520 | struct mmc_data *data; | |
521 | spin_lock(&host->lock); | |
522 | data = host->data; | |
523 | ||
524 | if (!data) | |
525 | goto out; | |
526 | ||
527 | if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) { | |
81e888da SU |
528 | u32 status = sd_ctrl_read32(host, CTL_STATUS); |
529 | bool done = false; | |
530 | ||
b6147490 GL |
531 | /* |
532 | * Has all data been written out yet? Testing on SuperH showed, | |
533 | * that in most cases the first interrupt comes already with the | |
534 | * BUSY status bit clear, but on some operations, like mount or | |
535 | * in the beginning of a write / sync / umount, there is one | |
536 | * DATAEND interrupt with the BUSY bit set, in this cases | |
537 | * waiting for one more interrupt fixes the problem. | |
538 | */ | |
81e888da SU |
539 | if (host->pdata->flags & TMIO_MMC_HAS_IDLE_WAIT) { |
540 | if (status & TMIO_STAT_ILL_FUNC) | |
541 | done = true; | |
542 | } else { | |
543 | if (!(status & TMIO_STAT_CMD_BUSY)) | |
544 | done = true; | |
545 | } | |
546 | ||
547 | if (done) { | |
b6147490 GL |
548 | tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND); |
549 | tasklet_schedule(&host->dma_complete); | |
550 | } | |
551 | } else if (host->chan_rx && (data->flags & MMC_DATA_READ) && !host->force_pio) { | |
552 | tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND); | |
553 | tasklet_schedule(&host->dma_complete); | |
554 | } else { | |
555 | tmio_mmc_do_data_irq(host); | |
556 | tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP); | |
557 | } | |
558 | out: | |
559 | spin_unlock(&host->lock); | |
560 | } | |
561 | ||
562 | static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host, | |
563 | unsigned int stat) | |
564 | { | |
565 | struct mmc_command *cmd = host->cmd; | |
566 | int i, addr; | |
567 | ||
568 | spin_lock(&host->lock); | |
569 | ||
570 | if (!host->cmd) { | |
571 | pr_debug("Spurious CMD irq\n"); | |
572 | goto out; | |
573 | } | |
574 | ||
575 | host->cmd = NULL; | |
576 | ||
577 | /* This controller is sicker than the PXA one. Not only do we need to | |
578 | * drop the top 8 bits of the first response word, we also need to | |
579 | * modify the order of the response for short response command types. | |
580 | */ | |
581 | ||
582 | for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4) | |
583 | cmd->resp[i] = sd_ctrl_read32(host, addr); | |
584 | ||
585 | if (cmd->flags & MMC_RSP_136) { | |
586 | cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24); | |
587 | cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24); | |
588 | cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24); | |
589 | cmd->resp[3] <<= 8; | |
590 | } else if (cmd->flags & MMC_RSP_R3) { | |
591 | cmd->resp[0] = cmd->resp[3]; | |
592 | } | |
593 | ||
594 | if (stat & TMIO_STAT_CMDTIMEOUT) | |
595 | cmd->error = -ETIMEDOUT; | |
596 | else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC) | |
597 | cmd->error = -EILSEQ; | |
598 | ||
599 | /* If there is data to handle we enable data IRQs here, and | |
600 | * we will ultimatley finish the request in the data_end handler. | |
601 | * If theres no data or we encountered an error, finish now. | |
602 | */ | |
603 | if (host->data && !cmd->error) { | |
604 | if (host->data->flags & MMC_DATA_READ) { | |
605 | if (host->force_pio || !host->chan_rx) | |
606 | tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_READOP); | |
607 | else | |
608 | tasklet_schedule(&host->dma_issue); | |
609 | } else { | |
610 | if (host->force_pio || !host->chan_tx) | |
611 | tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_WRITEOP); | |
612 | else | |
613 | tasklet_schedule(&host->dma_issue); | |
614 | } | |
615 | } else { | |
b9269fdd | 616 | schedule_work(&host->done); |
b6147490 GL |
617 | } |
618 | ||
619 | out: | |
620 | spin_unlock(&host->lock); | |
621 | } | |
622 | ||
7729c7a2 SH |
623 | static void tmio_mmc_card_irq_status(struct tmio_mmc_host *host, |
624 | int *ireg, int *status) | |
b6147490 | 625 | { |
7729c7a2 SH |
626 | *status = sd_ctrl_read32(host, CTL_STATUS); |
627 | *ireg = *status & TMIO_MASK_IRQ & ~host->sdcard_irq_mask; | |
b6147490 | 628 | |
7729c7a2 SH |
629 | pr_debug_status(*status); |
630 | pr_debug_status(*ireg); | |
f83bfa75 SU |
631 | |
632 | /* Clear the status except the interrupt status */ | |
633 | sd_ctrl_write32(host, CTL_STATUS, TMIO_MASK_IRQ); | |
7729c7a2 | 634 | } |
b6147490 | 635 | |
7729c7a2 SH |
636 | static bool __tmio_mmc_card_detect_irq(struct tmio_mmc_host *host, |
637 | int ireg, int status) | |
638 | { | |
639 | struct mmc_host *mmc = host->mmc; | |
b6147490 | 640 | |
e312eb1e PP |
641 | /* Card insert / remove attempts */ |
642 | if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) { | |
643 | tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT | | |
644 | TMIO_STAT_CARD_REMOVE); | |
71d111cd GL |
645 | if ((((ireg & TMIO_STAT_CARD_REMOVE) && mmc->card) || |
646 | ((ireg & TMIO_STAT_CARD_INSERT) && !mmc->card)) && | |
647 | !work_pending(&mmc->detect.work)) | |
b9269fdd | 648 | mmc_detect_change(host->mmc, msecs_to_jiffies(100)); |
7729c7a2 | 649 | return true; |
b6147490 GL |
650 | } |
651 | ||
7729c7a2 SH |
652 | return false; |
653 | } | |
654 | ||
655 | irqreturn_t tmio_mmc_card_detect_irq(int irq, void *devid) | |
656 | { | |
657 | unsigned int ireg, status; | |
658 | struct tmio_mmc_host *host = devid; | |
b6147490 | 659 | |
7729c7a2 SH |
660 | tmio_mmc_card_irq_status(host, &ireg, &status); |
661 | __tmio_mmc_card_detect_irq(host, ireg, status); | |
662 | ||
663 | return IRQ_HANDLED; | |
664 | } | |
665 | EXPORT_SYMBOL(tmio_mmc_card_detect_irq); | |
666 | ||
667 | static bool __tmio_mmc_sdcard_irq(struct tmio_mmc_host *host, | |
668 | int ireg, int status) | |
669 | { | |
e312eb1e PP |
670 | /* Command completion */ |
671 | if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) { | |
672 | tmio_mmc_ack_mmc_irqs(host, | |
673 | TMIO_STAT_CMDRESPEND | | |
674 | TMIO_STAT_CMDTIMEOUT); | |
675 | tmio_mmc_cmd_irq(host, status); | |
7729c7a2 | 676 | return true; |
e312eb1e | 677 | } |
b6147490 | 678 | |
e312eb1e PP |
679 | /* Data transfer */ |
680 | if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) { | |
681 | tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ); | |
682 | tmio_mmc_pio_irq(host); | |
7729c7a2 | 683 | return true; |
e312eb1e | 684 | } |
b6147490 | 685 | |
e312eb1e PP |
686 | /* Data transfer completion */ |
687 | if (ireg & TMIO_STAT_DATAEND) { | |
688 | tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_DATAEND); | |
689 | tmio_mmc_data_irq(host); | |
7729c7a2 | 690 | return true; |
b6147490 | 691 | } |
e312eb1e | 692 | |
7729c7a2 SH |
693 | return false; |
694 | } | |
695 | ||
696 | irqreturn_t tmio_mmc_sdcard_irq(int irq, void *devid) | |
697 | { | |
698 | unsigned int ireg, status; | |
699 | struct tmio_mmc_host *host = devid; | |
700 | ||
701 | tmio_mmc_card_irq_status(host, &ireg, &status); | |
702 | __tmio_mmc_sdcard_irq(host, ireg, status); | |
703 | ||
704 | return IRQ_HANDLED; | |
705 | } | |
706 | EXPORT_SYMBOL(tmio_mmc_sdcard_irq); | |
707 | ||
708 | irqreturn_t tmio_mmc_sdio_irq(int irq, void *devid) | |
709 | { | |
710 | struct tmio_mmc_host *host = devid; | |
711 | struct mmc_host *mmc = host->mmc; | |
712 | struct tmio_mmc_data *pdata = host->pdata; | |
713 | unsigned int ireg, status; | |
6b98757e | 714 | unsigned int sdio_status; |
7729c7a2 SH |
715 | |
716 | if (!(pdata->flags & TMIO_MMC_SDIO_IRQ)) | |
717 | return IRQ_HANDLED; | |
718 | ||
719 | status = sd_ctrl_read16(host, CTL_SDIO_STATUS); | |
720 | ireg = status & TMIO_SDIO_MASK_ALL & ~host->sdcard_irq_mask; | |
721 | ||
6b98757e SU |
722 | sdio_status = status & ~TMIO_SDIO_MASK_ALL; |
723 | if (pdata->flags & TMIO_MMC_SDIO_STATUS_QUIRK) | |
724 | sdio_status |= 6; | |
725 | ||
726 | sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status); | |
7729c7a2 SH |
727 | |
728 | if (mmc->caps & MMC_CAP_SDIO_IRQ && ireg & TMIO_SDIO_STAT_IOIRQ) | |
729 | mmc_signal_sdio_irq(mmc); | |
730 | ||
731 | return IRQ_HANDLED; | |
732 | } | |
733 | EXPORT_SYMBOL(tmio_mmc_sdio_irq); | |
734 | ||
735 | irqreturn_t tmio_mmc_irq(int irq, void *devid) | |
736 | { | |
737 | struct tmio_mmc_host *host = devid; | |
738 | unsigned int ireg, status; | |
739 | ||
740 | pr_debug("MMC IRQ begin\n"); | |
741 | ||
742 | tmio_mmc_card_irq_status(host, &ireg, &status); | |
743 | if (__tmio_mmc_card_detect_irq(host, ireg, status)) | |
744 | return IRQ_HANDLED; | |
745 | if (__tmio_mmc_sdcard_irq(host, ireg, status)) | |
746 | return IRQ_HANDLED; | |
747 | ||
748 | tmio_mmc_sdio_irq(irq, devid); | |
b6147490 | 749 | |
b6147490 GL |
750 | return IRQ_HANDLED; |
751 | } | |
8e7bfdb3 | 752 | EXPORT_SYMBOL(tmio_mmc_irq); |
b6147490 GL |
753 | |
754 | static int tmio_mmc_start_data(struct tmio_mmc_host *host, | |
755 | struct mmc_data *data) | |
756 | { | |
757 | struct tmio_mmc_data *pdata = host->pdata; | |
758 | ||
759 | pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n", | |
760 | data->blksz, data->blocks); | |
761 | ||
762 | /* Some hardware cannot perform 2 byte requests in 4 bit mode */ | |
763 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) { | |
764 | int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES; | |
765 | ||
766 | if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) { | |
767 | pr_err("%s: %d byte block unsupported in 4 bit mode\n", | |
768 | mmc_hostname(host->mmc), data->blksz); | |
769 | return -EINVAL; | |
770 | } | |
771 | } | |
772 | ||
773 | tmio_mmc_init_sg(host, data); | |
774 | host->data = data; | |
775 | ||
776 | /* Set transfer length / blocksize */ | |
777 | sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz); | |
778 | sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks); | |
779 | ||
780 | tmio_mmc_start_dma(host, data); | |
781 | ||
782 | return 0; | |
783 | } | |
784 | ||
785 | /* Process requests from the MMC layer */ | |
786 | static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
787 | { | |
788 | struct tmio_mmc_host *host = mmc_priv(mmc); | |
df3ef2d3 | 789 | unsigned long flags; |
b6147490 GL |
790 | int ret; |
791 | ||
df3ef2d3 GL |
792 | spin_lock_irqsave(&host->lock, flags); |
793 | ||
794 | if (host->mrq) { | |
b6147490 | 795 | pr_debug("request not null\n"); |
df3ef2d3 GL |
796 | if (IS_ERR(host->mrq)) { |
797 | spin_unlock_irqrestore(&host->lock, flags); | |
798 | mrq->cmd->error = -EAGAIN; | |
799 | mmc_request_done(mmc, mrq); | |
800 | return; | |
801 | } | |
802 | } | |
b6147490 GL |
803 | |
804 | host->last_req_ts = jiffies; | |
805 | wmb(); | |
806 | host->mrq = mrq; | |
807 | ||
df3ef2d3 GL |
808 | spin_unlock_irqrestore(&host->lock, flags); |
809 | ||
0369483e UH |
810 | pm_runtime_get_sync(mmc_dev(mmc)); |
811 | ||
b6147490 GL |
812 | if (mrq->data) { |
813 | ret = tmio_mmc_start_data(host, mrq->data); | |
814 | if (ret) | |
815 | goto fail; | |
816 | } | |
817 | ||
818 | ret = tmio_mmc_start_command(host, mrq->cmd); | |
819 | if (!ret) { | |
820 | schedule_delayed_work(&host->delayed_reset_work, | |
821 | msecs_to_jiffies(2000)); | |
822 | return; | |
823 | } | |
824 | ||
825 | fail: | |
b6147490 | 826 | host->force_pio = false; |
df3ef2d3 | 827 | host->mrq = NULL; |
b6147490 GL |
828 | mrq->cmd->error = ret; |
829 | mmc_request_done(mmc, mrq); | |
0369483e UH |
830 | |
831 | pm_runtime_mark_last_busy(mmc_dev(mmc)); | |
832 | pm_runtime_put_autosuspend(mmc_dev(mmc)); | |
b6147490 GL |
833 | } |
834 | ||
ae12d250 | 835 | static int tmio_mmc_clk_update(struct tmio_mmc_host *host) |
8c102a96 | 836 | { |
ae12d250 | 837 | struct mmc_host *mmc = host->mmc; |
8c102a96 GL |
838 | int ret; |
839 | ||
4fe2ec57 | 840 | if (!host->clk_enable) |
8c102a96 GL |
841 | return -ENOTSUPP; |
842 | ||
4fe2ec57 | 843 | ret = host->clk_enable(host->pdev, &mmc->f_max); |
8c102a96 GL |
844 | if (!ret) |
845 | mmc->f_min = mmc->f_max / 512; | |
846 | ||
847 | return ret; | |
848 | } | |
849 | ||
619b08d4 | 850 | static void tmio_mmc_power_on(struct tmio_mmc_host *host, unsigned short vdd) |
b958a67c GL |
851 | { |
852 | struct mmc_host *mmc = host->mmc; | |
619b08d4 GL |
853 | int ret = 0; |
854 | ||
855 | /* .set_ios() is returning void, so, no chance to report an error */ | |
b958a67c | 856 | |
9d731e75 CB |
857 | if (host->set_pwr) |
858 | host->set_pwr(host->pdev, 1); | |
859 | ||
619b08d4 GL |
860 | if (!IS_ERR(mmc->supply.vmmc)) { |
861 | ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); | |
862 | /* | |
863 | * Attention: empiric value. With a b43 WiFi SDIO card this | |
864 | * delay proved necessary for reliable card-insertion probing. | |
865 | * 100us were not enough. Is this the same 140us delay, as in | |
866 | * tmio_mmc_set_ios()? | |
867 | */ | |
868 | udelay(200); | |
869 | } | |
870 | /* | |
871 | * It seems, VccQ should be switched on after Vcc, this is also what the | |
872 | * omap_hsmmc.c driver does. | |
873 | */ | |
874 | if (!IS_ERR(mmc->supply.vqmmc) && !ret) { | |
6d1d6b47 | 875 | ret = regulator_enable(mmc->supply.vqmmc); |
619b08d4 GL |
876 | udelay(200); |
877 | } | |
6d1d6b47 GL |
878 | |
879 | if (ret < 0) | |
880 | dev_dbg(&host->pdev->dev, "Regulators failed to power up: %d\n", | |
881 | ret); | |
619b08d4 GL |
882 | } |
883 | ||
884 | static void tmio_mmc_power_off(struct tmio_mmc_host *host) | |
885 | { | |
886 | struct mmc_host *mmc = host->mmc; | |
887 | ||
888 | if (!IS_ERR(mmc->supply.vqmmc)) | |
889 | regulator_disable(mmc->supply.vqmmc); | |
890 | ||
b958a67c | 891 | if (!IS_ERR(mmc->supply.vmmc)) |
619b08d4 | 892 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); |
9d731e75 CB |
893 | |
894 | if (host->set_pwr) | |
895 | host->set_pwr(host->pdev, 0); | |
b958a67c GL |
896 | } |
897 | ||
9ae4ed7d UH |
898 | static void tmio_mmc_set_bus_width(struct tmio_mmc_host *host, |
899 | unsigned char bus_width) | |
900 | { | |
901 | switch (bus_width) { | |
902 | case MMC_BUS_WIDTH_1: | |
903 | sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0); | |
904 | break; | |
905 | case MMC_BUS_WIDTH_4: | |
906 | sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0); | |
907 | break; | |
908 | } | |
909 | } | |
910 | ||
b6147490 GL |
911 | /* Set MMC clock / power. |
912 | * Note: This controller uses a simple divider scheme therefore it cannot | |
913 | * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as | |
914 | * MMC wont run that fast, it has to be clocked at 12MHz which is the next | |
915 | * slowest setting. | |
916 | */ | |
917 | static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
918 | { | |
919 | struct tmio_mmc_host *host = mmc_priv(mmc); | |
4932bd64 | 920 | struct device *dev = &host->pdev->dev; |
df3ef2d3 GL |
921 | unsigned long flags; |
922 | ||
0369483e UH |
923 | pm_runtime_get_sync(mmc_dev(mmc)); |
924 | ||
b9269fdd GL |
925 | mutex_lock(&host->ios_lock); |
926 | ||
df3ef2d3 GL |
927 | spin_lock_irqsave(&host->lock, flags); |
928 | if (host->mrq) { | |
929 | if (IS_ERR(host->mrq)) { | |
4932bd64 | 930 | dev_dbg(dev, |
df3ef2d3 GL |
931 | "%s.%d: concurrent .set_ios(), clk %u, mode %u\n", |
932 | current->comm, task_pid_nr(current), | |
933 | ios->clock, ios->power_mode); | |
934 | host->mrq = ERR_PTR(-EINTR); | |
935 | } else { | |
4932bd64 | 936 | dev_dbg(dev, |
df3ef2d3 GL |
937 | "%s.%d: CMD%u active since %lu, now %lu!\n", |
938 | current->comm, task_pid_nr(current), | |
939 | host->mrq->cmd->opcode, host->last_req_ts, jiffies); | |
940 | } | |
941 | spin_unlock_irqrestore(&host->lock, flags); | |
b9269fdd GL |
942 | |
943 | mutex_unlock(&host->ios_lock); | |
df3ef2d3 GL |
944 | return; |
945 | } | |
946 | ||
947 | host->mrq = ERR_PTR(-EBUSY); | |
948 | ||
949 | spin_unlock_irqrestore(&host->lock, flags); | |
b6147490 | 950 | |
3b292bb0 UH |
951 | switch (ios->power_mode) { |
952 | case MMC_POWER_OFF: | |
953 | tmio_mmc_power_off(host); | |
954 | tmio_mmc_clk_stop(host); | |
955 | break; | |
956 | case MMC_POWER_UP: | |
71d111cd | 957 | tmio_mmc_set_clock(host, ios->clock); |
3b292bb0 | 958 | tmio_mmc_power_on(host, ios->vdd); |
5fd01579 | 959 | tmio_mmc_clk_start(host); |
9ae4ed7d | 960 | tmio_mmc_set_bus_width(host, ios->bus_width); |
3b292bb0 UH |
961 | break; |
962 | case MMC_POWER_ON: | |
963 | tmio_mmc_set_clock(host, ios->clock); | |
964 | tmio_mmc_clk_start(host); | |
965 | tmio_mmc_set_bus_width(host, ios->bus_width); | |
966 | break; | |
967 | } | |
b6147490 GL |
968 | |
969 | /* Let things settle. delay taken from winCE driver */ | |
970 | udelay(140); | |
df3ef2d3 GL |
971 | if (PTR_ERR(host->mrq) == -EINTR) |
972 | dev_dbg(&host->pdev->dev, | |
973 | "%s.%d: IOS interrupted: clk %u, mode %u", | |
974 | current->comm, task_pid_nr(current), | |
975 | ios->clock, ios->power_mode); | |
976 | host->mrq = NULL; | |
b9269fdd | 977 | |
ae12d250 UH |
978 | host->clk_cache = ios->clock; |
979 | ||
b9269fdd | 980 | mutex_unlock(&host->ios_lock); |
0369483e UH |
981 | |
982 | pm_runtime_mark_last_busy(mmc_dev(mmc)); | |
983 | pm_runtime_put_autosuspend(mmc_dev(mmc)); | |
b6147490 GL |
984 | } |
985 | ||
986 | static int tmio_mmc_get_ro(struct mmc_host *mmc) | |
987 | { | |
988 | struct tmio_mmc_host *host = mmc_priv(mmc); | |
989 | struct tmio_mmc_data *pdata = host->pdata; | |
3071cafb GL |
990 | int ret = mmc_gpio_get_ro(mmc); |
991 | if (ret >= 0) | |
992 | return ret; | |
b6147490 | 993 | |
0369483e UH |
994 | pm_runtime_get_sync(mmc_dev(mmc)); |
995 | ret = !((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) || | |
996 | (sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT)); | |
997 | pm_runtime_mark_last_busy(mmc_dev(mmc)); | |
998 | pm_runtime_put_autosuspend(mmc_dev(mmc)); | |
999 | ||
1000 | return ret; | |
b6147490 GL |
1001 | } |
1002 | ||
bbf0208d KM |
1003 | static int tmio_multi_io_quirk(struct mmc_card *card, |
1004 | unsigned int direction, int blk_size) | |
1005 | { | |
1006 | struct tmio_mmc_host *host = mmc_priv(card->host); | |
bbf0208d | 1007 | |
85c02ddd KM |
1008 | if (host->multi_io_quirk) |
1009 | return host->multi_io_quirk(card, direction, blk_size); | |
bbf0208d KM |
1010 | |
1011 | return blk_size; | |
1012 | } | |
1013 | ||
b6147490 GL |
1014 | static const struct mmc_host_ops tmio_mmc_ops = { |
1015 | .request = tmio_mmc_request, | |
1016 | .set_ios = tmio_mmc_set_ios, | |
1017 | .get_ro = tmio_mmc_get_ro, | |
2b63b341 | 1018 | .get_cd = mmc_gpio_get_cd, |
b6147490 | 1019 | .enable_sdio_irq = tmio_mmc_enable_sdio_irq, |
bbf0208d | 1020 | .multi_io_quirk = tmio_multi_io_quirk, |
b6147490 GL |
1021 | }; |
1022 | ||
05fae4a7 | 1023 | static int tmio_mmc_init_ocr(struct tmio_mmc_host *host) |
b958a67c GL |
1024 | { |
1025 | struct tmio_mmc_data *pdata = host->pdata; | |
1026 | struct mmc_host *mmc = host->mmc; | |
1027 | ||
1028 | mmc_regulator_get_supply(mmc); | |
1029 | ||
05fae4a7 | 1030 | /* use ocr_mask if no regulator */ |
b958a67c | 1031 | if (!mmc->ocr_avail) |
05fae4a7 KM |
1032 | mmc->ocr_avail = pdata->ocr_mask; |
1033 | ||
1034 | /* | |
1035 | * try again. | |
1036 | * There is possibility that regulator has not been probed | |
1037 | */ | |
1038 | if (!mmc->ocr_avail) | |
1039 | return -EPROBE_DEFER; | |
1040 | ||
1041 | return 0; | |
b958a67c GL |
1042 | } |
1043 | ||
5a00a971 GL |
1044 | static void tmio_mmc_of_parse(struct platform_device *pdev, |
1045 | struct tmio_mmc_data *pdata) | |
1046 | { | |
1047 | const struct device_node *np = pdev->dev.of_node; | |
1048 | if (!np) | |
1049 | return; | |
1050 | ||
1051 | if (of_get_property(np, "toshiba,mmc-wrprotect-disable", NULL)) | |
1052 | pdata->flags |= TMIO_MMC_WRPROTECT_DISABLE; | |
1053 | } | |
1054 | ||
94b110af KM |
1055 | struct tmio_mmc_host* |
1056 | tmio_mmc_host_alloc(struct platform_device *pdev) | |
b6147490 | 1057 | { |
94b110af | 1058 | struct tmio_mmc_host *host; |
b6147490 | 1059 | struct mmc_host *mmc; |
94b110af KM |
1060 | |
1061 | mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &pdev->dev); | |
1062 | if (!mmc) | |
1063 | return NULL; | |
1064 | ||
1065 | host = mmc_priv(mmc); | |
1066 | host->mmc = mmc; | |
1067 | host->pdev = pdev; | |
1068 | ||
1069 | return host; | |
1070 | } | |
1071 | EXPORT_SYMBOL(tmio_mmc_host_alloc); | |
1072 | ||
1073 | void tmio_mmc_host_free(struct tmio_mmc_host *host) | |
1074 | { | |
1075 | mmc_free_host(host->mmc); | |
94b110af KM |
1076 | } |
1077 | EXPORT_SYMBOL(tmio_mmc_host_free); | |
1078 | ||
1079 | int tmio_mmc_host_probe(struct tmio_mmc_host *_host, | |
1080 | struct tmio_mmc_data *pdata) | |
1081 | { | |
1082 | struct platform_device *pdev = _host->pdev; | |
1083 | struct mmc_host *mmc = _host->mmc; | |
b6147490 GL |
1084 | struct resource *res_ctl; |
1085 | int ret; | |
1086 | u32 irq_mask = TMIO_MASK_CMD; | |
1087 | ||
5a00a971 GL |
1088 | tmio_mmc_of_parse(pdev, pdata); |
1089 | ||
7b952137 | 1090 | if (!(pdata->flags & TMIO_MMC_HAS_IDLE_WAIT)) |
dfe9a229 | 1091 | _host->write16_hook = NULL; |
7b952137 | 1092 | |
b6147490 GL |
1093 | res_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1094 | if (!res_ctl) | |
1095 | return -EINVAL; | |
1096 | ||
274a752b SB |
1097 | ret = mmc_of_parse(mmc); |
1098 | if (ret < 0) | |
1099 | goto host_free; | |
5a00a971 | 1100 | |
b6147490 | 1101 | _host->pdata = pdata; |
b6147490 GL |
1102 | platform_set_drvdata(pdev, mmc); |
1103 | ||
9d731e75 | 1104 | _host->set_pwr = pdata->set_pwr; |
b6147490 GL |
1105 | _host->set_clk_div = pdata->set_clk_div; |
1106 | ||
05fae4a7 KM |
1107 | ret = tmio_mmc_init_ocr(_host); |
1108 | if (ret < 0) | |
1109 | goto host_free; | |
1110 | ||
7df56bbb IM |
1111 | _host->ctl = devm_ioremap(&pdev->dev, |
1112 | res_ctl->start, resource_size(res_ctl)); | |
b6147490 GL |
1113 | if (!_host->ctl) { |
1114 | ret = -ENOMEM; | |
1115 | goto host_free; | |
1116 | } | |
1117 | ||
1118 | mmc->ops = &tmio_mmc_ops; | |
5a00a971 | 1119 | mmc->caps |= MMC_CAP_4_BIT_DATA | pdata->capabilities; |
dd006b30 | 1120 | mmc->caps2 |= pdata->capabilities2; |
b6147490 GL |
1121 | mmc->max_segs = 32; |
1122 | mmc->max_blk_size = 512; | |
1123 | mmc->max_blk_count = (PAGE_CACHE_SIZE / mmc->max_blk_size) * | |
1124 | mmc->max_segs; | |
1125 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
1126 | mmc->max_seg_size = mmc->max_req_size; | |
b6147490 | 1127 | |
c8be24c2 | 1128 | _host->native_hotplug = !(pdata->flags & TMIO_MMC_USE_GPIO_CD || |
2b1ac5c2 | 1129 | mmc->caps & MMC_CAP_NEEDS_POLL || |
5a00a971 GL |
1130 | mmc->caps & MMC_CAP_NONREMOVABLE || |
1131 | mmc->slot.cd_irq >= 0); | |
2b1ac5c2 | 1132 | |
ae12d250 | 1133 | if (tmio_mmc_clk_update(_host) < 0) { |
8c102a96 GL |
1134 | mmc->f_max = pdata->hclk; |
1135 | mmc->f_min = mmc->f_max / 512; | |
1136 | } | |
1137 | ||
bb98d9d1 SS |
1138 | /* |
1139 | * Check the sanity of mmc->f_min to prevent tmio_mmc_set_clock() from | |
1140 | * looping forever... | |
1141 | */ | |
1142 | if (mmc->f_min == 0) { | |
1143 | ret = -EINVAL; | |
1144 | goto host_free; | |
1145 | } | |
1146 | ||
cbb18b30 | 1147 | /* |
0369483e UH |
1148 | * While using internal tmio hardware logic for card detection, we need |
1149 | * to ensure it stays powered for it to work. | |
cbb18b30 | 1150 | */ |
2b1ac5c2 | 1151 | if (_host->native_hotplug) |
cbb18b30 BH |
1152 | pm_runtime_get_noresume(&pdev->dev); |
1153 | ||
b6147490 GL |
1154 | tmio_mmc_clk_stop(_host); |
1155 | tmio_mmc_reset(_host); | |
1156 | ||
54680fe7 | 1157 | _host->sdcard_irq_mask = sd_ctrl_read32(_host, CTL_IRQ_MASK); |
b6147490 | 1158 | tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL); |
e0337cc8 GL |
1159 | |
1160 | /* Unmask the IRQs we want to know about */ | |
1161 | if (!_host->chan_rx) | |
1162 | irq_mask |= TMIO_MASK_READOP; | |
1163 | if (!_host->chan_tx) | |
1164 | irq_mask |= TMIO_MASK_WRITEOP; | |
1165 | if (!_host->native_hotplug) | |
1166 | irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT); | |
1167 | ||
1168 | _host->sdcard_irq_mask &= ~irq_mask; | |
1169 | ||
7501c431 UH |
1170 | _host->sdio_irq_enabled = false; |
1171 | if (pdata->flags & TMIO_MMC_SDIO_IRQ) { | |
1172 | _host->sdio_irq_mask = TMIO_SDIO_MASK_ALL; | |
1173 | sd_ctrl_write16(_host, CTL_SDIO_IRQ_MASK, _host->sdio_irq_mask); | |
1174 | sd_ctrl_write16(_host, CTL_TRANSACTION_CTL, 0x0000); | |
1175 | } | |
b6147490 | 1176 | |
b6147490 | 1177 | spin_lock_init(&_host->lock); |
b9269fdd | 1178 | mutex_init(&_host->ios_lock); |
b6147490 GL |
1179 | |
1180 | /* Init delayed work for request timeouts */ | |
1181 | INIT_DELAYED_WORK(&_host->delayed_reset_work, tmio_mmc_reset_work); | |
b9269fdd | 1182 | INIT_WORK(&_host->done, tmio_mmc_done_work); |
b6147490 GL |
1183 | |
1184 | /* See if we also get DMA */ | |
1185 | tmio_mmc_request_dma(_host, pdata); | |
1186 | ||
0369483e UH |
1187 | pm_runtime_set_active(&pdev->dev); |
1188 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); | |
1189 | pm_runtime_use_autosuspend(&pdev->dev); | |
1190 | pm_runtime_enable(&pdev->dev); | |
1191 | ||
8c102a96 | 1192 | ret = mmc_add_host(mmc); |
8c102a96 GL |
1193 | if (ret < 0) { |
1194 | tmio_mmc_host_remove(_host); | |
1195 | return ret; | |
1196 | } | |
b6147490 | 1197 | |
c419e611 RW |
1198 | dev_pm_qos_expose_latency_limit(&pdev->dev, 100); |
1199 | ||
c8be24c2 | 1200 | if (pdata->flags & TMIO_MMC_USE_GPIO_CD) { |
214fc309 | 1201 | ret = mmc_gpio_request_cd(mmc, pdata->cd_gpio, 0); |
c8be24c2 GL |
1202 | if (ret < 0) { |
1203 | tmio_mmc_host_remove(_host); | |
1204 | return ret; | |
1205 | } | |
d4d11449 | 1206 | mmc_gpiod_request_cd_irq(mmc); |
c8be24c2 GL |
1207 | } |
1208 | ||
b6147490 GL |
1209 | return 0; |
1210 | ||
b6147490 | 1211 | host_free: |
b6147490 GL |
1212 | |
1213 | return ret; | |
1214 | } | |
1215 | EXPORT_SYMBOL(tmio_mmc_host_probe); | |
1216 | ||
1217 | void tmio_mmc_host_remove(struct tmio_mmc_host *host) | |
1218 | { | |
e6ee7182 | 1219 | struct platform_device *pdev = host->pdev; |
c8be24c2 GL |
1220 | struct mmc_host *mmc = host->mmc; |
1221 | ||
2b1ac5c2 | 1222 | if (!host->native_hotplug) |
7311bef0 GL |
1223 | pm_runtime_get_sync(&pdev->dev); |
1224 | ||
c419e611 RW |
1225 | dev_pm_qos_hide_latency_limit(&pdev->dev); |
1226 | ||
c8be24c2 | 1227 | mmc_remove_host(mmc); |
b9269fdd | 1228 | cancel_work_sync(&host->done); |
b6147490 GL |
1229 | cancel_delayed_work_sync(&host->delayed_reset_work); |
1230 | tmio_mmc_release_dma(host); | |
e6ee7182 | 1231 | |
e6ee7182 GL |
1232 | pm_runtime_put_sync(&pdev->dev); |
1233 | pm_runtime_disable(&pdev->dev); | |
b6147490 GL |
1234 | } |
1235 | EXPORT_SYMBOL(tmio_mmc_host_remove); | |
1236 | ||
9ade7dbf | 1237 | #ifdef CONFIG_PM |
7311bef0 GL |
1238 | int tmio_mmc_host_runtime_suspend(struct device *dev) |
1239 | { | |
ae12d250 UH |
1240 | struct mmc_host *mmc = dev_get_drvdata(dev); |
1241 | struct tmio_mmc_host *host = mmc_priv(mmc); | |
1242 | ||
20e955c3 UH |
1243 | tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL); |
1244 | ||
ae12d250 UH |
1245 | if (host->clk_cache) |
1246 | tmio_mmc_clk_stop(host); | |
1247 | ||
00452c11 KM |
1248 | if (host->clk_disable) |
1249 | host->clk_disable(host->pdev); | |
ae12d250 | 1250 | |
7311bef0 GL |
1251 | return 0; |
1252 | } | |
1253 | EXPORT_SYMBOL(tmio_mmc_host_runtime_suspend); | |
1254 | ||
1255 | int tmio_mmc_host_runtime_resume(struct device *dev) | |
1256 | { | |
1257 | struct mmc_host *mmc = dev_get_drvdata(dev); | |
1258 | struct tmio_mmc_host *host = mmc_priv(mmc); | |
7311bef0 | 1259 | |
ae12d250 UH |
1260 | tmio_mmc_reset(host); |
1261 | tmio_mmc_clk_update(host); | |
1262 | ||
1263 | if (host->clk_cache) { | |
1264 | tmio_mmc_set_clock(host, host->clk_cache); | |
1265 | tmio_mmc_clk_start(host); | |
1266 | } | |
1267 | ||
162f43e3 | 1268 | tmio_mmc_enable_dma(host, true); |
7311bef0 | 1269 | |
7311bef0 GL |
1270 | return 0; |
1271 | } | |
1272 | EXPORT_SYMBOL(tmio_mmc_host_runtime_resume); | |
710dec95 | 1273 | #endif |
7311bef0 | 1274 | |
b6147490 | 1275 | MODULE_LICENSE("GPL v2"); |