]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/mmc/host/tmio_mmc_pio.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'rtc-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / tmio_mmc_pio.c
CommitLineData
b6147490
GL		 1/*
2 * linux/drivers/mmc/host/tmio_mmc_pio.c
3 *
bf96208f
WS		 4 * Copyright (C) 2016 Sang Engineering, Wolfram Sang
5 * Copyright (C) 2015-16 Renesas Electronics Corporation
b6147490
GL		 6 * Copyright (C) 2011 Guennadi Liakhovetski
7 * Copyright (C) 2007 Ian Molton
8 * Copyright (C) 2004 Ian Molton
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Driver for the MMC / SD / SDIO IP found in:
15 *
16 * TC6393XB, TC6391XB, TC6387XB, T7L66XB, ASIC3, SH-Mobile SoCs
17 *
18 * This driver draws mainly on scattered spec sheets, Reverse engineering
19 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
20 * support). (Further 4 bit support from a later datasheet).
21 *
22 * TODO:
23 * Investigate using a workqueue for PIO transfers
24 * Eliminate FIXMEs
b6147490
GL		 25 * Better Power management
26 * Handle MMC errors better
27 * double buffer support
28 *
29 */
30
31#include <linux/delay.h>
32#include <linux/device.h>
33#include <linux/highmem.h>
34#include <linux/interrupt.h>
35#include <linux/io.h>
36#include <linux/irq.h>
37#include <linux/mfd/tmio.h>
4f119977 38#include <linux/mmc/card.h>
b6147490 39#include <linux/mmc/host.h>
0f506a96 40#include <linux/mmc/mmc.h>
fd0ea65d 41#include <linux/mmc/slot-gpio.h>
b6147490
GL		 42#include <linux/module.h>
43#include <linux/pagemap.h>
44#include <linux/platform_device.h>
c419e611 45#include <linux/pm_qos.h>
e6ee7182 46#include <linux/pm_runtime.h>
619b08d4 47#include <linux/regulator/consumer.h>
b8d11962 48#include <linux/mmc/sdio.h>
b6147490 49#include <linux/scatterlist.h>
b6147490 50#include <linux/spinlock.h>
e3de2be7 51#include <linux/workqueue.h>
b6147490
GL		 52
53#include "tmio_mmc.h"
54
b6147490
GL		 55void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
56{
54680fe7 57 host->sdcard_irq_mask &= ~(i & TMIO_MASK_IRQ);
2c54506b 58 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
b6147490
GL		 59}
60
61void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
62{
54680fe7 63 host->sdcard_irq_mask |= (i & TMIO_MASK_IRQ);
2c54506b 64 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
b6147490
GL		 65}
66
67static void tmio_mmc_ack_mmc_irqs(struct tmio_mmc_host *host, u32 i)
68{
2c54506b 69 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, ~i);
b6147490
GL		 70}
71
72static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)
73{
74 host->sg_len = data->sg_len;
75 host->sg_ptr = data->sg;
76 host->sg_orig = data->sg;
77 host->sg_off = 0;
78}
79
80static int tmio_mmc_next_sg(struct tmio_mmc_host *host)
81{
82 host->sg_ptr = sg_next(host->sg_ptr);
83 host->sg_off = 0;
84 return --host->sg_len;
85}
86
0df9d2ea
TK		 87#define CMDREQ_TIMEOUT 5000
88
b6147490
GL		 89#ifdef CONFIG_MMC_DEBUG
90
91#define STATUS_TO_TEXT(a, status, i) \
92 do { \
93 if (status & TMIO_STAT_##a) { \
94 if (i++) \
95 printk(" | "); \
96 printk(#a); \
97 } \
98 } while (0)
99
100static void pr_debug_status(u32 status)
101{
102 int i = 0;
a3c76eb9 103 pr_debug("status: %08x = ", status);
b6147490
GL		 104 STATUS_TO_TEXT(CARD_REMOVE, status, i);
105 STATUS_TO_TEXT(CARD_INSERT, status, i);
106 STATUS_TO_TEXT(SIGSTATE, status, i);
107 STATUS_TO_TEXT(WRPROTECT, status, i);
108 STATUS_TO_TEXT(CARD_REMOVE_A, status, i);
109 STATUS_TO_TEXT(CARD_INSERT_A, status, i);
110 STATUS_TO_TEXT(SIGSTATE_A, status, i);
111 STATUS_TO_TEXT(CMD_IDX_ERR, status, i);
112 STATUS_TO_TEXT(STOPBIT_ERR, status, i);
113 STATUS_TO_TEXT(ILL_FUNC, status, i);
114 STATUS_TO_TEXT(CMD_BUSY, status, i);
115 STATUS_TO_TEXT(CMDRESPEND, status, i);
116 STATUS_TO_TEXT(DATAEND, status, i);
117 STATUS_TO_TEXT(CRCFAIL, status, i);
118 STATUS_TO_TEXT(DATATIMEOUT, status, i);
119 STATUS_TO_TEXT(CMDTIMEOUT, status, i);
120 STATUS_TO_TEXT(RXOVERFLOW, status, i);
121 STATUS_TO_TEXT(TXUNDERRUN, status, i);
122 STATUS_TO_TEXT(RXRDY, status, i);
123 STATUS_TO_TEXT(TXRQ, status, i);
124 STATUS_TO_TEXT(ILL_ACCESS, status, i);
125 printk("\n");
126}
127
128#else
129#define pr_debug_status(s) do { } while (0)
130#endif
131
132static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
133{
134 struct tmio_mmc_host *host = mmc_priv(mmc);
135
7501c431
UH		 136 if (enable && !host->sdio_irq_enabled) {
137 /* Keep device active while SDIO irq is enabled */
138 pm_runtime_get_sync(mmc_dev(mmc));
139 host->sdio_irq_enabled = true;
140
54680fe7
SH		 141 host->sdio_irq_mask = TMIO_SDIO_MASK_ALL &
142 ~TMIO_SDIO_STAT_IOIRQ;
b6147490 143 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
54680fe7 144 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
7501c431 145 } else if (!enable && host->sdio_irq_enabled) {
54680fe7
SH		 146 host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
147 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
b6147490 148 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000);
7501c431
UH		 149
150 host->sdio_irq_enabled = false;
0369483e
UH		 151 pm_runtime_mark_last_busy(mmc_dev(mmc));
152 pm_runtime_put_autosuspend(mmc_dev(mmc));
b6147490
GL		 153 }
154}
155
7fbc030d
WS		 156static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
157{
158 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
159 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
3d376fb2 160 msleep(host->pdata->flags & TMIO_MMC_MIN_RCAR2 ? 1 : 10);
7fbc030d
WS		 161
162 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
163 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
164 msleep(10);
165 }
166}
167
148634d2
WS		 168static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
169{
170 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
171 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
172 msleep(10);
173 }
174
175 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
176 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
3d376fb2 177 msleep(host->pdata->flags & TMIO_MMC_MIN_RCAR2 ? 5 : 10);
148634d2
WS		 178}
179
ae12d250
UH		 180static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
181 unsigned int new_clock)
b6147490
GL		 182{
183 u32 clk = 0, clock;
184
148634d2
WS		 185 if (new_clock == 0) {
186 tmio_mmc_clk_stop(host);
187 return;
188 }
2fb55956 189
148634d2
WS		 190 if (host->clk_update)
191 clock = host->clk_update(host, new_clock) / 512;
192 else
193 clock = host->mmc->f_min;
da29fe2b 194
148634d2
WS		 195 for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
196 clock <<= 1;
197
198 /* 1/1 clock is option */
199 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1))
200 clk |= 0xff;
b6147490
GL		 201
202 if (host->set_clk_div)
bf96208f 203 host->set_clk_div(host->pdev, (clk >> 22) & 1);
b6147490 204
14d5828f
WS		 205 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
206 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
bf96208f 207 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
3d376fb2 208 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
04e24b80 209 msleep(10);
7fbc030d
WS		 210
211 tmio_mmc_clk_start(host);
b6147490
GL		 212}
213
b6147490
GL		 214static void tmio_mmc_reset(struct tmio_mmc_host *host)
215{
216 /* FIXME - should we set stop clock reg here */
217 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
5d60e500 218 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG)
69d1fe18 219 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
b6147490
GL		 220 msleep(10);
221 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
5d60e500 222 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG)
69d1fe18 223 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
b6147490
GL		 224 msleep(10);
225}
226
227static void tmio_mmc_reset_work(struct work_struct *work)
228{
229 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
230 delayed_reset_work.work);
231 struct mmc_request *mrq;
232 unsigned long flags;
233
234 spin_lock_irqsave(&host->lock, flags);
235 mrq = host->mrq;
236
df3ef2d3
GL		 237 /*
238 * is request already finished? Since we use a non-blocking
239 * cancel_delayed_work(), it can happen, that a .set_ios() call preempts
240 * us, so, have to check for IS_ERR(host->mrq)
241 */
242 if (IS_ERR_OR_NULL(mrq)
b6147490 243 || time_is_after_jiffies(host->last_req_ts +
0df9d2ea 244 msecs_to_jiffies(CMDREQ_TIMEOUT))) {
b6147490
GL		 245 spin_unlock_irqrestore(&host->lock, flags);
246 return;
247 }
248
249 dev_warn(&host->pdev->dev,
250 "timeout waiting for hardware interrupt (CMD%u)\n",
251 mrq->cmd->opcode);
252
253 if (host->data)
254 host->data->error = -ETIMEDOUT;
255 else if (host->cmd)
256 host->cmd->error = -ETIMEDOUT;
257 else
258 mrq->cmd->error = -ETIMEDOUT;
259
260 host->cmd = NULL;
261 host->data = NULL;
b6147490
GL		 262 host->force_pio = false;
263
264 spin_unlock_irqrestore(&host->lock, flags);
265
266 tmio_mmc_reset(host);
267
df3ef2d3
GL		 268 /* Ready for new calls */
269 host->mrq = NULL;
270
e3de2be7 271 tmio_mmc_abort_dma(host);
b6147490
GL		 272 mmc_request_done(host->mmc, mrq);
273}
274
df3ef2d3 275/* called with host->lock held, interrupts disabled */
b6147490
GL		 276static void tmio_mmc_finish_request(struct tmio_mmc_host *host)
277{
b9269fdd
GL		 278 struct mmc_request *mrq;
279 unsigned long flags;
b6147490 280
b9269fdd
GL		 281 spin_lock_irqsave(&host->lock, flags);
282
283 mrq = host->mrq;
284 if (IS_ERR_OR_NULL(mrq)) {
285 spin_unlock_irqrestore(&host->lock, flags);
b6147490 286 return;
b9269fdd 287 }
b6147490 288
b6147490
GL		 289 host->cmd = NULL;
290 host->data = NULL;
291 host->force_pio = false;
292
293 cancel_delayed_work(&host->delayed_reset_work);
294
df3ef2d3 295 host->mrq = NULL;
b9269fdd 296 spin_unlock_irqrestore(&host->lock, flags);
df3ef2d3 297
e3de2be7
GL		 298 if (mrq->cmd->error || (mrq->data && mrq->data->error))
299 tmio_mmc_abort_dma(host);
300
4f119977
AK		 301 if (host->check_scc_error)
302 host->check_scc_error(host);
303
b6147490
GL		 304 mmc_request_done(host->mmc, mrq);
305}
306
b9269fdd
GL		 307static void tmio_mmc_done_work(struct work_struct *work)
308{
309 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
310 done);
311 tmio_mmc_finish_request(host);
312}
313
b6147490
GL		 314/* These are the bitmasks the tmio chip requires to implement the MMC response
315 * types. Note that R1 and R6 are the same in this scheme. */
316#define APP_CMD 0x0040
317#define RESP_NONE 0x0300
318#define RESP_R1 0x0400
319#define RESP_R1B 0x0500
320#define RESP_R2 0x0600
321#define RESP_R3 0x0700
322#define DATA_PRESENT 0x0800
323#define TRANSFER_READ 0x1000
324#define TRANSFER_MULTI 0x2000
325#define SECURITY_CMD 0x4000
b8d11962 326#define NO_CMD12_ISSUE 0x4000 /* TMIO_MMC_HAVE_CMD12_CTRL */
b6147490
GL		 327
328static int tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
329{
330 struct mmc_data *data = host->data;
331 int c = cmd->opcode;
e23cd53c 332 u32 irq_mask = TMIO_MASK_CMD;
b6147490 333
0f506a96
GL		 334 /* CMD12 is handled by hardware */
335 if (cmd->opcode == MMC_STOP_TRANSMISSION && !cmd->arg) {
b6147490
GL		 336 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
337 return 0;
338 }
339
340 switch (mmc_resp_type(cmd)) {
341 case MMC_RSP_NONE: c |= RESP_NONE; break;
0bc0b6e8
WS		 342 case MMC_RSP_R1:
343 case MMC_RSP_R1_NO_CRC:
344 c |= RESP_R1; break;
b6147490
GL		 345 case MMC_RSP_R1B: c |= RESP_R1B; break;
346 case MMC_RSP_R2: c |= RESP_R2; break;
347 case MMC_RSP_R3: c |= RESP_R3; break;
348 default:
349 pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
350 return -EINVAL;
351 }
352
353 host->cmd = cmd;
354
355/* FIXME - this seems to be ok commented out but the spec suggest this bit
356 * should be set when issuing app commands.
357 * if(cmd->flags & MMC_FLAG_ACMD)
358 * c |= APP_CMD;
359 */
360 if (data) {
361 c |= DATA_PRESENT;
362 if (data->blocks > 1) {
363 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
364 c |= TRANSFER_MULTI;
b8d11962
SU		 365
366 /*
367 * Disable auto CMD12 at IO_RW_EXTENDED when
368 * multiple block transfer
369 */
370 if ((host->pdata->flags & TMIO_MMC_HAVE_CMD12_CTRL) &&
371 (cmd->opcode == SD_IO_RW_EXTENDED))
372 c |= NO_CMD12_ISSUE;
b6147490
GL		 373 }
374 if (data->flags & MMC_DATA_READ)
375 c |= TRANSFER_READ;
376 }
377
e23cd53c
GL		 378 if (!host->native_hotplug)
379 irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
380 tmio_mmc_enable_mmc_irqs(host, irq_mask);
b6147490
GL		 381
382 /* Fire off the command */
2c54506b 383 sd_ctrl_write32_as_16_and_16(host, CTL_ARG_REG, cmd->arg);
b6147490
GL		 384 sd_ctrl_write16(host, CTL_SD_CMD, c);
385
386 return 0;
387}
388
b9bd7ff8
KM		 389static void tmio_mmc_transfer_data(struct tmio_mmc_host *host,
390 unsigned short *buf,
391 unsigned int count)
392{
393 int is_read = host->data->flags & MMC_DATA_READ;
394 u8 *buf8;
395
396 /*
397 * Transfer the data
398 */
8185e51f
CB		 399 if (host->pdata->flags & TMIO_MMC_32BIT_DATA_PORT) {
400 u8 data[4] = { };
401
402 if (is_read)
403 sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT, (u32 *)buf,
404 count >> 2);
405 else
406 sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT, (u32 *)buf,
407 count >> 2);
408
409 /* if count was multiple of 4 */
410 if (!(count & 0x3))
411 return;
412
413 buf8 = (u8 *)(buf + (count >> 2));
414 count %= 4;
415
416 if (is_read) {
417 sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT,
418 (u32 *)data, 1);
419 memcpy(buf8, data, count);
420 } else {
421 memcpy(data, buf8, count);
422 sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT,
423 (u32 *)data, 1);
424 }
425
426 return;
427 }
428
b9bd7ff8
KM		 429 if (is_read)
430 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
431 else
432 sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
433
434 /* if count was even number */
435 if (!(count & 0x1))
436 return;
437
438 /* if count was odd number */
439 buf8 = (u8 *)(buf + (count >> 1));
440
441 /*
442 * FIXME
443 *
444 * driver and this function are assuming that
445 * it is used as little endian
446 */
447 if (is_read)
448 *buf8 = sd_ctrl_read16(host, CTL_SD_DATA_PORT) & 0xff;
449 else
450 sd_ctrl_write16(host, CTL_SD_DATA_PORT, *buf8);
451}
452
b6147490
GL		 453/*
454 * This chip always returns (at least?) as much data as you ask for.
455 * I'm unsure what happens if you ask for less than a block. This should be
25985edc 456 * looked into to ensure that a funny length read doesn't hose the controller.
b6147490
GL		 457 */
458static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
459{
460 struct mmc_data *data = host->data;
461 void *sg_virt;
462 unsigned short *buf;
463 unsigned int count;
464 unsigned long flags;
465
466 if ((host->chan_tx || host->chan_rx) && !host->force_pio) {
467 pr_err("PIO IRQ in DMA mode!\n");
468 return;
469 } else if (!data) {
470 pr_debug("Spurious PIO IRQ\n");
471 return;
472 }
473
474 sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags);
475 buf = (unsigned short *)(sg_virt + host->sg_off);
476
477 count = host->sg_ptr->length - host->sg_off;
478 if (count > data->blksz)
479 count = data->blksz;
480
481 pr_debug("count: %08x offset: %08x flags %08x\n",
482 count, host->sg_off, data->flags);
483
484 /* Transfer the data */
b9bd7ff8 485 tmio_mmc_transfer_data(host, buf, count);
b6147490
GL		 486
487 host->sg_off += count;
488
489 tmio_mmc_kunmap_atomic(host->sg_ptr, &flags, sg_virt);
490
491 if (host->sg_off == host->sg_ptr->length)
492 tmio_mmc_next_sg(host);
493
494 return;
495}
496
497static void tmio_mmc_check_bounce_buffer(struct tmio_mmc_host *host)
498{
499 if (host->sg_ptr == &host->bounce_sg) {
500 unsigned long flags;
501 void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags);
502 memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length);
503 tmio_mmc_kunmap_atomic(host->sg_orig, &flags, sg_vaddr);
504 }
505}
506
507/* needs to be called with host->lock held */
508void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
509{
510 struct mmc_data *data = host->data;
511 struct mmc_command *stop;
512
513 host->data = NULL;
514
515 if (!data) {
516 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
517 return;
518 }
519 stop = data->stop;
520
521 /* FIXME - return correct transfer count on errors */
522 if (!data->error)
523 data->bytes_xfered = data->blocks * data->blksz;
524 else
525 data->bytes_xfered = 0;
526
527 pr_debug("Completed data request\n");
528
529 /*
530 * FIXME: other drivers allow an optional stop command of any given type
531 * which we dont do, as the chip can auto generate them.
532 * Perhaps we can be smarter about when to use auto CMD12 and
533 * only issue the auto request when we know this is the desired
534 * stop command, allowing fallback to the stop command the
535 * upper layers expect. For now, we do what works.
536 */
537
538 if (data->flags & MMC_DATA_READ) {
539 if (host->chan_rx && !host->force_pio)
540 tmio_mmc_check_bounce_buffer(host);
541 dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
542 host->mrq);
543 } else {
544 dev_dbg(&host->pdev->dev, "Complete Tx request %p\n",
545 host->mrq);
546 }
547
548 if (stop) {
0f506a96 549 if (stop->opcode == MMC_STOP_TRANSMISSION && !stop->arg)
b6147490
GL		 550 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
551 else
552 BUG();
553 }
554
b9269fdd 555 schedule_work(&host->done);
b6147490
GL		 556}
557
96e0b2ba 558static void tmio_mmc_data_irq(struct tmio_mmc_host *host, unsigned int stat)
b6147490
GL		 559{
560 struct mmc_data *data;
561 spin_lock(&host->lock);
562 data = host->data;
563
564 if (!data)
565 goto out;
566
96e0b2ba
AK		 567 if (stat & TMIO_STAT_CRCFAIL || stat & TMIO_STAT_STOPBIT_ERR ||
568 stat & TMIO_STAT_TXUNDERRUN)
569 data->error = -EILSEQ;
b6147490 570 if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) {
2c54506b 571 u32 status = sd_ctrl_read16_and_16_as_32(host, CTL_STATUS);
81e888da
SU		 572 bool done = false;
573
b6147490
GL		 574 /*
575 * Has all data been written out yet? Testing on SuperH showed,
576 * that in most cases the first interrupt comes already with the
577 * BUSY status bit clear, but on some operations, like mount or
578 * in the beginning of a write / sync / umount, there is one
579 * DATAEND interrupt with the BUSY bit set, in this cases
580 * waiting for one more interrupt fixes the problem.
581 */
81e888da 582 if (host->pdata->flags & TMIO_MMC_HAS_IDLE_WAIT) {
a21553c9 583 if (status & TMIO_STAT_SCLKDIVEN)
81e888da
SU		 584 done = true;
585 } else {
586 if (!(status & TMIO_STAT_CMD_BUSY))
587 done = true;
588 }
589
590 if (done) {
b6147490
GL		 591 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
592 tasklet_schedule(&host->dma_complete);
593 }
594 } else if (host->chan_rx && (data->flags & MMC_DATA_READ) && !host->force_pio) {
595 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
596 tasklet_schedule(&host->dma_complete);
597 } else {
598 tmio_mmc_do_data_irq(host);
599 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP);
600 }
601out:
602 spin_unlock(&host->lock);
603}
604
605static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
606 unsigned int stat)
607{
608 struct mmc_command *cmd = host->cmd;
609 int i, addr;
610
611 spin_lock(&host->lock);
612
613 if (!host->cmd) {
614 pr_debug("Spurious CMD irq\n");
615 goto out;
616 }
617
b6147490
GL		 618 /* This controller is sicker than the PXA one. Not only do we need to
619 * drop the top 8 bits of the first response word, we also need to
620 * modify the order of the response for short response command types.
621 */
622
623 for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
2c54506b 624 cmd->resp[i] = sd_ctrl_read16_and_16_as_32(host, addr);
b6147490
GL		 625
626 if (cmd->flags & MMC_RSP_136) {
627 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
628 cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
629 cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
630 cmd->resp[3] <<= 8;
631 } else if (cmd->flags & MMC_RSP_R3) {
632 cmd->resp[0] = cmd->resp[3];
633 }
634
635 if (stat & TMIO_STAT_CMDTIMEOUT)
636 cmd->error = -ETIMEDOUT;
96e0b2ba
AK		 637 else if ((stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC) ||
638 stat & TMIO_STAT_STOPBIT_ERR ||
639 stat & TMIO_STAT_CMD_IDX_ERR)
b6147490
GL		 640 cmd->error = -EILSEQ;
641
642 /* If there is data to handle we enable data IRQs here, and
643 * we will ultimatley finish the request in the data_end handler.
644 * If theres no data or we encountered an error, finish now.
645 */
96e0b2ba 646 if (host->data && (!cmd->error || cmd->error == -EILSEQ)) {
b6147490
GL		 647 if (host->data->flags & MMC_DATA_READ) {
648 if (host->force_pio || !host->chan_rx)
649 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_READOP);
650 else
651 tasklet_schedule(&host->dma_issue);
652 } else {
653 if (host->force_pio || !host->chan_tx)
654 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
655 else
656 tasklet_schedule(&host->dma_issue);
657 }
658 } else {
b9269fdd 659 schedule_work(&host->done);
b6147490
GL		 660 }
661
662out:
663 spin_unlock(&host->lock);
664}
665
7729c7a2
SH		 666static bool __tmio_mmc_card_detect_irq(struct tmio_mmc_host *host,
667 int ireg, int status)
668{
669 struct mmc_host *mmc = host->mmc;
b6147490 670
e312eb1e
PP		 671 /* Card insert / remove attempts */
672 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
673 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
674 TMIO_STAT_CARD_REMOVE);
71d111cd
GL		 675 if ((((ireg & TMIO_STAT_CARD_REMOVE) && mmc->card) ||
676 ((ireg & TMIO_STAT_CARD_INSERT) && !mmc->card)) &&
677 !work_pending(&mmc->detect.work))
b9269fdd 678 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
7729c7a2 679 return true;
b6147490
GL		 680 }
681
7729c7a2
SH		 682 return false;
683}
684
7729c7a2
SH		 685static bool __tmio_mmc_sdcard_irq(struct tmio_mmc_host *host,
686 int ireg, int status)
687{
e312eb1e
PP		 688 /* Command completion */
689 if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) {
690 tmio_mmc_ack_mmc_irqs(host,
691 TMIO_STAT_CMDRESPEND |
692 TMIO_STAT_CMDTIMEOUT);
693 tmio_mmc_cmd_irq(host, status);
7729c7a2 694 return true;
e312eb1e 695 }
b6147490 696
e312eb1e
PP		 697 /* Data transfer */
698 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
699 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
700 tmio_mmc_pio_irq(host);
7729c7a2 701 return true;
e312eb1e 702 }
b6147490 703
e312eb1e
PP		 704 /* Data transfer completion */
705 if (ireg & TMIO_STAT_DATAEND) {
706 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_DATAEND);
96e0b2ba 707 tmio_mmc_data_irq(host, status);
7729c7a2 708 return true;
b6147490 709 }
e312eb1e 710
7729c7a2
SH		 711 return false;
712}
713
4da98670 714static void tmio_mmc_sdio_irq(int irq, void *devid)
7729c7a2
SH		 715{
716 struct tmio_mmc_host *host = devid;
717 struct mmc_host *mmc = host->mmc;
718 struct tmio_mmc_data *pdata = host->pdata;
719 unsigned int ireg, status;
6b98757e 720 unsigned int sdio_status;
7729c7a2
SH		 721
722 if (!(pdata->flags & TMIO_MMC_SDIO_IRQ))
4da98670 723 return;
7729c7a2
SH		 724
725 status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
0c4bf5be 726 ireg = status & TMIO_SDIO_MASK_ALL & ~host->sdio_irq_mask;
7729c7a2 727
6b98757e
SU		 728 sdio_status = status & ~TMIO_SDIO_MASK_ALL;
729 if (pdata->flags & TMIO_MMC_SDIO_STATUS_QUIRK)
730 sdio_status |= 6;
731
732 sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status);
7729c7a2
SH		 733
734 if (mmc->caps & MMC_CAP_SDIO_IRQ && ireg & TMIO_SDIO_STAT_IOIRQ)
735 mmc_signal_sdio_irq(mmc);
7729c7a2 736}
7729c7a2
SH		 737
738irqreturn_t tmio_mmc_irq(int irq, void *devid)
739{
740 struct tmio_mmc_host *host = devid;
741 unsigned int ireg, status;
742
2c54506b 743 status = sd_ctrl_read16_and_16_as_32(host, CTL_STATUS);
95840126
WS		 744 ireg = status & TMIO_MASK_IRQ & ~host->sdcard_irq_mask;
745
746 pr_debug_status(status);
747 pr_debug_status(ireg);
748
749 /* Clear the status except the interrupt status */
2c54506b 750 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, TMIO_MASK_IRQ);
7729c7a2 751
7729c7a2
SH		 752 if (__tmio_mmc_card_detect_irq(host, ireg, status))
753 return IRQ_HANDLED;
754 if (__tmio_mmc_sdcard_irq(host, ireg, status))
755 return IRQ_HANDLED;
756
757 tmio_mmc_sdio_irq(irq, devid);
b6147490 758
b6147490
GL		 759 return IRQ_HANDLED;
760}
8e7bfdb3 761EXPORT_SYMBOL(tmio_mmc_irq);
b6147490
GL		 762
763static int tmio_mmc_start_data(struct tmio_mmc_host *host,
764 struct mmc_data *data)
765{
766 struct tmio_mmc_data *pdata = host->pdata;
767
768 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
769 data->blksz, data->blocks);
770
0bc0b6e8
WS		 771 /* Some hardware cannot perform 2 byte requests in 4/8 bit mode */
772 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4 ||
773 host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
b6147490
GL		 774 int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES;
775
776 if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) {
0bc0b6e8 777 pr_err("%s: %d byte block unsupported in 4/8 bit mode\n",
b6147490
GL		 778 mmc_hostname(host->mmc), data->blksz);
779 return -EINVAL;
780 }
781 }
782
783 tmio_mmc_init_sg(host, data);
784 host->data = data;
785
786 /* Set transfer length / blocksize */
787 sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
788 sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
789
790 tmio_mmc_start_dma(host, data);
791
792 return 0;
793}
794
e8f36b5d
AK		 795static void tmio_mmc_hw_reset(struct mmc_host *mmc)
796{
797 struct tmio_mmc_host *host = mmc_priv(mmc);
798
799 if (host->hw_reset)
800 host->hw_reset(host);
801}
802
4f119977
AK		 803static int tmio_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
804{
805 struct tmio_mmc_host *host = mmc_priv(mmc);
806 int i, ret = 0;
807
808 if (!host->tap_num) {
809 if (!host->init_tuning || !host->select_tuning)
810 /* Tuning is not supported */
811 goto out;
812
813 host->tap_num = host->init_tuning(host);
814 if (!host->tap_num)
815 /* Tuning is not supported */
816 goto out;
817 }
818
819 if (host->tap_num * 2 >= sizeof(host->taps) * BITS_PER_BYTE) {
820 dev_warn_once(&host->pdev->dev,
821 "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
822 goto out;
823 }
824
825 bitmap_zero(host->taps, host->tap_num * 2);
826
827 /* Issue CMD19 twice for each tap */
828 for (i = 0; i < 2 * host->tap_num; i++) {
829 if (host->prepare_tuning)
830 host->prepare_tuning(host, i % host->tap_num);
831
832 ret = mmc_send_tuning(mmc, opcode, NULL);
833 if (ret && ret != -EILSEQ)
834 goto out;
835 if (ret == 0)
836 set_bit(i, host->taps);
837
838 mdelay(1);
839 }
840
841 ret = host->select_tuning(host);
842
843out:
844 if (ret < 0) {
845 dev_warn(&host->pdev->dev, "Tuning procedure failed\n");
846 tmio_mmc_hw_reset(mmc);
847 }
848
849 return ret;
850}
851
b6147490
GL		 852/* Process requests from the MMC layer */
853static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
854{
855 struct tmio_mmc_host *host = mmc_priv(mmc);
df3ef2d3 856 unsigned long flags;
b6147490
GL		 857 int ret;
858
df3ef2d3
GL		 859 spin_lock_irqsave(&host->lock, flags);
860
861 if (host->mrq) {
b6147490 862 pr_debug("request not null\n");
df3ef2d3
GL		 863 if (IS_ERR(host->mrq)) {
864 spin_unlock_irqrestore(&host->lock, flags);
865 mrq->cmd->error = -EAGAIN;
866 mmc_request_done(mmc, mrq);
867 return;
868 }
869 }
b6147490
GL		 870
871 host->last_req_ts = jiffies;
872 wmb();
873 host->mrq = mrq;
874
df3ef2d3
GL		 875 spin_unlock_irqrestore(&host->lock, flags);
876
b6147490
GL		 877 if (mrq->data) {
878 ret = tmio_mmc_start_data(host, mrq->data);
879 if (ret)
880 goto fail;
881 }
882
883 ret = tmio_mmc_start_command(host, mrq->cmd);
884 if (!ret) {
885 schedule_delayed_work(&host->delayed_reset_work,
0df9d2ea 886 msecs_to_jiffies(CMDREQ_TIMEOUT));
b6147490
GL		 887 return;
888 }
889
890fail:
b6147490 891 host->force_pio = false;
df3ef2d3 892 host->mrq = NULL;
b6147490
GL		 893 mrq->cmd->error = ret;
894 mmc_request_done(mmc, mrq);
895}
896
2fb55956 897static int tmio_mmc_clk_enable(struct tmio_mmc_host *host)
8c102a96 898{
4fe2ec57 899 if (!host->clk_enable)
8c102a96
GL		 900 return -ENOTSUPP;
901
2fb55956 902 return host->clk_enable(host);
8c102a96
GL		 903}
904
619b08d4 905static void tmio_mmc_power_on(struct tmio_mmc_host *host, unsigned short vdd)
b958a67c
GL		 906{
907 struct mmc_host *mmc = host->mmc;
619b08d4
GL		 908 int ret = 0;
909
910 /* .set_ios() is returning void, so, no chance to report an error */
b958a67c 911
9d731e75
CB		 912 if (host->set_pwr)
913 host->set_pwr(host->pdev, 1);
914
619b08d4
GL		 915 if (!IS_ERR(mmc->supply.vmmc)) {
916 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
917 /*
918 * Attention: empiric value. With a b43 WiFi SDIO card this
919 * delay proved necessary for reliable card-insertion probing.
920 * 100us were not enough. Is this the same 140us delay, as in
921 * tmio_mmc_set_ios()?
922 */
923 udelay(200);
924 }
925 /*
926 * It seems, VccQ should be switched on after Vcc, this is also what the
927 * omap_hsmmc.c driver does.
928 */
929 if (!IS_ERR(mmc->supply.vqmmc) && !ret) {
6d1d6b47 930 ret = regulator_enable(mmc->supply.vqmmc);
619b08d4
GL		 931 udelay(200);
932 }
6d1d6b47
GL		 933
934 if (ret < 0)
935 dev_dbg(&host->pdev->dev, "Regulators failed to power up: %d\n",
936 ret);
619b08d4
GL		 937}
938
939static void tmio_mmc_power_off(struct tmio_mmc_host *host)
940{
941 struct mmc_host *mmc = host->mmc;
942
943 if (!IS_ERR(mmc->supply.vqmmc))
944 regulator_disable(mmc->supply.vqmmc);
945
b958a67c 946 if (!IS_ERR(mmc->supply.vmmc))
619b08d4 947 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
9d731e75
CB		 948
949 if (host->set_pwr)
950 host->set_pwr(host->pdev, 0);
b958a67c
GL		 951}
952
9ae4ed7d
UH		 953static void tmio_mmc_set_bus_width(struct tmio_mmc_host *host,
954 unsigned char bus_width)
955{
0bc0b6e8
WS		 956 u16 reg = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT)
957 & ~(CARD_OPT_WIDTH | CARD_OPT_WIDTH8);
958
959 /* reg now applies to MMC_BUS_WIDTH_4 */
960 if (bus_width == MMC_BUS_WIDTH_1)
961 reg |= CARD_OPT_WIDTH;
962 else if (bus_width == MMC_BUS_WIDTH_8)
963 reg |= CARD_OPT_WIDTH8;
964
965 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, reg);
9ae4ed7d
UH		 966}
967
b6147490
GL		 968/* Set MMC clock / power.
969 * Note: This controller uses a simple divider scheme therefore it cannot
970 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
971 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
972 * slowest setting.
973 */
974static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
975{
976 struct tmio_mmc_host *host = mmc_priv(mmc);
4932bd64 977 struct device *dev = &host->pdev->dev;
df3ef2d3
GL		 978 unsigned long flags;
979
b9269fdd
GL		 980 mutex_lock(&host->ios_lock);
981
df3ef2d3
GL		 982 spin_lock_irqsave(&host->lock, flags);
983 if (host->mrq) {
984 if (IS_ERR(host->mrq)) {
4932bd64 985 dev_dbg(dev,
df3ef2d3
GL		 986 "%s.%d: concurrent .set_ios(), clk %u, mode %u\n",
987 current->comm, task_pid_nr(current),
988 ios->clock, ios->power_mode);
989 host->mrq = ERR_PTR(-EINTR);
990 } else {
4932bd64 991 dev_dbg(dev,
df3ef2d3
GL		 992 "%s.%d: CMD%u active since %lu, now %lu!\n",
993 current->comm, task_pid_nr(current),
994 host->mrq->cmd->opcode, host->last_req_ts, jiffies);
995 }
996 spin_unlock_irqrestore(&host->lock, flags);
b9269fdd
GL		 997
998 mutex_unlock(&host->ios_lock);
df3ef2d3
GL		 999 return;
1000 }
1001
1002 host->mrq = ERR_PTR(-EBUSY);
1003
1004 spin_unlock_irqrestore(&host->lock, flags);
b6147490 1005
3b292bb0
UH		 1006 switch (ios->power_mode) {
1007 case MMC_POWER_OFF:
1008 tmio_mmc_power_off(host);
1009 tmio_mmc_clk_stop(host);
1010 break;
1011 case MMC_POWER_UP:
3b292bb0 1012 tmio_mmc_power_on(host, ios->vdd);
7fbc030d 1013 tmio_mmc_set_clock(host, ios->clock);
9ae4ed7d 1014 tmio_mmc_set_bus_width(host, ios->bus_width);
3b292bb0
UH		 1015 break;
1016 case MMC_POWER_ON:
1017 tmio_mmc_set_clock(host, ios->clock);
3b292bb0
UH		 1018 tmio_mmc_set_bus_width(host, ios->bus_width);
1019 break;
1020 }
b6147490
GL		 1021
1022 /* Let things settle. delay taken from winCE driver */
1023 udelay(140);
df3ef2d3
GL		 1024 if (PTR_ERR(host->mrq) == -EINTR)
1025 dev_dbg(&host->pdev->dev,
1026 "%s.%d: IOS interrupted: clk %u, mode %u",
1027 current->comm, task_pid_nr(current),
1028 ios->clock, ios->power_mode);
1029 host->mrq = NULL;
b9269fdd 1030
ae12d250
UH		 1031 host->clk_cache = ios->clock;
1032
b9269fdd 1033 mutex_unlock(&host->ios_lock);
b6147490
GL		 1034}
1035
1036static int tmio_mmc_get_ro(struct mmc_host *mmc)
1037{
1038 struct tmio_mmc_host *host = mmc_priv(mmc);
1039 struct tmio_mmc_data *pdata = host->pdata;
3071cafb
GL		 1040 int ret = mmc_gpio_get_ro(mmc);
1041 if (ret >= 0)
1042 return ret;
b6147490 1043
0369483e 1044 ret = !((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
2c54506b 1045 (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT));
0369483e
UH		 1046
1047 return ret;
b6147490
GL		 1048}
1049
bbf0208d
KM		 1050static int tmio_multi_io_quirk(struct mmc_card *card,
1051 unsigned int direction, int blk_size)
1052{
1053 struct tmio_mmc_host *host = mmc_priv(card->host);
bbf0208d 1054
85c02ddd
KM		 1055 if (host->multi_io_quirk)
1056 return host->multi_io_quirk(card, direction, blk_size);
bbf0208d
KM		 1057
1058 return blk_size;
1059}
1060
452e5eef 1061static struct mmc_host_ops tmio_mmc_ops = {
b6147490
GL		 1062 .request = tmio_mmc_request,
1063 .set_ios = tmio_mmc_set_ios,
1064 .get_ro = tmio_mmc_get_ro,
2b63b341 1065 .get_cd = mmc_gpio_get_cd,
b6147490 1066 .enable_sdio_irq = tmio_mmc_enable_sdio_irq,
bbf0208d 1067 .multi_io_quirk = tmio_multi_io_quirk,
e8f36b5d 1068 .hw_reset = tmio_mmc_hw_reset,
4f119977 1069 .execute_tuning = tmio_mmc_execute_tuning,
b6147490
GL		 1070};
1071
05fae4a7 1072static int tmio_mmc_init_ocr(struct tmio_mmc_host *host)
b958a67c
GL		 1073{
1074 struct tmio_mmc_data *pdata = host->pdata;
1075 struct mmc_host *mmc = host->mmc;
1076
1077 mmc_regulator_get_supply(mmc);
1078
05fae4a7 1079 /* use ocr_mask if no regulator */
b958a67c 1080 if (!mmc->ocr_avail)
05fae4a7
KM		 1081 mmc->ocr_avail = pdata->ocr_mask;
1082
1083 /*
1084 * try again.
1085 * There is possibility that regulator has not been probed
1086 */
1087 if (!mmc->ocr_avail)
1088 return -EPROBE_DEFER;
1089
1090 return 0;
b958a67c
GL		 1091}
1092
5a00a971
GL		 1093static void tmio_mmc_of_parse(struct platform_device *pdev,
1094 struct tmio_mmc_data *pdata)
1095{
1096 const struct device_node *np = pdev->dev.of_node;
1097 if (!np)
1098 return;
1099
1100 if (of_get_property(np, "toshiba,mmc-wrprotect-disable", NULL))
1101 pdata->flags |= TMIO_MMC_WRPROTECT_DISABLE;
1102}
1103
94b110af
KM		 1104struct tmio_mmc_host*
1105tmio_mmc_host_alloc(struct platform_device *pdev)
b6147490 1106{
94b110af 1107 struct tmio_mmc_host *host;
b6147490 1108 struct mmc_host *mmc;
94b110af
KM		 1109
1110 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &pdev->dev);
1111 if (!mmc)
1112 return NULL;
1113
1114 host = mmc_priv(mmc);
1115 host->mmc = mmc;
1116 host->pdev = pdev;
1117
1118 return host;
1119}
1120EXPORT_SYMBOL(tmio_mmc_host_alloc);
1121
1122void tmio_mmc_host_free(struct tmio_mmc_host *host)
1123{
1124 mmc_free_host(host->mmc);
94b110af
KM		 1125}
1126EXPORT_SYMBOL(tmio_mmc_host_free);
1127
1128int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
1129 struct tmio_mmc_data *pdata)
1130{
1131 struct platform_device *pdev = _host->pdev;
1132 struct mmc_host *mmc = _host->mmc;
b6147490
GL		 1133 struct resource *res_ctl;
1134 int ret;
1135 u32 irq_mask = TMIO_MASK_CMD;
1136
5a00a971
GL		 1137 tmio_mmc_of_parse(pdev, pdata);
1138
7b952137 1139 if (!(pdata->flags & TMIO_MMC_HAS_IDLE_WAIT))
dfe9a229 1140 _host->write16_hook = NULL;
7b952137 1141
b6147490
GL		 1142 res_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1143 if (!res_ctl)
1144 return -EINVAL;
1145
274a752b
SB		 1146 ret = mmc_of_parse(mmc);
1147 if (ret < 0)
1148 goto host_free;
5a00a971 1149
b6147490 1150 _host->pdata = pdata;
b6147490
GL		 1151 platform_set_drvdata(pdev, mmc);
1152
9d731e75 1153 _host->set_pwr = pdata->set_pwr;
b6147490
GL		 1154 _host->set_clk_div = pdata->set_clk_div;
1155
05fae4a7
KM		 1156 ret = tmio_mmc_init_ocr(_host);
1157 if (ret < 0)
1158 goto host_free;
1159
7df56bbb
IM		 1160 _host->ctl = devm_ioremap(&pdev->dev,
1161 res_ctl->start, resource_size(res_ctl));
b6147490
GL		 1162 if (!_host->ctl) {
1163 ret = -ENOMEM;
1164 goto host_free;
1165 }
1166
6a4679f3 1167 tmio_mmc_ops.card_busy = _host->card_busy;
452e5eef 1168 tmio_mmc_ops.start_signal_voltage_switch = _host->start_signal_voltage_switch;
b6147490 1169 mmc->ops = &tmio_mmc_ops;
452e5eef 1170
5a00a971 1171 mmc->caps |= MMC_CAP_4_BIT_DATA | pdata->capabilities;
dd006b30 1172 mmc->caps2 |= pdata->capabilities2;
b6147490
GL		 1173 mmc->max_segs = 32;
1174 mmc->max_blk_size = 512;
09cbfeaf 1175 mmc->max_blk_count = (PAGE_SIZE / mmc->max_blk_size) *
b6147490
GL		 1176 mmc->max_segs;
1177 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1178 mmc->max_seg_size = mmc->max_req_size;
b6147490 1179
c8be24c2 1180 _host->native_hotplug = !(pdata->flags & TMIO_MMC_USE_GPIO_CD ||
2b1ac5c2 1181 mmc->caps & MMC_CAP_NEEDS_POLL ||
860951c5 1182 !mmc_card_is_removable(mmc) ||
5a00a971 1183 mmc->slot.cd_irq >= 0);
2b1ac5c2 1184
0bc0b6e8
WS		 1185 /*
1186 * On Gen2+, eMMC with NONREMOVABLE currently fails because native
1187 * hotplug gets disabled. It seems RuntimePM related yet we need further
1188 * research. Since we are planning a PM overhaul anyway, let's enforce
1189 * for now the device being active by enabling native hotplug always.
1190 */
1191 if (pdata->flags & TMIO_MMC_MIN_RCAR2)
1192 _host->native_hotplug = true;
1193
2fb55956 1194 if (tmio_mmc_clk_enable(_host) < 0) {
8c102a96
GL		 1195 mmc->f_max = pdata->hclk;
1196 mmc->f_min = mmc->f_max / 512;
1197 }
1198
bb98d9d1
SS		 1199 /*
1200 * Check the sanity of mmc->f_min to prevent tmio_mmc_set_clock() from
1201 * looping forever...
1202 */
1203 if (mmc->f_min == 0) {
1204 ret = -EINVAL;
1205 goto host_free;
1206 }
1207
cbb18b30 1208 /*
0369483e
UH		 1209 * While using internal tmio hardware logic for card detection, we need
1210 * to ensure it stays powered for it to work.
cbb18b30 1211 */
2b1ac5c2 1212 if (_host->native_hotplug)
cbb18b30
BH		 1213 pm_runtime_get_noresume(&pdev->dev);
1214
b6147490
GL		 1215 tmio_mmc_clk_stop(_host);
1216 tmio_mmc_reset(_host);
1217
2c54506b 1218 _host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK);
b6147490 1219 tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL);
e0337cc8
GL		 1220
1221 /* Unmask the IRQs we want to know about */
1222 if (!_host->chan_rx)
1223 irq_mask |= TMIO_MASK_READOP;
1224 if (!_host->chan_tx)
1225 irq_mask |= TMIO_MASK_WRITEOP;
1226 if (!_host->native_hotplug)
1227 irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
1228
1229 _host->sdcard_irq_mask &= ~irq_mask;
1230
7501c431
UH		 1231 _host->sdio_irq_enabled = false;
1232 if (pdata->flags & TMIO_MMC_SDIO_IRQ) {
1233 _host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
1234 sd_ctrl_write16(_host, CTL_SDIO_IRQ_MASK, _host->sdio_irq_mask);
1235 sd_ctrl_write16(_host, CTL_TRANSACTION_CTL, 0x0000);
1236 }
b6147490 1237
b6147490 1238 spin_lock_init(&_host->lock);
b9269fdd 1239 mutex_init(&_host->ios_lock);
b6147490
GL		 1240
1241 /* Init delayed work for request timeouts */
1242 INIT_DELAYED_WORK(&_host->delayed_reset_work, tmio_mmc_reset_work);
b9269fdd 1243 INIT_WORK(&_host->done, tmio_mmc_done_work);
b6147490
GL		 1244
1245 /* See if we also get DMA */
1246 tmio_mmc_request_dma(_host, pdata);
1247
0369483e
UH		 1248 pm_runtime_set_active(&pdev->dev);
1249 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1250 pm_runtime_use_autosuspend(&pdev->dev);
1251 pm_runtime_enable(&pdev->dev);
1252
8c102a96 1253 ret = mmc_add_host(mmc);
8c102a96
GL		 1254 if (ret < 0) {
1255 tmio_mmc_host_remove(_host);
1256 return ret;
1257 }
b6147490 1258
c419e611
RW		 1259 dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1260
c8be24c2 1261 if (pdata->flags & TMIO_MMC_USE_GPIO_CD) {
214fc309 1262 ret = mmc_gpio_request_cd(mmc, pdata->cd_gpio, 0);
c8be24c2
GL		 1263 if (ret < 0) {
1264 tmio_mmc_host_remove(_host);
1265 return ret;
1266 }
d4d11449 1267 mmc_gpiod_request_cd_irq(mmc);
c8be24c2
GL		 1268 }
1269
b6147490
GL		 1270 return 0;
1271
b6147490 1272host_free:
b6147490
GL		 1273
1274 return ret;
1275}
1276EXPORT_SYMBOL(tmio_mmc_host_probe);
1277
1278void tmio_mmc_host_remove(struct tmio_mmc_host *host)
1279{
e6ee7182 1280 struct platform_device *pdev = host->pdev;
c8be24c2
GL		 1281 struct mmc_host *mmc = host->mmc;
1282
2b1ac5c2 1283 if (!host->native_hotplug)
7311bef0
GL		 1284 pm_runtime_get_sync(&pdev->dev);
1285
c419e611
RW		 1286 dev_pm_qos_hide_latency_limit(&pdev->dev);
1287
c8be24c2 1288 mmc_remove_host(mmc);
b9269fdd 1289 cancel_work_sync(&host->done);
b6147490
GL		 1290 cancel_delayed_work_sync(&host->delayed_reset_work);
1291 tmio_mmc_release_dma(host);
e6ee7182 1292
e6ee7182
GL		 1293 pm_runtime_put_sync(&pdev->dev);
1294 pm_runtime_disable(&pdev->dev);
b6147490
GL		 1295}
1296EXPORT_SYMBOL(tmio_mmc_host_remove);
1297
9ade7dbf 1298#ifdef CONFIG_PM
7311bef0
GL		 1299int tmio_mmc_host_runtime_suspend(struct device *dev)
1300{
ae12d250
UH		 1301 struct mmc_host *mmc = dev_get_drvdata(dev);
1302 struct tmio_mmc_host *host = mmc_priv(mmc);
1303
20e955c3
UH		 1304 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL);
1305
ae12d250
UH		 1306 if (host->clk_cache)
1307 tmio_mmc_clk_stop(host);
1308
00452c11 1309 if (host->clk_disable)
0ea28210 1310 host->clk_disable(host);
ae12d250 1311
7311bef0
GL		 1312 return 0;
1313}
1314EXPORT_SYMBOL(tmio_mmc_host_runtime_suspend);
1315
4f119977
AK		 1316static bool tmio_mmc_can_retune(struct tmio_mmc_host *host)
1317{
1318 return host->tap_num && mmc_can_retune(host->mmc);
1319}
1320
7311bef0
GL		 1321int tmio_mmc_host_runtime_resume(struct device *dev)
1322{
1323 struct mmc_host *mmc = dev_get_drvdata(dev);
1324 struct tmio_mmc_host *host = mmc_priv(mmc);
7311bef0 1325
ae12d250 1326 tmio_mmc_reset(host);
2fb55956 1327 tmio_mmc_clk_enable(host);
ae12d250 1328
7fbc030d 1329 if (host->clk_cache)
ae12d250 1330 tmio_mmc_set_clock(host, host->clk_cache);
ae12d250 1331
162f43e3 1332 tmio_mmc_enable_dma(host, true);
7311bef0 1333
4f119977
AK		 1334 if (tmio_mmc_can_retune(host) && host->select_tuning(host))
1335 dev_warn(&host->pdev->dev, "Tuning selection failed\n");
1336
7311bef0
GL		 1337 return 0;
1338}
1339EXPORT_SYMBOL(tmio_mmc_host_runtime_resume);
710dec95 1340#endif
7311bef0 1341
b6147490 1342MODULE_LICENSE("GPL v2");
Ubuntu Artful kernel mirror