[mirror_ubuntu-artful-kernel.git] / drivers / mmc / pxamci.c

/*
 *  linux/drivers/mmc/pxa.c - PXA MMCI driver
 *
 *  Copyright (C) 2003 Russell King, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This hardware is really sick:
 *   - No way to clear interrupts.
 *   - Have to turn off the clock whenever we touch the device.
 *   - Doesn't tell you how many data blocks were transferred.
 *  Yuck!
 *
 *	1 and 3 byte data transfers not supported
 *	max block length up to 1023
 */
#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/mmc/host.h>
#include <linux/mmc/protocol.h>

#include <asm/dma.h>
#include <asm/io.h>
#include <asm/scatterlist.h>
#include <asm/sizes.h>

#include <asm/arch/pxa-regs.h>
#include <asm/arch/mmc.h>

#include "pxamci.h"

#define DRIVER_NAME	"pxa2xx-mci"

#define NR_SG	1

struct pxamci_host {
	struct mmc_host		*mmc;
	spinlock_t		lock;
	struct resource		*res;
	void __iomem		*base;
	int			irq;
	int			dma;
	unsigned int		clkrt;
	unsigned int		cmdat;
	unsigned int		imask;
	unsigned int		power_mode;
	struct pxamci_platform_data *pdata;

	struct mmc_request	*mrq;
	struct mmc_command	*cmd;
	struct mmc_data		*data;

	dma_addr_t		sg_dma;
	struct pxa_dma_desc	*sg_cpu;
	unsigned int		dma_len;

	unsigned int		dma_dir;
};

static void pxamci_stop_clock(struct pxamci_host *host)
{
	if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
		unsigned long timeout = 10000;
		unsigned int v;

		writel(STOP_CLOCK, host->base + MMC_STRPCL);

		do {
			v = readl(host->base + MMC_STAT);
			if (!(v & STAT_CLK_EN))
				break;
			udelay(1);
		} while (timeout--);

		if (v & STAT_CLK_EN)
			dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
	}
}

static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
{
	unsigned long flags;

	spin_lock_irqsave(&host->lock, flags);
	host->imask &= ~mask;
	writel(host->imask, host->base + MMC_I_MASK);
	spin_unlock_irqrestore(&host->lock, flags);
}

static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
{
	unsigned long flags;

	spin_lock_irqsave(&host->lock, flags);
	host->imask |= mask;
	writel(host->imask, host->base + MMC_I_MASK);
	spin_unlock_irqrestore(&host->lock, flags);
}

static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
{
	unsigned int nob = data->blocks;
	unsigned long long clks;
	unsigned int timeout;
	u32 dcmd;
	int i;

	host->data = data;

	if (data->flags & MMC_DATA_STREAM)
		nob = 0xffff;

	writel(nob, host->base + MMC_NOB);
	writel(1 << data->blksz_bits, host->base + MMC_BLKLEN);

	clks = (unsigned long long)data->timeout_ns * CLOCKRATE;
	do_div(clks, 1000000000UL);
	timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
	writel((timeout + 255) / 256, host->base + MMC_RDTO);

	if (data->flags & MMC_DATA_READ) {
		host->dma_dir = DMA_FROM_DEVICE;
		dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG;
		DRCMRTXMMC = 0;
		DRCMRRXMMC = host->dma | DRCMR_MAPVLD;
	} else {
		host->dma_dir = DMA_TO_DEVICE;
		dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC;
		DRCMRRXMMC = 0;
		DRCMRTXMMC = host->dma | DRCMR_MAPVLD;
	}

	dcmd |= DCMD_BURST32 | DCMD_WIDTH1;

	host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
				   host->dma_dir);

	for (i = 0; i < host->dma_len; i++) {
		if (data->flags & MMC_DATA_READ) {
			host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
			host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
		} else {
			host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
			host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
		}
		host->sg_cpu[i].dcmd = dcmd | sg_dma_len(&data->sg[i]);
		host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
					sizeof(struct pxa_dma_desc);
	}
	host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
	wmb();

	DDADR(host->dma) = host->sg_dma;
	DCSR(host->dma) = DCSR_RUN;
}

static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
{
	WARN_ON(host->cmd != NULL);
	host->cmd = cmd;

	if (cmd->flags & MMC_RSP_BUSY)
		cmdat |= CMDAT_BUSY;

#define RSP_TYPE(x)	((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
	switch (RSP_TYPE(mmc_resp_type(cmd))) {
	case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6 */
		cmdat |= CMDAT_RESP_SHORT;
		break;
	case RSP_TYPE(MMC_RSP_R3):
		cmdat |= CMDAT_RESP_R3;
		break;
	case RSP_TYPE(MMC_RSP_R2):
		cmdat |= CMDAT_RESP_R2;
		break;
	default:
		break;
	}

	writel(cmd->opcode, host->base + MMC_CMD);
	writel(cmd->arg >> 16, host->base + MMC_ARGH);
	writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
	writel(cmdat, host->base + MMC_CMDAT);
	writel(host->clkrt, host->base + MMC_CLKRT);

	writel(START_CLOCK, host->base + MMC_STRPCL);

	pxamci_enable_irq(host, END_CMD_RES);
}

static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
{
	pr_debug("PXAMCI: request done\n");
	host->mrq = NULL;
	host->cmd = NULL;
	host->data = NULL;
	mmc_request_done(host->mmc, mrq);
}

static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
{
	struct mmc_command *cmd = host->cmd;
	int i;
	u32 v;

	if (!cmd)
		return 0;

	host->cmd = NULL;

	/*
	 * Did I mention this is Sick.  We always need to
	 * discard the upper 8 bits of the first 16-bit word.
	 */
	v = readl(host->base + MMC_RES) & 0xffff;
	for (i = 0; i < 4; i++) {
		u32 w1 = readl(host->base + MMC_RES) & 0xffff;
		u32 w2 = readl(host->base + MMC_RES) & 0xffff;
		cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
		v = w2;
	}

	if (stat & STAT_TIME_OUT_RESPONSE) {
		cmd->error = MMC_ERR_TIMEOUT;
	} else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
#ifdef CONFIG_PXA27x
		/*
		 * workaround for erratum #42:
		 * Intel PXA27x Family Processor Specification Update Rev 001
		 */
		if (cmd->opcode == MMC_ALL_SEND_CID ||
		    cmd->opcode == MMC_SEND_CSD ||
		    cmd->opcode == MMC_SEND_CID) {
			/* a bogus CRC error can appear if the msb of
			   the 15 byte response is a one */
			if ((cmd->resp[0] & 0x80000000) == 0)
				cmd->error = MMC_ERR_BADCRC;
		} else {
			pr_debug("ignoring CRC from command %d - *risky*\n",cmd->opcode);
		}
#else
		cmd->error = MMC_ERR_BADCRC;
#endif
	}

	pxamci_disable_irq(host, END_CMD_RES);
	if (host->data && cmd->error == MMC_ERR_NONE) {
		pxamci_enable_irq(host, DATA_TRAN_DONE);
	} else {
		pxamci_finish_request(host, host->mrq);
	}

	return 1;
}

static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
{
	struct mmc_data *data = host->data;

	if (!data)
		return 0;

	DCSR(host->dma) = 0;
	dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
		     host->dma_dir);

	if (stat & STAT_READ_TIME_OUT)
		data->error = MMC_ERR_TIMEOUT;
	else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
		data->error = MMC_ERR_BADCRC;

	/*
	 * There appears to be a hardware design bug here.  There seems to
	 * be no way to find out how much data was transferred to the card.
	 * This means that if there was an error on any block, we mark all
	 * data blocks as being in error.
	 */
	if (data->error == MMC_ERR_NONE)
		data->bytes_xfered = data->blocks << data->blksz_bits;
	else
		data->bytes_xfered = 0;

	pxamci_disable_irq(host, DATA_TRAN_DONE);

	host->data = NULL;
	if (host->mrq->stop) {
		pxamci_stop_clock(host);
		pxamci_start_cmd(host, host->mrq->stop, 0);
	} else {
		pxamci_finish_request(host, host->mrq);
	}

	return 1;
}

static irqreturn_t pxamci_irq(int irq, void *devid, struct pt_regs *regs)
{
	struct pxamci_host *host = devid;
	unsigned int ireg;
	int handled = 0;

	ireg = readl(host->base + MMC_I_REG);

	pr_debug("PXAMCI: irq %08x\n", ireg);

	if (ireg) {
		unsigned stat = readl(host->base + MMC_STAT);

		pr_debug("PXAMCI: stat %08x\n", stat);

		if (ireg & END_CMD_RES)
			handled |= pxamci_cmd_done(host, stat);
		if (ireg & DATA_TRAN_DONE)
			handled |= pxamci_data_done(host, stat);
	}

	return IRQ_RETVAL(handled);
}

static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
	struct pxamci_host *host = mmc_priv(mmc);
	unsigned int cmdat;

	WARN_ON(host->mrq != NULL);

	host->mrq = mrq;

	pxamci_stop_clock(host);

	cmdat = host->cmdat;
	host->cmdat &= ~CMDAT_INIT;

	if (mrq->data) {
		pxamci_setup_data(host, mrq->data);

		cmdat &= ~CMDAT_BUSY;
		cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
		if (mrq->data->flags & MMC_DATA_WRITE)
			cmdat |= CMDAT_WRITE;

		if (mrq->data->flags & MMC_DATA_STREAM)
			cmdat |= CMDAT_STREAM;
	}

	pxamci_start_cmd(host, mrq->cmd, cmdat);
}

static int pxamci_get_ro(struct mmc_host *mmc)
{
	struct pxamci_host *host = mmc_priv(mmc);

	if (host->pdata && host->pdata->get_ro)
		return host->pdata->get_ro(mmc->dev);
	/* Host doesn't support read only detection so assume writeable */
	return 0;
}

static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
	struct pxamci_host *host = mmc_priv(mmc);

	pr_debug("pxamci_set_ios: clock %u power %u vdd %u.%02u\n",
		 ios->clock, ios->power_mode, ios->vdd / 100,
		 ios->vdd % 100);

	if (ios->clock) {
		unsigned int clk = CLOCKRATE / ios->clock;
		if (CLOCKRATE / clk > ios->clock)
			clk <<= 1;
		host->clkrt = fls(clk) - 1;
		pxa_set_cken(CKEN12_MMC, 1);

		/*
		 * we write clkrt on the next command
		 */
	} else {
		pxamci_stop_clock(host);
		pxa_set_cken(CKEN12_MMC, 0);
	}

	if (host->power_mode != ios->power_mode) {
		host->power_mode = ios->power_mode;

		if (host->pdata && host->pdata->setpower)
			host->pdata->setpower(mmc->dev, ios->vdd);

		if (ios->power_mode == MMC_POWER_ON)
			host->cmdat |= CMDAT_INIT;
	}

	pr_debug("pxamci_set_ios: clkrt = %x cmdat = %x\n",
		 host->clkrt, host->cmdat);
}

static struct mmc_host_ops pxamci_ops = {
	.request	= pxamci_request,
	.get_ro		= pxamci_get_ro,
	.set_ios	= pxamci_set_ios,
};

static void pxamci_dma_irq(int dma, void *devid, struct pt_regs *regs)
{
	printk(KERN_ERR "DMA%d: IRQ???\n", dma);
	DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
}

static irqreturn_t pxamci_detect_irq(int irq, void *devid, struct pt_regs *regs)
{
	struct pxamci_host *host = mmc_priv(devid);

	mmc_detect_change(devid, host->pdata->detect_delay);
	return IRQ_HANDLED;
}

static int pxamci_probe(struct platform_device *pdev)
{
	struct mmc_host *mmc;
	struct pxamci_host *host = NULL;
	struct resource *r;
	int ret, irq;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq = platform_get_irq(pdev, 0);
	if (!r || irq < 0)
		return -ENXIO;

	r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
	if (!r)
		return -EBUSY;

	mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);
	if (!mmc) {
		ret = -ENOMEM;
		goto out;
	}

	mmc->ops = &pxamci_ops;
	mmc->f_min = CLOCKRATE_MIN;
	mmc->f_max = CLOCKRATE_MAX;

	/*
	 * We can do SG-DMA, but we don't because we never know how much
	 * data we successfully wrote to the card.
	 */
	mmc->max_phys_segs = NR_SG;

	/*
	 * Our hardware DMA can handle a maximum of one page per SG entry.
	 */
	mmc->max_seg_size = PAGE_SIZE;

	host = mmc_priv(mmc);
	host->mmc = mmc;
	host->dma = -1;
	host->pdata = pdev->dev.platform_data;
	mmc->ocr_avail = host->pdata ?
			 host->pdata->ocr_mask :
			 MMC_VDD_32_33|MMC_VDD_33_34;

	host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
	if (!host->sg_cpu) {
		ret = -ENOMEM;
		goto out;
	}

	spin_lock_init(&host->lock);
	host->res = r;
	host->irq = irq;
	host->imask = MMC_I_MASK_ALL;

	host->base = ioremap(r->start, SZ_4K);
	if (!host->base) {
		ret = -ENOMEM;
		goto out;
	}

	/*
	 * Ensure that the host controller is shut down, and setup
	 * with our defaults.
	 */
	pxamci_stop_clock(host);
	writel(0, host->base + MMC_SPI);
	writel(64, host->base + MMC_RESTO);
	writel(host->imask, host->base + MMC_I_MASK);

	host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
				    pxamci_dma_irq, host);
	if (host->dma < 0) {
		ret = -EBUSY;
		goto out;
	}

	ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
	if (ret)
		goto out;

	platform_set_drvdata(pdev, mmc);

	if (host->pdata && host->pdata->init)
		host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);

	mmc_add_host(mmc);

	return 0;

 out:
	if (host) {
		if (host->dma >= 0)
			pxa_free_dma(host->dma);
		if (host->base)
			iounmap(host->base);
		if (host->sg_cpu)
			dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
	}
	if (mmc)
		mmc_free_host(mmc);
	release_resource(r);
	return ret;
}

static int pxamci_remove(struct platform_device *pdev)
{
	struct mmc_host *mmc = platform_get_drvdata(pdev);

	platform_set_drvdata(pdev, NULL);

	if (mmc) {
		struct pxamci_host *host = mmc_priv(mmc);

		if (host->pdata && host->pdata->exit)
			host->pdata->exit(&pdev->dev, mmc);

		mmc_remove_host(mmc);

		pxamci_stop_clock(host);
		writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
		       END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
		       host->base + MMC_I_MASK);

		DRCMRRXMMC = 0;
		DRCMRTXMMC = 0;

		free_irq(host->irq, host);
		pxa_free_dma(host->dma);
		iounmap(host->base);
		dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);

		release_resource(host->res);

		mmc_free_host(mmc);
	}
	return 0;
}

#ifdef CONFIG_PM
static int pxamci_suspend(struct platform_device *dev, pm_message_t state)
{
	struct mmc_host *mmc = platform_get_drvdata(dev);
	int ret = 0;

	if (mmc)
		ret = mmc_suspend_host(mmc, state);

	return ret;
}

static int pxamci_resume(struct platform_device *dev)
{
	struct mmc_host *mmc = platform_get_drvdata(dev);
	int ret = 0;

	if (mmc)
		ret = mmc_resume_host(mmc);

	return ret;
}
#else
#define pxamci_suspend	NULL
#define pxamci_resume	NULL
#endif

static struct platform_driver pxamci_driver = {
	.probe		= pxamci_probe,
	.remove		= pxamci_remove,
	.suspend	= pxamci_suspend,
	.resume		= pxamci_resume,
	.driver		= {
		.name	= DRIVER_NAME,
	},
};

static int __init pxamci_init(void)
{
	return platform_driver_register(&pxamci_driver);
}

static void __exit pxamci_exit(void)
{
	platform_driver_unregister(&pxamci_driver);
}

module_init(pxamci_init);
module_exit(pxamci_exit);

MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/mmc/pxa.c - PXA MMCI driver
	3	*
	4	* Copyright (C) 2003 Russell King, All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This hardware is really sick:
	11	* - No way to clear interrupts.
	12	* - Have to turn off the clock whenever we touch the device.
	13	* - Doesn't tell you how many data blocks were transferred.
	14	* Yuck!
	15	*
	16	* 1 and 3 byte data transfers not supported
	17	* max block length up to 1023
	18	*/
	19	#include <linux/config.h>
	20	#include <linux/module.h>
	21	#include <linux/init.h>
	22	#include <linux/ioport.h>
d052d1be	23	#include <linux/platform_device.h>
1da177e4 LT	24	#include <linux/delay.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/dma-mapping.h>
	27	#include <linux/mmc/host.h>
	28	#include <linux/mmc/protocol.h>
	29
	30	#include <asm/dma.h>
	31	#include <asm/io.h>
1da177e4 LT	32	#include <asm/scatterlist.h>
	33	#include <asm/sizes.h>
	34
	35	#include <asm/arch/pxa-regs.h>
	36	#include <asm/arch/mmc.h>
	37
	38	#include "pxamci.h"
	39
1da177e4 LT	40	#define DRIVER_NAME "pxa2xx-mci"
	41
	42	#define NR_SG 1
	43
	44	struct pxamci_host {
	45	struct mmc_host *mmc;
	46	spinlock_t lock;
	47	struct resource *res;
	48	void __iomem *base;
	49	int irq;
	50	int dma;
	51	unsigned int clkrt;
	52	unsigned int cmdat;
	53	unsigned int imask;
	54	unsigned int power_mode;
	55	struct pxamci_platform_data *pdata;
	56
	57	struct mmc_request *mrq;
	58	struct mmc_command *cmd;
	59	struct mmc_data *data;
	60
	61	dma_addr_t sg_dma;
	62	struct pxa_dma_desc *sg_cpu;
	63	unsigned int dma_len;
	64
	65	unsigned int dma_dir;
	66	};
	67
1da177e4 LT	68	static void pxamci_stop_clock(struct pxamci_host *host)
	69	{
	70	if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
	71	unsigned long timeout = 10000;
	72	unsigned int v;
	73
	74	writel(STOP_CLOCK, host->base + MMC_STRPCL);
	75
	76	do {
	77	v = readl(host->base + MMC_STAT);
	78	if (!(v & STAT_CLK_EN))
	79	break;
	80	udelay(1);
	81	} while (timeout--);
	82
	83	if (v & STAT_CLK_EN)
	84	dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
	85	}
	86	}
	87
	88	static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
	89	{
	90	unsigned long flags;
	91
	92	spin_lock_irqsave(&host->lock, flags);
	93	host->imask &= ~mask;
	94	writel(host->imask, host->base + MMC_I_MASK);
	95	spin_unlock_irqrestore(&host->lock, flags);
	96	}
	97
	98	static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
	99	{
	100	unsigned long flags;
	101
	102	spin_lock_irqsave(&host->lock, flags);
	103	host->imask \|= mask;
	104	writel(host->imask, host->base + MMC_I_MASK);
	105	spin_unlock_irqrestore(&host->lock, flags);
	106	}
	107
	108	static void pxamci_setup_data(struct pxamci_host host, struct mmc_data data)
	109	{
	110	unsigned int nob = data->blocks;
3d63abe5	111	unsigned long long clks;
1da177e4 LT	112	unsigned int timeout;
	113	u32 dcmd;
	114	int i;
	115
	116	host->data = data;
	117
	118	if (data->flags & MMC_DATA_STREAM)
	119	nob = 0xffff;
	120
	121	writel(nob, host->base + MMC_NOB);
	122	writel(1 << data->blksz_bits, host->base + MMC_BLKLEN);
	123
3d63abe5 RK	124	clks = (unsigned long long)data->timeout_ns * CLOCKRATE;
	125	do_div(clks, 1000000000UL);
	126	timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
1da177e4 LT	127	writel((timeout + 255) / 256, host->base + MMC_RDTO);
	128
	129	if (data->flags & MMC_DATA_READ) {
	130	host->dma_dir = DMA_FROM_DEVICE;
	131	dcmd = DCMD_INCTRGADDR \| DCMD_FLOWTRG;
	132	DRCMRTXMMC = 0;
	133	DRCMRRXMMC = host->dma \| DRCMR_MAPVLD;
	134	} else {
	135	host->dma_dir = DMA_TO_DEVICE;
	136	dcmd = DCMD_INCSRCADDR \| DCMD_FLOWSRC;
	137	DRCMRRXMMC = 0;
	138	DRCMRTXMMC = host->dma \| DRCMR_MAPVLD;
	139	}
	140
	141	dcmd \|= DCMD_BURST32 \| DCMD_WIDTH1;
	142
	143	host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
	144	host->dma_dir);
	145
	146	for (i = 0; i < host->dma_len; i++) {
	147	if (data->flags & MMC_DATA_READ) {
	148	host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
	149	host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
	150	} else {
	151	host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
	152	host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
	153	}
	154	host->sg_cpu[i].dcmd = dcmd \| sg_dma_len(&data->sg[i]);
	155	host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
	156	sizeof(struct pxa_dma_desc);
	157	}
	158	host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
	159	wmb();
	160
	161	DDADR(host->dma) = host->sg_dma;
	162	DCSR(host->dma) = DCSR_RUN;
	163	}
	164
	165	static void pxamci_start_cmd(struct pxamci_host host, struct mmc_command cmd, unsigned int cmdat)
	166	{
	167	WARN_ON(host->cmd != NULL);
	168	host->cmd = cmd;
	169
	170	if (cmd->flags & MMC_RSP_BUSY)
	171	cmdat \|= CMDAT_BUSY;
	172
e9225176 RK	173	#define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY\|MMC_RSP_OPCODE))
	174	switch (RSP_TYPE(mmc_resp_type(cmd))) {
	175	case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6 */
1da177e4 LT	176	cmdat \|= CMDAT_RESP_SHORT;
1da177e4 LT	177	break;
e9225176	178	case RSP_TYPE(MMC_RSP_R3):
1da177e4 LT	179	cmdat \|= CMDAT_RESP_R3;
1da177e4 LT	180	break;
e9225176	181	case RSP_TYPE(MMC_RSP_R2):
1da177e4 LT	182	cmdat \|= CMDAT_RESP_R2;
	183	break;
	184	default:
	185	break;
	186	}
	187
	188	writel(cmd->opcode, host->base + MMC_CMD);
	189	writel(cmd->arg >> 16, host->base + MMC_ARGH);
	190	writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
	191	writel(cmdat, host->base + MMC_CMDAT);
	192	writel(host->clkrt, host->base + MMC_CLKRT);
	193
	194	writel(START_CLOCK, host->base + MMC_STRPCL);
	195
	196	pxamci_enable_irq(host, END_CMD_RES);
	197	}
	198
	199	static void pxamci_finish_request(struct pxamci_host host, struct mmc_request mrq)
	200	{
c6563178	201	pr_debug("PXAMCI: request done\n");
1da177e4 LT	202	host->mrq = NULL;
	203	host->cmd = NULL;
	204	host->data = NULL;
	205	mmc_request_done(host->mmc, mrq);
	206	}
	207
	208	static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
	209	{
	210	struct mmc_command *cmd = host->cmd;
	211	int i;
	212	u32 v;
	213
	214	if (!cmd)
	215	return 0;
	216
	217	host->cmd = NULL;
	218
	219	/*
	220	* Did I mention this is Sick. We always need to
	221	* discard the upper 8 bits of the first 16-bit word.
	222	*/
	223	v = readl(host->base + MMC_RES) & 0xffff;
	224	for (i = 0; i < 4; i++) {
	225	u32 w1 = readl(host->base + MMC_RES) & 0xffff;
	226	u32 w2 = readl(host->base + MMC_RES) & 0xffff;
	227	cmd->resp[i] = v << 24 \| w1 << 8 \| w2 >> 8;
	228	v = w2;
	229	}
	230
	231	if (stat & STAT_TIME_OUT_RESPONSE) {
	232	cmd->error = MMC_ERR_TIMEOUT;
	233	} else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
	234	#ifdef CONFIG_PXA27x
	235	/*
	236	* workaround for erratum #42:
	237	* Intel PXA27x Family Processor Specification Update Rev 001
	238	*/
	239	if (cmd->opcode == MMC_ALL_SEND_CID \|\|
	240	cmd->opcode == MMC_SEND_CSD \|\|
	241	cmd->opcode == MMC_SEND_CID) {
	242	/* a bogus CRC error can appear if the msb of
	243	the 15 byte response is a one */
	244	if ((cmd->resp[0] & 0x80000000) == 0)
	245	cmd->error = MMC_ERR_BADCRC;
	246	} else {
c6563178	247	pr_debug("ignoring CRC from command %d - risky\n",cmd->opcode);
1da177e4 LT	248	}
	249	#else
	250	cmd->error = MMC_ERR_BADCRC;
	251	#endif
	252	}
	253
	254	pxamci_disable_irq(host, END_CMD_RES);
	255	if (host->data && cmd->error == MMC_ERR_NONE) {
	256	pxamci_enable_irq(host, DATA_TRAN_DONE);
	257	} else {
	258	pxamci_finish_request(host, host->mrq);
	259	}
	260
	261	return 1;
	262	}
	263
	264	static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
	265	{
	266	struct mmc_data *data = host->data;
	267
	268	if (!data)
	269	return 0;
	270
	271	DCSR(host->dma) = 0;
	272	dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
	273	host->dma_dir);
	274
	275	if (stat & STAT_READ_TIME_OUT)
	276	data->error = MMC_ERR_TIMEOUT;
	277	else if (stat & (STAT_CRC_READ_ERROR\|STAT_CRC_WRITE_ERROR))
	278	data->error = MMC_ERR_BADCRC;
	279
	280	/*
	281	* There appears to be a hardware design bug here. There seems to
	282	* be no way to find out how much data was transferred to the card.
	283	* This means that if there was an error on any block, we mark all
	284	* data blocks as being in error.
	285	*/
	286	if (data->error == MMC_ERR_NONE)
	287	data->bytes_xfered = data->blocks << data->blksz_bits;
	288	else
	289	data->bytes_xfered = 0;
	290
	291	pxamci_disable_irq(host, DATA_TRAN_DONE);
	292
	293	host->data = NULL;
58741e8b	294	if (host->mrq->stop) {
1da177e4 LT	295	pxamci_stop_clock(host);
	296	pxamci_start_cmd(host, host->mrq->stop, 0);
	297	} else {
	298	pxamci_finish_request(host, host->mrq);
	299	}
	300
	301	return 1;
	302	}
	303
	304	static irqreturn_t pxamci_irq(int irq, void devid, struct pt_regs regs)
	305	{
	306	struct pxamci_host *host = devid;
	307	unsigned int ireg;
	308	int handled = 0;
	309
	310	ireg = readl(host->base + MMC_I_REG);
	311
c6563178	312	pr_debug("PXAMCI: irq %08x\n", ireg);
1da177e4 LT	313
	314	if (ireg) {
	315	unsigned stat = readl(host->base + MMC_STAT);
	316
c6563178	317	pr_debug("PXAMCI: stat %08x\n", stat);
1da177e4 LT	318
	319	if (ireg & END_CMD_RES)
	320	handled \|= pxamci_cmd_done(host, stat);
	321	if (ireg & DATA_TRAN_DONE)
	322	handled \|= pxamci_data_done(host, stat);
	323	}
	324
	325	return IRQ_RETVAL(handled);
	326	}
	327
	328	static void pxamci_request(struct mmc_host mmc, struct mmc_request mrq)
	329	{
	330	struct pxamci_host *host = mmc_priv(mmc);
	331	unsigned int cmdat;
	332
	333	WARN_ON(host->mrq != NULL);
	334
	335	host->mrq = mrq;
	336
	337	pxamci_stop_clock(host);
	338
	339	cmdat = host->cmdat;
	340	host->cmdat &= ~CMDAT_INIT;
	341
	342	if (mrq->data) {
	343	pxamci_setup_data(host, mrq->data);
	344
	345	cmdat &= ~CMDAT_BUSY;
	346	cmdat \|= CMDAT_DATAEN \| CMDAT_DMAEN;
	347	if (mrq->data->flags & MMC_DATA_WRITE)
	348	cmdat \|= CMDAT_WRITE;
	349
	350	if (mrq->data->flags & MMC_DATA_STREAM)
	351	cmdat \|= CMDAT_STREAM;
	352	}
	353
	354	pxamci_start_cmd(host, mrq->cmd, cmdat);
	355	}
	356
e619524f RP	357	static int pxamci_get_ro(struct mmc_host *mmc)
	358	{
	359	struct pxamci_host *host = mmc_priv(mmc);
	360
	361	if (host->pdata && host->pdata->get_ro)
	362	return host->pdata->get_ro(mmc->dev);
	363	/* Host doesn't support read only detection so assume writeable */
	364	return 0;
	365	}
	366
1da177e4 LT	367	static void pxamci_set_ios(struct mmc_host mmc, struct mmc_ios ios)
	368	{
	369	struct pxamci_host *host = mmc_priv(mmc);
	370
c6563178 RK	371	pr_debug("pxamci_set_ios: clock %u power %u vdd %u.%02u\n",
	372	ios->clock, ios->power_mode, ios->vdd / 100,
	373	ios->vdd % 100);
1da177e4 LT	374
	375	if (ios->clock) {
	376	unsigned int clk = CLOCKRATE / ios->clock;
	377	if (CLOCKRATE / clk > ios->clock)
	378	clk <<= 1;
	379	host->clkrt = fls(clk) - 1;
	380	pxa_set_cken(CKEN12_MMC, 1);
	381
	382	/*
	383	* we write clkrt on the next command
	384	*/
	385	} else {
	386	pxamci_stop_clock(host);
	387	pxa_set_cken(CKEN12_MMC, 0);
	388	}
	389
	390	if (host->power_mode != ios->power_mode) {
	391	host->power_mode = ios->power_mode;
	392
	393	if (host->pdata && host->pdata->setpower)
	394	host->pdata->setpower(mmc->dev, ios->vdd);
	395
	396	if (ios->power_mode == MMC_POWER_ON)
	397	host->cmdat \|= CMDAT_INIT;
	398	}
	399
c6563178 RK	400	pr_debug("pxamci_set_ios: clkrt = %x cmdat = %x\n",
c6563178 RK	401	host->clkrt, host->cmdat);
1da177e4 LT	402	}
	403
	404	static struct mmc_host_ops pxamci_ops = {
	405	.request = pxamci_request,
e619524f	406	.get_ro = pxamci_get_ro,
1da177e4 LT	407	.set_ios = pxamci_set_ios,
	408	};
	409
	410	static void pxamci_dma_irq(int dma, void devid, struct pt_regs regs)
	411	{
	412	printk(KERN_ERR "DMA%d: IRQ???\n", dma);
	413	DCSR(dma) = DCSR_STARTINTR\|DCSR_ENDINTR\|DCSR_BUSERR;
	414	}
	415
	416	static irqreturn_t pxamci_detect_irq(int irq, void devid, struct pt_regs regs)
	417	{
c26971cb RP	418	struct pxamci_host *host = mmc_priv(devid);
	419
	420	mmc_detect_change(devid, host->pdata->detect_delay);
1da177e4 LT	421	return IRQ_HANDLED;
	422	}
	423
3ae5eaec	424	static int pxamci_probe(struct platform_device *pdev)
1da177e4	425	{
1da177e4 LT	426	struct mmc_host *mmc;
	427	struct pxamci_host *host = NULL;
	428	struct resource *r;
	429	int ret, irq;
	430
	431	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	432	irq = platform_get_irq(pdev, 0);
48944738	433	if (!r \|\| irq < 0)
1da177e4 LT	434	return -ENXIO;
	435
	436	r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
	437	if (!r)
	438	return -EBUSY;
	439
3ae5eaec	440	mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);
1da177e4 LT	441	if (!mmc) {
	442	ret = -ENOMEM;
	443	goto out;
	444	}
	445
	446	mmc->ops = &pxamci_ops;
	447	mmc->f_min = CLOCKRATE_MIN;
	448	mmc->f_max = CLOCKRATE_MAX;
	449
	450	/*
	451	* We can do SG-DMA, but we don't because we never know how much
	452	* data we successfully wrote to the card.
	453	*/
	454	mmc->max_phys_segs = NR_SG;
	455
	456	/*
	457	* Our hardware DMA can handle a maximum of one page per SG entry.
	458	*/
	459	mmc->max_seg_size = PAGE_SIZE;
	460
	461	host = mmc_priv(mmc);
	462	host->mmc = mmc;
	463	host->dma = -1;
	464	host->pdata = pdev->dev.platform_data;
	465	mmc->ocr_avail = host->pdata ?
	466	host->pdata->ocr_mask :
	467	MMC_VDD_32_33\|MMC_VDD_33_34;
	468
3ae5eaec	469	host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
1da177e4 LT	470	if (!host->sg_cpu) {
	471	ret = -ENOMEM;
	472	goto out;
	473	}
	474
	475	spin_lock_init(&host->lock);
	476	host->res = r;
	477	host->irq = irq;
	478	host->imask = MMC_I_MASK_ALL;
	479
	480	host->base = ioremap(r->start, SZ_4K);
	481	if (!host->base) {
	482	ret = -ENOMEM;
	483	goto out;
	484	}
	485
	486	/*
	487	* Ensure that the host controller is shut down, and setup
	488	* with our defaults.
	489	*/
	490	pxamci_stop_clock(host);
	491	writel(0, host->base + MMC_SPI);
	492	writel(64, host->base + MMC_RESTO);
	493	writel(host->imask, host->base + MMC_I_MASK);
	494
	495	host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
	496	pxamci_dma_irq, host);
	497	if (host->dma < 0) {
	498	ret = -EBUSY;
	499	goto out;
	500	}
	501
	502	ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
	503	if (ret)
	504	goto out;
	505
3ae5eaec	506	platform_set_drvdata(pdev, mmc);
1da177e4 LT	507
1da177e4 LT	508	if (host->pdata && host->pdata->init)
3ae5eaec	509	host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);
1da177e4 LT	510
	511	mmc_add_host(mmc);
	512
	513	return 0;
	514
	515	out:
	516	if (host) {
	517	if (host->dma >= 0)
	518	pxa_free_dma(host->dma);
	519	if (host->base)
	520	iounmap(host->base);
	521	if (host->sg_cpu)
3ae5eaec	522	dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1da177e4 LT	523	}
	524	if (mmc)
	525	mmc_free_host(mmc);
	526	release_resource(r);
	527	return ret;
	528	}
	529
3ae5eaec	530	static int pxamci_remove(struct platform_device *pdev)
1da177e4	531	{
3ae5eaec	532	struct mmc_host *mmc = platform_get_drvdata(pdev);
1da177e4	533
3ae5eaec	534	platform_set_drvdata(pdev, NULL);
1da177e4 LT	535
	536	if (mmc) {
	537	struct pxamci_host *host = mmc_priv(mmc);
	538
	539	if (host->pdata && host->pdata->exit)
3ae5eaec	540	host->pdata->exit(&pdev->dev, mmc);
1da177e4 LT	541
	542	mmc_remove_host(mmc);
	543
	544	pxamci_stop_clock(host);
	545	writel(TXFIFO_WR_REQ\|RXFIFO_RD_REQ\|CLK_IS_OFF\|STOP_CMD\|
	546	END_CMD_RES\|PRG_DONE\|DATA_TRAN_DONE,
	547	host->base + MMC_I_MASK);
	548
	549	DRCMRRXMMC = 0;
	550	DRCMRTXMMC = 0;
	551
	552	free_irq(host->irq, host);
	553	pxa_free_dma(host->dma);
	554	iounmap(host->base);
3ae5eaec	555	dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1da177e4 LT	556
	557	release_resource(host->res);
	558
	559	mmc_free_host(mmc);
	560	}
	561	return 0;
	562	}
	563
	564	#ifdef CONFIG_PM
3ae5eaec	565	static int pxamci_suspend(struct platform_device *dev, pm_message_t state)
1da177e4	566	{
3ae5eaec	567	struct mmc_host *mmc = platform_get_drvdata(dev);
1da177e4 LT	568	int ret = 0;
1da177e4 LT	569
9480e307	570	if (mmc)
1da177e4 LT	571	ret = mmc_suspend_host(mmc, state);
	572
	573	return ret;
	574	}
	575
3ae5eaec	576	static int pxamci_resume(struct platform_device *dev)
1da177e4	577	{
3ae5eaec	578	struct mmc_host *mmc = platform_get_drvdata(dev);
1da177e4 LT	579	int ret = 0;
1da177e4 LT	580
9480e307	581	if (mmc)
1da177e4 LT	582	ret = mmc_resume_host(mmc);
	583
	584	return ret;
	585	}
	586	#else
	587	#define pxamci_suspend NULL
	588	#define pxamci_resume NULL
	589	#endif
	590
3ae5eaec	591	static struct platform_driver pxamci_driver = {
1da177e4 LT	592	.probe = pxamci_probe,
	593	.remove = pxamci_remove,
	594	.suspend = pxamci_suspend,
	595	.resume = pxamci_resume,
3ae5eaec RK	596	.driver = {
	597	.name = DRIVER_NAME,
	598	},
1da177e4 LT	599	};
	600
	601	static int __init pxamci_init(void)
	602	{
3ae5eaec	603	return platform_driver_register(&pxamci_driver);
1da177e4 LT	604	}
	605
	606	static void __exit pxamci_exit(void)
	607	{
3ae5eaec	608	platform_driver_unregister(&pxamci_driver);
1da177e4 LT	609	}
	610
	611	module_init(pxamci_init);
	612	module_exit(pxamci_exit);
	613
	614	MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
	615	MODULE_LICENSE("GPL");