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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/mmc/pxa.c - PXA MMCI driver | |
3 | * | |
4 | * Copyright (C) 2003 Russell King, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This hardware is really sick: | |
11 | * - No way to clear interrupts. | |
12 | * - Have to turn off the clock whenever we touch the device. | |
13 | * - Doesn't tell you how many data blocks were transferred. | |
14 | * Yuck! | |
15 | * | |
16 | * 1 and 3 byte data transfers not supported | |
17 | * max block length up to 1023 | |
18 | */ | |
1da177e4 LT |
19 | #include <linux/module.h> |
20 | #include <linux/init.h> | |
21 | #include <linux/ioport.h> | |
d052d1be | 22 | #include <linux/platform_device.h> |
1da177e4 LT |
23 | #include <linux/delay.h> |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/mmc/host.h> | |
27 | #include <linux/mmc/protocol.h> | |
28 | ||
29 | #include <asm/dma.h> | |
30 | #include <asm/io.h> | |
1da177e4 LT |
31 | #include <asm/scatterlist.h> |
32 | #include <asm/sizes.h> | |
33 | ||
34 | #include <asm/arch/pxa-regs.h> | |
35 | #include <asm/arch/mmc.h> | |
36 | ||
37 | #include "pxamci.h" | |
38 | ||
1da177e4 LT |
39 | #define DRIVER_NAME "pxa2xx-mci" |
40 | ||
41 | #define NR_SG 1 | |
42 | ||
43 | struct pxamci_host { | |
44 | struct mmc_host *mmc; | |
45 | spinlock_t lock; | |
46 | struct resource *res; | |
47 | void __iomem *base; | |
48 | int irq; | |
49 | int dma; | |
50 | unsigned int clkrt; | |
51 | unsigned int cmdat; | |
52 | unsigned int imask; | |
53 | unsigned int power_mode; | |
54 | struct pxamci_platform_data *pdata; | |
55 | ||
56 | struct mmc_request *mrq; | |
57 | struct mmc_command *cmd; | |
58 | struct mmc_data *data; | |
59 | ||
60 | dma_addr_t sg_dma; | |
61 | struct pxa_dma_desc *sg_cpu; | |
62 | unsigned int dma_len; | |
63 | ||
64 | unsigned int dma_dir; | |
65 | }; | |
66 | ||
1da177e4 LT |
67 | static void pxamci_stop_clock(struct pxamci_host *host) |
68 | { | |
69 | if (readl(host->base + MMC_STAT) & STAT_CLK_EN) { | |
70 | unsigned long timeout = 10000; | |
71 | unsigned int v; | |
72 | ||
73 | writel(STOP_CLOCK, host->base + MMC_STRPCL); | |
74 | ||
75 | do { | |
76 | v = readl(host->base + MMC_STAT); | |
77 | if (!(v & STAT_CLK_EN)) | |
78 | break; | |
79 | udelay(1); | |
80 | } while (timeout--); | |
81 | ||
82 | if (v & STAT_CLK_EN) | |
83 | dev_err(mmc_dev(host->mmc), "unable to stop clock\n"); | |
84 | } | |
85 | } | |
86 | ||
87 | static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask) | |
88 | { | |
89 | unsigned long flags; | |
90 | ||
91 | spin_lock_irqsave(&host->lock, flags); | |
92 | host->imask &= ~mask; | |
93 | writel(host->imask, host->base + MMC_I_MASK); | |
94 | spin_unlock_irqrestore(&host->lock, flags); | |
95 | } | |
96 | ||
97 | static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask) | |
98 | { | |
99 | unsigned long flags; | |
100 | ||
101 | spin_lock_irqsave(&host->lock, flags); | |
102 | host->imask |= mask; | |
103 | writel(host->imask, host->base + MMC_I_MASK); | |
104 | spin_unlock_irqrestore(&host->lock, flags); | |
105 | } | |
106 | ||
107 | static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data) | |
108 | { | |
109 | unsigned int nob = data->blocks; | |
3d63abe5 | 110 | unsigned long long clks; |
1da177e4 LT |
111 | unsigned int timeout; |
112 | u32 dcmd; | |
113 | int i; | |
114 | ||
115 | host->data = data; | |
116 | ||
117 | if (data->flags & MMC_DATA_STREAM) | |
118 | nob = 0xffff; | |
119 | ||
120 | writel(nob, host->base + MMC_NOB); | |
2c171bf1 | 121 | writel(data->blksz, host->base + MMC_BLKLEN); |
1da177e4 | 122 | |
3d63abe5 RK |
123 | clks = (unsigned long long)data->timeout_ns * CLOCKRATE; |
124 | do_div(clks, 1000000000UL); | |
125 | timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt); | |
1da177e4 LT |
126 | writel((timeout + 255) / 256, host->base + MMC_RDTO); |
127 | ||
128 | if (data->flags & MMC_DATA_READ) { | |
129 | host->dma_dir = DMA_FROM_DEVICE; | |
130 | dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG; | |
131 | DRCMRTXMMC = 0; | |
132 | DRCMRRXMMC = host->dma | DRCMR_MAPVLD; | |
133 | } else { | |
134 | host->dma_dir = DMA_TO_DEVICE; | |
135 | dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC; | |
136 | DRCMRRXMMC = 0; | |
137 | DRCMRTXMMC = host->dma | DRCMR_MAPVLD; | |
138 | } | |
139 | ||
140 | dcmd |= DCMD_BURST32 | DCMD_WIDTH1; | |
141 | ||
142 | host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, | |
143 | host->dma_dir); | |
144 | ||
145 | for (i = 0; i < host->dma_len; i++) { | |
146 | if (data->flags & MMC_DATA_READ) { | |
147 | host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO; | |
148 | host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]); | |
149 | } else { | |
150 | host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]); | |
151 | host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO; | |
152 | } | |
153 | host->sg_cpu[i].dcmd = dcmd | sg_dma_len(&data->sg[i]); | |
154 | host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) * | |
155 | sizeof(struct pxa_dma_desc); | |
156 | } | |
157 | host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP; | |
158 | wmb(); | |
159 | ||
160 | DDADR(host->dma) = host->sg_dma; | |
161 | DCSR(host->dma) = DCSR_RUN; | |
162 | } | |
163 | ||
164 | static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat) | |
165 | { | |
166 | WARN_ON(host->cmd != NULL); | |
167 | host->cmd = cmd; | |
168 | ||
169 | if (cmd->flags & MMC_RSP_BUSY) | |
170 | cmdat |= CMDAT_BUSY; | |
171 | ||
e9225176 RK |
172 | #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE)) |
173 | switch (RSP_TYPE(mmc_resp_type(cmd))) { | |
174 | case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6 */ | |
1da177e4 LT |
175 | cmdat |= CMDAT_RESP_SHORT; |
176 | break; | |
e9225176 | 177 | case RSP_TYPE(MMC_RSP_R3): |
1da177e4 LT |
178 | cmdat |= CMDAT_RESP_R3; |
179 | break; | |
e9225176 | 180 | case RSP_TYPE(MMC_RSP_R2): |
1da177e4 LT |
181 | cmdat |= CMDAT_RESP_R2; |
182 | break; | |
183 | default: | |
184 | break; | |
185 | } | |
186 | ||
187 | writel(cmd->opcode, host->base + MMC_CMD); | |
188 | writel(cmd->arg >> 16, host->base + MMC_ARGH); | |
189 | writel(cmd->arg & 0xffff, host->base + MMC_ARGL); | |
190 | writel(cmdat, host->base + MMC_CMDAT); | |
191 | writel(host->clkrt, host->base + MMC_CLKRT); | |
192 | ||
193 | writel(START_CLOCK, host->base + MMC_STRPCL); | |
194 | ||
195 | pxamci_enable_irq(host, END_CMD_RES); | |
196 | } | |
197 | ||
198 | static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq) | |
199 | { | |
1da177e4 LT |
200 | host->mrq = NULL; |
201 | host->cmd = NULL; | |
202 | host->data = NULL; | |
203 | mmc_request_done(host->mmc, mrq); | |
204 | } | |
205 | ||
206 | static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat) | |
207 | { | |
208 | struct mmc_command *cmd = host->cmd; | |
209 | int i; | |
210 | u32 v; | |
211 | ||
212 | if (!cmd) | |
213 | return 0; | |
214 | ||
215 | host->cmd = NULL; | |
216 | ||
217 | /* | |
218 | * Did I mention this is Sick. We always need to | |
219 | * discard the upper 8 bits of the first 16-bit word. | |
220 | */ | |
221 | v = readl(host->base + MMC_RES) & 0xffff; | |
222 | for (i = 0; i < 4; i++) { | |
223 | u32 w1 = readl(host->base + MMC_RES) & 0xffff; | |
224 | u32 w2 = readl(host->base + MMC_RES) & 0xffff; | |
225 | cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8; | |
226 | v = w2; | |
227 | } | |
228 | ||
229 | if (stat & STAT_TIME_OUT_RESPONSE) { | |
230 | cmd->error = MMC_ERR_TIMEOUT; | |
231 | } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) { | |
232 | #ifdef CONFIG_PXA27x | |
233 | /* | |
234 | * workaround for erratum #42: | |
235 | * Intel PXA27x Family Processor Specification Update Rev 001 | |
236 | */ | |
237 | if (cmd->opcode == MMC_ALL_SEND_CID || | |
238 | cmd->opcode == MMC_SEND_CSD || | |
239 | cmd->opcode == MMC_SEND_CID) { | |
240 | /* a bogus CRC error can appear if the msb of | |
241 | the 15 byte response is a one */ | |
242 | if ((cmd->resp[0] & 0x80000000) == 0) | |
243 | cmd->error = MMC_ERR_BADCRC; | |
244 | } else { | |
c6563178 | 245 | pr_debug("ignoring CRC from command %d - *risky*\n",cmd->opcode); |
1da177e4 LT |
246 | } |
247 | #else | |
248 | cmd->error = MMC_ERR_BADCRC; | |
249 | #endif | |
250 | } | |
251 | ||
252 | pxamci_disable_irq(host, END_CMD_RES); | |
253 | if (host->data && cmd->error == MMC_ERR_NONE) { | |
254 | pxamci_enable_irq(host, DATA_TRAN_DONE); | |
255 | } else { | |
256 | pxamci_finish_request(host, host->mrq); | |
257 | } | |
258 | ||
259 | return 1; | |
260 | } | |
261 | ||
262 | static int pxamci_data_done(struct pxamci_host *host, unsigned int stat) | |
263 | { | |
264 | struct mmc_data *data = host->data; | |
265 | ||
266 | if (!data) | |
267 | return 0; | |
268 | ||
269 | DCSR(host->dma) = 0; | |
270 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len, | |
271 | host->dma_dir); | |
272 | ||
273 | if (stat & STAT_READ_TIME_OUT) | |
274 | data->error = MMC_ERR_TIMEOUT; | |
275 | else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR)) | |
276 | data->error = MMC_ERR_BADCRC; | |
277 | ||
278 | /* | |
279 | * There appears to be a hardware design bug here. There seems to | |
280 | * be no way to find out how much data was transferred to the card. | |
281 | * This means that if there was an error on any block, we mark all | |
282 | * data blocks as being in error. | |
283 | */ | |
284 | if (data->error == MMC_ERR_NONE) | |
2c171bf1 | 285 | data->bytes_xfered = data->blocks * data->blksz; |
1da177e4 LT |
286 | else |
287 | data->bytes_xfered = 0; | |
288 | ||
289 | pxamci_disable_irq(host, DATA_TRAN_DONE); | |
290 | ||
291 | host->data = NULL; | |
58741e8b | 292 | if (host->mrq->stop) { |
1da177e4 LT |
293 | pxamci_stop_clock(host); |
294 | pxamci_start_cmd(host, host->mrq->stop, 0); | |
295 | } else { | |
296 | pxamci_finish_request(host, host->mrq); | |
297 | } | |
298 | ||
299 | return 1; | |
300 | } | |
301 | ||
7d12e780 | 302 | static irqreturn_t pxamci_irq(int irq, void *devid) |
1da177e4 LT |
303 | { |
304 | struct pxamci_host *host = devid; | |
305 | unsigned int ireg; | |
306 | int handled = 0; | |
307 | ||
308 | ireg = readl(host->base + MMC_I_REG); | |
309 | ||
1da177e4 LT |
310 | if (ireg) { |
311 | unsigned stat = readl(host->base + MMC_STAT); | |
312 | ||
d78e9079 | 313 | pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat); |
1da177e4 LT |
314 | |
315 | if (ireg & END_CMD_RES) | |
316 | handled |= pxamci_cmd_done(host, stat); | |
317 | if (ireg & DATA_TRAN_DONE) | |
318 | handled |= pxamci_data_done(host, stat); | |
319 | } | |
320 | ||
321 | return IRQ_RETVAL(handled); | |
322 | } | |
323 | ||
324 | static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
325 | { | |
326 | struct pxamci_host *host = mmc_priv(mmc); | |
327 | unsigned int cmdat; | |
328 | ||
329 | WARN_ON(host->mrq != NULL); | |
330 | ||
331 | host->mrq = mrq; | |
332 | ||
333 | pxamci_stop_clock(host); | |
334 | ||
335 | cmdat = host->cmdat; | |
336 | host->cmdat &= ~CMDAT_INIT; | |
337 | ||
338 | if (mrq->data) { | |
339 | pxamci_setup_data(host, mrq->data); | |
340 | ||
341 | cmdat &= ~CMDAT_BUSY; | |
342 | cmdat |= CMDAT_DATAEN | CMDAT_DMAEN; | |
343 | if (mrq->data->flags & MMC_DATA_WRITE) | |
344 | cmdat |= CMDAT_WRITE; | |
345 | ||
346 | if (mrq->data->flags & MMC_DATA_STREAM) | |
347 | cmdat |= CMDAT_STREAM; | |
348 | } | |
349 | ||
350 | pxamci_start_cmd(host, mrq->cmd, cmdat); | |
351 | } | |
352 | ||
e619524f RP |
353 | static int pxamci_get_ro(struct mmc_host *mmc) |
354 | { | |
355 | struct pxamci_host *host = mmc_priv(mmc); | |
356 | ||
357 | if (host->pdata && host->pdata->get_ro) | |
358 | return host->pdata->get_ro(mmc->dev); | |
359 | /* Host doesn't support read only detection so assume writeable */ | |
360 | return 0; | |
361 | } | |
362 | ||
1da177e4 LT |
363 | static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
364 | { | |
365 | struct pxamci_host *host = mmc_priv(mmc); | |
366 | ||
1da177e4 LT |
367 | if (ios->clock) { |
368 | unsigned int clk = CLOCKRATE / ios->clock; | |
369 | if (CLOCKRATE / clk > ios->clock) | |
370 | clk <<= 1; | |
371 | host->clkrt = fls(clk) - 1; | |
372 | pxa_set_cken(CKEN12_MMC, 1); | |
373 | ||
374 | /* | |
375 | * we write clkrt on the next command | |
376 | */ | |
377 | } else { | |
378 | pxamci_stop_clock(host); | |
379 | pxa_set_cken(CKEN12_MMC, 0); | |
380 | } | |
381 | ||
382 | if (host->power_mode != ios->power_mode) { | |
383 | host->power_mode = ios->power_mode; | |
384 | ||
385 | if (host->pdata && host->pdata->setpower) | |
386 | host->pdata->setpower(mmc->dev, ios->vdd); | |
387 | ||
388 | if (ios->power_mode == MMC_POWER_ON) | |
389 | host->cmdat |= CMDAT_INIT; | |
390 | } | |
391 | ||
d78e9079 | 392 | pr_debug("PXAMCI: clkrt = %x cmdat = %x\n", |
c6563178 | 393 | host->clkrt, host->cmdat); |
1da177e4 LT |
394 | } |
395 | ||
ab7aefd0 | 396 | static const struct mmc_host_ops pxamci_ops = { |
1da177e4 | 397 | .request = pxamci_request, |
e619524f | 398 | .get_ro = pxamci_get_ro, |
1da177e4 LT |
399 | .set_ios = pxamci_set_ios, |
400 | }; | |
401 | ||
7d12e780 | 402 | static void pxamci_dma_irq(int dma, void *devid) |
1da177e4 LT |
403 | { |
404 | printk(KERN_ERR "DMA%d: IRQ???\n", dma); | |
405 | DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; | |
406 | } | |
407 | ||
7d12e780 | 408 | static irqreturn_t pxamci_detect_irq(int irq, void *devid) |
1da177e4 | 409 | { |
c26971cb RP |
410 | struct pxamci_host *host = mmc_priv(devid); |
411 | ||
412 | mmc_detect_change(devid, host->pdata->detect_delay); | |
1da177e4 LT |
413 | return IRQ_HANDLED; |
414 | } | |
415 | ||
3ae5eaec | 416 | static int pxamci_probe(struct platform_device *pdev) |
1da177e4 | 417 | { |
1da177e4 LT |
418 | struct mmc_host *mmc; |
419 | struct pxamci_host *host = NULL; | |
420 | struct resource *r; | |
421 | int ret, irq; | |
422 | ||
423 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
424 | irq = platform_get_irq(pdev, 0); | |
48944738 | 425 | if (!r || irq < 0) |
1da177e4 LT |
426 | return -ENXIO; |
427 | ||
428 | r = request_mem_region(r->start, SZ_4K, DRIVER_NAME); | |
429 | if (!r) | |
430 | return -EBUSY; | |
431 | ||
3ae5eaec | 432 | mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev); |
1da177e4 LT |
433 | if (!mmc) { |
434 | ret = -ENOMEM; | |
435 | goto out; | |
436 | } | |
437 | ||
438 | mmc->ops = &pxamci_ops; | |
439 | mmc->f_min = CLOCKRATE_MIN; | |
440 | mmc->f_max = CLOCKRATE_MAX; | |
441 | ||
442 | /* | |
443 | * We can do SG-DMA, but we don't because we never know how much | |
444 | * data we successfully wrote to the card. | |
445 | */ | |
446 | mmc->max_phys_segs = NR_SG; | |
447 | ||
448 | /* | |
449 | * Our hardware DMA can handle a maximum of one page per SG entry. | |
450 | */ | |
451 | mmc->max_seg_size = PAGE_SIZE; | |
452 | ||
453 | host = mmc_priv(mmc); | |
454 | host->mmc = mmc; | |
455 | host->dma = -1; | |
456 | host->pdata = pdev->dev.platform_data; | |
457 | mmc->ocr_avail = host->pdata ? | |
458 | host->pdata->ocr_mask : | |
459 | MMC_VDD_32_33|MMC_VDD_33_34; | |
460 | ||
3ae5eaec | 461 | host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL); |
1da177e4 LT |
462 | if (!host->sg_cpu) { |
463 | ret = -ENOMEM; | |
464 | goto out; | |
465 | } | |
466 | ||
467 | spin_lock_init(&host->lock); | |
468 | host->res = r; | |
469 | host->irq = irq; | |
470 | host->imask = MMC_I_MASK_ALL; | |
471 | ||
472 | host->base = ioremap(r->start, SZ_4K); | |
473 | if (!host->base) { | |
474 | ret = -ENOMEM; | |
475 | goto out; | |
476 | } | |
477 | ||
478 | /* | |
479 | * Ensure that the host controller is shut down, and setup | |
480 | * with our defaults. | |
481 | */ | |
482 | pxamci_stop_clock(host); | |
483 | writel(0, host->base + MMC_SPI); | |
484 | writel(64, host->base + MMC_RESTO); | |
485 | writel(host->imask, host->base + MMC_I_MASK); | |
486 | ||
487 | host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW, | |
488 | pxamci_dma_irq, host); | |
489 | if (host->dma < 0) { | |
490 | ret = -EBUSY; | |
491 | goto out; | |
492 | } | |
493 | ||
494 | ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host); | |
495 | if (ret) | |
496 | goto out; | |
497 | ||
3ae5eaec | 498 | platform_set_drvdata(pdev, mmc); |
1da177e4 LT |
499 | |
500 | if (host->pdata && host->pdata->init) | |
3ae5eaec | 501 | host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc); |
1da177e4 LT |
502 | |
503 | mmc_add_host(mmc); | |
504 | ||
505 | return 0; | |
506 | ||
507 | out: | |
508 | if (host) { | |
509 | if (host->dma >= 0) | |
510 | pxa_free_dma(host->dma); | |
511 | if (host->base) | |
512 | iounmap(host->base); | |
513 | if (host->sg_cpu) | |
3ae5eaec | 514 | dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); |
1da177e4 LT |
515 | } |
516 | if (mmc) | |
517 | mmc_free_host(mmc); | |
518 | release_resource(r); | |
519 | return ret; | |
520 | } | |
521 | ||
3ae5eaec | 522 | static int pxamci_remove(struct platform_device *pdev) |
1da177e4 | 523 | { |
3ae5eaec | 524 | struct mmc_host *mmc = platform_get_drvdata(pdev); |
1da177e4 | 525 | |
3ae5eaec | 526 | platform_set_drvdata(pdev, NULL); |
1da177e4 LT |
527 | |
528 | if (mmc) { | |
529 | struct pxamci_host *host = mmc_priv(mmc); | |
530 | ||
531 | if (host->pdata && host->pdata->exit) | |
3ae5eaec | 532 | host->pdata->exit(&pdev->dev, mmc); |
1da177e4 LT |
533 | |
534 | mmc_remove_host(mmc); | |
535 | ||
536 | pxamci_stop_clock(host); | |
537 | writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD| | |
538 | END_CMD_RES|PRG_DONE|DATA_TRAN_DONE, | |
539 | host->base + MMC_I_MASK); | |
540 | ||
541 | DRCMRRXMMC = 0; | |
542 | DRCMRTXMMC = 0; | |
543 | ||
544 | free_irq(host->irq, host); | |
545 | pxa_free_dma(host->dma); | |
546 | iounmap(host->base); | |
3ae5eaec | 547 | dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); |
1da177e4 LT |
548 | |
549 | release_resource(host->res); | |
550 | ||
551 | mmc_free_host(mmc); | |
552 | } | |
553 | return 0; | |
554 | } | |
555 | ||
556 | #ifdef CONFIG_PM | |
3ae5eaec | 557 | static int pxamci_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 558 | { |
3ae5eaec | 559 | struct mmc_host *mmc = platform_get_drvdata(dev); |
1da177e4 LT |
560 | int ret = 0; |
561 | ||
9480e307 | 562 | if (mmc) |
1da177e4 LT |
563 | ret = mmc_suspend_host(mmc, state); |
564 | ||
565 | return ret; | |
566 | } | |
567 | ||
3ae5eaec | 568 | static int pxamci_resume(struct platform_device *dev) |
1da177e4 | 569 | { |
3ae5eaec | 570 | struct mmc_host *mmc = platform_get_drvdata(dev); |
1da177e4 LT |
571 | int ret = 0; |
572 | ||
9480e307 | 573 | if (mmc) |
1da177e4 LT |
574 | ret = mmc_resume_host(mmc); |
575 | ||
576 | return ret; | |
577 | } | |
578 | #else | |
579 | #define pxamci_suspend NULL | |
580 | #define pxamci_resume NULL | |
581 | #endif | |
582 | ||
3ae5eaec | 583 | static struct platform_driver pxamci_driver = { |
1da177e4 LT |
584 | .probe = pxamci_probe, |
585 | .remove = pxamci_remove, | |
586 | .suspend = pxamci_suspend, | |
587 | .resume = pxamci_resume, | |
3ae5eaec RK |
588 | .driver = { |
589 | .name = DRIVER_NAME, | |
590 | }, | |
1da177e4 LT |
591 | }; |
592 | ||
593 | static int __init pxamci_init(void) | |
594 | { | |
3ae5eaec | 595 | return platform_driver_register(&pxamci_driver); |
1da177e4 LT |
596 | } |
597 | ||
598 | static void __exit pxamci_exit(void) | |
599 | { | |
3ae5eaec | 600 | platform_driver_unregister(&pxamci_driver); |
1da177e4 LT |
601 | } |
602 | ||
603 | module_init(pxamci_init); | |
604 | module_exit(pxamci_exit); | |
605 | ||
606 | MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver"); | |
607 | MODULE_LICENSE("GPL"); |