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d129bceb PO |
1 | /* |
2 | * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver | |
3 | * | |
4 | * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
d129bceb PO |
10 | */ |
11 | ||
d129bceb PO |
12 | #include <linux/delay.h> |
13 | #include <linux/highmem.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | ||
17 | #include <linux/mmc/host.h> | |
18 | #include <linux/mmc/protocol.h> | |
19 | ||
20 | #include <asm/scatterlist.h> | |
21 | ||
22 | #include "sdhci.h" | |
23 | ||
24 | #define DRIVER_NAME "sdhci" | |
2c5f3940 | 25 | #define DRIVER_VERSION "0.12" |
d129bceb PO |
26 | |
27 | #define BUGMAIL "<sdhci-devel@list.drzeus.cx>" | |
28 | ||
d129bceb | 29 | #define DBG(f, x...) \ |
c6563178 | 30 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
d129bceb | 31 | |
67435274 PO |
32 | static unsigned int debug_nodma = 0; |
33 | static unsigned int debug_forcedma = 0; | |
df673b22 | 34 | static unsigned int debug_quirks = 0; |
67435274 | 35 | |
645289dc | 36 | #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) |
98608076 | 37 | #define SDHCI_QUIRK_FORCE_DMA (1<<1) |
645289dc | 38 | |
d129bceb | 39 | static const struct pci_device_id pci_ids[] __devinitdata = { |
645289dc PO |
40 | { |
41 | .vendor = PCI_VENDOR_ID_RICOH, | |
42 | .device = PCI_DEVICE_ID_RICOH_R5C822, | |
43 | .subvendor = PCI_VENDOR_ID_IBM, | |
44 | .subdevice = PCI_ANY_ID, | |
98608076 PO |
45 | .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET | |
46 | SDHCI_QUIRK_FORCE_DMA, | |
47 | }, | |
48 | ||
49 | { | |
50 | .vendor = PCI_VENDOR_ID_RICOH, | |
51 | .device = PCI_DEVICE_ID_RICOH_R5C822, | |
52 | .subvendor = PCI_ANY_ID, | |
53 | .subdevice = PCI_ANY_ID, | |
54 | .driver_data = SDHCI_QUIRK_FORCE_DMA, | |
55 | }, | |
56 | ||
57 | { | |
58 | .vendor = PCI_VENDOR_ID_TI, | |
59 | .device = PCI_DEVICE_ID_TI_XX21_XX11_SD, | |
60 | .subvendor = PCI_ANY_ID, | |
61 | .subdevice = PCI_ANY_ID, | |
62 | .driver_data = SDHCI_QUIRK_FORCE_DMA, | |
645289dc PO |
63 | }, |
64 | ||
65 | { /* Generic SD host controller */ | |
66 | PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) | |
67 | }, | |
68 | ||
d129bceb PO |
69 | { /* end: all zeroes */ }, |
70 | }; | |
71 | ||
72 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
73 | ||
74 | static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *); | |
75 | static void sdhci_finish_data(struct sdhci_host *); | |
76 | ||
77 | static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); | |
78 | static void sdhci_finish_command(struct sdhci_host *); | |
79 | ||
80 | static void sdhci_dumpregs(struct sdhci_host *host) | |
81 | { | |
82 | printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n"); | |
83 | ||
84 | printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", | |
85 | readl(host->ioaddr + SDHCI_DMA_ADDRESS), | |
86 | readw(host->ioaddr + SDHCI_HOST_VERSION)); | |
87 | printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", | |
88 | readw(host->ioaddr + SDHCI_BLOCK_SIZE), | |
89 | readw(host->ioaddr + SDHCI_BLOCK_COUNT)); | |
90 | printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", | |
91 | readl(host->ioaddr + SDHCI_ARGUMENT), | |
92 | readw(host->ioaddr + SDHCI_TRANSFER_MODE)); | |
93 | printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", | |
94 | readl(host->ioaddr + SDHCI_PRESENT_STATE), | |
95 | readb(host->ioaddr + SDHCI_HOST_CONTROL)); | |
96 | printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", | |
97 | readb(host->ioaddr + SDHCI_POWER_CONTROL), | |
98 | readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL)); | |
99 | printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", | |
100 | readb(host->ioaddr + SDHCI_WALK_UP_CONTROL), | |
101 | readw(host->ioaddr + SDHCI_CLOCK_CONTROL)); | |
102 | printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", | |
103 | readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL), | |
104 | readl(host->ioaddr + SDHCI_INT_STATUS)); | |
105 | printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", | |
106 | readl(host->ioaddr + SDHCI_INT_ENABLE), | |
107 | readl(host->ioaddr + SDHCI_SIGNAL_ENABLE)); | |
108 | printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", | |
109 | readw(host->ioaddr + SDHCI_ACMD12_ERR), | |
110 | readw(host->ioaddr + SDHCI_SLOT_INT_STATUS)); | |
111 | printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n", | |
112 | readl(host->ioaddr + SDHCI_CAPABILITIES), | |
113 | readl(host->ioaddr + SDHCI_MAX_CURRENT)); | |
114 | ||
115 | printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n"); | |
116 | } | |
117 | ||
118 | /*****************************************************************************\ | |
119 | * * | |
120 | * Low level functions * | |
121 | * * | |
122 | \*****************************************************************************/ | |
123 | ||
124 | static void sdhci_reset(struct sdhci_host *host, u8 mask) | |
125 | { | |
e16514d8 PO |
126 | unsigned long timeout; |
127 | ||
d129bceb PO |
128 | writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET); |
129 | ||
e16514d8 | 130 | if (mask & SDHCI_RESET_ALL) |
d129bceb PO |
131 | host->clock = 0; |
132 | ||
e16514d8 PO |
133 | /* Wait max 100 ms */ |
134 | timeout = 100; | |
135 | ||
136 | /* hw clears the bit when it's done */ | |
137 | while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) { | |
138 | if (timeout == 0) { | |
139 | printk(KERN_ERR "%s: Reset 0x%x never completed. " | |
140 | "Please report this to " BUGMAIL ".\n", | |
141 | mmc_hostname(host->mmc), (int)mask); | |
142 | sdhci_dumpregs(host); | |
143 | return; | |
144 | } | |
145 | timeout--; | |
146 | mdelay(1); | |
d129bceb PO |
147 | } |
148 | } | |
149 | ||
150 | static void sdhci_init(struct sdhci_host *host) | |
151 | { | |
152 | u32 intmask; | |
153 | ||
154 | sdhci_reset(host, SDHCI_RESET_ALL); | |
155 | ||
3192a28f PO |
156 | intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | |
157 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | | |
158 | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | | |
159 | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | | |
a406f5a3 | 160 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | |
3192a28f | 161 | SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE; |
d129bceb PO |
162 | |
163 | writel(intmask, host->ioaddr + SDHCI_INT_ENABLE); | |
164 | writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE); | |
d129bceb PO |
165 | } |
166 | ||
167 | static void sdhci_activate_led(struct sdhci_host *host) | |
168 | { | |
169 | u8 ctrl; | |
170 | ||
171 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
172 | ctrl |= SDHCI_CTRL_LED; | |
173 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); | |
174 | } | |
175 | ||
176 | static void sdhci_deactivate_led(struct sdhci_host *host) | |
177 | { | |
178 | u8 ctrl; | |
179 | ||
180 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
181 | ctrl &= ~SDHCI_CTRL_LED; | |
182 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); | |
183 | } | |
184 | ||
185 | /*****************************************************************************\ | |
186 | * * | |
187 | * Core functions * | |
188 | * * | |
189 | \*****************************************************************************/ | |
190 | ||
191 | static inline char* sdhci_kmap_sg(struct sdhci_host* host) | |
192 | { | |
193 | host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ); | |
194 | return host->mapped_sg + host->cur_sg->offset; | |
195 | } | |
196 | ||
197 | static inline void sdhci_kunmap_sg(struct sdhci_host* host) | |
198 | { | |
199 | kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ); | |
200 | } | |
201 | ||
202 | static inline int sdhci_next_sg(struct sdhci_host* host) | |
203 | { | |
204 | /* | |
205 | * Skip to next SG entry. | |
206 | */ | |
207 | host->cur_sg++; | |
208 | host->num_sg--; | |
209 | ||
210 | /* | |
211 | * Any entries left? | |
212 | */ | |
213 | if (host->num_sg > 0) { | |
214 | host->offset = 0; | |
215 | host->remain = host->cur_sg->length; | |
216 | } | |
217 | ||
218 | return host->num_sg; | |
219 | } | |
220 | ||
a406f5a3 | 221 | static void sdhci_read_block_pio(struct sdhci_host *host) |
d129bceb | 222 | { |
a406f5a3 PO |
223 | int blksize, chunk_remain; |
224 | u32 data; | |
d129bceb | 225 | char *buffer; |
a406f5a3 | 226 | int size; |
d129bceb | 227 | |
a406f5a3 | 228 | DBG("PIO reading\n"); |
d129bceb | 229 | |
a406f5a3 PO |
230 | blksize = host->data->blksz; |
231 | chunk_remain = 0; | |
232 | data = 0; | |
d129bceb PO |
233 | |
234 | buffer = sdhci_kmap_sg(host) + host->offset; | |
235 | ||
a406f5a3 PO |
236 | while (blksize) { |
237 | if (chunk_remain == 0) { | |
238 | data = readl(host->ioaddr + SDHCI_BUFFER); | |
239 | chunk_remain = min(blksize, 4); | |
240 | } | |
d129bceb | 241 | |
a406f5a3 PO |
242 | size = min(host->size, host->remain); |
243 | size = min(size, chunk_remain); | |
d129bceb | 244 | |
a406f5a3 PO |
245 | chunk_remain -= size; |
246 | blksize -= size; | |
247 | host->offset += size; | |
248 | host->remain -= size; | |
249 | host->size -= size; | |
250 | while (size) { | |
251 | *buffer = data & 0xFF; | |
252 | buffer++; | |
253 | data >>= 8; | |
254 | size--; | |
255 | } | |
d129bceb | 256 | |
a406f5a3 PO |
257 | if (host->remain == 0) { |
258 | sdhci_kunmap_sg(host); | |
259 | if (sdhci_next_sg(host) == 0) { | |
260 | BUG_ON(blksize != 0); | |
261 | return; | |
262 | } | |
263 | buffer = sdhci_kmap_sg(host); | |
d129bceb | 264 | } |
a406f5a3 | 265 | } |
d129bceb | 266 | |
a406f5a3 PO |
267 | sdhci_kunmap_sg(host); |
268 | } | |
d129bceb | 269 | |
a406f5a3 PO |
270 | static void sdhci_write_block_pio(struct sdhci_host *host) |
271 | { | |
272 | int blksize, chunk_remain; | |
273 | u32 data; | |
274 | char *buffer; | |
275 | int bytes, size; | |
d129bceb | 276 | |
a406f5a3 PO |
277 | DBG("PIO writing\n"); |
278 | ||
279 | blksize = host->data->blksz; | |
280 | chunk_remain = 4; | |
281 | data = 0; | |
d129bceb | 282 | |
a406f5a3 PO |
283 | bytes = 0; |
284 | buffer = sdhci_kmap_sg(host) + host->offset; | |
d129bceb | 285 | |
a406f5a3 PO |
286 | while (blksize) { |
287 | size = min(host->size, host->remain); | |
288 | size = min(size, chunk_remain); | |
289 | ||
290 | chunk_remain -= size; | |
291 | blksize -= size; | |
d129bceb PO |
292 | host->offset += size; |
293 | host->remain -= size; | |
d129bceb | 294 | host->size -= size; |
a406f5a3 PO |
295 | while (size) { |
296 | data >>= 8; | |
297 | data |= (u32)*buffer << 24; | |
298 | buffer++; | |
299 | size--; | |
300 | } | |
301 | ||
302 | if (chunk_remain == 0) { | |
303 | writel(data, host->ioaddr + SDHCI_BUFFER); | |
304 | chunk_remain = min(blksize, 4); | |
305 | } | |
d129bceb PO |
306 | |
307 | if (host->remain == 0) { | |
308 | sdhci_kunmap_sg(host); | |
309 | if (sdhci_next_sg(host) == 0) { | |
a406f5a3 | 310 | BUG_ON(blksize != 0); |
d129bceb PO |
311 | return; |
312 | } | |
313 | buffer = sdhci_kmap_sg(host); | |
314 | } | |
315 | } | |
316 | ||
317 | sdhci_kunmap_sg(host); | |
a406f5a3 PO |
318 | } |
319 | ||
320 | static void sdhci_transfer_pio(struct sdhci_host *host) | |
321 | { | |
322 | u32 mask; | |
323 | ||
324 | BUG_ON(!host->data); | |
325 | ||
326 | if (host->size == 0) | |
327 | return; | |
328 | ||
329 | if (host->data->flags & MMC_DATA_READ) | |
330 | mask = SDHCI_DATA_AVAILABLE; | |
331 | else | |
332 | mask = SDHCI_SPACE_AVAILABLE; | |
333 | ||
334 | while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { | |
335 | if (host->data->flags & MMC_DATA_READ) | |
336 | sdhci_read_block_pio(host); | |
337 | else | |
338 | sdhci_write_block_pio(host); | |
d129bceb | 339 | |
a406f5a3 PO |
340 | if (host->size == 0) |
341 | break; | |
342 | ||
343 | BUG_ON(host->num_sg == 0); | |
344 | } | |
d129bceb | 345 | |
a406f5a3 | 346 | DBG("PIO transfer complete.\n"); |
d129bceb PO |
347 | } |
348 | ||
349 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) | |
350 | { | |
1c8cde92 PO |
351 | u8 count; |
352 | unsigned target_timeout, current_timeout; | |
d129bceb PO |
353 | |
354 | WARN_ON(host->data); | |
355 | ||
c7fa9963 | 356 | if (data == NULL) |
d129bceb | 357 | return; |
d129bceb PO |
358 | |
359 | DBG("blksz %04x blks %04x flags %08x\n", | |
a3fd4a1b | 360 | data->blksz, data->blocks, data->flags); |
d129bceb PO |
361 | DBG("tsac %d ms nsac %d clk\n", |
362 | data->timeout_ns / 1000000, data->timeout_clks); | |
363 | ||
bab76961 PO |
364 | /* Sanity checks */ |
365 | BUG_ON(data->blksz * data->blocks > 524288); | |
1d676e02 PO |
366 | BUG_ON(data->blksz > host->max_block); |
367 | BUG_ON(data->blocks > 65535); | |
d129bceb | 368 | |
1c8cde92 PO |
369 | /* timeout in us */ |
370 | target_timeout = data->timeout_ns / 1000 + | |
371 | data->timeout_clks / host->clock; | |
d129bceb | 372 | |
1c8cde92 PO |
373 | /* |
374 | * Figure out needed cycles. | |
375 | * We do this in steps in order to fit inside a 32 bit int. | |
376 | * The first step is the minimum timeout, which will have a | |
377 | * minimum resolution of 6 bits: | |
378 | * (1) 2^13*1000 > 2^22, | |
379 | * (2) host->timeout_clk < 2^16 | |
380 | * => | |
381 | * (1) / (2) > 2^6 | |
382 | */ | |
383 | count = 0; | |
384 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; | |
385 | while (current_timeout < target_timeout) { | |
386 | count++; | |
387 | current_timeout <<= 1; | |
388 | if (count >= 0xF) | |
389 | break; | |
390 | } | |
391 | ||
392 | if (count >= 0xF) { | |
393 | printk(KERN_WARNING "%s: Too large timeout requested!\n", | |
394 | mmc_hostname(host->mmc)); | |
395 | count = 0xE; | |
396 | } | |
397 | ||
398 | writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL); | |
d129bceb PO |
399 | |
400 | if (host->flags & SDHCI_USE_DMA) { | |
401 | int count; | |
402 | ||
403 | count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len, | |
404 | (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE); | |
405 | BUG_ON(count != 1); | |
406 | ||
407 | writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS); | |
408 | } else { | |
a3fd4a1b | 409 | host->size = data->blksz * data->blocks; |
d129bceb PO |
410 | |
411 | host->cur_sg = data->sg; | |
412 | host->num_sg = data->sg_len; | |
413 | ||
414 | host->offset = 0; | |
415 | host->remain = host->cur_sg->length; | |
416 | } | |
c7fa9963 | 417 | |
bab76961 PO |
418 | /* We do not handle DMA boundaries, so set it to max (512 KiB) */ |
419 | writew(SDHCI_MAKE_BLKSZ(7, data->blksz), | |
420 | host->ioaddr + SDHCI_BLOCK_SIZE); | |
c7fa9963 PO |
421 | writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT); |
422 | } | |
423 | ||
424 | static void sdhci_set_transfer_mode(struct sdhci_host *host, | |
425 | struct mmc_data *data) | |
426 | { | |
427 | u16 mode; | |
428 | ||
429 | WARN_ON(host->data); | |
430 | ||
431 | if (data == NULL) | |
432 | return; | |
433 | ||
434 | mode = SDHCI_TRNS_BLK_CNT_EN; | |
435 | if (data->blocks > 1) | |
436 | mode |= SDHCI_TRNS_MULTI; | |
437 | if (data->flags & MMC_DATA_READ) | |
438 | mode |= SDHCI_TRNS_READ; | |
439 | if (host->flags & SDHCI_USE_DMA) | |
440 | mode |= SDHCI_TRNS_DMA; | |
441 | ||
442 | writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE); | |
d129bceb PO |
443 | } |
444 | ||
445 | static void sdhci_finish_data(struct sdhci_host *host) | |
446 | { | |
447 | struct mmc_data *data; | |
d129bceb PO |
448 | u16 blocks; |
449 | ||
450 | BUG_ON(!host->data); | |
451 | ||
452 | data = host->data; | |
453 | host->data = NULL; | |
454 | ||
455 | if (host->flags & SDHCI_USE_DMA) { | |
456 | pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len, | |
457 | (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE); | |
d129bceb PO |
458 | } |
459 | ||
460 | /* | |
461 | * Controller doesn't count down when in single block mode. | |
462 | */ | |
463 | if ((data->blocks == 1) && (data->error == MMC_ERR_NONE)) | |
464 | blocks = 0; | |
465 | else | |
466 | blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT); | |
a3fd4a1b | 467 | data->bytes_xfered = data->blksz * (data->blocks - blocks); |
d129bceb PO |
468 | |
469 | if ((data->error == MMC_ERR_NONE) && blocks) { | |
470 | printk(KERN_ERR "%s: Controller signalled completion even " | |
471 | "though there were blocks left. Please report this " | |
472 | "to " BUGMAIL ".\n", mmc_hostname(host->mmc)); | |
473 | data->error = MMC_ERR_FAILED; | |
4cca56c5 | 474 | } else if (host->size != 0) { |
d129bceb PO |
475 | printk(KERN_ERR "%s: %d bytes were left untransferred. " |
476 | "Please report this to " BUGMAIL ".\n", | |
477 | mmc_hostname(host->mmc), host->size); | |
478 | data->error = MMC_ERR_FAILED; | |
479 | } | |
480 | ||
481 | DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered); | |
482 | ||
483 | if (data->stop) { | |
484 | /* | |
485 | * The controller needs a reset of internal state machines | |
486 | * upon error conditions. | |
487 | */ | |
488 | if (data->error != MMC_ERR_NONE) { | |
489 | sdhci_reset(host, SDHCI_RESET_CMD); | |
490 | sdhci_reset(host, SDHCI_RESET_DATA); | |
491 | } | |
492 | ||
493 | sdhci_send_command(host, data->stop); | |
494 | } else | |
495 | tasklet_schedule(&host->finish_tasklet); | |
496 | } | |
497 | ||
498 | static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) | |
499 | { | |
500 | int flags; | |
fd2208d7 | 501 | u32 mask; |
7cb2c76f | 502 | unsigned long timeout; |
d129bceb PO |
503 | |
504 | WARN_ON(host->cmd); | |
505 | ||
506 | DBG("Sending cmd (%x)\n", cmd->opcode); | |
507 | ||
508 | /* Wait max 10 ms */ | |
7cb2c76f | 509 | timeout = 10; |
fd2208d7 PO |
510 | |
511 | mask = SDHCI_CMD_INHIBIT; | |
512 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) | |
513 | mask |= SDHCI_DATA_INHIBIT; | |
514 | ||
515 | /* We shouldn't wait for data inihibit for stop commands, even | |
516 | though they might use busy signaling */ | |
517 | if (host->mrq->data && (cmd == host->mrq->data->stop)) | |
518 | mask &= ~SDHCI_DATA_INHIBIT; | |
519 | ||
520 | while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { | |
7cb2c76f | 521 | if (timeout == 0) { |
d129bceb | 522 | printk(KERN_ERR "%s: Controller never released " |
fd2208d7 | 523 | "inhibit bit(s). Please report this to " |
d129bceb PO |
524 | BUGMAIL ".\n", mmc_hostname(host->mmc)); |
525 | sdhci_dumpregs(host); | |
526 | cmd->error = MMC_ERR_FAILED; | |
527 | tasklet_schedule(&host->finish_tasklet); | |
528 | return; | |
529 | } | |
7cb2c76f PO |
530 | timeout--; |
531 | mdelay(1); | |
532 | } | |
d129bceb PO |
533 | |
534 | mod_timer(&host->timer, jiffies + 10 * HZ); | |
535 | ||
536 | host->cmd = cmd; | |
537 | ||
538 | sdhci_prepare_data(host, cmd->data); | |
539 | ||
540 | writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT); | |
541 | ||
c7fa9963 PO |
542 | sdhci_set_transfer_mode(host, cmd->data); |
543 | ||
d129bceb PO |
544 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
545 | printk(KERN_ERR "%s: Unsupported response type! " | |
546 | "Please report this to " BUGMAIL ".\n", | |
547 | mmc_hostname(host->mmc)); | |
548 | cmd->error = MMC_ERR_INVALID; | |
549 | tasklet_schedule(&host->finish_tasklet); | |
550 | return; | |
551 | } | |
552 | ||
553 | if (!(cmd->flags & MMC_RSP_PRESENT)) | |
554 | flags = SDHCI_CMD_RESP_NONE; | |
555 | else if (cmd->flags & MMC_RSP_136) | |
556 | flags = SDHCI_CMD_RESP_LONG; | |
557 | else if (cmd->flags & MMC_RSP_BUSY) | |
558 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
559 | else | |
560 | flags = SDHCI_CMD_RESP_SHORT; | |
561 | ||
562 | if (cmd->flags & MMC_RSP_CRC) | |
563 | flags |= SDHCI_CMD_CRC; | |
564 | if (cmd->flags & MMC_RSP_OPCODE) | |
565 | flags |= SDHCI_CMD_INDEX; | |
566 | if (cmd->data) | |
567 | flags |= SDHCI_CMD_DATA; | |
568 | ||
fb61e289 | 569 | writew(SDHCI_MAKE_CMD(cmd->opcode, flags), |
d129bceb PO |
570 | host->ioaddr + SDHCI_COMMAND); |
571 | } | |
572 | ||
573 | static void sdhci_finish_command(struct sdhci_host *host) | |
574 | { | |
575 | int i; | |
576 | ||
577 | BUG_ON(host->cmd == NULL); | |
578 | ||
579 | if (host->cmd->flags & MMC_RSP_PRESENT) { | |
580 | if (host->cmd->flags & MMC_RSP_136) { | |
581 | /* CRC is stripped so we need to do some shifting. */ | |
582 | for (i = 0;i < 4;i++) { | |
583 | host->cmd->resp[i] = readl(host->ioaddr + | |
584 | SDHCI_RESPONSE + (3-i)*4) << 8; | |
585 | if (i != 3) | |
586 | host->cmd->resp[i] |= | |
587 | readb(host->ioaddr + | |
588 | SDHCI_RESPONSE + (3-i)*4-1); | |
589 | } | |
590 | } else { | |
591 | host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE); | |
592 | } | |
593 | } | |
594 | ||
595 | host->cmd->error = MMC_ERR_NONE; | |
596 | ||
597 | DBG("Ending cmd (%x)\n", host->cmd->opcode); | |
598 | ||
3192a28f | 599 | if (host->cmd->data) |
d129bceb | 600 | host->data = host->cmd->data; |
3192a28f | 601 | else |
d129bceb PO |
602 | tasklet_schedule(&host->finish_tasklet); |
603 | ||
604 | host->cmd = NULL; | |
605 | } | |
606 | ||
607 | static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) | |
608 | { | |
609 | int div; | |
610 | u16 clk; | |
7cb2c76f | 611 | unsigned long timeout; |
d129bceb PO |
612 | |
613 | if (clock == host->clock) | |
614 | return; | |
615 | ||
616 | writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
617 | ||
618 | if (clock == 0) | |
619 | goto out; | |
620 | ||
621 | for (div = 1;div < 256;div *= 2) { | |
622 | if ((host->max_clk / div) <= clock) | |
623 | break; | |
624 | } | |
625 | div >>= 1; | |
626 | ||
627 | clk = div << SDHCI_DIVIDER_SHIFT; | |
628 | clk |= SDHCI_CLOCK_INT_EN; | |
629 | writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
630 | ||
631 | /* Wait max 10 ms */ | |
7cb2c76f PO |
632 | timeout = 10; |
633 | while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL)) | |
634 | & SDHCI_CLOCK_INT_STABLE)) { | |
635 | if (timeout == 0) { | |
d129bceb PO |
636 | printk(KERN_ERR "%s: Internal clock never stabilised. " |
637 | "Please report this to " BUGMAIL ".\n", | |
638 | mmc_hostname(host->mmc)); | |
639 | sdhci_dumpregs(host); | |
640 | return; | |
641 | } | |
7cb2c76f PO |
642 | timeout--; |
643 | mdelay(1); | |
644 | } | |
d129bceb PO |
645 | |
646 | clk |= SDHCI_CLOCK_CARD_EN; | |
647 | writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
648 | ||
649 | out: | |
650 | host->clock = clock; | |
651 | } | |
652 | ||
146ad66e PO |
653 | static void sdhci_set_power(struct sdhci_host *host, unsigned short power) |
654 | { | |
655 | u8 pwr; | |
656 | ||
657 | if (host->power == power) | |
658 | return; | |
659 | ||
660 | writeb(0, host->ioaddr + SDHCI_POWER_CONTROL); | |
661 | ||
662 | if (power == (unsigned short)-1) | |
663 | goto out; | |
664 | ||
665 | pwr = SDHCI_POWER_ON; | |
666 | ||
667 | switch (power) { | |
668 | case MMC_VDD_170: | |
669 | case MMC_VDD_180: | |
670 | case MMC_VDD_190: | |
671 | pwr |= SDHCI_POWER_180; | |
672 | break; | |
673 | case MMC_VDD_290: | |
674 | case MMC_VDD_300: | |
675 | case MMC_VDD_310: | |
676 | pwr |= SDHCI_POWER_300; | |
677 | break; | |
678 | case MMC_VDD_320: | |
679 | case MMC_VDD_330: | |
680 | case MMC_VDD_340: | |
681 | pwr |= SDHCI_POWER_330; | |
682 | break; | |
683 | default: | |
684 | BUG(); | |
685 | } | |
686 | ||
687 | writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL); | |
688 | ||
689 | out: | |
690 | host->power = power; | |
691 | } | |
692 | ||
d129bceb PO |
693 | /*****************************************************************************\ |
694 | * * | |
695 | * MMC callbacks * | |
696 | * * | |
697 | \*****************************************************************************/ | |
698 | ||
699 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
700 | { | |
701 | struct sdhci_host *host; | |
702 | unsigned long flags; | |
703 | ||
704 | host = mmc_priv(mmc); | |
705 | ||
706 | spin_lock_irqsave(&host->lock, flags); | |
707 | ||
708 | WARN_ON(host->mrq != NULL); | |
709 | ||
710 | sdhci_activate_led(host); | |
711 | ||
712 | host->mrq = mrq; | |
713 | ||
714 | if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { | |
715 | host->mrq->cmd->error = MMC_ERR_TIMEOUT; | |
716 | tasklet_schedule(&host->finish_tasklet); | |
717 | } else | |
718 | sdhci_send_command(host, mrq->cmd); | |
719 | ||
720 | spin_unlock_irqrestore(&host->lock, flags); | |
721 | } | |
722 | ||
723 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
724 | { | |
725 | struct sdhci_host *host; | |
726 | unsigned long flags; | |
727 | u8 ctrl; | |
728 | ||
729 | host = mmc_priv(mmc); | |
730 | ||
731 | spin_lock_irqsave(&host->lock, flags); | |
732 | ||
d129bceb PO |
733 | /* |
734 | * Reset the chip on each power off. | |
735 | * Should clear out any weird states. | |
736 | */ | |
737 | if (ios->power_mode == MMC_POWER_OFF) { | |
738 | writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE); | |
d129bceb | 739 | sdhci_init(host); |
d129bceb PO |
740 | } |
741 | ||
742 | sdhci_set_clock(host, ios->clock); | |
743 | ||
744 | if (ios->power_mode == MMC_POWER_OFF) | |
146ad66e | 745 | sdhci_set_power(host, -1); |
d129bceb | 746 | else |
146ad66e | 747 | sdhci_set_power(host, ios->vdd); |
d129bceb PO |
748 | |
749 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
750 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
751 | ctrl |= SDHCI_CTRL_4BITBUS; | |
752 | else | |
753 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
754 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); | |
755 | ||
756 | spin_unlock_irqrestore(&host->lock, flags); | |
757 | } | |
758 | ||
759 | static int sdhci_get_ro(struct mmc_host *mmc) | |
760 | { | |
761 | struct sdhci_host *host; | |
762 | unsigned long flags; | |
763 | int present; | |
764 | ||
765 | host = mmc_priv(mmc); | |
766 | ||
767 | spin_lock_irqsave(&host->lock, flags); | |
768 | ||
769 | present = readl(host->ioaddr + SDHCI_PRESENT_STATE); | |
770 | ||
771 | spin_unlock_irqrestore(&host->lock, flags); | |
772 | ||
773 | return !(present & SDHCI_WRITE_PROTECT); | |
774 | } | |
775 | ||
776 | static struct mmc_host_ops sdhci_ops = { | |
777 | .request = sdhci_request, | |
778 | .set_ios = sdhci_set_ios, | |
779 | .get_ro = sdhci_get_ro, | |
780 | }; | |
781 | ||
782 | /*****************************************************************************\ | |
783 | * * | |
784 | * Tasklets * | |
785 | * * | |
786 | \*****************************************************************************/ | |
787 | ||
788 | static void sdhci_tasklet_card(unsigned long param) | |
789 | { | |
790 | struct sdhci_host *host; | |
791 | unsigned long flags; | |
792 | ||
793 | host = (struct sdhci_host*)param; | |
794 | ||
795 | spin_lock_irqsave(&host->lock, flags); | |
796 | ||
797 | if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { | |
798 | if (host->mrq) { | |
799 | printk(KERN_ERR "%s: Card removed during transfer!\n", | |
800 | mmc_hostname(host->mmc)); | |
801 | printk(KERN_ERR "%s: Resetting controller.\n", | |
802 | mmc_hostname(host->mmc)); | |
803 | ||
804 | sdhci_reset(host, SDHCI_RESET_CMD); | |
805 | sdhci_reset(host, SDHCI_RESET_DATA); | |
806 | ||
807 | host->mrq->cmd->error = MMC_ERR_FAILED; | |
808 | tasklet_schedule(&host->finish_tasklet); | |
809 | } | |
810 | } | |
811 | ||
812 | spin_unlock_irqrestore(&host->lock, flags); | |
813 | ||
814 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); | |
815 | } | |
816 | ||
817 | static void sdhci_tasklet_finish(unsigned long param) | |
818 | { | |
819 | struct sdhci_host *host; | |
820 | unsigned long flags; | |
821 | struct mmc_request *mrq; | |
822 | ||
823 | host = (struct sdhci_host*)param; | |
824 | ||
825 | spin_lock_irqsave(&host->lock, flags); | |
826 | ||
827 | del_timer(&host->timer); | |
828 | ||
829 | mrq = host->mrq; | |
830 | ||
831 | DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode); | |
832 | ||
833 | /* | |
834 | * The controller needs a reset of internal state machines | |
835 | * upon error conditions. | |
836 | */ | |
837 | if ((mrq->cmd->error != MMC_ERR_NONE) || | |
838 | (mrq->data && ((mrq->data->error != MMC_ERR_NONE) || | |
839 | (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) { | |
645289dc PO |
840 | |
841 | /* Some controllers need this kick or reset won't work here */ | |
842 | if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { | |
843 | unsigned int clock; | |
844 | ||
845 | /* This is to force an update */ | |
846 | clock = host->clock; | |
847 | host->clock = 0; | |
848 | sdhci_set_clock(host, clock); | |
849 | } | |
850 | ||
851 | /* Spec says we should do both at the same time, but Ricoh | |
852 | controllers do not like that. */ | |
d129bceb PO |
853 | sdhci_reset(host, SDHCI_RESET_CMD); |
854 | sdhci_reset(host, SDHCI_RESET_DATA); | |
855 | } | |
856 | ||
857 | host->mrq = NULL; | |
858 | host->cmd = NULL; | |
859 | host->data = NULL; | |
860 | ||
861 | sdhci_deactivate_led(host); | |
862 | ||
863 | spin_unlock_irqrestore(&host->lock, flags); | |
864 | ||
865 | mmc_request_done(host->mmc, mrq); | |
866 | } | |
867 | ||
868 | static void sdhci_timeout_timer(unsigned long data) | |
869 | { | |
870 | struct sdhci_host *host; | |
871 | unsigned long flags; | |
872 | ||
873 | host = (struct sdhci_host*)data; | |
874 | ||
875 | spin_lock_irqsave(&host->lock, flags); | |
876 | ||
877 | if (host->mrq) { | |
878 | printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. " | |
879 | "Please report this to " BUGMAIL ".\n", | |
880 | mmc_hostname(host->mmc)); | |
881 | sdhci_dumpregs(host); | |
882 | ||
883 | if (host->data) { | |
884 | host->data->error = MMC_ERR_TIMEOUT; | |
885 | sdhci_finish_data(host); | |
886 | } else { | |
887 | if (host->cmd) | |
888 | host->cmd->error = MMC_ERR_TIMEOUT; | |
889 | else | |
890 | host->mrq->cmd->error = MMC_ERR_TIMEOUT; | |
891 | ||
892 | tasklet_schedule(&host->finish_tasklet); | |
893 | } | |
894 | } | |
895 | ||
896 | spin_unlock_irqrestore(&host->lock, flags); | |
897 | } | |
898 | ||
899 | /*****************************************************************************\ | |
900 | * * | |
901 | * Interrupt handling * | |
902 | * * | |
903 | \*****************************************************************************/ | |
904 | ||
905 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) | |
906 | { | |
907 | BUG_ON(intmask == 0); | |
908 | ||
909 | if (!host->cmd) { | |
910 | printk(KERN_ERR "%s: Got command interrupt even though no " | |
911 | "command operation was in progress.\n", | |
912 | mmc_hostname(host->mmc)); | |
913 | printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n", | |
914 | mmc_hostname(host->mmc)); | |
915 | sdhci_dumpregs(host); | |
916 | return; | |
917 | } | |
918 | ||
919 | if (intmask & SDHCI_INT_RESPONSE) | |
920 | sdhci_finish_command(host); | |
921 | else { | |
922 | if (intmask & SDHCI_INT_TIMEOUT) | |
923 | host->cmd->error = MMC_ERR_TIMEOUT; | |
924 | else if (intmask & SDHCI_INT_CRC) | |
925 | host->cmd->error = MMC_ERR_BADCRC; | |
926 | else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) | |
927 | host->cmd->error = MMC_ERR_FAILED; | |
928 | else | |
929 | host->cmd->error = MMC_ERR_INVALID; | |
930 | ||
931 | tasklet_schedule(&host->finish_tasklet); | |
932 | } | |
933 | } | |
934 | ||
935 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) | |
936 | { | |
937 | BUG_ON(intmask == 0); | |
938 | ||
939 | if (!host->data) { | |
940 | /* | |
941 | * A data end interrupt is sent together with the response | |
942 | * for the stop command. | |
943 | */ | |
944 | if (intmask & SDHCI_INT_DATA_END) | |
945 | return; | |
946 | ||
947 | printk(KERN_ERR "%s: Got data interrupt even though no " | |
948 | "data operation was in progress.\n", | |
949 | mmc_hostname(host->mmc)); | |
950 | printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n", | |
951 | mmc_hostname(host->mmc)); | |
952 | sdhci_dumpregs(host); | |
953 | ||
954 | return; | |
955 | } | |
956 | ||
957 | if (intmask & SDHCI_INT_DATA_TIMEOUT) | |
958 | host->data->error = MMC_ERR_TIMEOUT; | |
959 | else if (intmask & SDHCI_INT_DATA_CRC) | |
960 | host->data->error = MMC_ERR_BADCRC; | |
961 | else if (intmask & SDHCI_INT_DATA_END_BIT) | |
962 | host->data->error = MMC_ERR_FAILED; | |
963 | ||
964 | if (host->data->error != MMC_ERR_NONE) | |
965 | sdhci_finish_data(host); | |
966 | else { | |
a406f5a3 | 967 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
d129bceb PO |
968 | sdhci_transfer_pio(host); |
969 | ||
970 | if (intmask & SDHCI_INT_DATA_END) | |
971 | sdhci_finish_data(host); | |
972 | } | |
973 | } | |
974 | ||
975 | static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs) | |
976 | { | |
977 | irqreturn_t result; | |
978 | struct sdhci_host* host = dev_id; | |
979 | u32 intmask; | |
980 | ||
981 | spin_lock(&host->lock); | |
982 | ||
983 | intmask = readl(host->ioaddr + SDHCI_INT_STATUS); | |
984 | ||
985 | if (!intmask) { | |
986 | result = IRQ_NONE; | |
987 | goto out; | |
988 | } | |
989 | ||
990 | DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask); | |
991 | ||
3192a28f PO |
992 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
993 | writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE), | |
994 | host->ioaddr + SDHCI_INT_STATUS); | |
d129bceb | 995 | tasklet_schedule(&host->card_tasklet); |
3192a28f | 996 | } |
d129bceb | 997 | |
3192a28f | 998 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); |
d129bceb | 999 | |
3192a28f | 1000 | if (intmask & SDHCI_INT_CMD_MASK) { |
d129bceb PO |
1001 | writel(intmask & SDHCI_INT_CMD_MASK, |
1002 | host->ioaddr + SDHCI_INT_STATUS); | |
3192a28f | 1003 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); |
d129bceb PO |
1004 | } |
1005 | ||
1006 | if (intmask & SDHCI_INT_DATA_MASK) { | |
d129bceb PO |
1007 | writel(intmask & SDHCI_INT_DATA_MASK, |
1008 | host->ioaddr + SDHCI_INT_STATUS); | |
3192a28f | 1009 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); |
d129bceb PO |
1010 | } |
1011 | ||
1012 | intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); | |
1013 | ||
d129bceb | 1014 | if (intmask & SDHCI_INT_BUS_POWER) { |
3192a28f | 1015 | printk(KERN_ERR "%s: Card is consuming too much power!\n", |
d129bceb | 1016 | mmc_hostname(host->mmc)); |
3192a28f | 1017 | writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS); |
d129bceb PO |
1018 | } |
1019 | ||
3192a28f PO |
1020 | intmask &= SDHCI_INT_BUS_POWER; |
1021 | ||
1022 | if (intmask) { | |
1023 | printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please " | |
d129bceb | 1024 | "report this to " BUGMAIL ".\n", |
3192a28f | 1025 | mmc_hostname(host->mmc), intmask); |
d129bceb PO |
1026 | sdhci_dumpregs(host); |
1027 | ||
d129bceb | 1028 | writel(intmask, host->ioaddr + SDHCI_INT_STATUS); |
3192a28f | 1029 | } |
d129bceb PO |
1030 | |
1031 | result = IRQ_HANDLED; | |
1032 | ||
1033 | out: | |
1034 | spin_unlock(&host->lock); | |
1035 | ||
1036 | return result; | |
1037 | } | |
1038 | ||
1039 | /*****************************************************************************\ | |
1040 | * * | |
1041 | * Suspend/resume * | |
1042 | * * | |
1043 | \*****************************************************************************/ | |
1044 | ||
1045 | #ifdef CONFIG_PM | |
1046 | ||
1047 | static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state) | |
1048 | { | |
1049 | struct sdhci_chip *chip; | |
1050 | int i, ret; | |
1051 | ||
1052 | chip = pci_get_drvdata(pdev); | |
1053 | if (!chip) | |
1054 | return 0; | |
1055 | ||
1056 | DBG("Suspending...\n"); | |
1057 | ||
1058 | for (i = 0;i < chip->num_slots;i++) { | |
1059 | if (!chip->hosts[i]) | |
1060 | continue; | |
1061 | ret = mmc_suspend_host(chip->hosts[i]->mmc, state); | |
1062 | if (ret) { | |
1063 | for (i--;i >= 0;i--) | |
1064 | mmc_resume_host(chip->hosts[i]->mmc); | |
1065 | return ret; | |
1066 | } | |
1067 | } | |
1068 | ||
1069 | pci_save_state(pdev); | |
1070 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); | |
1071 | pci_disable_device(pdev); | |
1072 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1073 | ||
1074 | return 0; | |
1075 | } | |
1076 | ||
1077 | static int sdhci_resume (struct pci_dev *pdev) | |
1078 | { | |
1079 | struct sdhci_chip *chip; | |
1080 | int i, ret; | |
1081 | ||
1082 | chip = pci_get_drvdata(pdev); | |
1083 | if (!chip) | |
1084 | return 0; | |
1085 | ||
1086 | DBG("Resuming...\n"); | |
1087 | ||
1088 | pci_set_power_state(pdev, PCI_D0); | |
1089 | pci_restore_state(pdev); | |
1090 | pci_enable_device(pdev); | |
1091 | ||
1092 | for (i = 0;i < chip->num_slots;i++) { | |
1093 | if (!chip->hosts[i]) | |
1094 | continue; | |
1095 | if (chip->hosts[i]->flags & SDHCI_USE_DMA) | |
1096 | pci_set_master(pdev); | |
1097 | sdhci_init(chip->hosts[i]); | |
1098 | ret = mmc_resume_host(chip->hosts[i]->mmc); | |
1099 | if (ret) | |
1100 | return ret; | |
1101 | } | |
1102 | ||
1103 | return 0; | |
1104 | } | |
1105 | ||
1106 | #else /* CONFIG_PM */ | |
1107 | ||
1108 | #define sdhci_suspend NULL | |
1109 | #define sdhci_resume NULL | |
1110 | ||
1111 | #endif /* CONFIG_PM */ | |
1112 | ||
1113 | /*****************************************************************************\ | |
1114 | * * | |
1115 | * Device probing/removal * | |
1116 | * * | |
1117 | \*****************************************************************************/ | |
1118 | ||
1119 | static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot) | |
1120 | { | |
1121 | int ret; | |
4a965505 | 1122 | unsigned int version; |
d129bceb PO |
1123 | struct sdhci_chip *chip; |
1124 | struct mmc_host *mmc; | |
1125 | struct sdhci_host *host; | |
1126 | ||
1127 | u8 first_bar; | |
1128 | unsigned int caps; | |
1129 | ||
1130 | chip = pci_get_drvdata(pdev); | |
1131 | BUG_ON(!chip); | |
1132 | ||
1133 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); | |
1134 | if (ret) | |
1135 | return ret; | |
1136 | ||
1137 | first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; | |
1138 | ||
1139 | if (first_bar > 5) { | |
1140 | printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n"); | |
1141 | return -ENODEV; | |
1142 | } | |
1143 | ||
1144 | if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) { | |
1145 | printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n"); | |
1146 | return -ENODEV; | |
1147 | } | |
1148 | ||
1149 | if (pci_resource_len(pdev, first_bar + slot) != 0x100) { | |
1150 | printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n"); | |
1151 | return -ENODEV; | |
1152 | } | |
1153 | ||
67435274 PO |
1154 | if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { |
1155 | printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n"); | |
1156 | return -ENODEV; | |
1157 | } | |
1158 | ||
1159 | if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { | |
1160 | printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n"); | |
1161 | return -ENODEV; | |
1162 | } | |
1163 | ||
d129bceb PO |
1164 | mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev); |
1165 | if (!mmc) | |
1166 | return -ENOMEM; | |
1167 | ||
1168 | host = mmc_priv(mmc); | |
1169 | host->mmc = mmc; | |
1170 | ||
1171 | host->bar = first_bar + slot; | |
1172 | ||
1173 | host->addr = pci_resource_start(pdev, host->bar); | |
1174 | host->irq = pdev->irq; | |
1175 | ||
1176 | DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq); | |
1177 | ||
1178 | snprintf(host->slot_descr, 20, "sdhci:slot%d", slot); | |
1179 | ||
1180 | ret = pci_request_region(pdev, host->bar, host->slot_descr); | |
1181 | if (ret) | |
1182 | goto free; | |
1183 | ||
1184 | host->ioaddr = ioremap_nocache(host->addr, | |
1185 | pci_resource_len(pdev, host->bar)); | |
1186 | if (!host->ioaddr) { | |
1187 | ret = -ENOMEM; | |
1188 | goto release; | |
1189 | } | |
1190 | ||
d96649ed PO |
1191 | sdhci_reset(host, SDHCI_RESET_ALL); |
1192 | ||
4a965505 PO |
1193 | version = readw(host->ioaddr + SDHCI_HOST_VERSION); |
1194 | version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; | |
1195 | if (version != 0) { | |
1196 | printk(KERN_ERR "%s: Unknown controller version (%d). " | |
8b1b2185 | 1197 | "You may experience problems.\n", host->slot_descr, |
4a965505 | 1198 | version); |
4a965505 PO |
1199 | } |
1200 | ||
d129bceb PO |
1201 | caps = readl(host->ioaddr + SDHCI_CAPABILITIES); |
1202 | ||
67435274 PO |
1203 | if (debug_nodma) |
1204 | DBG("DMA forced off\n"); | |
1205 | else if (debug_forcedma) { | |
1206 | DBG("DMA forced on\n"); | |
1207 | host->flags |= SDHCI_USE_DMA; | |
98608076 PO |
1208 | } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA) |
1209 | host->flags |= SDHCI_USE_DMA; | |
1210 | else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) | |
67435274 PO |
1211 | DBG("Controller doesn't have DMA interface\n"); |
1212 | else if (!(caps & SDHCI_CAN_DO_DMA)) | |
1213 | DBG("Controller doesn't have DMA capability\n"); | |
1214 | else | |
d129bceb PO |
1215 | host->flags |= SDHCI_USE_DMA; |
1216 | ||
1217 | if (host->flags & SDHCI_USE_DMA) { | |
1218 | if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { | |
1219 | printk(KERN_WARNING "%s: No suitable DMA available. " | |
1220 | "Falling back to PIO.\n", host->slot_descr); | |
1221 | host->flags &= ~SDHCI_USE_DMA; | |
1222 | } | |
1223 | } | |
1224 | ||
1225 | if (host->flags & SDHCI_USE_DMA) | |
1226 | pci_set_master(pdev); | |
1227 | else /* XXX: Hack to get MMC layer to avoid highmem */ | |
1228 | pdev->dma_mask = 0; | |
1229 | ||
8ef1a143 PO |
1230 | host->max_clk = |
1231 | (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; | |
1232 | if (host->max_clk == 0) { | |
1233 | printk(KERN_ERR "%s: Hardware doesn't specify base clock " | |
1234 | "frequency.\n", host->slot_descr); | |
1235 | ret = -ENODEV; | |
1236 | goto unmap; | |
1237 | } | |
d129bceb PO |
1238 | host->max_clk *= 1000000; |
1239 | ||
1c8cde92 PO |
1240 | host->timeout_clk = |
1241 | (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; | |
1242 | if (host->timeout_clk == 0) { | |
1243 | printk(KERN_ERR "%s: Hardware doesn't specify timeout clock " | |
1244 | "frequency.\n", host->slot_descr); | |
1245 | ret = -ENODEV; | |
1246 | goto unmap; | |
1247 | } | |
1248 | if (caps & SDHCI_TIMEOUT_CLK_UNIT) | |
1249 | host->timeout_clk *= 1000; | |
d129bceb | 1250 | |
1d676e02 PO |
1251 | host->max_block = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT; |
1252 | if (host->max_block >= 3) { | |
1253 | printk(KERN_ERR "%s: Invalid maximum block size.\n", | |
1254 | host->slot_descr); | |
1255 | ret = -ENODEV; | |
1256 | goto unmap; | |
1257 | } | |
1258 | host->max_block = 512 << host->max_block; | |
1259 | ||
d129bceb PO |
1260 | /* |
1261 | * Set host parameters. | |
1262 | */ | |
1263 | mmc->ops = &sdhci_ops; | |
1264 | mmc->f_min = host->max_clk / 256; | |
1265 | mmc->f_max = host->max_clk; | |
42431acb | 1266 | mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK; |
d129bceb | 1267 | |
146ad66e PO |
1268 | mmc->ocr_avail = 0; |
1269 | if (caps & SDHCI_CAN_VDD_330) | |
1270 | mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34; | |
1271 | else if (caps & SDHCI_CAN_VDD_300) | |
1272 | mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31; | |
1273 | else if (caps & SDHCI_CAN_VDD_180) | |
1274 | mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19; | |
1275 | ||
1276 | if (mmc->ocr_avail == 0) { | |
1277 | printk(KERN_ERR "%s: Hardware doesn't report any " | |
1278 | "support voltages.\n", host->slot_descr); | |
1279 | ret = -ENODEV; | |
1280 | goto unmap; | |
1281 | } | |
1282 | ||
d129bceb PO |
1283 | spin_lock_init(&host->lock); |
1284 | ||
1285 | /* | |
1286 | * Maximum number of segments. Hardware cannot do scatter lists. | |
1287 | */ | |
1288 | if (host->flags & SDHCI_USE_DMA) | |
1289 | mmc->max_hw_segs = 1; | |
1290 | else | |
1291 | mmc->max_hw_segs = 16; | |
1292 | mmc->max_phys_segs = 16; | |
1293 | ||
1294 | /* | |
bab76961 PO |
1295 | * Maximum number of sectors in one transfer. Limited by DMA boundary |
1296 | * size (512KiB), which means (512 KiB/512=) 1024 entries. | |
d129bceb | 1297 | */ |
bab76961 | 1298 | mmc->max_sectors = 1024; |
d129bceb PO |
1299 | |
1300 | /* | |
1301 | * Maximum segment size. Could be one segment with the maximum number | |
1302 | * of sectors. | |
1303 | */ | |
1304 | mmc->max_seg_size = mmc->max_sectors * 512; | |
1305 | ||
1306 | /* | |
1307 | * Init tasklets. | |
1308 | */ | |
1309 | tasklet_init(&host->card_tasklet, | |
1310 | sdhci_tasklet_card, (unsigned long)host); | |
1311 | tasklet_init(&host->finish_tasklet, | |
1312 | sdhci_tasklet_finish, (unsigned long)host); | |
1313 | ||
e474c66b | 1314 | setup_timer(&host->timer, sdhci_timeout_timer, (long)host); |
d129bceb | 1315 | |
dace1453 | 1316 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
d129bceb PO |
1317 | host->slot_descr, host); |
1318 | if (ret) | |
8ef1a143 | 1319 | goto untasklet; |
d129bceb PO |
1320 | |
1321 | sdhci_init(host); | |
1322 | ||
1323 | #ifdef CONFIG_MMC_DEBUG | |
1324 | sdhci_dumpregs(host); | |
1325 | #endif | |
1326 | ||
1327 | host->chip = chip; | |
1328 | chip->hosts[slot] = host; | |
1329 | ||
1330 | mmc_add_host(mmc); | |
1331 | ||
1332 | printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc), | |
1333 | host->addr, host->irq, | |
1334 | (host->flags & SDHCI_USE_DMA)?"DMA":"PIO"); | |
1335 | ||
1336 | return 0; | |
1337 | ||
8ef1a143 | 1338 | untasklet: |
d129bceb PO |
1339 | tasklet_kill(&host->card_tasklet); |
1340 | tasklet_kill(&host->finish_tasklet); | |
8ef1a143 | 1341 | unmap: |
d129bceb PO |
1342 | iounmap(host->ioaddr); |
1343 | release: | |
1344 | pci_release_region(pdev, host->bar); | |
1345 | free: | |
1346 | mmc_free_host(mmc); | |
1347 | ||
1348 | return ret; | |
1349 | } | |
1350 | ||
1351 | static void sdhci_remove_slot(struct pci_dev *pdev, int slot) | |
1352 | { | |
1353 | struct sdhci_chip *chip; | |
1354 | struct mmc_host *mmc; | |
1355 | struct sdhci_host *host; | |
1356 | ||
1357 | chip = pci_get_drvdata(pdev); | |
1358 | host = chip->hosts[slot]; | |
1359 | mmc = host->mmc; | |
1360 | ||
1361 | chip->hosts[slot] = NULL; | |
1362 | ||
1363 | mmc_remove_host(mmc); | |
1364 | ||
1365 | sdhci_reset(host, SDHCI_RESET_ALL); | |
1366 | ||
1367 | free_irq(host->irq, host); | |
1368 | ||
1369 | del_timer_sync(&host->timer); | |
1370 | ||
1371 | tasklet_kill(&host->card_tasklet); | |
1372 | tasklet_kill(&host->finish_tasklet); | |
1373 | ||
1374 | iounmap(host->ioaddr); | |
1375 | ||
1376 | pci_release_region(pdev, host->bar); | |
1377 | ||
1378 | mmc_free_host(mmc); | |
1379 | } | |
1380 | ||
1381 | static int __devinit sdhci_probe(struct pci_dev *pdev, | |
1382 | const struct pci_device_id *ent) | |
1383 | { | |
1384 | int ret, i; | |
51f82bc0 | 1385 | u8 slots, rev; |
d129bceb PO |
1386 | struct sdhci_chip *chip; |
1387 | ||
1388 | BUG_ON(pdev == NULL); | |
1389 | BUG_ON(ent == NULL); | |
1390 | ||
51f82bc0 PO |
1391 | pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev); |
1392 | ||
1393 | printk(KERN_INFO DRIVER_NAME | |
1394 | ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n", | |
1395 | pci_name(pdev), (int)pdev->vendor, (int)pdev->device, | |
1396 | (int)rev); | |
d129bceb PO |
1397 | |
1398 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); | |
1399 | if (ret) | |
1400 | return ret; | |
1401 | ||
1402 | slots = PCI_SLOT_INFO_SLOTS(slots) + 1; | |
1403 | DBG("found %d slot(s)\n", slots); | |
1404 | if (slots == 0) | |
1405 | return -ENODEV; | |
1406 | ||
1407 | ret = pci_enable_device(pdev); | |
1408 | if (ret) | |
1409 | return ret; | |
1410 | ||
1411 | chip = kzalloc(sizeof(struct sdhci_chip) + | |
1412 | sizeof(struct sdhci_host*) * slots, GFP_KERNEL); | |
1413 | if (!chip) { | |
1414 | ret = -ENOMEM; | |
1415 | goto err; | |
1416 | } | |
1417 | ||
1418 | chip->pdev = pdev; | |
df673b22 PO |
1419 | chip->quirks = ent->driver_data; |
1420 | ||
1421 | if (debug_quirks) | |
1422 | chip->quirks = debug_quirks; | |
d129bceb PO |
1423 | |
1424 | chip->num_slots = slots; | |
1425 | pci_set_drvdata(pdev, chip); | |
1426 | ||
1427 | for (i = 0;i < slots;i++) { | |
1428 | ret = sdhci_probe_slot(pdev, i); | |
1429 | if (ret) { | |
1430 | for (i--;i >= 0;i--) | |
1431 | sdhci_remove_slot(pdev, i); | |
1432 | goto free; | |
1433 | } | |
1434 | } | |
1435 | ||
1436 | return 0; | |
1437 | ||
1438 | free: | |
1439 | pci_set_drvdata(pdev, NULL); | |
1440 | kfree(chip); | |
1441 | ||
1442 | err: | |
1443 | pci_disable_device(pdev); | |
1444 | return ret; | |
1445 | } | |
1446 | ||
1447 | static void __devexit sdhci_remove(struct pci_dev *pdev) | |
1448 | { | |
1449 | int i; | |
1450 | struct sdhci_chip *chip; | |
1451 | ||
1452 | chip = pci_get_drvdata(pdev); | |
1453 | ||
1454 | if (chip) { | |
1455 | for (i = 0;i < chip->num_slots;i++) | |
1456 | sdhci_remove_slot(pdev, i); | |
1457 | ||
1458 | pci_set_drvdata(pdev, NULL); | |
1459 | ||
1460 | kfree(chip); | |
1461 | } | |
1462 | ||
1463 | pci_disable_device(pdev); | |
1464 | } | |
1465 | ||
1466 | static struct pci_driver sdhci_driver = { | |
1467 | .name = DRIVER_NAME, | |
1468 | .id_table = pci_ids, | |
1469 | .probe = sdhci_probe, | |
1470 | .remove = __devexit_p(sdhci_remove), | |
1471 | .suspend = sdhci_suspend, | |
1472 | .resume = sdhci_resume, | |
1473 | }; | |
1474 | ||
1475 | /*****************************************************************************\ | |
1476 | * * | |
1477 | * Driver init/exit * | |
1478 | * * | |
1479 | \*****************************************************************************/ | |
1480 | ||
1481 | static int __init sdhci_drv_init(void) | |
1482 | { | |
1483 | printk(KERN_INFO DRIVER_NAME | |
1484 | ": Secure Digital Host Controller Interface driver, " | |
1485 | DRIVER_VERSION "\n"); | |
1486 | printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); | |
1487 | ||
1488 | return pci_register_driver(&sdhci_driver); | |
1489 | } | |
1490 | ||
1491 | static void __exit sdhci_drv_exit(void) | |
1492 | { | |
1493 | DBG("Exiting\n"); | |
1494 | ||
1495 | pci_unregister_driver(&sdhci_driver); | |
1496 | } | |
1497 | ||
1498 | module_init(sdhci_drv_init); | |
1499 | module_exit(sdhci_drv_exit); | |
1500 | ||
67435274 PO |
1501 | module_param(debug_nodma, uint, 0444); |
1502 | module_param(debug_forcedma, uint, 0444); | |
df673b22 | 1503 | module_param(debug_quirks, uint, 0444); |
67435274 | 1504 | |
d129bceb PO |
1505 | MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>"); |
1506 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver"); | |
1507 | MODULE_VERSION(DRIVER_VERSION); | |
1508 | MODULE_LICENSE("GPL"); | |
67435274 PO |
1509 | |
1510 | MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)"); | |
1511 | MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)"); | |
df673b22 | 1512 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |