[mirror_ubuntu-bionic-kernel.git] / drivers / mtd / chips / Kconfig

# drivers/mtd/chips/Kconfig

menu "RAM/ROM/Flash chip drivers"
	depends on MTD!=n

config MTD_CFI
	tristate "Detect flash chips by Common Flash Interface (CFI) probe"
	select MTD_GEN_PROBE
	help
	  The Common Flash Interface specification was developed by Intel,
	  AMD and other flash manufactures that provides a universal method
	  for probing the capabilities of flash devices. If you wish to
	  support any device that is CFI-compliant, you need to enable this
	  option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
	  for more information on CFI.

config MTD_JEDECPROBE
	tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
	select MTD_GEN_PROBE
	help
	  This option enables JEDEC-style probing of flash chips which are not
	  compatible with the Common Flash Interface, but will use the common
	  CFI-targetted flash drivers for any chips which are identified which
	  are in fact compatible in all but the probe method. This actually
	  covers most AMD/Fujitsu-compatible chips and also non-CFI
	  Intel chips.

config MTD_GEN_PROBE
	tristate

config MTD_CFI_ADV_OPTIONS
	bool "Flash chip driver advanced configuration options"
	depends on MTD_GEN_PROBE
	help
	  If you need to specify a specific endianness for access to flash
	  chips, or if you wish to reduce the size of the kernel by including
	  support for only specific arrangements of flash chips, say 'Y'. This
	  option does not directly affect the code, but will enable other
	  configuration options which allow you to do so.

	  If unsure, say 'N'.

choice
	prompt "Flash cmd/query data swapping"
	depends on MTD_CFI_ADV_OPTIONS
	default MTD_CFI_NOSWAP

config MTD_CFI_NOSWAP
	bool "NO"
	---help---
	  This option defines the way in which the CPU attempts to arrange
	  data bits when writing the 'magic' commands to the chips. Saying
	  'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
	  enabled, means that the CPU will not do any swapping; the chips
	  are expected to be wired to the CPU in 'host-endian' form.
	  Specific arrangements are possible with the BIG_ENDIAN_BYTE and
	  LITTLE_ENDIAN_BYTE, if the bytes are reversed.

	  If you have a LART, on which the data (and address) lines were
	  connected in a fashion which ensured that the nets were as short
	  as possible, resulting in a bit-shuffling which seems utterly
	  random to the untrained eye, you need the LART_ENDIAN_BYTE option.

	  Yes, there really exists something sicker than PDP-endian :)

config MTD_CFI_BE_BYTE_SWAP
	bool "BIG_ENDIAN_BYTE"

config MTD_CFI_LE_BYTE_SWAP
	bool "LITTLE_ENDIAN_BYTE"

endchoice

config MTD_CFI_GEOMETRY
	bool "Specific CFI Flash geometry selection"
	depends on MTD_CFI_ADV_OPTIONS
	help
	  This option does not affect the code directly, but will enable
	  some other configuration options which would allow you to reduce
	  the size of the kernel by including support for only certain
	  arrangements of CFI chips. If unsure, say 'N' and all options
	  which are supported by the current code will be enabled.

config MTD_MAP_BANK_WIDTH_1
	bool "Support  8-bit buswidth" if MTD_CFI_GEOMETRY
	default y
	help
	  If you wish to support CFI devices on a physical bus which is
	  8 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_2
	bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
	default y
	help
	  If you wish to support CFI devices on a physical bus which is
	  16 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_4
	bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
	default y
	help
	  If you wish to support CFI devices on a physical bus which is
	  32 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_8
	bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
	default n
	help
	  If you wish to support CFI devices on a physical bus which is
	  64 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_16
	bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
	default n
	help
	  If you wish to support CFI devices on a physical bus which is
	  128 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_32
	bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
	default n
	help
	  If you wish to support CFI devices on a physical bus which is
	  256 bits wide, say 'Y'.

config MTD_CFI_I1
	bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
	default y
	help
	  If your flash chips are not interleaved - i.e. you only have one
	  flash chip addressed by each bus cycle, then say 'Y'.

config MTD_CFI_I2
	bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
	default y
	help
	  If your flash chips are interleaved in pairs - i.e. you have two
	  flash chips addressed by each bus cycle, then say 'Y'.

config MTD_CFI_I4
	bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
	default n
	help
	  If your flash chips are interleaved in fours - i.e. you have four
	  flash chips addressed by each bus cycle, then say 'Y'.

config MTD_CFI_I8
	bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
	default n
	help
	  If your flash chips are interleaved in eights - i.e. you have eight
	  flash chips addressed by each bus cycle, then say 'Y'.

config MTD_OTP
	bool "Protection Registers aka one-time programmable (OTP) bits"
	depends on MTD_CFI_ADV_OPTIONS
	select HAVE_MTD_OTP
	default n
	help
	  This enables support for reading, writing and locking so called
	  "Protection Registers" present on some flash chips.
	  A subset of them are pre-programmed at the factory with a
	  unique set of values. The rest is user-programmable.

	  The user-programmable Protection Registers contain one-time
	  programmable (OTP) bits; when programmed, register bits cannot be
	  erased. Each Protection Register can be accessed multiple times to
	  program individual bits, as long as the register remains unlocked.

	  Each Protection Register has an associated Lock Register bit. When a
	  Lock Register bit is programmed, the associated Protection Register
	  can only be read; it can no longer be programmed. Additionally,
	  because the Lock Register bits themselves are OTP, when programmed,
	  Lock Register bits cannot be erased. Therefore, when a Protection
	  Register is locked, it cannot be unlocked.

	  This feature should therefore be used with extreme care. Any mistake
	  in the programming of OTP bits will waste them.

config MTD_CFI_INTELEXT
	tristate "Support for Intel/Sharp flash chips"
	depends on MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface defines a number of different command
	  sets which a CFI-compliant chip may claim to implement. This code
	  provides support for one of those command sets, used on Intel
	  StrataFlash and other parts.

config MTD_CFI_AMDSTD
	tristate "Support for AMD/Fujitsu flash chips"
	depends on MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface defines a number of different command
	  sets which a CFI-compliant chip may claim to implement. This code
	  provides support for one of those command sets, used on chips
	  including the AMD Am29LV320.

config MTD_CFI_STAA
	tristate "Support for ST (Advanced Architecture) flash chips"
	depends on MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface defines a number of different command
	  sets which a CFI-compliant chip may claim to implement. This code
	  provides support for one of those command sets.

config MTD_CFI_UTIL
	tristate

config MTD_RAM
	tristate "Support for RAM chips in bus mapping"
	help
	  This option enables basic support for RAM chips accessed through
	  a bus mapping driver.

config MTD_ROM
	tristate "Support for ROM chips in bus mapping"
	help
	  This option enables basic support for ROM chips accessed through
	  a bus mapping driver.

config MTD_ABSENT
	tristate "Support for absent chips in bus mapping"
	help
	  This option enables support for a dummy probing driver used to
	  allocated placeholder MTD devices on systems that have socketed
	  or removable media.  Use of this driver as a fallback chip probe
	  preserves the expected registration order of MTD device nodes on
	  the system regardless of media presence.  Device nodes created
	  with this driver will return -ENODEV upon access.

config MTD_XIP
	bool "XIP aware MTD support"
	depends on !SMP && (MTD_CFI_INTELEXT || MTD_CFI_AMDSTD) && EXPERIMENTAL && ARCH_MTD_XIP
	default y if XIP_KERNEL
	help
	  This allows MTD support to work with flash memory which is also
	  used for XIP purposes.  If you're not sure what this is all about
	  then say N.

endmenu
Commit	Line	Data
1da177e4	1	# drivers/mtd/chips/Kconfig
1da177e4 LT	2
	3	menu "RAM/ROM/Flash chip drivers"
	4	depends on MTD!=n
	5
	6	config MTD_CFI
	7	tristate "Detect flash chips by Common Flash Interface (CFI) probe"
1da177e4 LT	8	select MTD_GEN_PROBE
	9	help
	10	The Common Flash Interface specification was developed by Intel,
	11	AMD and other flash manufactures that provides a universal method
	12	for probing the capabilities of flash devices. If you wish to
	13	support any device that is CFI-compliant, you need to enable this
	14	option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
	15	for more information on CFI.
	16
	17	config MTD_JEDECPROBE
	18	tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
1da177e4 LT	19	select MTD_GEN_PROBE
	20	help
	21	This option enables JEDEC-style probing of flash chips which are not
	22	compatible with the Common Flash Interface, but will use the common
	23	CFI-targetted flash drivers for any chips which are identified which
	24	are in fact compatible in all but the probe method. This actually
8917f6f7 AB	25	covers most AMD/Fujitsu-compatible chips and also non-CFI
8917f6f7 AB	26	Intel chips.
1da177e4 LT	27
	28	config MTD_GEN_PROBE
	29	tristate
	30
	31	config MTD_CFI_ADV_OPTIONS
	32	bool "Flash chip driver advanced configuration options"
	33	depends on MTD_GEN_PROBE
	34	help
	35	If you need to specify a specific endianness for access to flash
	36	chips, or if you wish to reduce the size of the kernel by including
	37	support for only specific arrangements of flash chips, say 'Y'. This
1f948b43	38	option does not directly affect the code, but will enable other
1da177e4 LT	39	configuration options which allow you to do so.
	40
	41	If unsure, say 'N'.
	42
	43	choice
	44	prompt "Flash cmd/query data swapping"
	45	depends on MTD_CFI_ADV_OPTIONS
	46	default MTD_CFI_NOSWAP
	47
	48	config MTD_CFI_NOSWAP
	49	bool "NO"
	50	---help---
	51	This option defines the way in which the CPU attempts to arrange
	52	data bits when writing the 'magic' commands to the chips. Saying
	53	'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
	54	enabled, means that the CPU will not do any swapping; the chips
1f948b43	55	are expected to be wired to the CPU in 'host-endian' form.
1da177e4 LT	56	Specific arrangements are possible with the BIG_ENDIAN_BYTE and
	57	LITTLE_ENDIAN_BYTE, if the bytes are reversed.
	58
	59	If you have a LART, on which the data (and address) lines were
	60	connected in a fashion which ensured that the nets were as short
	61	as possible, resulting in a bit-shuffling which seems utterly
	62	random to the untrained eye, you need the LART_ENDIAN_BYTE option.
	63
	64	Yes, there really exists something sicker than PDP-endian :)
	65
	66	config MTD_CFI_BE_BYTE_SWAP
	67	bool "BIG_ENDIAN_BYTE"
	68
	69	config MTD_CFI_LE_BYTE_SWAP
	70	bool "LITTLE_ENDIAN_BYTE"
	71
	72	endchoice
	73
	74	config MTD_CFI_GEOMETRY
	75	bool "Specific CFI Flash geometry selection"
	76	depends on MTD_CFI_ADV_OPTIONS
	77	help
1f948b43	78	This option does not affect the code directly, but will enable
1da177e4	79	some other configuration options which would allow you to reduce
1f948b43 TG	80	the size of the kernel by including support for only certain
1f948b43 TG	81	arrangements of CFI chips. If unsure, say 'N' and all options
1da177e4 LT	82	which are supported by the current code will be enabled.
	83
	84	config MTD_MAP_BANK_WIDTH_1
	85	bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
	86	default y
	87	help
	88	If you wish to support CFI devices on a physical bus which is
	89	8 bits wide, say 'Y'.
	90
	91	config MTD_MAP_BANK_WIDTH_2
	92	bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
	93	default y
	94	help
	95	If you wish to support CFI devices on a physical bus which is
	96	16 bits wide, say 'Y'.
	97
	98	config MTD_MAP_BANK_WIDTH_4
	99	bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
	100	default y
	101	help
	102	If you wish to support CFI devices on a physical bus which is
	103	32 bits wide, say 'Y'.
	104
	105	config MTD_MAP_BANK_WIDTH_8
	106	bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
	107	default n
	108	help
	109	If you wish to support CFI devices on a physical bus which is
	110	64 bits wide, say 'Y'.
	111
	112	config MTD_MAP_BANK_WIDTH_16
	113	bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
	114	default n
	115	help
	116	If you wish to support CFI devices on a physical bus which is
	117	128 bits wide, say 'Y'.
	118
	119	config MTD_MAP_BANK_WIDTH_32
	120	bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
	121	default n
	122	help
	123	If you wish to support CFI devices on a physical bus which is
	124	256 bits wide, say 'Y'.
	125
	126	config MTD_CFI_I1
	127	bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
	128	default y
	129	help
	130	If your flash chips are not interleaved - i.e. you only have one
	131	flash chip addressed by each bus cycle, then say 'Y'.
	132
	133	config MTD_CFI_I2
	134	bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
	135	default y
	136	help
	137	If your flash chips are interleaved in pairs - i.e. you have two
	138	flash chips addressed by each bus cycle, then say 'Y'.
	139
	140	config MTD_CFI_I4
	141	bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
	142	default n
	143	help
	144	If your flash chips are interleaved in fours - i.e. you have four
	145	flash chips addressed by each bus cycle, then say 'Y'.
146
147	config MTD_CFI_I8
148	bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
149	default n
150	help
151	If your flash chips are interleaved in eights - i.e. you have eight
152	flash chips addressed by each bus cycle, then say 'Y'.
153
f77814dd NP	154	config MTD_OTP
	155	bool "Protection Registers aka one-time programmable (OTP) bits"
	156	depends on MTD_CFI_ADV_OPTIONS
34a82443	157	select HAVE_MTD_OTP
f77814dd NP	158	default n
	159	help
	160	This enables support for reading, writing and locking so called
	161	"Protection Registers" present on some flash chips.
	162	A subset of them are pre-programmed at the factory with a
	163	unique set of values. The rest is user-programmable.
	164
	165	The user-programmable Protection Registers contain one-time
	166	programmable (OTP) bits; when programmed, register bits cannot be
	167	erased. Each Protection Register can be accessed multiple times to
	168	program individual bits, as long as the register remains unlocked.
	169
	170	Each Protection Register has an associated Lock Register bit. When a
	171	Lock Register bit is programmed, the associated Protection Register
	172	can only be read; it can no longer be programmed. Additionally,
	173	because the Lock Register bits themselves are OTP, when programmed,
	174	Lock Register bits cannot be erased. Therefore, when a Protection
	175	Register is locked, it cannot be unlocked.
	176
	177	This feature should therefore be used with extreme care. Any mistake
	178	in the programming of OTP bits will waste them.
	179
1da177e4 LT	180	config MTD_CFI_INTELEXT
	181	tristate "Support for Intel/Sharp flash chips"
	182	depends on MTD_GEN_PROBE
	183	select MTD_CFI_UTIL
	184	help
	185	The Common Flash Interface defines a number of different command
	186	sets which a CFI-compliant chip may claim to implement. This code
	187	provides support for one of those command sets, used on Intel
	188	StrataFlash and other parts.
	189
	190	config MTD_CFI_AMDSTD
	191	tristate "Support for AMD/Fujitsu flash chips"
	192	depends on MTD_GEN_PROBE
	193	select MTD_CFI_UTIL
	194	help
	195	The Common Flash Interface defines a number of different command
	196	sets which a CFI-compliant chip may claim to implement. This code
1f948b43	197	provides support for one of those command sets, used on chips
1da177e4 LT	198	including the AMD Am29LV320.
1da177e4 LT	199
1da177e4 LT	200	config MTD_CFI_STAA
	201	tristate "Support for ST (Advanced Architecture) flash chips"
	202	depends on MTD_GEN_PROBE
	203	select MTD_CFI_UTIL
	204	help
	205	The Common Flash Interface defines a number of different command
	206	sets which a CFI-compliant chip may claim to implement. This code
	207	provides support for one of those command sets.
	208
	209	config MTD_CFI_UTIL
	210	tristate
	211
	212	config MTD_RAM
	213	tristate "Support for RAM chips in bus mapping"
1da177e4	214	help
1f948b43	215	This option enables basic support for RAM chips accessed through
1da177e4 LT	216	a bus mapping driver.
	217
	218	config MTD_ROM
	219	tristate "Support for ROM chips in bus mapping"
1da177e4	220	help
1f948b43	221	This option enables basic support for ROM chips accessed through
1da177e4 LT	222	a bus mapping driver.
	223
	224	config MTD_ABSENT
	225	tristate "Support for absent chips in bus mapping"
1da177e4 LT	226	help
	227	This option enables support for a dummy probing driver used to
	228	allocated placeholder MTD devices on systems that have socketed
	229	or removable media. Use of this driver as a fallback chip probe
	230	preserves the expected registration order of MTD device nodes on
	231	the system regardless of media presence. Device nodes created
	232	with this driver will return -ENODEV upon access.
	233
1da177e4 LT	234	config MTD_XIP
1da177e4 LT	235	bool "XIP aware MTD support"
034d2f5a	236	depends on !SMP && (MTD_CFI_INTELEXT \|\| MTD_CFI_AMDSTD) && EXPERIMENTAL && ARCH_MTD_XIP
1da177e4 LT	237	default y if XIP_KERNEL
	238	help
	239	This allows MTD support to work with flash memory which is also
	240	used for XIP purposes. If you're not sure what this is all about
	241	then say N.
	242
	243	endmenu
	244