]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Common Flash Interface support: | |
3 | * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002) | |
4 | * | |
5 | * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp> | |
6 | * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com> | |
02b15e34 | 7 | * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com> |
1da177e4 LT |
8 | * |
9 | * 2_by_8 routines added by Simon Munton | |
10 | * | |
11 | * 4_by_16 work by Carolyn J. Smith | |
12 | * | |
1f948b43 | 13 | * XIP support hooks by Vitaly Wool (based on code for Intel flash |
02b15e34 | 14 | * by Nicolas Pitre) |
1f948b43 | 15 | * |
87e92c06 CM |
16 | * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0 |
17 | * | |
1da177e4 LT |
18 | * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com |
19 | * | |
20 | * This code is GPL | |
1da177e4 LT |
21 | */ |
22 | ||
1da177e4 LT |
23 | #include <linux/module.h> |
24 | #include <linux/types.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/init.h> | |
28 | #include <asm/io.h> | |
29 | #include <asm/byteorder.h> | |
30 | ||
31 | #include <linux/errno.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/interrupt.h> | |
eafe1311 | 35 | #include <linux/reboot.h> |
1da177e4 LT |
36 | #include <linux/mtd/compatmac.h> |
37 | #include <linux/mtd/map.h> | |
38 | #include <linux/mtd/mtd.h> | |
39 | #include <linux/mtd/cfi.h> | |
02b15e34 | 40 | #include <linux/mtd/xip.h> |
1da177e4 LT |
41 | |
42 | #define AMD_BOOTLOC_BUG | |
43 | #define FORCE_WORD_WRITE 0 | |
44 | ||
45 | #define MAX_WORD_RETRIES 3 | |
46 | ||
1da177e4 | 47 | #define SST49LF004B 0x0060 |
89072ef9 | 48 | #define SST49LF040B 0x0050 |
fb4a90bf | 49 | #define SST49LF008A 0x005a |
0165508c | 50 | #define AT49BV6416 0x00d6 |
1da177e4 LT |
51 | |
52 | static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); | |
53 | static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); | |
54 | static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); | |
55 | static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *); | |
56 | static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *); | |
57 | static void cfi_amdstd_sync (struct mtd_info *); | |
58 | static int cfi_amdstd_suspend (struct mtd_info *); | |
59 | static void cfi_amdstd_resume (struct mtd_info *); | |
eafe1311 | 60 | static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *); |
1da177e4 LT |
61 | static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); |
62 | ||
63 | static void cfi_amdstd_destroy(struct mtd_info *); | |
64 | ||
65 | struct mtd_info *cfi_cmdset_0002(struct map_info *, int); | |
66 | static struct mtd_info *cfi_amdstd_setup (struct mtd_info *); | |
67 | ||
68 | static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode); | |
69 | static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr); | |
70 | #include "fwh_lock.h" | |
71 | ||
69423d99 AH |
72 | static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); |
73 | static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); | |
0165508c | 74 | |
1da177e4 LT |
75 | static struct mtd_chip_driver cfi_amdstd_chipdrv = { |
76 | .probe = NULL, /* Not usable directly */ | |
77 | .destroy = cfi_amdstd_destroy, | |
78 | .name = "cfi_cmdset_0002", | |
79 | .module = THIS_MODULE | |
80 | }; | |
81 | ||
82 | ||
83 | /* #define DEBUG_CFI_FEATURES */ | |
84 | ||
85 | ||
86 | #ifdef DEBUG_CFI_FEATURES | |
87 | static void cfi_tell_features(struct cfi_pri_amdstd *extp) | |
88 | { | |
89 | const char* erase_suspend[3] = { | |
90 | "Not supported", "Read only", "Read/write" | |
91 | }; | |
92 | const char* top_bottom[6] = { | |
93 | "No WP", "8x8KiB sectors at top & bottom, no WP", | |
94 | "Bottom boot", "Top boot", | |
95 | "Uniform, Bottom WP", "Uniform, Top WP" | |
96 | }; | |
97 | ||
98 | printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1); | |
1f948b43 | 99 | printk(" Address sensitive unlock: %s\n", |
1da177e4 LT |
100 | (extp->SiliconRevision & 1) ? "Not required" : "Required"); |
101 | ||
102 | if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend)) | |
103 | printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]); | |
104 | else | |
105 | printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend); | |
106 | ||
107 | if (extp->BlkProt == 0) | |
108 | printk(" Block protection: Not supported\n"); | |
109 | else | |
110 | printk(" Block protection: %d sectors per group\n", extp->BlkProt); | |
111 | ||
112 | ||
113 | printk(" Temporary block unprotect: %s\n", | |
114 | extp->TmpBlkUnprotect ? "Supported" : "Not supported"); | |
115 | printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot); | |
116 | printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps); | |
117 | printk(" Burst mode: %s\n", | |
118 | extp->BurstMode ? "Supported" : "Not supported"); | |
119 | if (extp->PageMode == 0) | |
120 | printk(" Page mode: Not supported\n"); | |
121 | else | |
122 | printk(" Page mode: %d word page\n", extp->PageMode << 2); | |
123 | ||
1f948b43 | 124 | printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n", |
1da177e4 | 125 | extp->VppMin >> 4, extp->VppMin & 0xf); |
1f948b43 | 126 | printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n", |
1da177e4 LT |
127 | extp->VppMax >> 4, extp->VppMax & 0xf); |
128 | ||
129 | if (extp->TopBottom < ARRAY_SIZE(top_bottom)) | |
130 | printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]); | |
131 | else | |
132 | printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom); | |
133 | } | |
134 | #endif | |
135 | ||
136 | #ifdef AMD_BOOTLOC_BUG | |
137 | /* Wheee. Bring me the head of someone at AMD. */ | |
138 | static void fixup_amd_bootblock(struct mtd_info *mtd, void* param) | |
139 | { | |
140 | struct map_info *map = mtd->priv; | |
141 | struct cfi_private *cfi = map->fldrv_priv; | |
142 | struct cfi_pri_amdstd *extp = cfi->cmdset_priv; | |
143 | __u8 major = extp->MajorVersion; | |
144 | __u8 minor = extp->MinorVersion; | |
145 | ||
146 | if (((major << 8) | minor) < 0x3131) { | |
147 | /* CFI version 1.0 => don't trust bootloc */ | |
87e92c06 CM |
148 | |
149 | DEBUG(MTD_DEBUG_LEVEL1, | |
150 | "%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n", | |
151 | map->name, cfi->mfr, cfi->id); | |
152 | ||
153 | /* AFAICS all 29LV400 with a bottom boot block have a device ID | |
154 | * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode. | |
155 | * These were badly detected as they have the 0x80 bit set | |
156 | * so treat them as a special case. | |
157 | */ | |
158 | if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) && | |
159 | ||
160 | /* Macronix added CFI to their 2nd generation | |
161 | * MX29LV400C B/T but AFAICS no other 29LV400 (AMD, | |
162 | * Fujitsu, Spansion, EON, ESI and older Macronix) | |
163 | * has CFI. | |
164 | * | |
165 | * Therefore also check the manufacturer. | |
166 | * This reduces the risk of false detection due to | |
167 | * the 8-bit device ID. | |
168 | */ | |
f3e69c65 | 169 | (cfi->mfr == CFI_MFR_MACRONIX)) { |
87e92c06 CM |
170 | DEBUG(MTD_DEBUG_LEVEL1, |
171 | "%s: Macronix MX29LV400C with bottom boot block" | |
172 | " detected\n", map->name); | |
173 | extp->TopBottom = 2; /* bottom boot */ | |
174 | } else | |
1da177e4 LT |
175 | if (cfi->id & 0x80) { |
176 | printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id); | |
177 | extp->TopBottom = 3; /* top boot */ | |
178 | } else { | |
179 | extp->TopBottom = 2; /* bottom boot */ | |
180 | } | |
87e92c06 CM |
181 | |
182 | DEBUG(MTD_DEBUG_LEVEL1, | |
183 | "%s: AMD CFI PRI V%c.%c has no boot block field;" | |
184 | " deduced %s from Device ID\n", map->name, major, minor, | |
185 | extp->TopBottom == 2 ? "bottom" : "top"); | |
1da177e4 LT |
186 | } |
187 | } | |
188 | #endif | |
189 | ||
190 | static void fixup_use_write_buffers(struct mtd_info *mtd, void *param) | |
191 | { | |
192 | struct map_info *map = mtd->priv; | |
193 | struct cfi_private *cfi = map->fldrv_priv; | |
194 | if (cfi->cfiq->BufWriteTimeoutTyp) { | |
195 | DEBUG(MTD_DEBUG_LEVEL1, "Using buffer write method\n" ); | |
196 | mtd->write = cfi_amdstd_write_buffers; | |
197 | } | |
198 | } | |
199 | ||
5b0c5c2c HS |
200 | /* Atmel chips don't use the same PRI format as AMD chips */ |
201 | static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param) | |
202 | { | |
203 | struct map_info *map = mtd->priv; | |
204 | struct cfi_private *cfi = map->fldrv_priv; | |
205 | struct cfi_pri_amdstd *extp = cfi->cmdset_priv; | |
206 | struct cfi_pri_atmel atmel_pri; | |
207 | ||
208 | memcpy(&atmel_pri, extp, sizeof(atmel_pri)); | |
de591dac | 209 | memset((char *)extp + 5, 0, sizeof(*extp) - 5); |
5b0c5c2c HS |
210 | |
211 | if (atmel_pri.Features & 0x02) | |
212 | extp->EraseSuspend = 2; | |
213 | ||
be8f78b8 HS |
214 | /* Some chips got it backwards... */ |
215 | if (cfi->id == AT49BV6416) { | |
216 | if (atmel_pri.BottomBoot) | |
217 | extp->TopBottom = 3; | |
218 | else | |
219 | extp->TopBottom = 2; | |
220 | } else { | |
221 | if (atmel_pri.BottomBoot) | |
222 | extp->TopBottom = 2; | |
223 | else | |
224 | extp->TopBottom = 3; | |
225 | } | |
d10a39d1 HCE |
226 | |
227 | /* burst write mode not supported */ | |
228 | cfi->cfiq->BufWriteTimeoutTyp = 0; | |
229 | cfi->cfiq->BufWriteTimeoutMax = 0; | |
5b0c5c2c HS |
230 | } |
231 | ||
1da177e4 LT |
232 | static void fixup_use_secsi(struct mtd_info *mtd, void *param) |
233 | { | |
234 | /* Setup for chips with a secsi area */ | |
235 | mtd->read_user_prot_reg = cfi_amdstd_secsi_read; | |
236 | mtd->read_fact_prot_reg = cfi_amdstd_secsi_read; | |
237 | } | |
238 | ||
239 | static void fixup_use_erase_chip(struct mtd_info *mtd, void *param) | |
240 | { | |
241 | struct map_info *map = mtd->priv; | |
242 | struct cfi_private *cfi = map->fldrv_priv; | |
243 | if ((cfi->cfiq->NumEraseRegions == 1) && | |
244 | ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) { | |
245 | mtd->erase = cfi_amdstd_erase_chip; | |
246 | } | |
1f948b43 | 247 | |
1da177e4 LT |
248 | } |
249 | ||
0165508c HS |
250 | /* |
251 | * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors | |
252 | * locked by default. | |
253 | */ | |
254 | static void fixup_use_atmel_lock(struct mtd_info *mtd, void *param) | |
255 | { | |
256 | mtd->lock = cfi_atmel_lock; | |
257 | mtd->unlock = cfi_atmel_unlock; | |
e619a75f | 258 | mtd->flags |= MTD_POWERUP_LOCK; |
0165508c HS |
259 | } |
260 | ||
83dcd3bb GL |
261 | static void fixup_old_sst_eraseregion(struct mtd_info *mtd) |
262 | { | |
263 | struct map_info *map = mtd->priv; | |
264 | struct cfi_private *cfi = map->fldrv_priv; | |
265 | ||
266 | /* | |
267 | * These flashes report two seperate eraseblock regions based on the | |
268 | * sector_erase-size and block_erase-size, although they both operate on the | |
269 | * same memory. This is not allowed according to CFI, so we just pick the | |
270 | * sector_erase-size. | |
271 | */ | |
272 | cfi->cfiq->NumEraseRegions = 1; | |
273 | } | |
274 | ||
275 | static void fixup_sst39vf(struct mtd_info *mtd, void *param) | |
276 | { | |
277 | struct map_info *map = mtd->priv; | |
278 | struct cfi_private *cfi = map->fldrv_priv; | |
279 | ||
280 | fixup_old_sst_eraseregion(mtd); | |
281 | ||
282 | cfi->addr_unlock1 = 0x5555; | |
283 | cfi->addr_unlock2 = 0x2AAA; | |
284 | } | |
285 | ||
5a0563f0 GL |
286 | static void fixup_sst39vf_rev_b(struct mtd_info *mtd, void *param) |
287 | { | |
288 | struct map_info *map = mtd->priv; | |
289 | struct cfi_private *cfi = map->fldrv_priv; | |
290 | ||
291 | fixup_old_sst_eraseregion(mtd); | |
292 | ||
293 | cfi->addr_unlock1 = 0x555; | |
294 | cfi->addr_unlock2 = 0x2AA; | |
295 | } | |
296 | ||
70b07255 TP |
297 | static void fixup_s29gl064n_sectors(struct mtd_info *mtd, void *param) |
298 | { | |
299 | struct map_info *map = mtd->priv; | |
300 | struct cfi_private *cfi = map->fldrv_priv; | |
301 | ||
302 | if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) { | |
303 | cfi->cfiq->EraseRegionInfo[0] |= 0x0040; | |
304 | pr_warning("%s: Bad S29GL064N CFI data, adjust from 64 to 128 sectors\n", mtd->name); | |
305 | } | |
306 | } | |
307 | ||
308 | static void fixup_s29gl032n_sectors(struct mtd_info *mtd, void *param) | |
309 | { | |
310 | struct map_info *map = mtd->priv; | |
311 | struct cfi_private *cfi = map->fldrv_priv; | |
312 | ||
313 | if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) { | |
314 | cfi->cfiq->EraseRegionInfo[1] &= ~0x0040; | |
315 | pr_warning("%s: Bad S29GL032N CFI data, adjust from 127 to 63 sectors\n", mtd->name); | |
316 | } | |
317 | } | |
318 | ||
83dcd3bb GL |
319 | /* Used to fix CFI-Tables of chips without Extended Query Tables */ |
320 | static struct cfi_fixup cfi_nopri_fixup_table[] = { | |
321 | { CFI_MFR_SST, 0x234A, fixup_sst39vf, NULL, }, // SST39VF1602 | |
322 | { CFI_MFR_SST, 0x234B, fixup_sst39vf, NULL, }, // SST39VF1601 | |
323 | { CFI_MFR_SST, 0x235A, fixup_sst39vf, NULL, }, // SST39VF3202 | |
324 | { CFI_MFR_SST, 0x235B, fixup_sst39vf, NULL, }, // SST39VF3201 | |
5a0563f0 GL |
325 | { CFI_MFR_SST, 0x235C, fixup_sst39vf_rev_b, NULL, }, // SST39VF3202B |
326 | { CFI_MFR_SST, 0x235D, fixup_sst39vf_rev_b, NULL, }, // SST39VF3201B | |
327 | { CFI_MFR_SST, 0x236C, fixup_sst39vf_rev_b, NULL, }, // SST39VF6402B | |
328 | { CFI_MFR_SST, 0x236D, fixup_sst39vf_rev_b, NULL, }, // SST39VF6401B | |
83dcd3bb GL |
329 | { 0, 0, NULL, NULL } |
330 | }; | |
331 | ||
1da177e4 | 332 | static struct cfi_fixup cfi_fixup_table[] = { |
d10a39d1 | 333 | { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL }, |
1da177e4 LT |
334 | #ifdef AMD_BOOTLOC_BUG |
335 | { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL }, | |
f3e69c65 | 336 | { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock, NULL }, |
1da177e4 LT |
337 | #endif |
338 | { CFI_MFR_AMD, 0x0050, fixup_use_secsi, NULL, }, | |
339 | { CFI_MFR_AMD, 0x0053, fixup_use_secsi, NULL, }, | |
340 | { CFI_MFR_AMD, 0x0055, fixup_use_secsi, NULL, }, | |
341 | { CFI_MFR_AMD, 0x0056, fixup_use_secsi, NULL, }, | |
342 | { CFI_MFR_AMD, 0x005C, fixup_use_secsi, NULL, }, | |
343 | { CFI_MFR_AMD, 0x005F, fixup_use_secsi, NULL, }, | |
70b07255 TP |
344 | { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors, NULL, }, |
345 | { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors, NULL, }, | |
346 | { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors, NULL, }, | |
347 | { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors, NULL, }, | |
1da177e4 LT |
348 | #if !FORCE_WORD_WRITE |
349 | { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, }, | |
350 | #endif | |
351 | { 0, 0, NULL, NULL } | |
352 | }; | |
353 | static struct cfi_fixup jedec_fixup_table[] = { | |
f3e69c65 GL |
354 | { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock, NULL, }, |
355 | { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock, NULL, }, | |
356 | { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock, NULL, }, | |
1da177e4 LT |
357 | { 0, 0, NULL, NULL } |
358 | }; | |
359 | ||
360 | static struct cfi_fixup fixup_table[] = { | |
361 | /* The CFI vendor ids and the JEDEC vendor IDs appear | |
362 | * to be common. It is like the devices id's are as | |
363 | * well. This table is to pick all cases where | |
364 | * we know that is the case. | |
365 | */ | |
366 | { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip, NULL }, | |
0165508c | 367 | { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock, NULL }, |
1da177e4 LT |
368 | { 0, 0, NULL, NULL } |
369 | }; | |
370 | ||
371 | ||
fefae48b WG |
372 | static void cfi_fixup_major_minor(struct cfi_private *cfi, |
373 | struct cfi_pri_amdstd *extp) | |
374 | { | |
375 | if (cfi->mfr == CFI_MFR_SAMSUNG && cfi->id == 0x257e && | |
376 | extp->MajorVersion == '0') | |
377 | extp->MajorVersion = '1'; | |
378 | } | |
379 | ||
1da177e4 LT |
380 | struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary) |
381 | { | |
382 | struct cfi_private *cfi = map->fldrv_priv; | |
383 | struct mtd_info *mtd; | |
384 | int i; | |
385 | ||
95b93a0c | 386 | mtd = kzalloc(sizeof(*mtd), GFP_KERNEL); |
1da177e4 LT |
387 | if (!mtd) { |
388 | printk(KERN_WARNING "Failed to allocate memory for MTD device\n"); | |
389 | return NULL; | |
390 | } | |
1da177e4 LT |
391 | mtd->priv = map; |
392 | mtd->type = MTD_NORFLASH; | |
393 | ||
394 | /* Fill in the default mtd operations */ | |
395 | mtd->erase = cfi_amdstd_erase_varsize; | |
396 | mtd->write = cfi_amdstd_write_words; | |
397 | mtd->read = cfi_amdstd_read; | |
398 | mtd->sync = cfi_amdstd_sync; | |
399 | mtd->suspend = cfi_amdstd_suspend; | |
400 | mtd->resume = cfi_amdstd_resume; | |
401 | mtd->flags = MTD_CAP_NORFLASH; | |
402 | mtd->name = map->name; | |
783ed81f | 403 | mtd->writesize = 1; |
1da177e4 | 404 | |
eafe1311 KC |
405 | mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot; |
406 | ||
1da177e4 LT |
407 | if (cfi->cfi_mode==CFI_MODE_CFI){ |
408 | unsigned char bootloc; | |
1da177e4 LT |
409 | __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR; |
410 | struct cfi_pri_amdstd *extp; | |
411 | ||
412 | extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu"); | |
564b8497 GL |
413 | if (extp) { |
414 | /* | |
415 | * It's a real CFI chip, not one for which the probe | |
416 | * routine faked a CFI structure. | |
417 | */ | |
418 | cfi_fixup_major_minor(cfi, extp); | |
419 | ||
420 | if (extp->MajorVersion != '1' || | |
421 | (extp->MinorVersion < '0' || extp->MinorVersion > '4')) { | |
422 | printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query " | |
423 | "version %c.%c.\n", extp->MajorVersion, | |
424 | extp->MinorVersion); | |
425 | kfree(extp); | |
426 | kfree(mtd); | |
427 | return NULL; | |
428 | } | |
d88f977b | 429 | |
564b8497 GL |
430 | /* Install our own private info structure */ |
431 | cfi->cmdset_priv = extp; | |
1da177e4 | 432 | |
564b8497 GL |
433 | /* Apply cfi device specific fixups */ |
434 | cfi_fixup(mtd, cfi_fixup_table); | |
1da177e4 LT |
435 | |
436 | #ifdef DEBUG_CFI_FEATURES | |
564b8497 GL |
437 | /* Tell the user about it in lots of lovely detail */ |
438 | cfi_tell_features(extp); | |
1f948b43 | 439 | #endif |
1da177e4 | 440 | |
564b8497 | 441 | bootloc = extp->TopBottom; |
412da2f6 DW |
442 | if ((bootloc < 2) || (bootloc > 5)) { |
443 | printk(KERN_WARNING "%s: CFI contains unrecognised boot " | |
444 | "bank location (%d). Assuming bottom.\n", | |
abab7ebf | 445 | map->name, bootloc); |
564b8497 GL |
446 | bootloc = 2; |
447 | } | |
1da177e4 | 448 | |
564b8497 | 449 | if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) { |
412da2f6 | 450 | printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name); |
1f948b43 | 451 | |
564b8497 GL |
452 | for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) { |
453 | int j = (cfi->cfiq->NumEraseRegions-1)-i; | |
454 | __u32 swap; | |
1f948b43 | 455 | |
564b8497 GL |
456 | swap = cfi->cfiq->EraseRegionInfo[i]; |
457 | cfi->cfiq->EraseRegionInfo[i] = cfi->cfiq->EraseRegionInfo[j]; | |
458 | cfi->cfiq->EraseRegionInfo[j] = swap; | |
459 | } | |
1da177e4 | 460 | } |
564b8497 GL |
461 | /* Set the default CFI lock/unlock addresses */ |
462 | cfi->addr_unlock1 = 0x555; | |
463 | cfi->addr_unlock2 = 0x2aa; | |
464 | } | |
83dcd3bb | 465 | cfi_fixup(mtd, cfi_nopri_fixup_table); |
564b8497 GL |
466 | |
467 | if (!cfi->addr_unlock1 || !cfi->addr_unlock2) { | |
468 | kfree(mtd); | |
469 | return NULL; | |
1da177e4 | 470 | } |
1da177e4 LT |
471 | |
472 | } /* CFI mode */ | |
473 | else if (cfi->cfi_mode == CFI_MODE_JEDEC) { | |
474 | /* Apply jedec specific fixups */ | |
475 | cfi_fixup(mtd, jedec_fixup_table); | |
476 | } | |
477 | /* Apply generic fixups */ | |
478 | cfi_fixup(mtd, fixup_table); | |
479 | ||
480 | for (i=0; i< cfi->numchips; i++) { | |
481 | cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp; | |
482 | cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp; | |
483 | cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp; | |
83d48091 VS |
484 | cfi->chips[i].ref_point_counter = 0; |
485 | init_waitqueue_head(&(cfi->chips[i].wq)); | |
1f948b43 TG |
486 | } |
487 | ||
1da177e4 | 488 | map->fldrv = &cfi_amdstd_chipdrv; |
1f948b43 | 489 | |
1da177e4 LT |
490 | return cfi_amdstd_setup(mtd); |
491 | } | |
1e804cec | 492 | struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002"))); |
83ea4ef2 | 493 | EXPORT_SYMBOL_GPL(cfi_cmdset_0002); |
1e804cec | 494 | EXPORT_SYMBOL_GPL(cfi_cmdset_0701); |
1da177e4 LT |
495 | |
496 | static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd) | |
497 | { | |
498 | struct map_info *map = mtd->priv; | |
499 | struct cfi_private *cfi = map->fldrv_priv; | |
500 | unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave; | |
501 | unsigned long offset = 0; | |
502 | int i,j; | |
503 | ||
1f948b43 | 504 | printk(KERN_NOTICE "number of %s chips: %d\n", |
1da177e4 | 505 | (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips); |
1f948b43 | 506 | /* Select the correct geometry setup */ |
1da177e4 LT |
507 | mtd->size = devsize * cfi->numchips; |
508 | ||
509 | mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips; | |
510 | mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info) | |
511 | * mtd->numeraseregions, GFP_KERNEL); | |
1f948b43 | 512 | if (!mtd->eraseregions) { |
1da177e4 LT |
513 | printk(KERN_WARNING "Failed to allocate memory for MTD erase region info\n"); |
514 | goto setup_err; | |
515 | } | |
1f948b43 | 516 | |
1da177e4 LT |
517 | for (i=0; i<cfi->cfiq->NumEraseRegions; i++) { |
518 | unsigned long ernum, ersize; | |
519 | ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave; | |
520 | ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1; | |
1f948b43 | 521 | |
1da177e4 LT |
522 | if (mtd->erasesize < ersize) { |
523 | mtd->erasesize = ersize; | |
524 | } | |
525 | for (j=0; j<cfi->numchips; j++) { | |
526 | mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset; | |
527 | mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize; | |
528 | mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum; | |
529 | } | |
530 | offset += (ersize * ernum); | |
531 | } | |
532 | if (offset != devsize) { | |
533 | /* Argh */ | |
534 | printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize); | |
535 | goto setup_err; | |
536 | } | |
537 | #if 0 | |
538 | // debug | |
539 | for (i=0; i<mtd->numeraseregions;i++){ | |
540 | printk("%d: offset=0x%x,size=0x%x,blocks=%d\n", | |
541 | i,mtd->eraseregions[i].offset, | |
542 | mtd->eraseregions[i].erasesize, | |
543 | mtd->eraseregions[i].numblocks); | |
544 | } | |
545 | #endif | |
546 | ||
1da177e4 | 547 | __module_get(THIS_MODULE); |
eafe1311 | 548 | register_reboot_notifier(&mtd->reboot_notifier); |
1da177e4 LT |
549 | return mtd; |
550 | ||
551 | setup_err: | |
17fabf15 JS |
552 | kfree(mtd->eraseregions); |
553 | kfree(mtd); | |
1da177e4 LT |
554 | kfree(cfi->cmdset_priv); |
555 | kfree(cfi->cfiq); | |
556 | return NULL; | |
557 | } | |
558 | ||
559 | /* | |
560 | * Return true if the chip is ready. | |
561 | * | |
562 | * Ready is one of: read mode, query mode, erase-suspend-read mode (in any | |
563 | * non-suspended sector) and is indicated by no toggle bits toggling. | |
564 | * | |
565 | * Note that anything more complicated than checking if no bits are toggling | |
566 | * (including checking DQ5 for an error status) is tricky to get working | |
567 | * correctly and is therefore not done (particulary with interleaved chips | |
568 | * as each chip must be checked independantly of the others). | |
569 | */ | |
02b15e34 | 570 | static int __xipram chip_ready(struct map_info *map, unsigned long addr) |
1da177e4 LT |
571 | { |
572 | map_word d, t; | |
573 | ||
574 | d = map_read(map, addr); | |
575 | t = map_read(map, addr); | |
576 | ||
577 | return map_word_equal(map, d, t); | |
578 | } | |
579 | ||
fb4a90bf EB |
580 | /* |
581 | * Return true if the chip is ready and has the correct value. | |
582 | * | |
583 | * Ready is one of: read mode, query mode, erase-suspend-read mode (in any | |
584 | * non-suspended sector) and it is indicated by no bits toggling. | |
585 | * | |
586 | * Error are indicated by toggling bits or bits held with the wrong value, | |
587 | * or with bits toggling. | |
588 | * | |
589 | * Note that anything more complicated than checking if no bits are toggling | |
590 | * (including checking DQ5 for an error status) is tricky to get working | |
591 | * correctly and is therefore not done (particulary with interleaved chips | |
592 | * as each chip must be checked independantly of the others). | |
593 | * | |
594 | */ | |
02b15e34 | 595 | static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected) |
fb4a90bf EB |
596 | { |
597 | map_word oldd, curd; | |
598 | ||
599 | oldd = map_read(map, addr); | |
600 | curd = map_read(map, addr); | |
601 | ||
1f948b43 | 602 | return map_word_equal(map, oldd, curd) && |
fb4a90bf EB |
603 | map_word_equal(map, curd, expected); |
604 | } | |
605 | ||
1da177e4 LT |
606 | static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode) |
607 | { | |
608 | DECLARE_WAITQUEUE(wait, current); | |
609 | struct cfi_private *cfi = map->fldrv_priv; | |
610 | unsigned long timeo; | |
611 | struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv; | |
612 | ||
613 | resettime: | |
614 | timeo = jiffies + HZ; | |
615 | retry: | |
616 | switch (chip->state) { | |
617 | ||
618 | case FL_STATUS: | |
619 | for (;;) { | |
620 | if (chip_ready(map, adr)) | |
621 | break; | |
622 | ||
623 | if (time_after(jiffies, timeo)) { | |
624 | printk(KERN_ERR "Waiting for chip to be ready timed out.\n"); | |
1da177e4 LT |
625 | return -EIO; |
626 | } | |
c4e77376 | 627 | mutex_unlock(&chip->mutex); |
1da177e4 | 628 | cfi_udelay(1); |
c4e77376 | 629 | mutex_lock(&chip->mutex); |
1da177e4 LT |
630 | /* Someone else might have been playing with it. */ |
631 | goto retry; | |
632 | } | |
1f948b43 | 633 | |
1da177e4 LT |
634 | case FL_READY: |
635 | case FL_CFI_QUERY: | |
636 | case FL_JEDEC_QUERY: | |
637 | return 0; | |
638 | ||
639 | case FL_ERASING: | |
2695eab9 JT |
640 | if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) || |
641 | !(mode == FL_READY || mode == FL_POINT || | |
642 | (mode == FL_WRITING && (cfip->EraseSuspend & 0x2)))) | |
1da177e4 LT |
643 | goto sleep; |
644 | ||
645 | /* We could check to see if we're trying to access the sector | |
646 | * that is currently being erased. However, no user will try | |
647 | * anything like that so we just wait for the timeout. */ | |
648 | ||
649 | /* Erase suspend */ | |
650 | /* It's harmless to issue the Erase-Suspend and Erase-Resume | |
651 | * commands when the erase algorithm isn't in progress. */ | |
652 | map_write(map, CMD(0xB0), chip->in_progress_block_addr); | |
653 | chip->oldstate = FL_ERASING; | |
654 | chip->state = FL_ERASE_SUSPENDING; | |
655 | chip->erase_suspended = 1; | |
656 | for (;;) { | |
657 | if (chip_ready(map, adr)) | |
658 | break; | |
659 | ||
660 | if (time_after(jiffies, timeo)) { | |
661 | /* Should have suspended the erase by now. | |
662 | * Send an Erase-Resume command as either | |
663 | * there was an error (so leave the erase | |
664 | * routine to recover from it) or we trying to | |
665 | * use the erase-in-progress sector. */ | |
666 | map_write(map, CMD(0x30), chip->in_progress_block_addr); | |
667 | chip->state = FL_ERASING; | |
668 | chip->oldstate = FL_READY; | |
669 | printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__); | |
670 | return -EIO; | |
671 | } | |
1f948b43 | 672 | |
c4e77376 | 673 | mutex_unlock(&chip->mutex); |
1da177e4 | 674 | cfi_udelay(1); |
c4e77376 | 675 | mutex_lock(&chip->mutex); |
1da177e4 LT |
676 | /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING. |
677 | So we can just loop here. */ | |
678 | } | |
679 | chip->state = FL_READY; | |
680 | return 0; | |
681 | ||
02b15e34 TP |
682 | case FL_XIP_WHILE_ERASING: |
683 | if (mode != FL_READY && mode != FL_POINT && | |
684 | (!cfip || !(cfip->EraseSuspend&2))) | |
685 | goto sleep; | |
686 | chip->oldstate = chip->state; | |
687 | chip->state = FL_READY; | |
688 | return 0; | |
689 | ||
eafe1311 KC |
690 | case FL_SHUTDOWN: |
691 | /* The machine is rebooting */ | |
692 | return -EIO; | |
693 | ||
1da177e4 LT |
694 | case FL_POINT: |
695 | /* Only if there's no operation suspended... */ | |
696 | if (mode == FL_READY && chip->oldstate == FL_READY) | |
697 | return 0; | |
698 | ||
699 | default: | |
700 | sleep: | |
701 | set_current_state(TASK_UNINTERRUPTIBLE); | |
702 | add_wait_queue(&chip->wq, &wait); | |
c4e77376 | 703 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
704 | schedule(); |
705 | remove_wait_queue(&chip->wq, &wait); | |
c4e77376 | 706 | mutex_lock(&chip->mutex); |
1da177e4 LT |
707 | goto resettime; |
708 | } | |
709 | } | |
710 | ||
711 | ||
712 | static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr) | |
713 | { | |
714 | struct cfi_private *cfi = map->fldrv_priv; | |
715 | ||
716 | switch(chip->oldstate) { | |
717 | case FL_ERASING: | |
718 | chip->state = chip->oldstate; | |
719 | map_write(map, CMD(0x30), chip->in_progress_block_addr); | |
720 | chip->oldstate = FL_READY; | |
721 | chip->state = FL_ERASING; | |
722 | break; | |
723 | ||
02b15e34 TP |
724 | case FL_XIP_WHILE_ERASING: |
725 | chip->state = chip->oldstate; | |
726 | chip->oldstate = FL_READY; | |
727 | break; | |
728 | ||
1da177e4 LT |
729 | case FL_READY: |
730 | case FL_STATUS: | |
731 | /* We should really make set_vpp() count, rather than doing this */ | |
732 | DISABLE_VPP(map); | |
733 | break; | |
734 | default: | |
735 | printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate); | |
736 | } | |
737 | wake_up(&chip->wq); | |
738 | } | |
739 | ||
02b15e34 TP |
740 | #ifdef CONFIG_MTD_XIP |
741 | ||
742 | /* | |
743 | * No interrupt what so ever can be serviced while the flash isn't in array | |
744 | * mode. This is ensured by the xip_disable() and xip_enable() functions | |
745 | * enclosing any code path where the flash is known not to be in array mode. | |
746 | * And within a XIP disabled code path, only functions marked with __xipram | |
747 | * may be called and nothing else (it's a good thing to inspect generated | |
748 | * assembly to make sure inline functions were actually inlined and that gcc | |
749 | * didn't emit calls to its own support functions). Also configuring MTD CFI | |
750 | * support to a single buswidth and a single interleave is also recommended. | |
751 | */ | |
f8eb321b | 752 | |
02b15e34 TP |
753 | static void xip_disable(struct map_info *map, struct flchip *chip, |
754 | unsigned long adr) | |
755 | { | |
756 | /* TODO: chips with no XIP use should ignore and return */ | |
757 | (void) map_read(map, adr); /* ensure mmu mapping is up to date */ | |
758 | local_irq_disable(); | |
759 | } | |
760 | ||
761 | static void __xipram xip_enable(struct map_info *map, struct flchip *chip, | |
762 | unsigned long adr) | |
763 | { | |
764 | struct cfi_private *cfi = map->fldrv_priv; | |
765 | ||
766 | if (chip->state != FL_POINT && chip->state != FL_READY) { | |
767 | map_write(map, CMD(0xf0), adr); | |
768 | chip->state = FL_READY; | |
769 | } | |
770 | (void) map_read(map, adr); | |
97f927a4 | 771 | xip_iprefetch(); |
02b15e34 TP |
772 | local_irq_enable(); |
773 | } | |
774 | ||
775 | /* | |
776 | * When a delay is required for the flash operation to complete, the | |
777 | * xip_udelay() function is polling for both the given timeout and pending | |
778 | * (but still masked) hardware interrupts. Whenever there is an interrupt | |
1f948b43 | 779 | * pending then the flash erase operation is suspended, array mode restored |
02b15e34 TP |
780 | * and interrupts unmasked. Task scheduling might also happen at that |
781 | * point. The CPU eventually returns from the interrupt or the call to | |
782 | * schedule() and the suspended flash operation is resumed for the remaining | |
783 | * of the delay period. | |
784 | * | |
785 | * Warning: this function _will_ fool interrupt latency tracing tools. | |
786 | */ | |
787 | ||
788 | static void __xipram xip_udelay(struct map_info *map, struct flchip *chip, | |
789 | unsigned long adr, int usec) | |
790 | { | |
791 | struct cfi_private *cfi = map->fldrv_priv; | |
792 | struct cfi_pri_amdstd *extp = cfi->cmdset_priv; | |
793 | map_word status, OK = CMD(0x80); | |
794 | unsigned long suspended, start = xip_currtime(); | |
795 | flstate_t oldstate; | |
796 | ||
797 | do { | |
798 | cpu_relax(); | |
799 | if (xip_irqpending() && extp && | |
800 | ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) && | |
801 | (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) { | |
802 | /* | |
1f948b43 TG |
803 | * Let's suspend the erase operation when supported. |
804 | * Note that we currently don't try to suspend | |
805 | * interleaved chips if there is already another | |
02b15e34 TP |
806 | * operation suspended (imagine what happens |
807 | * when one chip was already done with the current | |
808 | * operation while another chip suspended it, then | |
809 | * we resume the whole thing at once). Yes, it | |
810 | * can happen! | |
811 | */ | |
812 | map_write(map, CMD(0xb0), adr); | |
813 | usec -= xip_elapsed_since(start); | |
814 | suspended = xip_currtime(); | |
815 | do { | |
816 | if (xip_elapsed_since(suspended) > 100000) { | |
817 | /* | |
818 | * The chip doesn't want to suspend | |
819 | * after waiting for 100 msecs. | |
820 | * This is a critical error but there | |
821 | * is not much we can do here. | |
822 | */ | |
823 | return; | |
824 | } | |
825 | status = map_read(map, adr); | |
826 | } while (!map_word_andequal(map, status, OK, OK)); | |
827 | ||
828 | /* Suspend succeeded */ | |
829 | oldstate = chip->state; | |
830 | if (!map_word_bitsset(map, status, CMD(0x40))) | |
831 | break; | |
832 | chip->state = FL_XIP_WHILE_ERASING; | |
833 | chip->erase_suspended = 1; | |
834 | map_write(map, CMD(0xf0), adr); | |
835 | (void) map_read(map, adr); | |
ca5c23c3 | 836 | xip_iprefetch(); |
02b15e34 | 837 | local_irq_enable(); |
c4e77376 | 838 | mutex_unlock(&chip->mutex); |
ca5c23c3 | 839 | xip_iprefetch(); |
02b15e34 TP |
840 | cond_resched(); |
841 | ||
842 | /* | |
843 | * We're back. However someone else might have | |
844 | * decided to go write to the chip if we are in | |
845 | * a suspended erase state. If so let's wait | |
846 | * until it's done. | |
847 | */ | |
c4e77376 | 848 | mutex_lock(&chip->mutex); |
02b15e34 TP |
849 | while (chip->state != FL_XIP_WHILE_ERASING) { |
850 | DECLARE_WAITQUEUE(wait, current); | |
851 | set_current_state(TASK_UNINTERRUPTIBLE); | |
852 | add_wait_queue(&chip->wq, &wait); | |
c4e77376 | 853 | mutex_unlock(&chip->mutex); |
02b15e34 TP |
854 | schedule(); |
855 | remove_wait_queue(&chip->wq, &wait); | |
c4e77376 | 856 | mutex_lock(&chip->mutex); |
02b15e34 TP |
857 | } |
858 | /* Disallow XIP again */ | |
859 | local_irq_disable(); | |
860 | ||
861 | /* Resume the write or erase operation */ | |
862 | map_write(map, CMD(0x30), adr); | |
863 | chip->state = oldstate; | |
864 | start = xip_currtime(); | |
865 | } else if (usec >= 1000000/HZ) { | |
866 | /* | |
867 | * Try to save on CPU power when waiting delay | |
868 | * is at least a system timer tick period. | |
869 | * No need to be extremely accurate here. | |
870 | */ | |
871 | xip_cpu_idle(); | |
872 | } | |
873 | status = map_read(map, adr); | |
874 | } while (!map_word_andequal(map, status, OK, OK) | |
875 | && xip_elapsed_since(start) < usec); | |
876 | } | |
877 | ||
878 | #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec) | |
879 | ||
880 | /* | |
881 | * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while | |
882 | * the flash is actively programming or erasing since we have to poll for | |
883 | * the operation to complete anyway. We can't do that in a generic way with | |
884 | * a XIP setup so do it before the actual flash operation in this case | |
885 | * and stub it out from INVALIDATE_CACHE_UDELAY. | |
886 | */ | |
887 | #define XIP_INVAL_CACHED_RANGE(map, from, size) \ | |
888 | INVALIDATE_CACHED_RANGE(map, from, size) | |
889 | ||
890 | #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \ | |
891 | UDELAY(map, chip, adr, usec) | |
892 | ||
893 | /* | |
894 | * Extra notes: | |
895 | * | |
896 | * Activating this XIP support changes the way the code works a bit. For | |
897 | * example the code to suspend the current process when concurrent access | |
898 | * happens is never executed because xip_udelay() will always return with the | |
899 | * same chip state as it was entered with. This is why there is no care for | |
900 | * the presence of add_wait_queue() or schedule() calls from within a couple | |
901 | * xip_disable()'d areas of code, like in do_erase_oneblock for example. | |
902 | * The queueing and scheduling are always happening within xip_udelay(). | |
903 | * | |
904 | * Similarly, get_chip() and put_chip() just happen to always be executed | |
905 | * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state | |
906 | * is in array mode, therefore never executing many cases therein and not | |
907 | * causing any problem with XIP. | |
908 | */ | |
909 | ||
910 | #else | |
911 | ||
912 | #define xip_disable(map, chip, adr) | |
913 | #define xip_enable(map, chip, adr) | |
914 | #define XIP_INVAL_CACHED_RANGE(x...) | |
915 | ||
916 | #define UDELAY(map, chip, adr, usec) \ | |
917 | do { \ | |
c4e77376 | 918 | mutex_unlock(&chip->mutex); \ |
02b15e34 | 919 | cfi_udelay(usec); \ |
c4e77376 | 920 | mutex_lock(&chip->mutex); \ |
02b15e34 TP |
921 | } while (0) |
922 | ||
923 | #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \ | |
924 | do { \ | |
c4e77376 | 925 | mutex_unlock(&chip->mutex); \ |
02b15e34 TP |
926 | INVALIDATE_CACHED_RANGE(map, adr, len); \ |
927 | cfi_udelay(usec); \ | |
c4e77376 | 928 | mutex_lock(&chip->mutex); \ |
02b15e34 TP |
929 | } while (0) |
930 | ||
931 | #endif | |
1da177e4 LT |
932 | |
933 | static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf) | |
934 | { | |
935 | unsigned long cmd_addr; | |
936 | struct cfi_private *cfi = map->fldrv_priv; | |
937 | int ret; | |
938 | ||
939 | adr += chip->start; | |
940 | ||
1f948b43 TG |
941 | /* Ensure cmd read/writes are aligned. */ |
942 | cmd_addr = adr & ~(map_bankwidth(map)-1); | |
1da177e4 | 943 | |
c4e77376 | 944 | mutex_lock(&chip->mutex); |
1da177e4 LT |
945 | ret = get_chip(map, chip, cmd_addr, FL_READY); |
946 | if (ret) { | |
c4e77376 | 947 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
948 | return ret; |
949 | } | |
950 | ||
951 | if (chip->state != FL_POINT && chip->state != FL_READY) { | |
952 | map_write(map, CMD(0xf0), cmd_addr); | |
953 | chip->state = FL_READY; | |
954 | } | |
955 | ||
956 | map_copy_from(map, buf, adr, len); | |
957 | ||
958 | put_chip(map, chip, cmd_addr); | |
959 | ||
c4e77376 | 960 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
961 | return 0; |
962 | } | |
963 | ||
964 | ||
965 | static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) | |
966 | { | |
967 | struct map_info *map = mtd->priv; | |
968 | struct cfi_private *cfi = map->fldrv_priv; | |
969 | unsigned long ofs; | |
970 | int chipnum; | |
971 | int ret = 0; | |
972 | ||
973 | /* ofs: offset within the first chip that the first read should start */ | |
974 | ||
975 | chipnum = (from >> cfi->chipshift); | |
976 | ofs = from - (chipnum << cfi->chipshift); | |
977 | ||
978 | ||
979 | *retlen = 0; | |
980 | ||
981 | while (len) { | |
982 | unsigned long thislen; | |
983 | ||
984 | if (chipnum >= cfi->numchips) | |
985 | break; | |
986 | ||
987 | if ((len + ofs -1) >> cfi->chipshift) | |
988 | thislen = (1<<cfi->chipshift) - ofs; | |
989 | else | |
990 | thislen = len; | |
991 | ||
992 | ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf); | |
993 | if (ret) | |
994 | break; | |
995 | ||
996 | *retlen += thislen; | |
997 | len -= thislen; | |
998 | buf += thislen; | |
999 | ||
1000 | ofs = 0; | |
1001 | chipnum++; | |
1002 | } | |
1003 | return ret; | |
1004 | } | |
1005 | ||
1006 | ||
1007 | static inline int do_read_secsi_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf) | |
1008 | { | |
1009 | DECLARE_WAITQUEUE(wait, current); | |
1010 | unsigned long timeo = jiffies + HZ; | |
1011 | struct cfi_private *cfi = map->fldrv_priv; | |
1012 | ||
1013 | retry: | |
c4e77376 | 1014 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1015 | |
1016 | if (chip->state != FL_READY){ | |
1017 | #if 0 | |
1018 | printk(KERN_DEBUG "Waiting for chip to read, status = %d\n", chip->state); | |
1019 | #endif | |
1020 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1021 | add_wait_queue(&chip->wq, &wait); | |
1f948b43 | 1022 | |
c4e77376 | 1023 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1024 | |
1025 | schedule(); | |
1026 | remove_wait_queue(&chip->wq, &wait); | |
1027 | #if 0 | |
1028 | if(signal_pending(current)) | |
1029 | return -EINTR; | |
1030 | #endif | |
1031 | timeo = jiffies + HZ; | |
1032 | ||
1033 | goto retry; | |
1f948b43 | 1034 | } |
1da177e4 LT |
1035 | |
1036 | adr += chip->start; | |
1037 | ||
1038 | chip->state = FL_READY; | |
1039 | ||
1040 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1041 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1042 | cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1f948b43 | 1043 | |
1da177e4 LT |
1044 | map_copy_from(map, buf, adr, len); |
1045 | ||
1046 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1047 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1048 | cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1049 | cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1f948b43 | 1050 | |
1da177e4 | 1051 | wake_up(&chip->wq); |
c4e77376 | 1052 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1053 | |
1054 | return 0; | |
1055 | } | |
1056 | ||
1057 | static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) | |
1058 | { | |
1059 | struct map_info *map = mtd->priv; | |
1060 | struct cfi_private *cfi = map->fldrv_priv; | |
1061 | unsigned long ofs; | |
1062 | int chipnum; | |
1063 | int ret = 0; | |
1064 | ||
1065 | ||
1066 | /* ofs: offset within the first chip that the first read should start */ | |
1067 | ||
1068 | /* 8 secsi bytes per chip */ | |
1069 | chipnum=from>>3; | |
1070 | ofs=from & 7; | |
1071 | ||
1072 | ||
1073 | *retlen = 0; | |
1074 | ||
1075 | while (len) { | |
1076 | unsigned long thislen; | |
1077 | ||
1078 | if (chipnum >= cfi->numchips) | |
1079 | break; | |
1080 | ||
1081 | if ((len + ofs -1) >> 3) | |
1082 | thislen = (1<<3) - ofs; | |
1083 | else | |
1084 | thislen = len; | |
1085 | ||
1086 | ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf); | |
1087 | if (ret) | |
1088 | break; | |
1089 | ||
1090 | *retlen += thislen; | |
1091 | len -= thislen; | |
1092 | buf += thislen; | |
1093 | ||
1094 | ofs = 0; | |
1095 | chipnum++; | |
1096 | } | |
1097 | return ret; | |
1098 | } | |
1099 | ||
1100 | ||
02b15e34 | 1101 | static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, unsigned long adr, map_word datum) |
1da177e4 LT |
1102 | { |
1103 | struct cfi_private *cfi = map->fldrv_priv; | |
1104 | unsigned long timeo = jiffies + HZ; | |
1105 | /* | |
1106 | * We use a 1ms + 1 jiffies generic timeout for writes (most devices | |
1107 | * have a max write time of a few hundreds usec). However, we should | |
1108 | * use the maximum timeout value given by the chip at probe time | |
1109 | * instead. Unfortunately, struct flchip does have a field for | |
1110 | * maximum timeout, only for typical which can be far too short | |
1111 | * depending of the conditions. The ' + 1' is to avoid having a | |
1112 | * timeout of 0 jiffies if HZ is smaller than 1000. | |
1113 | */ | |
1114 | unsigned long uWriteTimeout = ( HZ / 1000 ) + 1; | |
1115 | int ret = 0; | |
1116 | map_word oldd; | |
1117 | int retry_cnt = 0; | |
1118 | ||
1119 | adr += chip->start; | |
1120 | ||
c4e77376 | 1121 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1122 | ret = get_chip(map, chip, adr, FL_WRITING); |
1123 | if (ret) { | |
c4e77376 | 1124 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1125 | return ret; |
1126 | } | |
1127 | ||
1128 | DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n", | |
1129 | __func__, adr, datum.x[0] ); | |
1130 | ||
1131 | /* | |
1132 | * Check for a NOP for the case when the datum to write is already | |
1133 | * present - it saves time and works around buggy chips that corrupt | |
1134 | * data at other locations when 0xff is written to a location that | |
1135 | * already contains 0xff. | |
1136 | */ | |
1137 | oldd = map_read(map, adr); | |
1138 | if (map_word_equal(map, oldd, datum)) { | |
1139 | DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): NOP\n", | |
1140 | __func__); | |
1141 | goto op_done; | |
1142 | } | |
1143 | ||
02b15e34 | 1144 | XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map)); |
1da177e4 | 1145 | ENABLE_VPP(map); |
02b15e34 | 1146 | xip_disable(map, chip, adr); |
1da177e4 LT |
1147 | retry: |
1148 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1149 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1150 | cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1151 | map_write(map, datum, adr); | |
1152 | chip->state = FL_WRITING; | |
1153 | ||
02b15e34 TP |
1154 | INVALIDATE_CACHE_UDELAY(map, chip, |
1155 | adr, map_bankwidth(map), | |
1156 | chip->word_write_time); | |
1da177e4 LT |
1157 | |
1158 | /* See comment above for timeout value. */ | |
1f948b43 | 1159 | timeo = jiffies + uWriteTimeout; |
1da177e4 LT |
1160 | for (;;) { |
1161 | if (chip->state != FL_WRITING) { | |
1162 | /* Someone's suspended the write. Sleep */ | |
1163 | DECLARE_WAITQUEUE(wait, current); | |
1164 | ||
1165 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1166 | add_wait_queue(&chip->wq, &wait); | |
c4e77376 | 1167 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1168 | schedule(); |
1169 | remove_wait_queue(&chip->wq, &wait); | |
1170 | timeo = jiffies + (HZ / 2); /* FIXME */ | |
c4e77376 | 1171 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1172 | continue; |
1173 | } | |
1174 | ||
b95f9609 | 1175 | if (time_after(jiffies, timeo) && !chip_ready(map, adr)){ |
02b15e34 | 1176 | xip_enable(map, chip, adr); |
fb4a90bf | 1177 | printk(KERN_WARNING "MTD %s(): software timeout\n", __func__); |
02b15e34 | 1178 | xip_disable(map, chip, adr); |
b95f9609 | 1179 | break; |
fb4a90bf | 1180 | } |
1da177e4 | 1181 | |
b95f9609 KB |
1182 | if (chip_ready(map, adr)) |
1183 | break; | |
1184 | ||
1da177e4 | 1185 | /* Latency issues. Drop the lock, wait a while and retry */ |
02b15e34 | 1186 | UDELAY(map, chip, adr, 1); |
1da177e4 | 1187 | } |
fb4a90bf EB |
1188 | /* Did we succeed? */ |
1189 | if (!chip_good(map, adr, datum)) { | |
1190 | /* reset on all failures. */ | |
1191 | map_write( map, CMD(0xF0), chip->start ); | |
1192 | /* FIXME - should have reset delay before continuing */ | |
1da177e4 | 1193 | |
1f948b43 | 1194 | if (++retry_cnt <= MAX_WORD_RETRIES) |
fb4a90bf | 1195 | goto retry; |
1da177e4 | 1196 | |
fb4a90bf EB |
1197 | ret = -EIO; |
1198 | } | |
02b15e34 | 1199 | xip_enable(map, chip, adr); |
1da177e4 LT |
1200 | op_done: |
1201 | chip->state = FL_READY; | |
1202 | put_chip(map, chip, adr); | |
c4e77376 | 1203 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1204 | |
1205 | return ret; | |
1206 | } | |
1207 | ||
1208 | ||
1209 | static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len, | |
1210 | size_t *retlen, const u_char *buf) | |
1211 | { | |
1212 | struct map_info *map = mtd->priv; | |
1213 | struct cfi_private *cfi = map->fldrv_priv; | |
1214 | int ret = 0; | |
1215 | int chipnum; | |
1216 | unsigned long ofs, chipstart; | |
1217 | DECLARE_WAITQUEUE(wait, current); | |
1218 | ||
1219 | *retlen = 0; | |
1220 | if (!len) | |
1221 | return 0; | |
1222 | ||
1223 | chipnum = to >> cfi->chipshift; | |
1224 | ofs = to - (chipnum << cfi->chipshift); | |
1225 | chipstart = cfi->chips[chipnum].start; | |
1226 | ||
1227 | /* If it's not bus-aligned, do the first byte write */ | |
1228 | if (ofs & (map_bankwidth(map)-1)) { | |
1229 | unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1); | |
1230 | int i = ofs - bus_ofs; | |
1231 | int n = 0; | |
1232 | map_word tmp_buf; | |
1233 | ||
1234 | retry: | |
c4e77376 | 1235 | mutex_lock(&cfi->chips[chipnum].mutex); |
1da177e4 LT |
1236 | |
1237 | if (cfi->chips[chipnum].state != FL_READY) { | |
1238 | #if 0 | |
1239 | printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state); | |
1240 | #endif | |
1241 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1242 | add_wait_queue(&cfi->chips[chipnum].wq, &wait); | |
1243 | ||
c4e77376 | 1244 | mutex_unlock(&cfi->chips[chipnum].mutex); |
1da177e4 LT |
1245 | |
1246 | schedule(); | |
1247 | remove_wait_queue(&cfi->chips[chipnum].wq, &wait); | |
1248 | #if 0 | |
1249 | if(signal_pending(current)) | |
1250 | return -EINTR; | |
1251 | #endif | |
1252 | goto retry; | |
1253 | } | |
1254 | ||
1255 | /* Load 'tmp_buf' with old contents of flash */ | |
1256 | tmp_buf = map_read(map, bus_ofs+chipstart); | |
1257 | ||
c4e77376 | 1258 | mutex_unlock(&cfi->chips[chipnum].mutex); |
1da177e4 LT |
1259 | |
1260 | /* Number of bytes to copy from buffer */ | |
1261 | n = min_t(int, len, map_bankwidth(map)-i); | |
1f948b43 | 1262 | |
1da177e4 LT |
1263 | tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n); |
1264 | ||
1f948b43 | 1265 | ret = do_write_oneword(map, &cfi->chips[chipnum], |
1da177e4 | 1266 | bus_ofs, tmp_buf); |
1f948b43 | 1267 | if (ret) |
1da177e4 | 1268 | return ret; |
1f948b43 | 1269 | |
1da177e4 LT |
1270 | ofs += n; |
1271 | buf += n; | |
1272 | (*retlen) += n; | |
1273 | len -= n; | |
1274 | ||
1275 | if (ofs >> cfi->chipshift) { | |
1f948b43 | 1276 | chipnum ++; |
1da177e4 LT |
1277 | ofs = 0; |
1278 | if (chipnum == cfi->numchips) | |
1279 | return 0; | |
1280 | } | |
1281 | } | |
1f948b43 | 1282 | |
1da177e4 LT |
1283 | /* We are now aligned, write as much as possible */ |
1284 | while(len >= map_bankwidth(map)) { | |
1285 | map_word datum; | |
1286 | ||
1287 | datum = map_word_load(map, buf); | |
1288 | ||
1289 | ret = do_write_oneword(map, &cfi->chips[chipnum], | |
1290 | ofs, datum); | |
1291 | if (ret) | |
1292 | return ret; | |
1293 | ||
1294 | ofs += map_bankwidth(map); | |
1295 | buf += map_bankwidth(map); | |
1296 | (*retlen) += map_bankwidth(map); | |
1297 | len -= map_bankwidth(map); | |
1298 | ||
1299 | if (ofs >> cfi->chipshift) { | |
1f948b43 | 1300 | chipnum ++; |
1da177e4 LT |
1301 | ofs = 0; |
1302 | if (chipnum == cfi->numchips) | |
1303 | return 0; | |
1304 | chipstart = cfi->chips[chipnum].start; | |
1305 | } | |
1306 | } | |
1307 | ||
1308 | /* Write the trailing bytes if any */ | |
1309 | if (len & (map_bankwidth(map)-1)) { | |
1310 | map_word tmp_buf; | |
1311 | ||
1312 | retry1: | |
c4e77376 | 1313 | mutex_lock(&cfi->chips[chipnum].mutex); |
1da177e4 LT |
1314 | |
1315 | if (cfi->chips[chipnum].state != FL_READY) { | |
1316 | #if 0 | |
1317 | printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state); | |
1318 | #endif | |
1319 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1320 | add_wait_queue(&cfi->chips[chipnum].wq, &wait); | |
1321 | ||
c4e77376 | 1322 | mutex_unlock(&cfi->chips[chipnum].mutex); |
1da177e4 LT |
1323 | |
1324 | schedule(); | |
1325 | remove_wait_queue(&cfi->chips[chipnum].wq, &wait); | |
1326 | #if 0 | |
1327 | if(signal_pending(current)) | |
1328 | return -EINTR; | |
1329 | #endif | |
1330 | goto retry1; | |
1331 | } | |
1332 | ||
1333 | tmp_buf = map_read(map, ofs + chipstart); | |
1334 | ||
c4e77376 | 1335 | mutex_unlock(&cfi->chips[chipnum].mutex); |
1da177e4 LT |
1336 | |
1337 | tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len); | |
1f948b43 TG |
1338 | |
1339 | ret = do_write_oneword(map, &cfi->chips[chipnum], | |
1da177e4 | 1340 | ofs, tmp_buf); |
1f948b43 | 1341 | if (ret) |
1da177e4 | 1342 | return ret; |
1f948b43 | 1343 | |
1da177e4 LT |
1344 | (*retlen) += len; |
1345 | } | |
1346 | ||
1347 | return 0; | |
1348 | } | |
1349 | ||
1350 | ||
1351 | /* | |
1352 | * FIXME: interleaved mode not tested, and probably not supported! | |
1353 | */ | |
02b15e34 | 1354 | static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip, |
1f948b43 | 1355 | unsigned long adr, const u_char *buf, |
02b15e34 | 1356 | int len) |
1da177e4 LT |
1357 | { |
1358 | struct cfi_private *cfi = map->fldrv_priv; | |
1359 | unsigned long timeo = jiffies + HZ; | |
1360 | /* see comments in do_write_oneword() regarding uWriteTimeo. */ | |
1361 | unsigned long uWriteTimeout = ( HZ / 1000 ) + 1; | |
1362 | int ret = -EIO; | |
1363 | unsigned long cmd_adr; | |
1364 | int z, words; | |
1365 | map_word datum; | |
1366 | ||
1367 | adr += chip->start; | |
1368 | cmd_adr = adr; | |
1369 | ||
c4e77376 | 1370 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1371 | ret = get_chip(map, chip, adr, FL_WRITING); |
1372 | if (ret) { | |
c4e77376 | 1373 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1374 | return ret; |
1375 | } | |
1376 | ||
1377 | datum = map_word_load(map, buf); | |
1378 | ||
1379 | DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n", | |
1380 | __func__, adr, datum.x[0] ); | |
1381 | ||
02b15e34 | 1382 | XIP_INVAL_CACHED_RANGE(map, adr, len); |
1da177e4 | 1383 | ENABLE_VPP(map); |
02b15e34 | 1384 | xip_disable(map, chip, cmd_adr); |
1f948b43 | 1385 | |
1da177e4 LT |
1386 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); |
1387 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1388 | //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1389 | ||
1390 | /* Write Buffer Load */ | |
1391 | map_write(map, CMD(0x25), cmd_adr); | |
1392 | ||
1393 | chip->state = FL_WRITING_TO_BUFFER; | |
1394 | ||
1395 | /* Write length of data to come */ | |
1396 | words = len / map_bankwidth(map); | |
1397 | map_write(map, CMD(words - 1), cmd_adr); | |
1398 | /* Write data */ | |
1399 | z = 0; | |
1400 | while(z < words * map_bankwidth(map)) { | |
1401 | datum = map_word_load(map, buf); | |
1402 | map_write(map, datum, adr + z); | |
1403 | ||
1404 | z += map_bankwidth(map); | |
1405 | buf += map_bankwidth(map); | |
1406 | } | |
1407 | z -= map_bankwidth(map); | |
1408 | ||
1409 | adr += z; | |
1410 | ||
1411 | /* Write Buffer Program Confirm: GO GO GO */ | |
1412 | map_write(map, CMD(0x29), cmd_adr); | |
1413 | chip->state = FL_WRITING; | |
1414 | ||
02b15e34 TP |
1415 | INVALIDATE_CACHE_UDELAY(map, chip, |
1416 | adr, map_bankwidth(map), | |
1417 | chip->word_write_time); | |
1da177e4 | 1418 | |
1f948b43 TG |
1419 | timeo = jiffies + uWriteTimeout; |
1420 | ||
1da177e4 LT |
1421 | for (;;) { |
1422 | if (chip->state != FL_WRITING) { | |
1423 | /* Someone's suspended the write. Sleep */ | |
1424 | DECLARE_WAITQUEUE(wait, current); | |
1425 | ||
1426 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1427 | add_wait_queue(&chip->wq, &wait); | |
c4e77376 | 1428 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1429 | schedule(); |
1430 | remove_wait_queue(&chip->wq, &wait); | |
1431 | timeo = jiffies + (HZ / 2); /* FIXME */ | |
c4e77376 | 1432 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1433 | continue; |
1434 | } | |
1435 | ||
b95f9609 KB |
1436 | if (time_after(jiffies, timeo) && !chip_ready(map, adr)) |
1437 | break; | |
1438 | ||
02b15e34 TP |
1439 | if (chip_ready(map, adr)) { |
1440 | xip_enable(map, chip, adr); | |
1da177e4 | 1441 | goto op_done; |
02b15e34 | 1442 | } |
1da177e4 LT |
1443 | |
1444 | /* Latency issues. Drop the lock, wait a while and retry */ | |
02b15e34 | 1445 | UDELAY(map, chip, adr, 1); |
1da177e4 LT |
1446 | } |
1447 | ||
1da177e4 LT |
1448 | /* reset on all failures. */ |
1449 | map_write( map, CMD(0xF0), chip->start ); | |
02b15e34 | 1450 | xip_enable(map, chip, adr); |
1da177e4 LT |
1451 | /* FIXME - should have reset delay before continuing */ |
1452 | ||
02b15e34 TP |
1453 | printk(KERN_WARNING "MTD %s(): software timeout\n", |
1454 | __func__ ); | |
1455 | ||
1da177e4 LT |
1456 | ret = -EIO; |
1457 | op_done: | |
1458 | chip->state = FL_READY; | |
1459 | put_chip(map, chip, adr); | |
c4e77376 | 1460 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1461 | |
1462 | return ret; | |
1463 | } | |
1464 | ||
1465 | ||
1466 | static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len, | |
1467 | size_t *retlen, const u_char *buf) | |
1468 | { | |
1469 | struct map_info *map = mtd->priv; | |
1470 | struct cfi_private *cfi = map->fldrv_priv; | |
1471 | int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize; | |
1472 | int ret = 0; | |
1473 | int chipnum; | |
1474 | unsigned long ofs; | |
1475 | ||
1476 | *retlen = 0; | |
1477 | if (!len) | |
1478 | return 0; | |
1479 | ||
1480 | chipnum = to >> cfi->chipshift; | |
1481 | ofs = to - (chipnum << cfi->chipshift); | |
1482 | ||
1483 | /* If it's not bus-aligned, do the first word write */ | |
1484 | if (ofs & (map_bankwidth(map)-1)) { | |
1485 | size_t local_len = (-ofs)&(map_bankwidth(map)-1); | |
1486 | if (local_len > len) | |
1487 | local_len = len; | |
1488 | ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift), | |
1489 | local_len, retlen, buf); | |
1490 | if (ret) | |
1491 | return ret; | |
1492 | ofs += local_len; | |
1493 | buf += local_len; | |
1494 | len -= local_len; | |
1495 | ||
1496 | if (ofs >> cfi->chipshift) { | |
1497 | chipnum ++; | |
1498 | ofs = 0; | |
1499 | if (chipnum == cfi->numchips) | |
1500 | return 0; | |
1501 | } | |
1502 | } | |
1503 | ||
1504 | /* Write buffer is worth it only if more than one word to write... */ | |
1505 | while (len >= map_bankwidth(map) * 2) { | |
1506 | /* We must not cross write block boundaries */ | |
1507 | int size = wbufsize - (ofs & (wbufsize-1)); | |
1508 | ||
1509 | if (size > len) | |
1510 | size = len; | |
1511 | if (size % map_bankwidth(map)) | |
1512 | size -= size % map_bankwidth(map); | |
1513 | ||
1f948b43 | 1514 | ret = do_write_buffer(map, &cfi->chips[chipnum], |
1da177e4 LT |
1515 | ofs, buf, size); |
1516 | if (ret) | |
1517 | return ret; | |
1518 | ||
1519 | ofs += size; | |
1520 | buf += size; | |
1521 | (*retlen) += size; | |
1522 | len -= size; | |
1523 | ||
1524 | if (ofs >> cfi->chipshift) { | |
1f948b43 | 1525 | chipnum ++; |
1da177e4 LT |
1526 | ofs = 0; |
1527 | if (chipnum == cfi->numchips) | |
1528 | return 0; | |
1529 | } | |
1530 | } | |
1531 | ||
1532 | if (len) { | |
1533 | size_t retlen_dregs = 0; | |
1534 | ||
1535 | ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift), | |
1536 | len, &retlen_dregs, buf); | |
1537 | ||
1538 | *retlen += retlen_dregs; | |
1539 | return ret; | |
1540 | } | |
1541 | ||
1542 | return 0; | |
1543 | } | |
1544 | ||
1545 | ||
1546 | /* | |
1547 | * Handle devices with one erase region, that only implement | |
1548 | * the chip erase command. | |
1549 | */ | |
02b15e34 | 1550 | static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip) |
1da177e4 LT |
1551 | { |
1552 | struct cfi_private *cfi = map->fldrv_priv; | |
1553 | unsigned long timeo = jiffies + HZ; | |
1554 | unsigned long int adr; | |
1555 | DECLARE_WAITQUEUE(wait, current); | |
1556 | int ret = 0; | |
1557 | ||
1558 | adr = cfi->addr_unlock1; | |
1559 | ||
c4e77376 | 1560 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1561 | ret = get_chip(map, chip, adr, FL_WRITING); |
1562 | if (ret) { | |
c4e77376 | 1563 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1564 | return ret; |
1565 | } | |
1566 | ||
1567 | DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n", | |
1568 | __func__, chip->start ); | |
1569 | ||
02b15e34 | 1570 | XIP_INVAL_CACHED_RANGE(map, adr, map->size); |
1da177e4 | 1571 | ENABLE_VPP(map); |
02b15e34 TP |
1572 | xip_disable(map, chip, adr); |
1573 | ||
1da177e4 LT |
1574 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); |
1575 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1576 | cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1577 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1578 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1579 | cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1580 | ||
1581 | chip->state = FL_ERASING; | |
1582 | chip->erase_suspended = 0; | |
1583 | chip->in_progress_block_addr = adr; | |
1584 | ||
02b15e34 TP |
1585 | INVALIDATE_CACHE_UDELAY(map, chip, |
1586 | adr, map->size, | |
1587 | chip->erase_time*500); | |
1da177e4 LT |
1588 | |
1589 | timeo = jiffies + (HZ*20); | |
1590 | ||
1591 | for (;;) { | |
1592 | if (chip->state != FL_ERASING) { | |
1593 | /* Someone's suspended the erase. Sleep */ | |
1594 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1595 | add_wait_queue(&chip->wq, &wait); | |
c4e77376 | 1596 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1597 | schedule(); |
1598 | remove_wait_queue(&chip->wq, &wait); | |
c4e77376 | 1599 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1600 | continue; |
1601 | } | |
1602 | if (chip->erase_suspended) { | |
1603 | /* This erase was suspended and resumed. | |
1604 | Adjust the timeout */ | |
1605 | timeo = jiffies + (HZ*20); /* FIXME */ | |
1606 | chip->erase_suspended = 0; | |
1607 | } | |
1608 | ||
1609 | if (chip_ready(map, adr)) | |
fb4a90bf | 1610 | break; |
1da177e4 | 1611 | |
fb4a90bf EB |
1612 | if (time_after(jiffies, timeo)) { |
1613 | printk(KERN_WARNING "MTD %s(): software timeout\n", | |
1614 | __func__ ); | |
1da177e4 | 1615 | break; |
fb4a90bf | 1616 | } |
1da177e4 LT |
1617 | |
1618 | /* Latency issues. Drop the lock, wait a while and retry */ | |
02b15e34 | 1619 | UDELAY(map, chip, adr, 1000000/HZ); |
1da177e4 | 1620 | } |
fb4a90bf EB |
1621 | /* Did we succeed? */ |
1622 | if (!chip_good(map, adr, map_word_ff(map))) { | |
1623 | /* reset on all failures. */ | |
1624 | map_write( map, CMD(0xF0), chip->start ); | |
1625 | /* FIXME - should have reset delay before continuing */ | |
1da177e4 | 1626 | |
fb4a90bf EB |
1627 | ret = -EIO; |
1628 | } | |
1da177e4 | 1629 | |
1da177e4 | 1630 | chip->state = FL_READY; |
02b15e34 | 1631 | xip_enable(map, chip, adr); |
1da177e4 | 1632 | put_chip(map, chip, adr); |
c4e77376 | 1633 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1634 | |
1635 | return ret; | |
1636 | } | |
1637 | ||
1638 | ||
02b15e34 | 1639 | static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk) |
1da177e4 LT |
1640 | { |
1641 | struct cfi_private *cfi = map->fldrv_priv; | |
1642 | unsigned long timeo = jiffies + HZ; | |
1643 | DECLARE_WAITQUEUE(wait, current); | |
1644 | int ret = 0; | |
1645 | ||
1646 | adr += chip->start; | |
1647 | ||
c4e77376 | 1648 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1649 | ret = get_chip(map, chip, adr, FL_ERASING); |
1650 | if (ret) { | |
c4e77376 | 1651 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1652 | return ret; |
1653 | } | |
1654 | ||
1655 | DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n", | |
1656 | __func__, adr ); | |
1657 | ||
02b15e34 | 1658 | XIP_INVAL_CACHED_RANGE(map, adr, len); |
1da177e4 | 1659 | ENABLE_VPP(map); |
02b15e34 TP |
1660 | xip_disable(map, chip, adr); |
1661 | ||
1da177e4 LT |
1662 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); |
1663 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1664 | cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1665 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1666 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1667 | map_write(map, CMD(0x30), adr); | |
1668 | ||
1669 | chip->state = FL_ERASING; | |
1670 | chip->erase_suspended = 0; | |
1671 | chip->in_progress_block_addr = adr; | |
02b15e34 TP |
1672 | |
1673 | INVALIDATE_CACHE_UDELAY(map, chip, | |
1674 | adr, len, | |
1675 | chip->erase_time*500); | |
1da177e4 LT |
1676 | |
1677 | timeo = jiffies + (HZ*20); | |
1678 | ||
1679 | for (;;) { | |
1680 | if (chip->state != FL_ERASING) { | |
1681 | /* Someone's suspended the erase. Sleep */ | |
1682 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1683 | add_wait_queue(&chip->wq, &wait); | |
c4e77376 | 1684 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1685 | schedule(); |
1686 | remove_wait_queue(&chip->wq, &wait); | |
c4e77376 | 1687 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1688 | continue; |
1689 | } | |
1690 | if (chip->erase_suspended) { | |
1691 | /* This erase was suspended and resumed. | |
1692 | Adjust the timeout */ | |
1693 | timeo = jiffies + (HZ*20); /* FIXME */ | |
1694 | chip->erase_suspended = 0; | |
1695 | } | |
1696 | ||
02b15e34 TP |
1697 | if (chip_ready(map, adr)) { |
1698 | xip_enable(map, chip, adr); | |
fb4a90bf | 1699 | break; |
02b15e34 | 1700 | } |
1da177e4 | 1701 | |
fb4a90bf | 1702 | if (time_after(jiffies, timeo)) { |
02b15e34 | 1703 | xip_enable(map, chip, adr); |
fb4a90bf EB |
1704 | printk(KERN_WARNING "MTD %s(): software timeout\n", |
1705 | __func__ ); | |
1da177e4 | 1706 | break; |
fb4a90bf | 1707 | } |
1da177e4 LT |
1708 | |
1709 | /* Latency issues. Drop the lock, wait a while and retry */ | |
02b15e34 | 1710 | UDELAY(map, chip, adr, 1000000/HZ); |
1da177e4 | 1711 | } |
fb4a90bf | 1712 | /* Did we succeed? */ |
22fd9a87 | 1713 | if (!chip_good(map, adr, map_word_ff(map))) { |
fb4a90bf EB |
1714 | /* reset on all failures. */ |
1715 | map_write( map, CMD(0xF0), chip->start ); | |
1716 | /* FIXME - should have reset delay before continuing */ | |
1717 | ||
1718 | ret = -EIO; | |
1719 | } | |
1da177e4 | 1720 | |
1da177e4 LT |
1721 | chip->state = FL_READY; |
1722 | put_chip(map, chip, adr); | |
c4e77376 | 1723 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1724 | return ret; |
1725 | } | |
1726 | ||
1727 | ||
ce0f33ad | 1728 | static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 LT |
1729 | { |
1730 | unsigned long ofs, len; | |
1731 | int ret; | |
1732 | ||
1733 | ofs = instr->addr; | |
1734 | len = instr->len; | |
1735 | ||
1736 | ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL); | |
1737 | if (ret) | |
1738 | return ret; | |
1739 | ||
1740 | instr->state = MTD_ERASE_DONE; | |
1741 | mtd_erase_callback(instr); | |
1f948b43 | 1742 | |
1da177e4 LT |
1743 | return 0; |
1744 | } | |
1745 | ||
1746 | ||
1747 | static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr) | |
1748 | { | |
1749 | struct map_info *map = mtd->priv; | |
1750 | struct cfi_private *cfi = map->fldrv_priv; | |
1751 | int ret = 0; | |
1752 | ||
1753 | if (instr->addr != 0) | |
1754 | return -EINVAL; | |
1755 | ||
1756 | if (instr->len != mtd->size) | |
1757 | return -EINVAL; | |
1758 | ||
1759 | ret = do_erase_chip(map, &cfi->chips[0]); | |
1760 | if (ret) | |
1761 | return ret; | |
1762 | ||
1763 | instr->state = MTD_ERASE_DONE; | |
1764 | mtd_erase_callback(instr); | |
1f948b43 | 1765 | |
1da177e4 LT |
1766 | return 0; |
1767 | } | |
1768 | ||
0165508c HS |
1769 | static int do_atmel_lock(struct map_info *map, struct flchip *chip, |
1770 | unsigned long adr, int len, void *thunk) | |
1771 | { | |
1772 | struct cfi_private *cfi = map->fldrv_priv; | |
1773 | int ret; | |
1774 | ||
c4e77376 | 1775 | mutex_lock(&chip->mutex); |
0165508c HS |
1776 | ret = get_chip(map, chip, adr + chip->start, FL_LOCKING); |
1777 | if (ret) | |
1778 | goto out_unlock; | |
1779 | chip->state = FL_LOCKING; | |
1780 | ||
1781 | DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n", | |
1782 | __func__, adr, len); | |
1783 | ||
1784 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, | |
1785 | cfi->device_type, NULL); | |
1786 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, | |
1787 | cfi->device_type, NULL); | |
1788 | cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, | |
1789 | cfi->device_type, NULL); | |
1790 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, | |
1791 | cfi->device_type, NULL); | |
1792 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, | |
1793 | cfi->device_type, NULL); | |
1794 | map_write(map, CMD(0x40), chip->start + adr); | |
1795 | ||
1796 | chip->state = FL_READY; | |
1797 | put_chip(map, chip, adr + chip->start); | |
1798 | ret = 0; | |
1799 | ||
1800 | out_unlock: | |
c4e77376 | 1801 | mutex_unlock(&chip->mutex); |
0165508c HS |
1802 | return ret; |
1803 | } | |
1804 | ||
1805 | static int do_atmel_unlock(struct map_info *map, struct flchip *chip, | |
1806 | unsigned long adr, int len, void *thunk) | |
1807 | { | |
1808 | struct cfi_private *cfi = map->fldrv_priv; | |
1809 | int ret; | |
1810 | ||
c4e77376 | 1811 | mutex_lock(&chip->mutex); |
0165508c HS |
1812 | ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING); |
1813 | if (ret) | |
1814 | goto out_unlock; | |
1815 | chip->state = FL_UNLOCKING; | |
1816 | ||
1817 | DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n", | |
1818 | __func__, adr, len); | |
1819 | ||
1820 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, | |
1821 | cfi->device_type, NULL); | |
1822 | map_write(map, CMD(0x70), adr); | |
1823 | ||
1824 | chip->state = FL_READY; | |
1825 | put_chip(map, chip, adr + chip->start); | |
1826 | ret = 0; | |
1827 | ||
1828 | out_unlock: | |
c4e77376 | 1829 | mutex_unlock(&chip->mutex); |
0165508c HS |
1830 | return ret; |
1831 | } | |
1832 | ||
69423d99 | 1833 | static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
0165508c HS |
1834 | { |
1835 | return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL); | |
1836 | } | |
1837 | ||
69423d99 | 1838 | static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
0165508c HS |
1839 | { |
1840 | return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL); | |
1841 | } | |
1842 | ||
1da177e4 LT |
1843 | |
1844 | static void cfi_amdstd_sync (struct mtd_info *mtd) | |
1845 | { | |
1846 | struct map_info *map = mtd->priv; | |
1847 | struct cfi_private *cfi = map->fldrv_priv; | |
1848 | int i; | |
1849 | struct flchip *chip; | |
1850 | int ret = 0; | |
1851 | DECLARE_WAITQUEUE(wait, current); | |
1852 | ||
1853 | for (i=0; !ret && i<cfi->numchips; i++) { | |
1854 | chip = &cfi->chips[i]; | |
1855 | ||
1856 | retry: | |
c4e77376 | 1857 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1858 | |
1859 | switch(chip->state) { | |
1860 | case FL_READY: | |
1861 | case FL_STATUS: | |
1862 | case FL_CFI_QUERY: | |
1863 | case FL_JEDEC_QUERY: | |
1864 | chip->oldstate = chip->state; | |
1865 | chip->state = FL_SYNCING; | |
1f948b43 | 1866 | /* No need to wake_up() on this state change - |
1da177e4 LT |
1867 | * as the whole point is that nobody can do anything |
1868 | * with the chip now anyway. | |
1869 | */ | |
1870 | case FL_SYNCING: | |
c4e77376 | 1871 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1872 | break; |
1873 | ||
1874 | default: | |
1875 | /* Not an idle state */ | |
f8e30e44 | 1876 | set_current_state(TASK_UNINTERRUPTIBLE); |
1da177e4 | 1877 | add_wait_queue(&chip->wq, &wait); |
1f948b43 | 1878 | |
c4e77376 | 1879 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1880 | |
1881 | schedule(); | |
1882 | ||
1883 | remove_wait_queue(&chip->wq, &wait); | |
1f948b43 | 1884 | |
1da177e4 LT |
1885 | goto retry; |
1886 | } | |
1887 | } | |
1888 | ||
1889 | /* Unlock the chips again */ | |
1890 | ||
1891 | for (i--; i >=0; i--) { | |
1892 | chip = &cfi->chips[i]; | |
1893 | ||
c4e77376 | 1894 | mutex_lock(&chip->mutex); |
1f948b43 | 1895 | |
1da177e4 LT |
1896 | if (chip->state == FL_SYNCING) { |
1897 | chip->state = chip->oldstate; | |
1898 | wake_up(&chip->wq); | |
1899 | } | |
c4e77376 | 1900 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1901 | } |
1902 | } | |
1903 | ||
1904 | ||
1905 | static int cfi_amdstd_suspend(struct mtd_info *mtd) | |
1906 | { | |
1907 | struct map_info *map = mtd->priv; | |
1908 | struct cfi_private *cfi = map->fldrv_priv; | |
1909 | int i; | |
1910 | struct flchip *chip; | |
1911 | int ret = 0; | |
1912 | ||
1913 | for (i=0; !ret && i<cfi->numchips; i++) { | |
1914 | chip = &cfi->chips[i]; | |
1915 | ||
c4e77376 | 1916 | mutex_lock(&chip->mutex); |
1da177e4 LT |
1917 | |
1918 | switch(chip->state) { | |
1919 | case FL_READY: | |
1920 | case FL_STATUS: | |
1921 | case FL_CFI_QUERY: | |
1922 | case FL_JEDEC_QUERY: | |
1923 | chip->oldstate = chip->state; | |
1924 | chip->state = FL_PM_SUSPENDED; | |
1f948b43 | 1925 | /* No need to wake_up() on this state change - |
1da177e4 LT |
1926 | * as the whole point is that nobody can do anything |
1927 | * with the chip now anyway. | |
1928 | */ | |
1929 | case FL_PM_SUSPENDED: | |
1930 | break; | |
1931 | ||
1932 | default: | |
1933 | ret = -EAGAIN; | |
1934 | break; | |
1935 | } | |
c4e77376 | 1936 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1937 | } |
1938 | ||
1939 | /* Unlock the chips again */ | |
1940 | ||
1941 | if (ret) { | |
1942 | for (i--; i >=0; i--) { | |
1943 | chip = &cfi->chips[i]; | |
1944 | ||
c4e77376 | 1945 | mutex_lock(&chip->mutex); |
1f948b43 | 1946 | |
1da177e4 LT |
1947 | if (chip->state == FL_PM_SUSPENDED) { |
1948 | chip->state = chip->oldstate; | |
1949 | wake_up(&chip->wq); | |
1950 | } | |
c4e77376 | 1951 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1952 | } |
1953 | } | |
1f948b43 | 1954 | |
1da177e4 LT |
1955 | return ret; |
1956 | } | |
1957 | ||
1958 | ||
1959 | static void cfi_amdstd_resume(struct mtd_info *mtd) | |
1960 | { | |
1961 | struct map_info *map = mtd->priv; | |
1962 | struct cfi_private *cfi = map->fldrv_priv; | |
1963 | int i; | |
1964 | struct flchip *chip; | |
1965 | ||
1966 | for (i=0; i<cfi->numchips; i++) { | |
1f948b43 | 1967 | |
1da177e4 LT |
1968 | chip = &cfi->chips[i]; |
1969 | ||
c4e77376 | 1970 | mutex_lock(&chip->mutex); |
1f948b43 | 1971 | |
1da177e4 LT |
1972 | if (chip->state == FL_PM_SUSPENDED) { |
1973 | chip->state = FL_READY; | |
1974 | map_write(map, CMD(0xF0), chip->start); | |
1975 | wake_up(&chip->wq); | |
1976 | } | |
1977 | else | |
1978 | printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n"); | |
1979 | ||
c4e77376 | 1980 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
1981 | } |
1982 | } | |
1983 | ||
eafe1311 KC |
1984 | |
1985 | /* | |
1986 | * Ensure that the flash device is put back into read array mode before | |
1987 | * unloading the driver or rebooting. On some systems, rebooting while | |
1988 | * the flash is in query/program/erase mode will prevent the CPU from | |
1989 | * fetching the bootloader code, requiring a hard reset or power cycle. | |
1990 | */ | |
1991 | static int cfi_amdstd_reset(struct mtd_info *mtd) | |
1992 | { | |
1993 | struct map_info *map = mtd->priv; | |
1994 | struct cfi_private *cfi = map->fldrv_priv; | |
1995 | int i, ret; | |
1996 | struct flchip *chip; | |
1997 | ||
1998 | for (i = 0; i < cfi->numchips; i++) { | |
1999 | ||
2000 | chip = &cfi->chips[i]; | |
2001 | ||
2002 | mutex_lock(&chip->mutex); | |
2003 | ||
2004 | ret = get_chip(map, chip, chip->start, FL_SHUTDOWN); | |
2005 | if (!ret) { | |
2006 | map_write(map, CMD(0xF0), chip->start); | |
2007 | chip->state = FL_SHUTDOWN; | |
2008 | put_chip(map, chip, chip->start); | |
2009 | } | |
2010 | ||
2011 | mutex_unlock(&chip->mutex); | |
2012 | } | |
2013 | ||
2014 | return 0; | |
2015 | } | |
2016 | ||
2017 | ||
2018 | static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val, | |
2019 | void *v) | |
2020 | { | |
2021 | struct mtd_info *mtd; | |
2022 | ||
2023 | mtd = container_of(nb, struct mtd_info, reboot_notifier); | |
2024 | cfi_amdstd_reset(mtd); | |
2025 | return NOTIFY_DONE; | |
2026 | } | |
2027 | ||
2028 | ||
1da177e4 LT |
2029 | static void cfi_amdstd_destroy(struct mtd_info *mtd) |
2030 | { | |
2031 | struct map_info *map = mtd->priv; | |
2032 | struct cfi_private *cfi = map->fldrv_priv; | |
fa671646 | 2033 | |
eafe1311 KC |
2034 | cfi_amdstd_reset(mtd); |
2035 | unregister_reboot_notifier(&mtd->reboot_notifier); | |
1da177e4 LT |
2036 | kfree(cfi->cmdset_priv); |
2037 | kfree(cfi->cfiq); | |
2038 | kfree(cfi); | |
2039 | kfree(mtd->eraseregions); | |
2040 | } | |
2041 | ||
1da177e4 LT |
2042 | MODULE_LICENSE("GPL"); |
2043 | MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al."); | |
2044 | MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips"); | |
1e804cec | 2045 | MODULE_ALIAS("cfi_cmdset_0701"); |