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1da177e4
LT		 1/*
2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
4 *
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
02b15e34 7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
1da177e4
LT		 8 *
9 * 2_by_8 routines added by Simon Munton
10 *
11 * 4_by_16 work by Carolyn J. Smith
12 *
1f948b43 13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
02b15e34 14 * by Nicolas Pitre)
1f948b43 15 *
87e92c06
CM		 16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
17 *
1da177e4
LT		 18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
19 *
20 * This code is GPL
1da177e4
LT		 21 */
22
1da177e4
LT		 23#include <linux/module.h>
24#include <linux/types.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
1da177e4
LT		 27#include <asm/io.h>
28#include <asm/byteorder.h>
29
30#include <linux/errno.h>
31#include <linux/slab.h>
32#include <linux/delay.h>
33#include <linux/interrupt.h>
eafe1311 34#include <linux/reboot.h>
1648eaaa
SR		 35#include <linux/of.h>
36#include <linux/of_platform.h>
1da177e4
LT		 37#include <linux/mtd/map.h>
38#include <linux/mtd/mtd.h>
39#include <linux/mtd/cfi.h>
02b15e34 40#include <linux/mtd/xip.h>
1da177e4
LT		 41
42#define AMD_BOOTLOC_BUG
43#define FORCE_WORD_WRITE 0
44
85a82e28 45#define MAX_RETRIES 3
1da177e4 46
ea092fb3
TI		 47#define SST49LF004B 0x0060
48#define SST49LF040B 0x0050
fb4a90bf 49#define SST49LF008A 0x005a
0165508c 50#define AT49BV6416 0x00d6
1da177e4
LT		 51
52static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
53static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
54static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
55static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
56static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
57static void cfi_amdstd_sync (struct mtd_info *);
58static int cfi_amdstd_suspend (struct mtd_info *);
59static void cfi_amdstd_resume (struct mtd_info *);
eafe1311 60static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *);
dc7e9ecd
CR		 61static int cfi_amdstd_get_fact_prot_info(struct mtd_info *, size_t,
62 size_t *, struct otp_info *);
63static int cfi_amdstd_get_user_prot_info(struct mtd_info *, size_t,
64 size_t *, struct otp_info *);
1da177e4 65static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
dc7e9ecd
CR		 66static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *, loff_t, size_t,
67 size_t *, u_char *);
68static int cfi_amdstd_read_user_prot_reg(struct mtd_info *, loff_t, size_t,
69 size_t *, u_char *);
af744750
CR		 70static int cfi_amdstd_write_user_prot_reg(struct mtd_info *, loff_t, size_t,
71 size_t *, u_char *);
4f5cb243 72static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *, loff_t, size_t);
1da177e4 73
30ec5a2c
IS		 74static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
75 size_t *retlen, const u_char *buf);
76
1da177e4
LT		 77static void cfi_amdstd_destroy(struct mtd_info *);
78
79struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
80static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
81
82static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
83static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
84#include "fwh_lock.h"
85
69423d99
AH		 86static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
87static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
0165508c 88
1648eaaa
SR		 89static int cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
90static int cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
91static int cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len);
92
1da177e4
LT		 93static struct mtd_chip_driver cfi_amdstd_chipdrv = {
94 .probe = NULL, /* Not usable directly */
95 .destroy = cfi_amdstd_destroy,
96 .name = "cfi_cmdset_0002",
97 .module = THIS_MODULE
98};
99
100
101/* #define DEBUG_CFI_FEATURES */
102
103
104#ifdef DEBUG_CFI_FEATURES
105static void cfi_tell_features(struct cfi_pri_amdstd *extp)
106{
107 const char* erase_suspend[3] = {
108 "Not supported", "Read only", "Read/write"
109 };
110 const char* top_bottom[6] = {
111 "No WP", "8x8KiB sectors at top & bottom, no WP",
112 "Bottom boot", "Top boot",
113 "Uniform, Bottom WP", "Uniform, Top WP"
114 };
115
116 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
1f948b43 117 printk(" Address sensitive unlock: %s\n",
1da177e4
LT		 118 (extp->SiliconRevision & 1) ? "Not required" : "Required");
119
120 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
121 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
122 else
123 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
124
125 if (extp->BlkProt == 0)
126 printk(" Block protection: Not supported\n");
127 else
128 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
129
130
131 printk(" Temporary block unprotect: %s\n",
132 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
133 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
134 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
135 printk(" Burst mode: %s\n",
136 extp->BurstMode ? "Supported" : "Not supported");
137 if (extp->PageMode == 0)
138 printk(" Page mode: Not supported\n");
139 else
140 printk(" Page mode: %d word page\n", extp->PageMode << 2);
141
1f948b43 142 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
1da177e4 143 extp->VppMin >> 4, extp->VppMin & 0xf);
1f948b43 144 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
1da177e4
LT		 145 extp->VppMax >> 4, extp->VppMax & 0xf);
146
147 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
148 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
149 else
150 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
151}
152#endif
153
154#ifdef AMD_BOOTLOC_BUG
155/* Wheee. Bring me the head of someone at AMD. */
cc318222 156static void fixup_amd_bootblock(struct mtd_info *mtd)
1da177e4
LT		 157{
158 struct map_info *map = mtd->priv;
159 struct cfi_private *cfi = map->fldrv_priv;
160 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
161 __u8 major = extp->MajorVersion;
162 __u8 minor = extp->MinorVersion;
163
164 if (((major << 8) | minor) < 0x3131) {
165 /* CFI version 1.0 => don't trust bootloc */
87e92c06 166
289c0522 167 pr_debug("%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
87e92c06
CM		 168 map->name, cfi->mfr, cfi->id);
169
170 /* AFAICS all 29LV400 with a bottom boot block have a device ID
171 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode.
172 * These were badly detected as they have the 0x80 bit set
173 * so treat them as a special case.
174 */
175 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
176
177 /* Macronix added CFI to their 2nd generation
178 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD,
179 * Fujitsu, Spansion, EON, ESI and older Macronix)
180 * has CFI.
181 *
182 * Therefore also check the manufacturer.
183 * This reduces the risk of false detection due to
184 * the 8-bit device ID.
185 */
f3e69c65 186 (cfi->mfr == CFI_MFR_MACRONIX)) {
289c0522 187 pr_debug("%s: Macronix MX29LV400C with bottom boot block"
87e92c06
CM		 188 " detected\n", map->name);
189 extp->TopBottom = 2; /* bottom boot */
190 } else
1da177e4
LT		 191 if (cfi->id & 0x80) {
192 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
193 extp->TopBottom = 3; /* top boot */
194 } else {
195 extp->TopBottom = 2; /* bottom boot */
196 }
87e92c06 197
289c0522 198 pr_debug("%s: AMD CFI PRI V%c.%c has no boot block field;"
87e92c06
CM		 199 " deduced %s from Device ID\n", map->name, major, minor,
200 extp->TopBottom == 2 ? "bottom" : "top");
1da177e4
LT		 201 }
202}
203#endif
204
cc318222 205static void fixup_use_write_buffers(struct mtd_info *mtd)
1da177e4
LT		 206{
207 struct map_info *map = mtd->priv;
208 struct cfi_private *cfi = map->fldrv_priv;
209 if (cfi->cfiq->BufWriteTimeoutTyp) {
ea092fb3 210 pr_debug("Using buffer write method\n");
3c3c10bb 211 mtd->_write = cfi_amdstd_write_buffers;
1da177e4
LT		 212 }
213}
214
5b0c5c2c 215/* Atmel chips don't use the same PRI format as AMD chips */
cc318222 216static void fixup_convert_atmel_pri(struct mtd_info *mtd)
5b0c5c2c
HS		 217{
218 struct map_info *map = mtd->priv;
219 struct cfi_private *cfi = map->fldrv_priv;
220 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
221 struct cfi_pri_atmel atmel_pri;
222
223 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
de591dac 224 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
5b0c5c2c
HS		 225
226 if (atmel_pri.Features & 0x02)
227 extp->EraseSuspend = 2;
228
be8f78b8
HS		 229 /* Some chips got it backwards... */
230 if (cfi->id == AT49BV6416) {
231 if (atmel_pri.BottomBoot)
232 extp->TopBottom = 3;
233 else
234 extp->TopBottom = 2;
235 } else {
236 if (atmel_pri.BottomBoot)
237 extp->TopBottom = 2;
238 else
239 extp->TopBottom = 3;
240 }
d10a39d1
HCE		 241
242 /* burst write mode not supported */
243 cfi->cfiq->BufWriteTimeoutTyp = 0;
244 cfi->cfiq->BufWriteTimeoutMax = 0;
5b0c5c2c
HS		 245}
246
cc318222 247static void fixup_use_secsi(struct mtd_info *mtd)
1da177e4
LT		 248{
249 /* Setup for chips with a secsi area */
3c3c10bb
AB		 250 mtd->_read_user_prot_reg = cfi_amdstd_secsi_read;
251 mtd->_read_fact_prot_reg = cfi_amdstd_secsi_read;
1da177e4
LT		 252}
253
cc318222 254static void fixup_use_erase_chip(struct mtd_info *mtd)
1da177e4
LT		 255{
256 struct map_info *map = mtd->priv;
257 struct cfi_private *cfi = map->fldrv_priv;
258 if ((cfi->cfiq->NumEraseRegions == 1) &&
259 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
3c3c10bb 260 mtd->_erase = cfi_amdstd_erase_chip;
1da177e4 261 }
1f948b43 262
1da177e4
LT		 263}
264
0165508c
HS		 265/*
266 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
267 * locked by default.
268 */
cc318222 269static void fixup_use_atmel_lock(struct mtd_info *mtd)
0165508c 270{
3c3c10bb
AB		 271 mtd->_lock = cfi_atmel_lock;
272 mtd->_unlock = cfi_atmel_unlock;
e619a75f 273 mtd->flags |= MTD_POWERUP_LOCK;
0165508c
HS		 274}
275
83dcd3bb
GL		 276static void fixup_old_sst_eraseregion(struct mtd_info *mtd)
277{
278 struct map_info *map = mtd->priv;
279 struct cfi_private *cfi = map->fldrv_priv;
280
281 /*
25985edc 282 * These flashes report two separate eraseblock regions based on the
83dcd3bb
GL		 283 * sector_erase-size and block_erase-size, although they both operate on the
284 * same memory. This is not allowed according to CFI, so we just pick the
285 * sector_erase-size.
286 */
287 cfi->cfiq->NumEraseRegions = 1;
288}
289
cc318222 290static void fixup_sst39vf(struct mtd_info *mtd)
83dcd3bb
GL		 291{
292 struct map_info *map = mtd->priv;
293 struct cfi_private *cfi = map->fldrv_priv;
294
295 fixup_old_sst_eraseregion(mtd);
296
297 cfi->addr_unlock1 = 0x5555;
298 cfi->addr_unlock2 = 0x2AAA;
299}
300
cc318222 301static void fixup_sst39vf_rev_b(struct mtd_info *mtd)
5a0563f0
GL		 302{
303 struct map_info *map = mtd->priv;
304 struct cfi_private *cfi = map->fldrv_priv;
305
306 fixup_old_sst_eraseregion(mtd);
307
308 cfi->addr_unlock1 = 0x555;
309 cfi->addr_unlock2 = 0x2AA;
08968041
GL		 310
311 cfi->sector_erase_cmd = CMD(0x50);
5a0563f0
GL		 312}
313
cc318222 314static void fixup_sst38vf640x_sectorsize(struct mtd_info *mtd)
9fc05fca
GL		 315{
316 struct map_info *map = mtd->priv;
317 struct cfi_private *cfi = map->fldrv_priv;
318
cc318222 319 fixup_sst39vf_rev_b(mtd);
9fc05fca
GL		 320
321 /*
322 * CFI reports 1024 sectors (0x03ff+1) of 64KBytes (0x0100*256) where
323 * it should report a size of 8KBytes (0x0020*256).
324 */
325 cfi->cfiq->EraseRegionInfo[0] = 0x002003ff;
e8348dc5
JP		 326 pr_warn("%s: Bad 38VF640x CFI data; adjusting sector size from 64 to 8KiB\n",
327 mtd->name);
9fc05fca
GL		 328}
329
cc318222 330static void fixup_s29gl064n_sectors(struct mtd_info *mtd)
70b07255
TP		 331{
332 struct map_info *map = mtd->priv;
333 struct cfi_private *cfi = map->fldrv_priv;
334
335 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) {
336 cfi->cfiq->EraseRegionInfo[0] |= 0x0040;
e8348dc5
JP		 337 pr_warn("%s: Bad S29GL064N CFI data; adjust from 64 to 128 sectors\n",
338 mtd->name);
70b07255
TP		 339 }
340}
341
cc318222 342static void fixup_s29gl032n_sectors(struct mtd_info *mtd)
70b07255
TP		 343{
344 struct map_info *map = mtd->priv;
345 struct cfi_private *cfi = map->fldrv_priv;
346
347 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) {
348 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040;
e8348dc5
JP		 349 pr_warn("%s: Bad S29GL032N CFI data; adjust from 127 to 63 sectors\n",
350 mtd->name);
70b07255
TP		 351 }
352}
353
43dc03c7
JM		 354static void fixup_s29ns512p_sectors(struct mtd_info *mtd)
355{
356 struct map_info *map = mtd->priv;
357 struct cfi_private *cfi = map->fldrv_priv;
358
359 /*
360 * S29NS512P flash uses more than 8bits to report number of sectors,
361 * which is not permitted by CFI.
362 */
363 cfi->cfiq->EraseRegionInfo[0] = 0x020001ff;
e8348dc5
JP		 364 pr_warn("%s: Bad S29NS512P CFI data; adjust to 512 sectors\n",
365 mtd->name);
43dc03c7
JM		 366}
367
83dcd3bb
GL		 368/* Used to fix CFI-Tables of chips without Extended Query Tables */
369static struct cfi_fixup cfi_nopri_fixup_table[] = {
cc318222
GL		 370 { CFI_MFR_SST, 0x234a, fixup_sst39vf }, /* SST39VF1602 */
371 { CFI_MFR_SST, 0x234b, fixup_sst39vf }, /* SST39VF1601 */
372 { CFI_MFR_SST, 0x235a, fixup_sst39vf }, /* SST39VF3202 */
373 { CFI_MFR_SST, 0x235b, fixup_sst39vf }, /* SST39VF3201 */
374 { CFI_MFR_SST, 0x235c, fixup_sst39vf_rev_b }, /* SST39VF3202B */
375 { CFI_MFR_SST, 0x235d, fixup_sst39vf_rev_b }, /* SST39VF3201B */
376 { CFI_MFR_SST, 0x236c, fixup_sst39vf_rev_b }, /* SST39VF6402B */
377 { CFI_MFR_SST, 0x236d, fixup_sst39vf_rev_b }, /* SST39VF6401B */
378 { 0, 0, NULL }
83dcd3bb
GL		 379};
380
1da177e4 381static struct cfi_fixup cfi_fixup_table[] = {
cc318222 382 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri },
1da177e4 383#ifdef AMD_BOOTLOC_BUG
cc318222 384 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock },
1065cda8 385 { CFI_MFR_AMIC, CFI_ID_ANY, fixup_amd_bootblock },
cc318222 386 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock },
1da177e4 387#endif
cc318222
GL		 388 { CFI_MFR_AMD, 0x0050, fixup_use_secsi },
389 { CFI_MFR_AMD, 0x0053, fixup_use_secsi },
390 { CFI_MFR_AMD, 0x0055, fixup_use_secsi },
391 { CFI_MFR_AMD, 0x0056, fixup_use_secsi },
392 { CFI_MFR_AMD, 0x005C, fixup_use_secsi },
393 { CFI_MFR_AMD, 0x005F, fixup_use_secsi },
394 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors },
395 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors },
396 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors },
397 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors },
43dc03c7 398 { CFI_MFR_AMD, 0x3f00, fixup_s29ns512p_sectors },
cc318222
GL		 399 { CFI_MFR_SST, 0x536a, fixup_sst38vf640x_sectorsize }, /* SST38VF6402 */
400 { CFI_MFR_SST, 0x536b, fixup_sst38vf640x_sectorsize }, /* SST38VF6401 */
401 { CFI_MFR_SST, 0x536c, fixup_sst38vf640x_sectorsize }, /* SST38VF6404 */
402 { CFI_MFR_SST, 0x536d, fixup_sst38vf640x_sectorsize }, /* SST38VF6403 */
1da177e4 403#if !FORCE_WORD_WRITE
cc318222 404 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers },
1da177e4 405#endif
cc318222 406 { 0, 0, NULL }
1da177e4
LT		 407};
408static struct cfi_fixup jedec_fixup_table[] = {
cc318222
GL		 409 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock },
410 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock },
411 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock },
412 { 0, 0, NULL }
1da177e4
LT		 413};
414
415static struct cfi_fixup fixup_table[] = {
416 /* The CFI vendor ids and the JEDEC vendor IDs appear
417 * to be common. It is like the devices id's are as
418 * well. This table is to pick all cases where
419 * we know that is the case.
420 */
cc318222
GL		 421 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip },
422 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock },
423 { 0, 0, NULL }
1da177e4
LT		 424};
425
426
fefae48b
WG		 427static void cfi_fixup_major_minor(struct cfi_private *cfi,
428 struct cfi_pri_amdstd *extp)
429{
e6372763 430 if (cfi->mfr == CFI_MFR_SAMSUNG) {
e8953b73
GL		 431 if ((extp->MajorVersion == '0' && extp->MinorVersion == '0') ||
432 (extp->MajorVersion == '3' && extp->MinorVersion == '3')) {
e6372763
GL		 433 /*
434 * Samsung K8P2815UQB and K8D6x16UxM chips
435 * report major=0 / minor=0.
e8953b73 436 * K8D3x16UxC chips report major=3 / minor=3.
e6372763
GL		 437 */
438 printk(KERN_NOTICE " Fixing Samsung's Amd/Fujitsu"
439 " Extended Query version to 1.%c\n",
440 extp->MinorVersion);
441 extp->MajorVersion = '1';
442 }
443 }
444
9fc05fca
GL		 445 /*
446 * SST 38VF640x chips report major=0xFF / minor=0xFF.
447 */
448 if (cfi->mfr == CFI_MFR_SST && (cfi->id >> 4) == 0x0536) {
449 extp->MajorVersion = '1';
450 extp->MinorVersion = '0';
451 }
fefae48b
WG		 452}
453
42096288
GF		 454static int is_m29ew(struct cfi_private *cfi)
455{
456 if (cfi->mfr == CFI_MFR_INTEL &&
457 ((cfi->device_type == CFI_DEVICETYPE_X8 && (cfi->id & 0xff) == 0x7e) ||
458 (cfi->device_type == CFI_DEVICETYPE_X16 && cfi->id == 0x227e)))
459 return 1;
460 return 0;
461}
462
463/*
464 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 20:
465 * Some revisions of the M29EW suffer from erase suspend hang ups. In
466 * particular, it can occur when the sequence
467 * Erase Confirm -> Suspend -> Program -> Resume
468 * causes a lockup due to internal timing issues. The consequence is that the
469 * erase cannot be resumed without inserting a dummy command after programming
470 * and prior to resuming. [...] The work-around is to issue a dummy write cycle
471 * that writes an F0 command code before the RESUME command.
472 */
473static void cfi_fixup_m29ew_erase_suspend(struct map_info *map,
474 unsigned long adr)
475{
476 struct cfi_private *cfi = map->fldrv_priv;
477 /* before resume, insert a dummy 0xF0 cycle for Micron M29EW devices */
478 if (is_m29ew(cfi))
479 map_write(map, CMD(0xF0), adr);
480}
481
482/*
483 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 22:
484 *
485 * Some revisions of the M29EW (for example, A1 and A2 step revisions)
486 * are affected by a problem that could cause a hang up when an ERASE SUSPEND
487 * command is issued after an ERASE RESUME operation without waiting for a
488 * minimum delay. The result is that once the ERASE seems to be completed
489 * (no bits are toggling), the contents of the Flash memory block on which
490 * the erase was ongoing could be inconsistent with the expected values
491 * (typically, the array value is stuck to the 0xC0, 0xC4, 0x80, or 0x84
492 * values), causing a consequent failure of the ERASE operation.
493 * The occurrence of this issue could be high, especially when file system
494 * operations on the Flash are intensive. As a result, it is recommended
495 * that a patch be applied. Intensive file system operations can cause many
496 * calls to the garbage routine to free Flash space (also by erasing physical
497 * Flash blocks) and as a result, many consecutive SUSPEND and RESUME
498 * commands can occur. The problem disappears when a delay is inserted after
499 * the RESUME command by using the udelay() function available in Linux.
500 * The DELAY value must be tuned based on the customer's platform.
501 * The maximum value that fixes the problem in all cases is 500us.
502 * But, in our experience, a delay of 30 µs to 50 µs is sufficient
503 * in most cases.
504 * We have chosen 500µs because this latency is acceptable.
505 */
506static void cfi_fixup_m29ew_delay_after_resume(struct cfi_private *cfi)
507{
508 /*
509 * Resolving the Delay After Resume Issue see Micron TN-13-07
510 * Worst case delay must be 500µs but 30-50µs should be ok as well
511 */
512 if (is_m29ew(cfi))
513 cfi_udelay(500);
514}
515
1da177e4
LT		 516struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
517{
518 struct cfi_private *cfi = map->fldrv_priv;
1648eaaa 519 struct device_node __maybe_unused *np = map->device_node;
1da177e4
LT		 520 struct mtd_info *mtd;
521 int i;
522
95b93a0c 523 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
5c8b1fbb 524 if (!mtd)
1da177e4 525 return NULL;
1da177e4
LT		 526 mtd->priv = map;
527 mtd->type = MTD_NORFLASH;
528
529 /* Fill in the default mtd operations */
3c3c10bb
AB		 530 mtd->_erase = cfi_amdstd_erase_varsize;
531 mtd->_write = cfi_amdstd_write_words;
532 mtd->_read = cfi_amdstd_read;
533 mtd->_sync = cfi_amdstd_sync;
534 mtd->_suspend = cfi_amdstd_suspend;
535 mtd->_resume = cfi_amdstd_resume;
dc7e9ecd
CR		 536 mtd->_read_user_prot_reg = cfi_amdstd_read_user_prot_reg;
537 mtd->_read_fact_prot_reg = cfi_amdstd_read_fact_prot_reg;
538 mtd->_get_fact_prot_info = cfi_amdstd_get_fact_prot_info;
539 mtd->_get_user_prot_info = cfi_amdstd_get_user_prot_info;
af744750 540 mtd->_write_user_prot_reg = cfi_amdstd_write_user_prot_reg;
4f5cb243 541 mtd->_lock_user_prot_reg = cfi_amdstd_lock_user_prot_reg;
1da177e4
LT		 542 mtd->flags = MTD_CAP_NORFLASH;
543 mtd->name = map->name;
783ed81f 544 mtd->writesize = 1;
13ce77f4 545 mtd->writebufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
d261c72a 546
0a32a102
BN		 547 pr_debug("MTD %s(): write buffer size %d\n", __func__,
548 mtd->writebufsize);
1da177e4 549
3c3c10bb 550 mtd->_panic_write = cfi_amdstd_panic_write;
eafe1311
KC		 551 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot;
552
1da177e4
LT		 553 if (cfi->cfi_mode==CFI_MODE_CFI){
554 unsigned char bootloc;
1da177e4
LT		 555 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
556 struct cfi_pri_amdstd *extp;
557
558 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
564b8497
GL		 559 if (extp) {
560 /*
561 * It's a real CFI chip, not one for which the probe
562 * routine faked a CFI structure.
563 */
564 cfi_fixup_major_minor(cfi, extp);
565
e17f47a1 566 /*
c9ddab25 567 * Valid primary extension versions are: 1.0, 1.1, 1.2, 1.3, 1.4, 1.5
631dd1a8
JM		 568 * see: http://cs.ozerki.net/zap/pub/axim-x5/docs/cfi_r20.pdf, page 19
569 * http://www.spansion.com/Support/AppNotes/cfi_100_20011201.pdf
5da19532 570 * http://www.spansion.com/Support/Datasheets/s29ws-p_00_a12_e.pdf
c9ddab25 571 * http://www.spansion.com/Support/Datasheets/S29GL_128S_01GS_00_02_e.pdf
e17f47a1 572 */
564b8497 573 if (extp->MajorVersion != '1' ||
c9ddab25 574 (extp->MajorVersion == '1' && (extp->MinorVersion < '0' || extp->MinorVersion > '5'))) {
564b8497 575 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
e17f47a1
GL		 576 "version %c.%c (%#02x/%#02x).\n",
577 extp->MajorVersion, extp->MinorVersion,
578 extp->MajorVersion, extp->MinorVersion);
564b8497
GL		 579 kfree(extp);
580 kfree(mtd);
581 return NULL;
582 }
d88f977b 583
e17f47a1
GL		 584 printk(KERN_INFO " Amd/Fujitsu Extended Query version %c.%c.\n",
585 extp->MajorVersion, extp->MinorVersion);
586
564b8497
GL		 587 /* Install our own private info structure */
588 cfi->cmdset_priv = extp;
1da177e4 589
564b8497
GL		 590 /* Apply cfi device specific fixups */
591 cfi_fixup(mtd, cfi_fixup_table);
1da177e4
LT		 592
593#ifdef DEBUG_CFI_FEATURES
564b8497
GL		 594 /* Tell the user about it in lots of lovely detail */
595 cfi_tell_features(extp);
1f948b43 596#endif
1da177e4 597
1648eaaa
SR		 598#ifdef CONFIG_OF
599 if (np && of_property_read_bool(
600 np, "use-advanced-sector-protection")
601 && extp->BlkProtUnprot == 8) {
602 printk(KERN_INFO " Advanced Sector Protection (PPB Locking) supported\n");
603 mtd->_lock = cfi_ppb_lock;
604 mtd->_unlock = cfi_ppb_unlock;
605 mtd->_is_locked = cfi_ppb_is_locked;
606 }
607#endif
608
564b8497 609 bootloc = extp->TopBottom;
412da2f6
DW		 610 if ((bootloc < 2) || (bootloc > 5)) {
611 printk(KERN_WARNING "%s: CFI contains unrecognised boot "
612 "bank location (%d). Assuming bottom.\n",
abab7ebf 613 map->name, bootloc);
564b8497
GL		 614 bootloc = 2;
615 }
1da177e4 616
564b8497 617 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
412da2f6 618 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name);
1f948b43 619
564b8497
GL		 620 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
621 int j = (cfi->cfiq->NumEraseRegions-1)-i;
1f948b43 622
fdd9d27c
FF		 623 swap(cfi->cfiq->EraseRegionInfo[i],
624 cfi->cfiq->EraseRegionInfo[j]);
564b8497 625 }
1da177e4 626 }
564b8497
GL		 627 /* Set the default CFI lock/unlock addresses */
628 cfi->addr_unlock1 = 0x555;
629 cfi->addr_unlock2 = 0x2aa;
630 }
83dcd3bb 631 cfi_fixup(mtd, cfi_nopri_fixup_table);
564b8497
GL		 632
633 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) {
634 kfree(mtd);
635 return NULL;
1da177e4 636 }
1da177e4
LT		 637
638 } /* CFI mode */
639 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
640 /* Apply jedec specific fixups */
641 cfi_fixup(mtd, jedec_fixup_table);
642 }
643 /* Apply generic fixups */
644 cfi_fixup(mtd, fixup_table);
645
646 for (i=0; i< cfi->numchips; i++) {
647 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
648 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
649 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
6534e680
BH		 650 /*
651 * First calculate the timeout max according to timeout field
652 * of struct cfi_ident that probed from chip's CFI aera, if
653 * available. Specify a minimum of 2000us, in case the CFI data
654 * is wrong.
655 */
656 if (cfi->cfiq->BufWriteTimeoutTyp &&
657 cfi->cfiq->BufWriteTimeoutMax)
658 cfi->chips[i].buffer_write_time_max =
659 1 << (cfi->cfiq->BufWriteTimeoutTyp +
660 cfi->cfiq->BufWriteTimeoutMax);
661 else
662 cfi->chips[i].buffer_write_time_max = 0;
663
664 cfi->chips[i].buffer_write_time_max =
665 max(cfi->chips[i].buffer_write_time_max, 2000);
666
83d48091
VS		 667 cfi->chips[i].ref_point_counter = 0;
668 init_waitqueue_head(&(cfi->chips[i].wq));
1f948b43
TG		 669 }
670
1da177e4 671 map->fldrv = &cfi_amdstd_chipdrv;
1f948b43 672
1da177e4
LT		 673 return cfi_amdstd_setup(mtd);
674}
80461128 675struct mtd_info *cfi_cmdset_0006(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
1e804cec 676struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
83ea4ef2 677EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
80461128 678EXPORT_SYMBOL_GPL(cfi_cmdset_0006);
1e804cec 679EXPORT_SYMBOL_GPL(cfi_cmdset_0701);
1da177e4
LT		 680
681static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
682{
683 struct map_info *map = mtd->priv;
684 struct cfi_private *cfi = map->fldrv_priv;
685 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
686 unsigned long offset = 0;
687 int i,j;
688
1f948b43 689 printk(KERN_NOTICE "number of %s chips: %d\n",
1da177e4 690 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
1f948b43 691 /* Select the correct geometry setup */
1da177e4
LT		 692 mtd->size = devsize * cfi->numchips;
693
694 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
6da2ec56
KC		 695 mtd->eraseregions = kmalloc_array(mtd->numeraseregions,
696 sizeof(struct mtd_erase_region_info),
697 GFP_KERNEL);
5c8b1fbb 698 if (!mtd->eraseregions)
1da177e4 699 goto setup_err;
1f948b43 700
1da177e4
LT		 701 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
702 unsigned long ernum, ersize;
703 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
704 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
1f948b43 705
1da177e4
LT		 706 if (mtd->erasesize < ersize) {
707 mtd->erasesize = ersize;
708 }
709 for (j=0; j<cfi->numchips; j++) {
710 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
711 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
712 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
713 }
714 offset += (ersize * ernum);
715 }
716 if (offset != devsize) {
717 /* Argh */
718 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
719 goto setup_err;
720 }
1da177e4 721
1da177e4 722 __module_get(THIS_MODULE);
eafe1311 723 register_reboot_notifier(&mtd->reboot_notifier);
1da177e4
LT		 724 return mtd;
725
726 setup_err:
17fabf15
JS		 727 kfree(mtd->eraseregions);
728 kfree(mtd);
1da177e4
LT		 729 kfree(cfi->cmdset_priv);
730 kfree(cfi->cfiq);
731 return NULL;
732}
733
734/*
735 * Return true if the chip is ready.
736 *
737 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
738 * non-suspended sector) and is indicated by no toggle bits toggling.
739 *
740 * Note that anything more complicated than checking if no bits are toggling
741 * (including checking DQ5 for an error status) is tricky to get working
25985edc
LDM		 742 * correctly and is therefore not done (particularly with interleaved chips
743 * as each chip must be checked independently of the others).
1da177e4 744 */
02b15e34 745static int __xipram chip_ready(struct map_info *map, unsigned long addr)
1da177e4
LT		 746{
747 map_word d, t;
748
749 d = map_read(map, addr);
750 t = map_read(map, addr);
751
752 return map_word_equal(map, d, t);
753}
754
fb4a90bf
EB		 755/*
756 * Return true if the chip is ready and has the correct value.
757 *
758 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
759 * non-suspended sector) and it is indicated by no bits toggling.
760 *
761 * Error are indicated by toggling bits or bits held with the wrong value,
762 * or with bits toggling.
763 *
764 * Note that anything more complicated than checking if no bits are toggling
765 * (including checking DQ5 for an error status) is tricky to get working
25985edc
LDM		 766 * correctly and is therefore not done (particularly with interleaved chips
767 * as each chip must be checked independently of the others).
fb4a90bf
EB		 768 *
769 */
02b15e34 770static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
fb4a90bf
EB		 771{
772 map_word oldd, curd;
773
774 oldd = map_read(map, addr);
775 curd = map_read(map, addr);
776
1f948b43 777 return map_word_equal(map, oldd, curd) &&
fb4a90bf
EB		 778 map_word_equal(map, curd, expected);
779}
780
1da177e4
LT		 781static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
782{
783 DECLARE_WAITQUEUE(wait, current);
784 struct cfi_private *cfi = map->fldrv_priv;
785 unsigned long timeo;
786 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
787
788 resettime:
789 timeo = jiffies + HZ;
790 retry:
791 switch (chip->state) {
792
793 case FL_STATUS:
794 for (;;) {
795 if (chip_ready(map, adr))
796 break;
797
798 if (time_after(jiffies, timeo)) {
799 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
1da177e4
LT		 800 return -EIO;
801 }
c4e77376 802 mutex_unlock(&chip->mutex);
1da177e4 803 cfi_udelay(1);
c4e77376 804 mutex_lock(&chip->mutex);
1da177e4
LT		 805 /* Someone else might have been playing with it. */
806 goto retry;
807 }
1f948b43 808
1da177e4
LT		 809 case FL_READY:
810 case FL_CFI_QUERY:
811 case FL_JEDEC_QUERY:
812 return 0;
813
814 case FL_ERASING:
2695eab9
JT		 815 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
816 !(mode == FL_READY || mode == FL_POINT ||
817 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
1da177e4
LT		 818 goto sleep;
819
7b70eb14
JT		 820 /* Do not allow suspend iff read/write to EB address */
821 if ((adr & chip->in_progress_block_mask) ==
822 chip->in_progress_block_addr)
823 goto sleep;
1da177e4
LT		 824
825 /* Erase suspend */
826 /* It's harmless to issue the Erase-Suspend and Erase-Resume
827 * commands when the erase algorithm isn't in progress. */
828 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
829 chip->oldstate = FL_ERASING;
830 chip->state = FL_ERASE_SUSPENDING;
831 chip->erase_suspended = 1;
832 for (;;) {
833 if (chip_ready(map, adr))
834 break;
835
836 if (time_after(jiffies, timeo)) {
837 /* Should have suspended the erase by now.
838 * Send an Erase-Resume command as either
839 * there was an error (so leave the erase
840 * routine to recover from it) or we trying to
841 * use the erase-in-progress sector. */
100f2341 842 put_chip(map, chip, adr);
1da177e4
LT		 843 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
844 return -EIO;
845 }
1f948b43 846
c4e77376 847 mutex_unlock(&chip->mutex);
1da177e4 848 cfi_udelay(1);
c4e77376 849 mutex_lock(&chip->mutex);
1da177e4
LT		 850 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
851 So we can just loop here. */
852 }
853 chip->state = FL_READY;
854 return 0;
855
02b15e34
TP		 856 case FL_XIP_WHILE_ERASING:
857 if (mode != FL_READY && mode != FL_POINT &&
858 (!cfip || !(cfip->EraseSuspend&2)))
859 goto sleep;
860 chip->oldstate = chip->state;
861 chip->state = FL_READY;
862 return 0;
863
eafe1311
KC		 864 case FL_SHUTDOWN:
865 /* The machine is rebooting */
866 return -EIO;
867
1da177e4
LT		 868 case FL_POINT:
869 /* Only if there's no operation suspended... */
870 if (mode == FL_READY && chip->oldstate == FL_READY)
871 return 0;
872
873 default:
874 sleep:
875 set_current_state(TASK_UNINTERRUPTIBLE);
876 add_wait_queue(&chip->wq, &wait);
c4e77376 877 mutex_unlock(&chip->mutex);
1da177e4
LT		 878 schedule();
879 remove_wait_queue(&chip->wq, &wait);
c4e77376 880 mutex_lock(&chip->mutex);
1da177e4
LT		 881 goto resettime;
882 }
883}
884
885
886static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
887{
888 struct cfi_private *cfi = map->fldrv_priv;
889
890 switch(chip->oldstate) {
891 case FL_ERASING:
42096288
GF		 892 cfi_fixup_m29ew_erase_suspend(map,
893 chip->in_progress_block_addr);
08968041 894 map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr);
42096288 895 cfi_fixup_m29ew_delay_after_resume(cfi);
1da177e4
LT		 896 chip->oldstate = FL_READY;
897 chip->state = FL_ERASING;
898 break;
899
02b15e34
TP		 900 case FL_XIP_WHILE_ERASING:
901 chip->state = chip->oldstate;
902 chip->oldstate = FL_READY;
903 break;
904
1da177e4
LT		 905 case FL_READY:
906 case FL_STATUS:
1da177e4
LT		 907 break;
908 default:
909 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
910 }
911 wake_up(&chip->wq);
912}
913
02b15e34
TP		 914#ifdef CONFIG_MTD_XIP
915
916/*
917 * No interrupt what so ever can be serviced while the flash isn't in array
918 * mode. This is ensured by the xip_disable() and xip_enable() functions
919 * enclosing any code path where the flash is known not to be in array mode.
920 * And within a XIP disabled code path, only functions marked with __xipram
921 * may be called and nothing else (it's a good thing to inspect generated
922 * assembly to make sure inline functions were actually inlined and that gcc
923 * didn't emit calls to its own support functions). Also configuring MTD CFI
924 * support to a single buswidth and a single interleave is also recommended.
925 */
f8eb321b 926
02b15e34
TP		 927static void xip_disable(struct map_info *map, struct flchip *chip,
928 unsigned long adr)
929{
930 /* TODO: chips with no XIP use should ignore and return */
931 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
932 local_irq_disable();
933}
934
935static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
936 unsigned long adr)
937{
938 struct cfi_private *cfi = map->fldrv_priv;
939
940 if (chip->state != FL_POINT && chip->state != FL_READY) {
941 map_write(map, CMD(0xf0), adr);
942 chip->state = FL_READY;
943 }
944 (void) map_read(map, adr);
97f927a4 945 xip_iprefetch();
02b15e34
TP		 946 local_irq_enable();
947}
948
949/*
950 * When a delay is required for the flash operation to complete, the
951 * xip_udelay() function is polling for both the given timeout and pending
952 * (but still masked) hardware interrupts. Whenever there is an interrupt
1f948b43 953 * pending then the flash erase operation is suspended, array mode restored
02b15e34
TP		 954 * and interrupts unmasked. Task scheduling might also happen at that
955 * point. The CPU eventually returns from the interrupt or the call to
956 * schedule() and the suspended flash operation is resumed for the remaining
957 * of the delay period.
958 *
959 * Warning: this function _will_ fool interrupt latency tracing tools.
960 */
961
962static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
963 unsigned long adr, int usec)
964{
965 struct cfi_private *cfi = map->fldrv_priv;
966 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
967 map_word status, OK = CMD(0x80);
968 unsigned long suspended, start = xip_currtime();
969 flstate_t oldstate;
970
971 do {
972 cpu_relax();
973 if (xip_irqpending() && extp &&
974 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
975 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
976 /*
1f948b43
TG		 977 * Let's suspend the erase operation when supported.
978 * Note that we currently don't try to suspend
979 * interleaved chips if there is already another
02b15e34
TP		 980 * operation suspended (imagine what happens
981 * when one chip was already done with the current
982 * operation while another chip suspended it, then
983 * we resume the whole thing at once). Yes, it
984 * can happen!
985 */
986 map_write(map, CMD(0xb0), adr);
987 usec -= xip_elapsed_since(start);
988 suspended = xip_currtime();
989 do {
990 if (xip_elapsed_since(suspended) > 100000) {
991 /*
992 * The chip doesn't want to suspend
993 * after waiting for 100 msecs.
994 * This is a critical error but there
995 * is not much we can do here.
996 */
997 return;
998 }
999 status = map_read(map, adr);
1000 } while (!map_word_andequal(map, status, OK, OK));
1001
1002 /* Suspend succeeded */
1003 oldstate = chip->state;
1004 if (!map_word_bitsset(map, status, CMD(0x40)))
1005 break;
1006 chip->state = FL_XIP_WHILE_ERASING;
1007 chip->erase_suspended = 1;
1008 map_write(map, CMD(0xf0), adr);
1009 (void) map_read(map, adr);
ca5c23c3 1010 xip_iprefetch();
02b15e34 1011 local_irq_enable();
c4e77376 1012 mutex_unlock(&chip->mutex);
ca5c23c3 1013 xip_iprefetch();
02b15e34
TP		 1014 cond_resched();
1015
1016 /*
1017 * We're back. However someone else might have
1018 * decided to go write to the chip if we are in
1019 * a suspended erase state. If so let's wait
1020 * until it's done.
1021 */
c4e77376 1022 mutex_lock(&chip->mutex);
02b15e34
TP		 1023 while (chip->state != FL_XIP_WHILE_ERASING) {
1024 DECLARE_WAITQUEUE(wait, current);
1025 set_current_state(TASK_UNINTERRUPTIBLE);
1026 add_wait_queue(&chip->wq, &wait);
c4e77376 1027 mutex_unlock(&chip->mutex);
02b15e34
TP		 1028 schedule();
1029 remove_wait_queue(&chip->wq, &wait);
c4e77376 1030 mutex_lock(&chip->mutex);
02b15e34
TP		 1031 }
1032 /* Disallow XIP again */
1033 local_irq_disable();
1034
42096288
GF		 1035 /* Correct Erase Suspend Hangups for M29EW */
1036 cfi_fixup_m29ew_erase_suspend(map, adr);
02b15e34 1037 /* Resume the write or erase operation */
08968041 1038 map_write(map, cfi->sector_erase_cmd, adr);
02b15e34
TP		 1039 chip->state = oldstate;
1040 start = xip_currtime();
1041 } else if (usec >= 1000000/HZ) {
1042 /*
1043 * Try to save on CPU power when waiting delay
1044 * is at least a system timer tick period.
1045 * No need to be extremely accurate here.
1046 */
1047 xip_cpu_idle();
1048 }
1049 status = map_read(map, adr);
1050 } while (!map_word_andequal(map, status, OK, OK)
1051 && xip_elapsed_since(start) < usec);
1052}
1053
1054#define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
1055
1056/*
1057 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
1058 * the flash is actively programming or erasing since we have to poll for
1059 * the operation to complete anyway. We can't do that in a generic way with
1060 * a XIP setup so do it before the actual flash operation in this case
1061 * and stub it out from INVALIDATE_CACHE_UDELAY.
1062 */
1063#define XIP_INVAL_CACHED_RANGE(map, from, size) \
1064 INVALIDATE_CACHED_RANGE(map, from, size)
1065
1066#define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1067 UDELAY(map, chip, adr, usec)
1068
1069/*
1070 * Extra notes:
1071 *
1072 * Activating this XIP support changes the way the code works a bit. For
1073 * example the code to suspend the current process when concurrent access
1074 * happens is never executed because xip_udelay() will always return with the
1075 * same chip state as it was entered with. This is why there is no care for
1076 * the presence of add_wait_queue() or schedule() calls from within a couple
1077 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
1078 * The queueing and scheduling are always happening within xip_udelay().
1079 *
1080 * Similarly, get_chip() and put_chip() just happen to always be executed
1081 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
1082 * is in array mode, therefore never executing many cases therein and not
1083 * causing any problem with XIP.
1084 */
1085
1086#else
1087
1088#define xip_disable(map, chip, adr)
1089#define xip_enable(map, chip, adr)
1090#define XIP_INVAL_CACHED_RANGE(x...)
1091
1092#define UDELAY(map, chip, adr, usec) \
1093do { \
c4e77376 1094 mutex_unlock(&chip->mutex); \
02b15e34 1095 cfi_udelay(usec); \
c4e77376 1096 mutex_lock(&chip->mutex); \
02b15e34
TP		 1097} while (0)
1098
1099#define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1100do { \
c4e77376 1101 mutex_unlock(&chip->mutex); \
02b15e34
TP		 1102 INVALIDATE_CACHED_RANGE(map, adr, len); \
1103 cfi_udelay(usec); \
c4e77376 1104 mutex_lock(&chip->mutex); \
02b15e34
TP		 1105} while (0)
1106
1107#endif
1da177e4
LT		 1108
1109static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
1110{
1111 unsigned long cmd_addr;
1112 struct cfi_private *cfi = map->fldrv_priv;
1113 int ret;
1114
1115 adr += chip->start;
1116
1f948b43
TG		 1117 /* Ensure cmd read/writes are aligned. */
1118 cmd_addr = adr & ~(map_bankwidth(map)-1);
1da177e4 1119
c4e77376 1120 mutex_lock(&chip->mutex);
1da177e4
LT		 1121 ret = get_chip(map, chip, cmd_addr, FL_READY);
1122 if (ret) {
c4e77376 1123 mutex_unlock(&chip->mutex);
1da177e4
LT		 1124 return ret;
1125 }
1126
1127 if (chip->state != FL_POINT && chip->state != FL_READY) {
1128 map_write(map, CMD(0xf0), cmd_addr);
1129 chip->state = FL_READY;
1130 }
1131
1132 map_copy_from(map, buf, adr, len);
1133
1134 put_chip(map, chip, cmd_addr);
1135
c4e77376 1136 mutex_unlock(&chip->mutex);
1da177e4
LT		 1137 return 0;
1138}
1139
1140
1141static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1142{
1143 struct map_info *map = mtd->priv;
1144 struct cfi_private *cfi = map->fldrv_priv;
1145 unsigned long ofs;
1146 int chipnum;
1147 int ret = 0;
1148
1149 /* ofs: offset within the first chip that the first read should start */
1da177e4
LT		 1150 chipnum = (from >> cfi->chipshift);
1151 ofs = from - (chipnum << cfi->chipshift);
1152
1da177e4
LT		 1153 while (len) {
1154 unsigned long thislen;
1155
1156 if (chipnum >= cfi->numchips)
1157 break;
1158
1159 if ((len + ofs -1) >> cfi->chipshift)
1160 thislen = (1<<cfi->chipshift) - ofs;
1161 else
1162 thislen = len;
1163
1164 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1165 if (ret)
1166 break;
1167
1168 *retlen += thislen;
1169 len -= thislen;
1170 buf += thislen;
1171
1172 ofs = 0;
1173 chipnum++;
1174 }
1175 return ret;
1176}
1177
dc7e9ecd 1178typedef int (*otp_op_t)(struct map_info *map, struct flchip *chip,
4f5cb243 1179 loff_t adr, size_t len, u_char *buf, size_t grouplen);
1da177e4 1180
feb86779
CR		 1181static inline void otp_enter(struct map_info *map, struct flchip *chip,
1182 loff_t adr, size_t len)
1183{
1184 struct cfi_private *cfi = map->fldrv_priv;
1185
1186 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1187 cfi->device_type, NULL);
1188 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1189 cfi->device_type, NULL);
1190 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi,
1191 cfi->device_type, NULL);
1192
1193 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1194}
1195
1196static inline void otp_exit(struct map_info *map, struct flchip *chip,
1197 loff_t adr, size_t len)
1198{
1199 struct cfi_private *cfi = map->fldrv_priv;
1200
1201 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1202 cfi->device_type, NULL);
1203 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1204 cfi->device_type, NULL);
1205 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi,
1206 cfi->device_type, NULL);
1207 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi,
1208 cfi->device_type, NULL);
1209
1210 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1211}
1212
4f5cb243
CR		 1213static inline int do_read_secsi_onechip(struct map_info *map,
1214 struct flchip *chip, loff_t adr,
1215 size_t len, u_char *buf,
1216 size_t grouplen)
1da177e4
LT		 1217{
1218 DECLARE_WAITQUEUE(wait, current);
1219 unsigned long timeo = jiffies + HZ;
1da177e4
LT		 1220
1221 retry:
c4e77376 1222 mutex_lock(&chip->mutex);
1da177e4
LT		 1223
1224 if (chip->state != FL_READY){
1da177e4
LT		 1225 set_current_state(TASK_UNINTERRUPTIBLE);
1226 add_wait_queue(&chip->wq, &wait);
1f948b43 1227
c4e77376 1228 mutex_unlock(&chip->mutex);
1da177e4
LT		 1229
1230 schedule();
1231 remove_wait_queue(&chip->wq, &wait);
1da177e4
LT		 1232 timeo = jiffies + HZ;
1233
1234 goto retry;
1f948b43 1235 }
1da177e4
LT		 1236
1237 adr += chip->start;
1238
1239 chip->state = FL_READY;
1240
feb86779 1241 otp_enter(map, chip, adr, len);
1da177e4 1242 map_copy_from(map, buf, adr, len);
feb86779 1243 otp_exit(map, chip, adr, len);
1f948b43 1244
1da177e4 1245 wake_up(&chip->wq);
c4e77376 1246 mutex_unlock(&chip->mutex);
1da177e4
LT		 1247
1248 return 0;
1249}
1250
1251static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1252{
1253 struct map_info *map = mtd->priv;
1254 struct cfi_private *cfi = map->fldrv_priv;
1255 unsigned long ofs;
1256 int chipnum;
1257 int ret = 0;
1258
1da177e4 1259 /* ofs: offset within the first chip that the first read should start */
1da177e4
LT		 1260 /* 8 secsi bytes per chip */
1261 chipnum=from>>3;
1262 ofs=from & 7;
1263
1da177e4
LT		 1264 while (len) {
1265 unsigned long thislen;
1266
1267 if (chipnum >= cfi->numchips)
1268 break;
1269
1270 if ((len + ofs -1) >> 3)
1271 thislen = (1<<3) - ofs;
1272 else
1273 thislen = len;
1274
4f5cb243
CR		 1275 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs,
1276 thislen, buf, 0);
1da177e4
LT		 1277 if (ret)
1278 break;
1279
1280 *retlen += thislen;
1281 len -= thislen;
1282 buf += thislen;
1283
1284 ofs = 0;
1285 chipnum++;
1286 }
1287 return ret;
1288}
1289
af744750
CR		 1290static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1291 unsigned long adr, map_word datum,
1292 int mode);
1293
1294static int do_otp_write(struct map_info *map, struct flchip *chip, loff_t adr,
4f5cb243 1295 size_t len, u_char *buf, size_t grouplen)
af744750
CR		 1296{
1297 int ret;
1298 while (len) {
1299 unsigned long bus_ofs = adr & ~(map_bankwidth(map)-1);
1300 int gap = adr - bus_ofs;
1301 int n = min_t(int, len, map_bankwidth(map) - gap);
636fdbf8 1302 map_word datum = map_word_ff(map);
af744750
CR		 1303
1304 if (n != map_bankwidth(map)) {
1305 /* partial write of a word, load old contents */
1306 otp_enter(map, chip, bus_ofs, map_bankwidth(map));
1307 datum = map_read(map, bus_ofs);
1308 otp_exit(map, chip, bus_ofs, map_bankwidth(map));
1309 }
1310
1311 datum = map_word_load_partial(map, datum, buf, gap, n);
1312 ret = do_write_oneword(map, chip, bus_ofs, datum, FL_OTP_WRITE);
1313 if (ret)
1314 return ret;
1315
1316 adr += n;
1317 buf += n;
1318 len -= n;
1319 }
1320
1321 return 0;
1322}
1323
4f5cb243
CR		 1324static int do_otp_lock(struct map_info *map, struct flchip *chip, loff_t adr,
1325 size_t len, u_char *buf, size_t grouplen)
1326{
1327 struct cfi_private *cfi = map->fldrv_priv;
1328 uint8_t lockreg;
1329 unsigned long timeo;
1330 int ret;
1331
1332 /* make sure area matches group boundaries */
1333 if ((adr != 0) || (len != grouplen))
1334 return -EINVAL;
1335
1336 mutex_lock(&chip->mutex);
1337 ret = get_chip(map, chip, chip->start, FL_LOCKING);
1338 if (ret) {
1339 mutex_unlock(&chip->mutex);
1340 return ret;
1341 }
1342 chip->state = FL_LOCKING;
1343
1344 /* Enter lock register command */
1345 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1346 cfi->device_type, NULL);
1347 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1348 cfi->device_type, NULL);
1349 cfi_send_gen_cmd(0x40, cfi->addr_unlock1, chip->start, map, cfi,
1350 cfi->device_type, NULL);
1351
1352 /* read lock register */
1353 lockreg = cfi_read_query(map, 0);
1354
1355 /* set bit 0 to protect extended memory block */
1356 lockreg &= ~0x01;
1357
1358 /* set bit 0 to protect extended memory block */
1359 /* write lock register */
1360 map_write(map, CMD(0xA0), chip->start);
1361 map_write(map, CMD(lockreg), chip->start);
1362
1363 /* wait for chip to become ready */
1364 timeo = jiffies + msecs_to_jiffies(2);
1365 for (;;) {
1366 if (chip_ready(map, adr))
1367 break;
1368
1369 if (time_after(jiffies, timeo)) {
1370 pr_err("Waiting for chip to be ready timed out.\n");
1371 ret = -EIO;
1372 break;
1373 }
1374 UDELAY(map, chip, 0, 1);
1375 }
1376
1377 /* exit protection commands */
1378 map_write(map, CMD(0x90), chip->start);
1379 map_write(map, CMD(0x00), chip->start);
1380
1381 chip->state = FL_READY;
1382 put_chip(map, chip, chip->start);
1383 mutex_unlock(&chip->mutex);
1384
1385 return ret;
1386}
1387
dc7e9ecd
CR		 1388static int cfi_amdstd_otp_walk(struct mtd_info *mtd, loff_t from, size_t len,
1389 size_t *retlen, u_char *buf,
1390 otp_op_t action, int user_regs)
1391{
1392 struct map_info *map = mtd->priv;
1393 struct cfi_private *cfi = map->fldrv_priv;
1394 int ofs_factor = cfi->interleave * cfi->device_type;
1395 unsigned long base;
1396 int chipnum;
1397 struct flchip *chip;
1398 uint8_t otp, lockreg;
1399 int ret;
1400
1401 size_t user_size, factory_size, otpsize;
1402 loff_t user_offset, factory_offset, otpoffset;
1403 int user_locked = 0, otplocked;
1404
1405 *retlen = 0;
1406
1407 for (chipnum = 0; chipnum < cfi->numchips; chipnum++) {
1408 chip = &cfi->chips[chipnum];
1409 factory_size = 0;
1410 user_size = 0;
1411
1412 /* Micron M29EW family */
1413 if (is_m29ew(cfi)) {
1414 base = chip->start;
1415
1416 /* check whether secsi area is factory locked
1417 or user lockable */
1418 mutex_lock(&chip->mutex);
1419 ret = get_chip(map, chip, base, FL_CFI_QUERY);
1420 if (ret) {
1421 mutex_unlock(&chip->mutex);
1422 return ret;
1423 }
1424 cfi_qry_mode_on(base, map, cfi);
1425 otp = cfi_read_query(map, base + 0x3 * ofs_factor);
1426 cfi_qry_mode_off(base, map, cfi);
1427 put_chip(map, chip, base);
1428 mutex_unlock(&chip->mutex);
1429
1430 if (otp & 0x80) {
1431 /* factory locked */
1432 factory_offset = 0;
1433 factory_size = 0x100;
1434 } else {
1435 /* customer lockable */
1436 user_offset = 0;
1437 user_size = 0x100;
1438
1439 mutex_lock(&chip->mutex);
1440 ret = get_chip(map, chip, base, FL_LOCKING);
5d20bad1
BN		 1441 if (ret) {
1442 mutex_unlock(&chip->mutex);
1443 return ret;
1444 }
dc7e9ecd
CR		 1445
1446 /* Enter lock register command */
1447 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1,
1448 chip->start, map, cfi,
1449 cfi->device_type, NULL);
1450 cfi_send_gen_cmd(0x55, cfi->addr_unlock2,
1451 chip->start, map, cfi,
1452 cfi->device_type, NULL);
1453 cfi_send_gen_cmd(0x40, cfi->addr_unlock1,
1454 chip->start, map, cfi,
1455 cfi->device_type, NULL);
1456 /* read lock register */
1457 lockreg = cfi_read_query(map, 0);
1458 /* exit protection commands */
1459 map_write(map, CMD(0x90), chip->start);
1460 map_write(map, CMD(0x00), chip->start);
1461 put_chip(map, chip, chip->start);
1462 mutex_unlock(&chip->mutex);
1463
1464 user_locked = ((lockreg & 0x01) == 0x00);
1465 }
1466 }
1467
1468 otpsize = user_regs ? user_size : factory_size;
1469 if (!otpsize)
1470 continue;
1471 otpoffset = user_regs ? user_offset : factory_offset;
1472 otplocked = user_regs ? user_locked : 1;
1473
1474 if (!action) {
1475 /* return otpinfo */
1476 struct otp_info *otpinfo;
1477 len -= sizeof(*otpinfo);
1478 if (len <= 0)
1479 return -ENOSPC;
1480 otpinfo = (struct otp_info *)buf;
1481 otpinfo->start = from;
1482 otpinfo->length = otpsize;
1483 otpinfo->locked = otplocked;
1484 buf += sizeof(*otpinfo);
1485 *retlen += sizeof(*otpinfo);
1486 from += otpsize;
1487 } else if ((from < otpsize) && (len > 0)) {
1488 size_t size;
1489 size = (len < otpsize - from) ? len : otpsize - from;
4f5cb243
CR		 1490 ret = action(map, chip, otpoffset + from, size, buf,
1491 otpsize);
dc7e9ecd
CR		 1492 if (ret < 0)
1493 return ret;
1494
1495 buf += size;
1496 len -= size;
1497 *retlen += size;
1498 from = 0;
1499 } else {
1500 from -= otpsize;
1501 }
1502 }
1503 return 0;
1504}
1505
1506static int cfi_amdstd_get_fact_prot_info(struct mtd_info *mtd, size_t len,
1507 size_t *retlen, struct otp_info *buf)
1508{
1509 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1510 NULL, 0);
1511}
1512
1513static int cfi_amdstd_get_user_prot_info(struct mtd_info *mtd, size_t len,
1514 size_t *retlen, struct otp_info *buf)
1515{
1516 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1517 NULL, 1);
1518}
1519
1520static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from,
1521 size_t len, size_t *retlen,
1522 u_char *buf)
1523{
1524 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1525 buf, do_read_secsi_onechip, 0);
1526}
1527
1528static int cfi_amdstd_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
1529 size_t len, size_t *retlen,
1530 u_char *buf)
1531{
1532 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1533 buf, do_read_secsi_onechip, 1);
1534}
1da177e4 1535
af744750
CR		 1536static int cfi_amdstd_write_user_prot_reg(struct mtd_info *mtd, loff_t from,
1537 size_t len, size_t *retlen,
1538 u_char *buf)
1539{
1540 return cfi_amdstd_otp_walk(mtd, from, len, retlen, buf,
1541 do_otp_write, 1);
1542}
1543
4f5cb243
CR		 1544static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
1545 size_t len)
1546{
1547 size_t retlen;
1548 return cfi_amdstd_otp_walk(mtd, from, len, &retlen, NULL,
1549 do_otp_lock, 1);
1550}
1551
af744750
CR		 1552static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1553 unsigned long adr, map_word datum,
1554 int mode)
1da177e4
LT		 1555{
1556 struct cfi_private *cfi = map->fldrv_priv;
1557 unsigned long timeo = jiffies + HZ;
1558 /*
1559 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
1560 * have a max write time of a few hundreds usec). However, we should
1561 * use the maximum timeout value given by the chip at probe time
1562 * instead. Unfortunately, struct flchip does have a field for
1563 * maximum timeout, only for typical which can be far too short
1564 * depending of the conditions. The ' + 1' is to avoid having a
1565 * timeout of 0 jiffies if HZ is smaller than 1000.
1566 */
ea092fb3 1567 unsigned long uWriteTimeout = (HZ / 1000) + 1;
1da177e4
LT		 1568 int ret = 0;
1569 map_word oldd;
1570 int retry_cnt = 0;
1571
1572 adr += chip->start;
1573
c4e77376 1574 mutex_lock(&chip->mutex);
af744750 1575 ret = get_chip(map, chip, adr, mode);
1da177e4 1576 if (ret) {
c4e77376 1577 mutex_unlock(&chip->mutex);
1da177e4
LT		 1578 return ret;
1579 }
1580
289c0522 1581 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
ea092fb3 1582 __func__, adr, datum.x[0]);
1da177e4 1583
af744750
CR		 1584 if (mode == FL_OTP_WRITE)
1585 otp_enter(map, chip, adr, map_bankwidth(map));
1586
1da177e4
LT		 1587 /*
1588 * Check for a NOP for the case when the datum to write is already
1589 * present - it saves time and works around buggy chips that corrupt
1590 * data at other locations when 0xff is written to a location that
1591 * already contains 0xff.
1592 */
1593 oldd = map_read(map, adr);
1594 if (map_word_equal(map, oldd, datum)) {
289c0522 1595 pr_debug("MTD %s(): NOP\n",
1da177e4
LT		 1596 __func__);
1597 goto op_done;
1598 }
1599
02b15e34 1600 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1da177e4 1601 ENABLE_VPP(map);
02b15e34 1602 xip_disable(map, chip, adr);
af744750 1603
1da177e4
LT		 1604 retry:
1605 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1606 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1607 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1608 map_write(map, datum, adr);
af744750 1609 chip->state = mode;
1da177e4 1610
02b15e34
TP		 1611 INVALIDATE_CACHE_UDELAY(map, chip,
1612 adr, map_bankwidth(map),
1613 chip->word_write_time);
1da177e4
LT		 1614
1615 /* See comment above for timeout value. */
1f948b43 1616 timeo = jiffies + uWriteTimeout;
1da177e4 1617 for (;;) {
af744750 1618 if (chip->state != mode) {
1da177e4
LT		 1619 /* Someone's suspended the write. Sleep */
1620 DECLARE_WAITQUEUE(wait, current);
1621
1622 set_current_state(TASK_UNINTERRUPTIBLE);
1623 add_wait_queue(&chip->wq, &wait);
c4e77376 1624 mutex_unlock(&chip->mutex);
1da177e4
LT		 1625 schedule();
1626 remove_wait_queue(&chip->wq, &wait);
1627 timeo = jiffies + (HZ / 2); /* FIXME */
c4e77376 1628 mutex_lock(&chip->mutex);
1da177e4
LT		 1629 continue;
1630 }
1631
b95f9609 1632 if (time_after(jiffies, timeo) && !chip_ready(map, adr)){
02b15e34 1633 xip_enable(map, chip, adr);
fb4a90bf 1634 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
02b15e34 1635 xip_disable(map, chip, adr);
b95f9609 1636 break;
fb4a90bf 1637 }
1da177e4 1638
b95f9609
KB		 1639 if (chip_ready(map, adr))
1640 break;
1641
1da177e4 1642 /* Latency issues. Drop the lock, wait a while and retry */
02b15e34 1643 UDELAY(map, chip, adr, 1);
1da177e4 1644 }
fb4a90bf
EB		 1645 /* Did we succeed? */
1646 if (!chip_good(map, adr, datum)) {
1647 /* reset on all failures. */
ea092fb3 1648 map_write(map, CMD(0xF0), chip->start);
fb4a90bf 1649 /* FIXME - should have reset delay before continuing */
1da177e4 1650
85a82e28 1651 if (++retry_cnt <= MAX_RETRIES)
fb4a90bf 1652 goto retry;
1da177e4 1653
fb4a90bf
EB		 1654 ret = -EIO;
1655 }
02b15e34 1656 xip_enable(map, chip, adr);
1da177e4 1657 op_done:
af744750
CR		 1658 if (mode == FL_OTP_WRITE)
1659 otp_exit(map, chip, adr, map_bankwidth(map));
1da177e4 1660 chip->state = FL_READY;
e7d9377e 1661 DISABLE_VPP(map);
1da177e4 1662 put_chip(map, chip, adr);
c4e77376 1663 mutex_unlock(&chip->mutex);
1da177e4
LT		 1664
1665 return ret;
1666}
1667
1668
1669static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1670 size_t *retlen, const u_char *buf)
1671{
1672 struct map_info *map = mtd->priv;
1673 struct cfi_private *cfi = map->fldrv_priv;
1674 int ret = 0;
1675 int chipnum;
1676 unsigned long ofs, chipstart;
1677 DECLARE_WAITQUEUE(wait, current);
1678
1da177e4
LT		 1679 chipnum = to >> cfi->chipshift;
1680 ofs = to - (chipnum << cfi->chipshift);
1681 chipstart = cfi->chips[chipnum].start;
1682
1683 /* If it's not bus-aligned, do the first byte write */
1684 if (ofs & (map_bankwidth(map)-1)) {
1685 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1686 int i = ofs - bus_ofs;
1687 int n = 0;
1688 map_word tmp_buf;
1689
1690 retry:
c4e77376 1691 mutex_lock(&cfi->chips[chipnum].mutex);
1da177e4
LT		 1692
1693 if (cfi->chips[chipnum].state != FL_READY) {
1da177e4
LT		 1694 set_current_state(TASK_UNINTERRUPTIBLE);
1695 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1696
c4e77376 1697 mutex_unlock(&cfi->chips[chipnum].mutex);
1da177e4
LT		 1698
1699 schedule();
1700 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1da177e4
LT		 1701 goto retry;
1702 }
1703
1704 /* Load 'tmp_buf' with old contents of flash */
1705 tmp_buf = map_read(map, bus_ofs+chipstart);
1706
c4e77376 1707 mutex_unlock(&cfi->chips[chipnum].mutex);
1da177e4
LT		 1708
1709 /* Number of bytes to copy from buffer */
1710 n = min_t(int, len, map_bankwidth(map)-i);
1f948b43 1711
1da177e4
LT		 1712 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1713
1f948b43 1714 ret = do_write_oneword(map, &cfi->chips[chipnum],
af744750 1715 bus_ofs, tmp_buf, FL_WRITING);
1f948b43 1716 if (ret)
1da177e4 1717 return ret;
1f948b43 1718
1da177e4
LT		 1719 ofs += n;
1720 buf += n;
1721 (*retlen) += n;
1722 len -= n;
1723
1724 if (ofs >> cfi->chipshift) {
1f948b43 1725 chipnum ++;
1da177e4
LT		 1726 ofs = 0;
1727 if (chipnum == cfi->numchips)
1728 return 0;
1729 }
1730 }
1f948b43 1731
1da177e4
LT		 1732 /* We are now aligned, write as much as possible */
1733 while(len >= map_bankwidth(map)) {
1734 map_word datum;
1735
1736 datum = map_word_load(map, buf);
1737
1738 ret = do_write_oneword(map, &cfi->chips[chipnum],
af744750 1739 ofs, datum, FL_WRITING);
1da177e4
LT		 1740 if (ret)
1741 return ret;
1742
1743 ofs += map_bankwidth(map);
1744 buf += map_bankwidth(map);
1745 (*retlen) += map_bankwidth(map);
1746 len -= map_bankwidth(map);
1747
1748 if (ofs >> cfi->chipshift) {
1f948b43 1749 chipnum ++;
1da177e4
LT		 1750 ofs = 0;
1751 if (chipnum == cfi->numchips)
1752 return 0;
1753 chipstart = cfi->chips[chipnum].start;
1754 }
1755 }
1756
1757 /* Write the trailing bytes if any */
1758 if (len & (map_bankwidth(map)-1)) {
1759 map_word tmp_buf;
1760
1761 retry1:
c4e77376 1762 mutex_lock(&cfi->chips[chipnum].mutex);
1da177e4
LT		 1763
1764 if (cfi->chips[chipnum].state != FL_READY) {
1da177e4
LT		 1765 set_current_state(TASK_UNINTERRUPTIBLE);
1766 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1767
c4e77376 1768 mutex_unlock(&cfi->chips[chipnum].mutex);
1da177e4
LT		 1769
1770 schedule();
1771 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1da177e4
LT		 1772 goto retry1;
1773 }
1774
1775 tmp_buf = map_read(map, ofs + chipstart);
1776
c4e77376 1777 mutex_unlock(&cfi->chips[chipnum].mutex);
1da177e4
LT		 1778
1779 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1f948b43
TG		 1780
1781 ret = do_write_oneword(map, &cfi->chips[chipnum],
af744750 1782 ofs, tmp_buf, FL_WRITING);
1f948b43 1783 if (ret)
1da177e4 1784 return ret;
1f948b43 1785
1da177e4
LT		 1786 (*retlen) += len;
1787 }
1788
1789 return 0;
1790}
1791
1792
1793/*
1794 * FIXME: interleaved mode not tested, and probably not supported!
1795 */
02b15e34 1796static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1f948b43 1797 unsigned long adr, const u_char *buf,
02b15e34 1798 int len)
1da177e4
LT		 1799{
1800 struct cfi_private *cfi = map->fldrv_priv;
1801 unsigned long timeo = jiffies + HZ;
6534e680
BH		 1802 /*
1803 * Timeout is calculated according to CFI data, if available.
1804 * See more comments in cfi_cmdset_0002().
1805 */
1806 unsigned long uWriteTimeout =
1807 usecs_to_jiffies(chip->buffer_write_time_max);
1da177e4
LT		 1808 int ret = -EIO;
1809 unsigned long cmd_adr;
1810 int z, words;
1811 map_word datum;
1812
1813 adr += chip->start;
1814 cmd_adr = adr;
1815
c4e77376 1816 mutex_lock(&chip->mutex);
1da177e4
LT		 1817 ret = get_chip(map, chip, adr, FL_WRITING);
1818 if (ret) {
c4e77376 1819 mutex_unlock(&chip->mutex);
1da177e4
LT		 1820 return ret;
1821 }
1822
1823 datum = map_word_load(map, buf);
1824
289c0522 1825 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
ea092fb3 1826 __func__, adr, datum.x[0]);
1da177e4 1827
02b15e34 1828 XIP_INVAL_CACHED_RANGE(map, adr, len);
1da177e4 1829 ENABLE_VPP(map);
02b15e34 1830 xip_disable(map, chip, cmd_adr);
1f948b43 1831
1da177e4
LT		 1832 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1833 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1da177e4
LT		 1834
1835 /* Write Buffer Load */
1836 map_write(map, CMD(0x25), cmd_adr);
1837
1838 chip->state = FL_WRITING_TO_BUFFER;
1839
1840 /* Write length of data to come */
1841 words = len / map_bankwidth(map);
1842 map_write(map, CMD(words - 1), cmd_adr);
1843 /* Write data */
1844 z = 0;
1845 while(z < words * map_bankwidth(map)) {
1846 datum = map_word_load(map, buf);
1847 map_write(map, datum, adr + z);
1848
1849 z += map_bankwidth(map);
1850 buf += map_bankwidth(map);
1851 }
1852 z -= map_bankwidth(map);
1853
1854 adr += z;
1855
1856 /* Write Buffer Program Confirm: GO GO GO */
1857 map_write(map, CMD(0x29), cmd_adr);
1858 chip->state = FL_WRITING;
1859
02b15e34
TP		 1860 INVALIDATE_CACHE_UDELAY(map, chip,
1861 adr, map_bankwidth(map),
1862 chip->word_write_time);
1da177e4 1863
1f948b43
TG		 1864 timeo = jiffies + uWriteTimeout;
1865
1da177e4
LT		 1866 for (;;) {
1867 if (chip->state != FL_WRITING) {
1868 /* Someone's suspended the write. Sleep */
1869 DECLARE_WAITQUEUE(wait, current);
1870
1871 set_current_state(TASK_UNINTERRUPTIBLE);
1872 add_wait_queue(&chip->wq, &wait);
c4e77376 1873 mutex_unlock(&chip->mutex);
1da177e4
LT		 1874 schedule();
1875 remove_wait_queue(&chip->wq, &wait);
1876 timeo = jiffies + (HZ / 2); /* FIXME */
c4e77376 1877 mutex_lock(&chip->mutex);
1da177e4
LT		 1878 continue;
1879 }
1880
b95f9609
KB		 1881 if (time_after(jiffies, timeo) && !chip_ready(map, adr))
1882 break;
1883
dfeae107 1884 if (chip_good(map, adr, datum)) {
02b15e34 1885 xip_enable(map, chip, adr);
1da177e4 1886 goto op_done;
02b15e34 1887 }
1da177e4
LT		 1888
1889 /* Latency issues. Drop the lock, wait a while and retry */
02b15e34 1890 UDELAY(map, chip, adr, 1);
1da177e4
LT		 1891 }
1892
070c3222
HNH		 1893 /*
1894 * Recovery from write-buffer programming failures requires
1895 * the write-to-buffer-reset sequence. Since the last part
1896 * of the sequence also works as a normal reset, we can run
1897 * the same commands regardless of why we are here.
1898 * See e.g.
1899 * http://www.spansion.com/Support/Application%20Notes/MirrorBit_Write_Buffer_Prog_Page_Buffer_Read_AN.pdf
1900 */
1901 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1902 cfi->device_type, NULL);
1903 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1904 cfi->device_type, NULL);
1905 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, chip->start, map, cfi,
1906 cfi->device_type, NULL);
02b15e34 1907 xip_enable(map, chip, adr);
1da177e4
LT		 1908 /* FIXME - should have reset delay before continuing */
1909
25983b18
HS		 1910 printk(KERN_WARNING "MTD %s(): software timeout, address:0x%.8lx.\n",
1911 __func__, adr);
02b15e34 1912
1da177e4
LT		 1913 ret = -EIO;
1914 op_done:
1915 chip->state = FL_READY;
e7d9377e 1916 DISABLE_VPP(map);
1da177e4 1917 put_chip(map, chip, adr);
c4e77376 1918 mutex_unlock(&chip->mutex);
1da177e4
LT		 1919
1920 return ret;
1921}
1922
1923
1924static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1925 size_t *retlen, const u_char *buf)
1926{
1927 struct map_info *map = mtd->priv;
1928 struct cfi_private *cfi = map->fldrv_priv;
1929 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1930 int ret = 0;
1931 int chipnum;
1932 unsigned long ofs;
1933
1da177e4
LT		 1934 chipnum = to >> cfi->chipshift;
1935 ofs = to - (chipnum << cfi->chipshift);
1936
1937 /* If it's not bus-aligned, do the first word write */
1938 if (ofs & (map_bankwidth(map)-1)) {
1939 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1940 if (local_len > len)
1941 local_len = len;
1942 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1943 local_len, retlen, buf);
1944 if (ret)
1945 return ret;
1946 ofs += local_len;
1947 buf += local_len;
1948 len -= local_len;
1949
1950 if (ofs >> cfi->chipshift) {
1951 chipnum ++;
1952 ofs = 0;
1953 if (chipnum == cfi->numchips)
1954 return 0;
1955 }
1956 }
1957
1958 /* Write buffer is worth it only if more than one word to write... */
1959 while (len >= map_bankwidth(map) * 2) {
1960 /* We must not cross write block boundaries */
1961 int size = wbufsize - (ofs & (wbufsize-1));
1962
1963 if (size > len)
1964 size = len;
1965 if (size % map_bankwidth(map))
1966 size -= size % map_bankwidth(map);
1967
1f948b43 1968 ret = do_write_buffer(map, &cfi->chips[chipnum],
1da177e4
LT		 1969 ofs, buf, size);
1970 if (ret)
1971 return ret;
1972
1973 ofs += size;
1974 buf += size;
1975 (*retlen) += size;
1976 len -= size;
1977
1978 if (ofs >> cfi->chipshift) {
1f948b43 1979 chipnum ++;
1da177e4
LT		 1980 ofs = 0;
1981 if (chipnum == cfi->numchips)
1982 return 0;
1983 }
1984 }
1985
1986 if (len) {
1987 size_t retlen_dregs = 0;
1988
1989 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1990 len, &retlen_dregs, buf);
1991
1992 *retlen += retlen_dregs;
1993 return ret;
1994 }
1995
1996 return 0;
1997}
1998
30ec5a2c
IS		 1999/*
2000 * Wait for the flash chip to become ready to write data
2001 *
2002 * This is only called during the panic_write() path. When panic_write()
2003 * is called, the kernel is in the process of a panic, and will soon be
2004 * dead. Therefore we don't take any locks, and attempt to get access
2005 * to the chip as soon as possible.
2006 */
2007static int cfi_amdstd_panic_wait(struct map_info *map, struct flchip *chip,
2008 unsigned long adr)
2009{
2010 struct cfi_private *cfi = map->fldrv_priv;
2011 int retries = 10;
2012 int i;
2013
2014 /*
2015 * If the driver thinks the chip is idle, and no toggle bits
2016 * are changing, then the chip is actually idle for sure.
2017 */
2018 if (chip->state == FL_READY && chip_ready(map, adr))
2019 return 0;
2020
2021 /*
2022 * Try several times to reset the chip and then wait for it
2023 * to become idle. The upper limit of a few milliseconds of
2024 * delay isn't a big problem: the kernel is dying anyway. It
2025 * is more important to save the messages.
2026 */
2027 while (retries > 0) {
2028 const unsigned long timeo = (HZ / 1000) + 1;
2029
2030 /* send the reset command */
2031 map_write(map, CMD(0xF0), chip->start);
2032
2033 /* wait for the chip to become ready */
2034 for (i = 0; i < jiffies_to_usecs(timeo); i++) {
2035 if (chip_ready(map, adr))
2036 return 0;
2037
2038 udelay(1);
2039 }
36c6a7ac
BN		 2040
2041 retries--;
30ec5a2c
IS		 2042 }
2043
2044 /* the chip never became ready */
2045 return -EBUSY;
2046}
2047
2048/*
2049 * Write out one word of data to a single flash chip during a kernel panic
2050 *
2051 * This is only called during the panic_write() path. When panic_write()
2052 * is called, the kernel is in the process of a panic, and will soon be
2053 * dead. Therefore we don't take any locks, and attempt to get access
2054 * to the chip as soon as possible.
2055 *
2056 * The implementation of this routine is intentionally similar to
2057 * do_write_oneword(), in order to ease code maintenance.
2058 */
2059static int do_panic_write_oneword(struct map_info *map, struct flchip *chip,
2060 unsigned long adr, map_word datum)
2061{
2062 const unsigned long uWriteTimeout = (HZ / 1000) + 1;
2063 struct cfi_private *cfi = map->fldrv_priv;
2064 int retry_cnt = 0;
2065 map_word oldd;
2066 int ret = 0;
2067 int i;
2068
2069 adr += chip->start;
2070
2071 ret = cfi_amdstd_panic_wait(map, chip, adr);
2072 if (ret)
2073 return ret;
2074
2075 pr_debug("MTD %s(): PANIC WRITE 0x%.8lx(0x%.8lx)\n",
2076 __func__, adr, datum.x[0]);
2077
2078 /*
2079 * Check for a NOP for the case when the datum to write is already
2080 * present - it saves time and works around buggy chips that corrupt
2081 * data at other locations when 0xff is written to a location that
2082 * already contains 0xff.
2083 */
2084 oldd = map_read(map, adr);
2085 if (map_word_equal(map, oldd, datum)) {
2086 pr_debug("MTD %s(): NOP\n", __func__);
2087 goto op_done;
2088 }
2089
2090 ENABLE_VPP(map);
2091
2092retry:
2093 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2094 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2095 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2096 map_write(map, datum, adr);
2097
2098 for (i = 0; i < jiffies_to_usecs(uWriteTimeout); i++) {
2099 if (chip_ready(map, adr))
2100 break;
2101
2102 udelay(1);
2103 }
2104
2105 if (!chip_good(map, adr, datum)) {
2106 /* reset on all failures. */
2107 map_write(map, CMD(0xF0), chip->start);
2108 /* FIXME - should have reset delay before continuing */
2109
85a82e28 2110 if (++retry_cnt <= MAX_RETRIES)
30ec5a2c
IS		 2111 goto retry;
2112
2113 ret = -EIO;
2114 }
2115
2116op_done:
2117 DISABLE_VPP(map);
2118 return ret;
2119}
2120
2121/*
2122 * Write out some data during a kernel panic
2123 *
2124 * This is used by the mtdoops driver to save the dying messages from a
2125 * kernel which has panic'd.
2126 *
2127 * This routine ignores all of the locking used throughout the rest of the
2128 * driver, in order to ensure that the data gets written out no matter what
2129 * state this driver (and the flash chip itself) was in when the kernel crashed.
2130 *
2131 * The implementation of this routine is intentionally similar to
2132 * cfi_amdstd_write_words(), in order to ease code maintenance.
2133 */
2134static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
2135 size_t *retlen, const u_char *buf)
2136{
2137 struct map_info *map = mtd->priv;
2138 struct cfi_private *cfi = map->fldrv_priv;
2139 unsigned long ofs, chipstart;
2140 int ret = 0;
2141 int chipnum;
2142
30ec5a2c
IS		 2143 chipnum = to >> cfi->chipshift;
2144 ofs = to - (chipnum << cfi->chipshift);
2145 chipstart = cfi->chips[chipnum].start;
2146
2147 /* If it's not bus aligned, do the first byte write */
2148 if (ofs & (map_bankwidth(map) - 1)) {
2149 unsigned long bus_ofs = ofs & ~(map_bankwidth(map) - 1);
2150 int i = ofs - bus_ofs;
2151 int n = 0;
2152 map_word tmp_buf;
2153
2154 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], bus_ofs);
2155 if (ret)
2156 return ret;
2157
2158 /* Load 'tmp_buf' with old contents of flash */
2159 tmp_buf = map_read(map, bus_ofs + chipstart);
2160
2161 /* Number of bytes to copy from buffer */
2162 n = min_t(int, len, map_bankwidth(map) - i);
2163
2164 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
2165
2166 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2167 bus_ofs, tmp_buf);
2168 if (ret)
2169 return ret;
2170
2171 ofs += n;
2172 buf += n;
2173 (*retlen) += n;
2174 len -= n;
2175
2176 if (ofs >> cfi->chipshift) {
2177 chipnum++;
2178 ofs = 0;
2179 if (chipnum == cfi->numchips)
2180 return 0;
2181 }
2182 }
2183
2184 /* We are now aligned, write as much as possible */
2185 while (len >= map_bankwidth(map)) {
2186 map_word datum;
2187
2188 datum = map_word_load(map, buf);
2189
2190 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2191 ofs, datum);
2192 if (ret)
2193 return ret;
2194
2195 ofs += map_bankwidth(map);
2196 buf += map_bankwidth(map);
2197 (*retlen) += map_bankwidth(map);
2198 len -= map_bankwidth(map);
2199
2200 if (ofs >> cfi->chipshift) {
2201 chipnum++;
2202 ofs = 0;
2203 if (chipnum == cfi->numchips)
2204 return 0;
2205
2206 chipstart = cfi->chips[chipnum].start;
2207 }
2208 }
2209
2210 /* Write the trailing bytes if any */
2211 if (len & (map_bankwidth(map) - 1)) {
2212 map_word tmp_buf;
2213
2214 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], ofs);
2215 if (ret)
2216 return ret;
2217
2218 tmp_buf = map_read(map, ofs + chipstart);
2219
2220 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
2221
2222 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2223 ofs, tmp_buf);
2224 if (ret)
2225 return ret;
2226
2227 (*retlen) += len;
2228 }
2229
2230 return 0;
2231}
2232
1da177e4
LT		 2233
2234/*
2235 * Handle devices with one erase region, that only implement
2236 * the chip erase command.
2237 */
02b15e34 2238static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
1da177e4
LT		 2239{
2240 struct cfi_private *cfi = map->fldrv_priv;
2241 unsigned long timeo = jiffies + HZ;
2242 unsigned long int adr;
2243 DECLARE_WAITQUEUE(wait, current);
2244 int ret = 0;
45f75b8a 2245 int retry_cnt = 0;
1da177e4
LT		 2246
2247 adr = cfi->addr_unlock1;
2248
c4e77376 2249 mutex_lock(&chip->mutex);
1da177e4
LT		 2250 ret = get_chip(map, chip, adr, FL_WRITING);
2251 if (ret) {
c4e77376 2252 mutex_unlock(&chip->mutex);
1da177e4
LT		 2253 return ret;
2254 }
2255
289c0522 2256 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
ea092fb3 2257 __func__, chip->start);
1da177e4 2258
02b15e34 2259 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
1da177e4 2260 ENABLE_VPP(map);
02b15e34
TP		 2261 xip_disable(map, chip, adr);
2262
45f75b8a 2263 retry:
1da177e4
LT		 2264 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2265 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2266 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2267 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2268 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2269 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2270
2271 chip->state = FL_ERASING;
2272 chip->erase_suspended = 0;
2273 chip->in_progress_block_addr = adr;
7b70eb14 2274 chip->in_progress_block_mask = ~(map->size - 1);
1da177e4 2275
02b15e34
TP		 2276 INVALIDATE_CACHE_UDELAY(map, chip,
2277 adr, map->size,
2278 chip->erase_time*500);
1da177e4
LT		 2279
2280 timeo = jiffies + (HZ*20);
2281
2282 for (;;) {
2283 if (chip->state != FL_ERASING) {
2284 /* Someone's suspended the erase. Sleep */
2285 set_current_state(TASK_UNINTERRUPTIBLE);
2286 add_wait_queue(&chip->wq, &wait);
c4e77376 2287 mutex_unlock(&chip->mutex);
1da177e4
LT		 2288 schedule();
2289 remove_wait_queue(&chip->wq, &wait);
c4e77376 2290 mutex_lock(&chip->mutex);
1da177e4
LT		 2291 continue;
2292 }
2293 if (chip->erase_suspended) {
2294 /* This erase was suspended and resumed.
2295 Adjust the timeout */
2296 timeo = jiffies + (HZ*20); /* FIXME */
2297 chip->erase_suspended = 0;
2298 }
2299
79ca484b 2300 if (chip_good(map, adr, map_word_ff(map)))
fb4a90bf 2301 break;
1da177e4 2302
fb4a90bf
EB		 2303 if (time_after(jiffies, timeo)) {
2304 printk(KERN_WARNING "MTD %s(): software timeout\n",
ea092fb3 2305 __func__);
79ca484b 2306 ret = -EIO;
1da177e4 2307 break;
fb4a90bf 2308 }
1da177e4
LT		 2309
2310 /* Latency issues. Drop the lock, wait a while and retry */
02b15e34 2311 UDELAY(map, chip, adr, 1000000/HZ);
1da177e4 2312 }
fb4a90bf 2313 /* Did we succeed? */
79ca484b 2314 if (ret) {
fb4a90bf 2315 /* reset on all failures. */
ea092fb3 2316 map_write(map, CMD(0xF0), chip->start);
fb4a90bf 2317 /* FIXME - should have reset delay before continuing */
1da177e4 2318
79ca484b
TI		 2319 if (++retry_cnt <= MAX_RETRIES) {
2320 ret = 0;
45f75b8a 2321 goto retry;
79ca484b 2322 }
fb4a90bf 2323 }
1da177e4 2324
1da177e4 2325 chip->state = FL_READY;
02b15e34 2326 xip_enable(map, chip, adr);
e7d9377e 2327 DISABLE_VPP(map);
1da177e4 2328 put_chip(map, chip, adr);
c4e77376 2329 mutex_unlock(&chip->mutex);
1da177e4
LT		 2330
2331 return ret;
2332}
2333
2334
02b15e34 2335static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
1da177e4
LT		 2336{
2337 struct cfi_private *cfi = map->fldrv_priv;
2338 unsigned long timeo = jiffies + HZ;
2339 DECLARE_WAITQUEUE(wait, current);
2340 int ret = 0;
45f75b8a 2341 int retry_cnt = 0;
1da177e4
LT		 2342
2343 adr += chip->start;
2344
c4e77376 2345 mutex_lock(&chip->mutex);
1da177e4
LT		 2346 ret = get_chip(map, chip, adr, FL_ERASING);
2347 if (ret) {
c4e77376 2348 mutex_unlock(&chip->mutex);
1da177e4
LT		 2349 return ret;
2350 }
2351
289c0522 2352 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
ea092fb3 2353 __func__, adr);
1da177e4 2354
02b15e34 2355 XIP_INVAL_CACHED_RANGE(map, adr, len);
1da177e4 2356 ENABLE_VPP(map);
02b15e34
TP		 2357 xip_disable(map, chip, adr);
2358
45f75b8a 2359 retry:
1da177e4
LT		 2360 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2361 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2362 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2363 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2364 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
08968041 2365 map_write(map, cfi->sector_erase_cmd, adr);
1da177e4
LT		 2366
2367 chip->state = FL_ERASING;
2368 chip->erase_suspended = 0;
2369 chip->in_progress_block_addr = adr;
7b70eb14 2370 chip->in_progress_block_mask = ~(len - 1);
02b15e34
TP		 2371
2372 INVALIDATE_CACHE_UDELAY(map, chip,
2373 adr, len,
2374 chip->erase_time*500);
1da177e4
LT		 2375
2376 timeo = jiffies + (HZ*20);
2377
2378 for (;;) {
2379 if (chip->state != FL_ERASING) {
2380 /* Someone's suspended the erase. Sleep */
2381 set_current_state(TASK_UNINTERRUPTIBLE);
2382 add_wait_queue(&chip->wq, &wait);
c4e77376 2383 mutex_unlock(&chip->mutex);
1da177e4
LT		 2384 schedule();
2385 remove_wait_queue(&chip->wq, &wait);
c4e77376 2386 mutex_lock(&chip->mutex);
1da177e4
LT		 2387 continue;
2388 }
2389 if (chip->erase_suspended) {
2390 /* This erase was suspended and resumed.
2391 Adjust the timeout */
2392 timeo = jiffies + (HZ*20); /* FIXME */
2393 chip->erase_suspended = 0;
2394 }
2395
c64d4419 2396 if (chip_good(map, adr, map_word_ff(map)))
fb4a90bf 2397 break;
1da177e4 2398
fb4a90bf
EB		 2399 if (time_after(jiffies, timeo)) {
2400 printk(KERN_WARNING "MTD %s(): software timeout\n",
ea092fb3 2401 __func__);
79ca484b 2402 ret = -EIO;
1da177e4 2403 break;
fb4a90bf 2404 }
1da177e4
LT		 2405
2406 /* Latency issues. Drop the lock, wait a while and retry */
02b15e34 2407 UDELAY(map, chip, adr, 1000000/HZ);
1da177e4 2408 }
fb4a90bf 2409 /* Did we succeed? */
79ca484b 2410 if (ret) {
fb4a90bf 2411 /* reset on all failures. */
ea092fb3 2412 map_write(map, CMD(0xF0), chip->start);
fb4a90bf
EB		 2413 /* FIXME - should have reset delay before continuing */
2414
79ca484b
TI		 2415 if (++retry_cnt <= MAX_RETRIES) {
2416 ret = 0;
45f75b8a 2417 goto retry;
79ca484b 2418 }
fb4a90bf 2419 }
1da177e4 2420
1da177e4 2421 chip->state = FL_READY;
c64d4419 2422 xip_enable(map, chip, adr);
e7d9377e 2423 DISABLE_VPP(map);
1da177e4 2424 put_chip(map, chip, adr);
c4e77376 2425 mutex_unlock(&chip->mutex);
1da177e4
LT		 2426 return ret;
2427}
2428
2429
ce0f33ad 2430static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2431{
e7bfb3fd
BB		 2432 return cfi_varsize_frob(mtd, do_erase_oneblock, instr->addr,
2433 instr->len, NULL);
1da177e4
LT		 2434}
2435
2436
2437static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
2438{
2439 struct map_info *map = mtd->priv;
2440 struct cfi_private *cfi = map->fldrv_priv;
1da177e4
LT		 2441
2442 if (instr->addr != 0)
2443 return -EINVAL;
2444
2445 if (instr->len != mtd->size)
2446 return -EINVAL;
2447
e7bfb3fd 2448 return do_erase_chip(map, &cfi->chips[0]);
1da177e4
LT		 2449}
2450
0165508c
HS		 2451static int do_atmel_lock(struct map_info *map, struct flchip *chip,
2452 unsigned long adr, int len, void *thunk)
2453{
2454 struct cfi_private *cfi = map->fldrv_priv;
2455 int ret;
2456
c4e77376 2457 mutex_lock(&chip->mutex);
0165508c
HS		 2458 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
2459 if (ret)
2460 goto out_unlock;
2461 chip->state = FL_LOCKING;
2462
0a32a102 2463 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
0165508c
HS		 2464
2465 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2466 cfi->device_type, NULL);
2467 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2468 cfi->device_type, NULL);
2469 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
2470 cfi->device_type, NULL);
2471 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2472 cfi->device_type, NULL);
2473 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2474 cfi->device_type, NULL);
2475 map_write(map, CMD(0x40), chip->start + adr);
2476
2477 chip->state = FL_READY;
2478 put_chip(map, chip, adr + chip->start);
2479 ret = 0;
2480
2481out_unlock:
c4e77376 2482 mutex_unlock(&chip->mutex);
0165508c
HS		 2483 return ret;
2484}
2485
2486static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
2487 unsigned long adr, int len, void *thunk)
2488{
2489 struct cfi_private *cfi = map->fldrv_priv;
2490 int ret;
2491
c4e77376 2492 mutex_lock(&chip->mutex);
0165508c
HS		 2493 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
2494 if (ret)
2495 goto out_unlock;
2496 chip->state = FL_UNLOCKING;
2497
0a32a102 2498 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
0165508c
HS		 2499
2500 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2501 cfi->device_type, NULL);
2502 map_write(map, CMD(0x70), adr);
2503
2504 chip->state = FL_READY;
2505 put_chip(map, chip, adr + chip->start);
2506 ret = 0;
2507
2508out_unlock:
c4e77376 2509 mutex_unlock(&chip->mutex);
0165508c
HS		 2510 return ret;
2511}
2512
69423d99 2513static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
0165508c
HS		 2514{
2515 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
2516}
2517
69423d99 2518static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
0165508c
HS		 2519{
2520 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
2521}
2522
1648eaaa
SR		 2523/*
2524 * Advanced Sector Protection - PPB (Persistent Protection Bit) locking
2525 */
2526
2527struct ppb_lock {
2528 struct flchip *chip;
2529 loff_t offset;
2530 int locked;
2531};
2532
2533#define MAX_SECTORS 512
2534
2535#define DO_XXLOCK_ONEBLOCK_LOCK ((void *)1)
2536#define DO_XXLOCK_ONEBLOCK_UNLOCK ((void *)2)
2537#define DO_XXLOCK_ONEBLOCK_GETLOCK ((void *)3)
2538
2539static int __maybe_unused do_ppb_xxlock(struct map_info *map,
2540 struct flchip *chip,
2541 unsigned long adr, int len, void *thunk)
2542{
2543 struct cfi_private *cfi = map->fldrv_priv;
2544 unsigned long timeo;
2545 int ret;
2546
2547 mutex_lock(&chip->mutex);
2548 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
2549 if (ret) {
2550 mutex_unlock(&chip->mutex);
2551 return ret;
2552 }
2553
2554 pr_debug("MTD %s(): XXLOCK 0x%08lx len %d\n", __func__, adr, len);
2555
2556 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2557 cfi->device_type, NULL);
2558 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2559 cfi->device_type, NULL);
2560 /* PPB entry command */
2561 cfi_send_gen_cmd(0xC0, cfi->addr_unlock1, chip->start, map, cfi,
2562 cfi->device_type, NULL);
2563
2564 if (thunk == DO_XXLOCK_ONEBLOCK_LOCK) {
2565 chip->state = FL_LOCKING;
2566 map_write(map, CMD(0xA0), chip->start + adr);
2567 map_write(map, CMD(0x00), chip->start + adr);
2568 } else if (thunk == DO_XXLOCK_ONEBLOCK_UNLOCK) {
2569 /*
2570 * Unlocking of one specific sector is not supported, so we
2571 * have to unlock all sectors of this device instead
2572 */
2573 chip->state = FL_UNLOCKING;
2574 map_write(map, CMD(0x80), chip->start);
2575 map_write(map, CMD(0x30), chip->start);
2576 } else if (thunk == DO_XXLOCK_ONEBLOCK_GETLOCK) {
2577 chip->state = FL_JEDEC_QUERY;
2578 /* Return locked status: 0->locked, 1->unlocked */
2579 ret = !cfi_read_query(map, adr);
2580 } else
2581 BUG();
2582
2583 /*
2584 * Wait for some time as unlocking of all sectors takes quite long
2585 */
2586 timeo = jiffies + msecs_to_jiffies(2000); /* 2s max (un)locking */
2587 for (;;) {
2588 if (chip_ready(map, adr))
2589 break;
2590
2591 if (time_after(jiffies, timeo)) {
2592 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
2593 ret = -EIO;
2594 break;
2595 }
2596
2597 UDELAY(map, chip, adr, 1);
2598 }
2599
2600 /* Exit BC commands */
2601 map_write(map, CMD(0x90), chip->start);
2602 map_write(map, CMD(0x00), chip->start);
2603
2604 chip->state = FL_READY;
2605 put_chip(map, chip, adr + chip->start);
2606 mutex_unlock(&chip->mutex);
2607
2608 return ret;
2609}
2610
2611static int __maybe_unused cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs,
2612 uint64_t len)
2613{
2614 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2615 DO_XXLOCK_ONEBLOCK_LOCK);
2616}
2617
2618static int __maybe_unused cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs,
2619 uint64_t len)
2620{
2621 struct mtd_erase_region_info *regions = mtd->eraseregions;
2622 struct map_info *map = mtd->priv;
2623 struct cfi_private *cfi = map->fldrv_priv;
2624 struct ppb_lock *sect;
2625 unsigned long adr;
2626 loff_t offset;
2627 uint64_t length;
2628 int chipnum;
2629 int i;
2630 int sectors;
2631 int ret;
2632
2633 /*
2634 * PPB unlocking always unlocks all sectors of the flash chip.
2635 * We need to re-lock all previously locked sectors. So lets
2636 * first check the locking status of all sectors and save
2637 * it for future use.
2638 */
2639 sect = kzalloc(MAX_SECTORS * sizeof(struct ppb_lock), GFP_KERNEL);
2640 if (!sect)
2641 return -ENOMEM;
2642
2643 /*
2644 * This code to walk all sectors is a slightly modified version
2645 * of the cfi_varsize_frob() code.
2646 */
2647 i = 0;
2648 chipnum = 0;
2649 adr = 0;
2650 sectors = 0;
2651 offset = 0;
2652 length = mtd->size;
2653
2654 while (length) {
2655 int size = regions[i].erasesize;
2656
2657 /*
2658 * Only test sectors that shall not be unlocked. The other
2659 * sectors shall be unlocked, so lets keep their locking
2660 * status at "unlocked" (locked=0) for the final re-locking.
2661 */
2662 if ((adr < ofs) || (adr >= (ofs + len))) {
2663 sect[sectors].chip = &cfi->chips[chipnum];
2664 sect[sectors].offset = offset;
2665 sect[sectors].locked = do_ppb_xxlock(
2666 map, &cfi->chips[chipnum], adr, 0,
2667 DO_XXLOCK_ONEBLOCK_GETLOCK);
2668 }
2669
2670 adr += size;
2671 offset += size;
2672 length -= size;
2673
2674 if (offset == regions[i].offset + size * regions[i].numblocks)
2675 i++;
2676
2677 if (adr >> cfi->chipshift) {
2678 adr = 0;
2679 chipnum++;
2680
2681 if (chipnum >= cfi->numchips)
2682 break;
2683 }
2684
2685 sectors++;
2686 if (sectors >= MAX_SECTORS) {
2687 printk(KERN_ERR "Only %d sectors for PPB locking supported!\n",
2688 MAX_SECTORS);
2689 kfree(sect);
2690 return -EINVAL;
2691 }
2692 }
2693
2694 /* Now unlock the whole chip */
2695 ret = cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2696 DO_XXLOCK_ONEBLOCK_UNLOCK);
2697 if (ret) {
2698 kfree(sect);
2699 return ret;
2700 }
2701
2702 /*
2703 * PPB unlocking always unlocks all sectors of the flash chip.
2704 * We need to re-lock all previously locked sectors.
2705 */
2706 for (i = 0; i < sectors; i++) {
2707 if (sect[i].locked)
2708 do_ppb_xxlock(map, sect[i].chip, sect[i].offset, 0,
2709 DO_XXLOCK_ONEBLOCK_LOCK);
2710 }
2711
2712 kfree(sect);
2713 return ret;
2714}
2715
2716static int __maybe_unused cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs,
2717 uint64_t len)
2718{
2719 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2720 DO_XXLOCK_ONEBLOCK_GETLOCK) ? 1 : 0;
2721}
1da177e4
LT		 2722
2723static void cfi_amdstd_sync (struct mtd_info *mtd)
2724{
2725 struct map_info *map = mtd->priv;
2726 struct cfi_private *cfi = map->fldrv_priv;
2727 int i;
2728 struct flchip *chip;
2729 int ret = 0;
2730 DECLARE_WAITQUEUE(wait, current);
2731
2732 for (i=0; !ret && i<cfi->numchips; i++) {
2733 chip = &cfi->chips[i];
2734
2735 retry:
c4e77376 2736 mutex_lock(&chip->mutex);
1da177e4
LT		 2737
2738 switch(chip->state) {
2739 case FL_READY:
2740 case FL_STATUS:
2741 case FL_CFI_QUERY:
2742 case FL_JEDEC_QUERY:
2743 chip->oldstate = chip->state;
2744 chip->state = FL_SYNCING;
1f948b43 2745 /* No need to wake_up() on this state change -
1da177e4
LT		 2746 * as the whole point is that nobody can do anything
2747 * with the chip now anyway.
2748 */
2749 case FL_SYNCING:
c4e77376 2750 mutex_unlock(&chip->mutex);
1da177e4
LT		 2751 break;
2752
2753 default:
2754 /* Not an idle state */
f8e30e44 2755 set_current_state(TASK_UNINTERRUPTIBLE);
1da177e4 2756 add_wait_queue(&chip->wq, &wait);
1f948b43 2757
c4e77376 2758 mutex_unlock(&chip->mutex);
1da177e4
LT		 2759
2760 schedule();
2761
2762 remove_wait_queue(&chip->wq, &wait);
1f948b43 2763
1da177e4
LT		 2764 goto retry;
2765 }
2766 }
2767
2768 /* Unlock the chips again */
2769
2770 for (i--; i >=0; i--) {
2771 chip = &cfi->chips[i];
2772
c4e77376 2773 mutex_lock(&chip->mutex);
1f948b43 2774
1da177e4
LT		 2775 if (chip->state == FL_SYNCING) {
2776 chip->state = chip->oldstate;
2777 wake_up(&chip->wq);
2778 }
c4e77376 2779 mutex_unlock(&chip->mutex);
1da177e4
LT		 2780 }
2781}
2782
2783
2784static int cfi_amdstd_suspend(struct mtd_info *mtd)
2785{
2786 struct map_info *map = mtd->priv;
2787 struct cfi_private *cfi = map->fldrv_priv;
2788 int i;
2789 struct flchip *chip;
2790 int ret = 0;
2791
2792 for (i=0; !ret && i<cfi->numchips; i++) {
2793 chip = &cfi->chips[i];
2794
c4e77376 2795 mutex_lock(&chip->mutex);
1da177e4
LT		 2796
2797 switch(chip->state) {
2798 case FL_READY:
2799 case FL_STATUS:
2800 case FL_CFI_QUERY:
2801 case FL_JEDEC_QUERY:
2802 chip->oldstate = chip->state;
2803 chip->state = FL_PM_SUSPENDED;
1f948b43 2804 /* No need to wake_up() on this state change -
1da177e4
LT		 2805 * as the whole point is that nobody can do anything
2806 * with the chip now anyway.
2807 */
2808 case FL_PM_SUSPENDED:
2809 break;
2810
2811 default:
2812 ret = -EAGAIN;
2813 break;
2814 }
c4e77376 2815 mutex_unlock(&chip->mutex);
1da177e4
LT		 2816 }
2817
2818 /* Unlock the chips again */
2819
2820 if (ret) {
2821 for (i--; i >=0; i--) {
2822 chip = &cfi->chips[i];
2823
c4e77376 2824 mutex_lock(&chip->mutex);
1f948b43 2825
1da177e4
LT		 2826 if (chip->state == FL_PM_SUSPENDED) {
2827 chip->state = chip->oldstate;
2828 wake_up(&chip->wq);
2829 }
c4e77376 2830 mutex_unlock(&chip->mutex);
1da177e4
LT		 2831 }
2832 }
1f948b43 2833
1da177e4
LT		 2834 return ret;
2835}
2836
2837
2838static void cfi_amdstd_resume(struct mtd_info *mtd)
2839{
2840 struct map_info *map = mtd->priv;
2841 struct cfi_private *cfi = map->fldrv_priv;
2842 int i;
2843 struct flchip *chip;
2844
2845 for (i=0; i<cfi->numchips; i++) {
1f948b43 2846
1da177e4
LT		 2847 chip = &cfi->chips[i];
2848
c4e77376 2849 mutex_lock(&chip->mutex);
1f948b43 2850
1da177e4
LT		 2851 if (chip->state == FL_PM_SUSPENDED) {
2852 chip->state = FL_READY;
2853 map_write(map, CMD(0xF0), chip->start);
2854 wake_up(&chip->wq);
2855 }
2856 else
2857 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
2858
c4e77376 2859 mutex_unlock(&chip->mutex);
1da177e4
LT		 2860 }
2861}
2862
eafe1311
KC		 2863
2864/*
2865 * Ensure that the flash device is put back into read array mode before
2866 * unloading the driver or rebooting. On some systems, rebooting while
2867 * the flash is in query/program/erase mode will prevent the CPU from
2868 * fetching the bootloader code, requiring a hard reset or power cycle.
2869 */
2870static int cfi_amdstd_reset(struct mtd_info *mtd)
2871{
2872 struct map_info *map = mtd->priv;
2873 struct cfi_private *cfi = map->fldrv_priv;
2874 int i, ret;
2875 struct flchip *chip;
2876
2877 for (i = 0; i < cfi->numchips; i++) {
2878
2879 chip = &cfi->chips[i];
2880
2881 mutex_lock(&chip->mutex);
2882
2883 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
2884 if (!ret) {
2885 map_write(map, CMD(0xF0), chip->start);
2886 chip->state = FL_SHUTDOWN;
2887 put_chip(map, chip, chip->start);
2888 }
2889
2890 mutex_unlock(&chip->mutex);
2891 }
2892
2893 return 0;
2894}
2895
2896
2897static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val,
2898 void *v)
2899{
2900 struct mtd_info *mtd;
2901
2902 mtd = container_of(nb, struct mtd_info, reboot_notifier);
2903 cfi_amdstd_reset(mtd);
2904 return NOTIFY_DONE;
2905}
2906
2907
1da177e4
LT		 2908static void cfi_amdstd_destroy(struct mtd_info *mtd)
2909{
2910 struct map_info *map = mtd->priv;
2911 struct cfi_private *cfi = map->fldrv_priv;
fa671646 2912
eafe1311
KC		 2913 cfi_amdstd_reset(mtd);
2914 unregister_reboot_notifier(&mtd->reboot_notifier);
1da177e4
LT		 2915 kfree(cfi->cmdset_priv);
2916 kfree(cfi->cfiq);
2917 kfree(cfi);
2918 kfree(mtd->eraseregions);
2919}
2920
1da177e4
LT		 2921MODULE_LICENSE("GPL");
2922MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
2923MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");
80461128 2924MODULE_ALIAS("cfi_cmdset_0006");
1e804cec 2925MODULE_ALIAS("cfi_cmdset_0701");
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