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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Common Flash Interface support: | |
3 | * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002) | |
4 | * | |
5 | * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp> | |
6 | * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com> | |
02b15e34 | 7 | * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com> |
1da177e4 LT |
8 | * |
9 | * 2_by_8 routines added by Simon Munton | |
10 | * | |
11 | * 4_by_16 work by Carolyn J. Smith | |
12 | * | |
1f948b43 | 13 | * XIP support hooks by Vitaly Wool (based on code for Intel flash |
02b15e34 | 14 | * by Nicolas Pitre) |
1f948b43 | 15 | * |
87e92c06 CM |
16 | * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0 |
17 | * | |
1da177e4 LT |
18 | * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com |
19 | * | |
20 | * This code is GPL | |
1da177e4 LT |
21 | */ |
22 | ||
1da177e4 LT |
23 | #include <linux/module.h> |
24 | #include <linux/types.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/init.h> | |
28 | #include <asm/io.h> | |
29 | #include <asm/byteorder.h> | |
30 | ||
31 | #include <linux/errno.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/mtd/compatmac.h> | |
36 | #include <linux/mtd/map.h> | |
37 | #include <linux/mtd/mtd.h> | |
38 | #include <linux/mtd/cfi.h> | |
02b15e34 | 39 | #include <linux/mtd/xip.h> |
1da177e4 LT |
40 | |
41 | #define AMD_BOOTLOC_BUG | |
42 | #define FORCE_WORD_WRITE 0 | |
43 | ||
44 | #define MAX_WORD_RETRIES 3 | |
45 | ||
46 | #define MANUFACTURER_AMD 0x0001 | |
0165508c | 47 | #define MANUFACTURER_ATMEL 0x001F |
87e92c06 | 48 | #define MANUFACTURER_MACRONIX 0x00C2 |
1da177e4 LT |
49 | #define MANUFACTURER_SST 0x00BF |
50 | #define SST49LF004B 0x0060 | |
89072ef9 | 51 | #define SST49LF040B 0x0050 |
fb4a90bf | 52 | #define SST49LF008A 0x005a |
0165508c | 53 | #define AT49BV6416 0x00d6 |
1da177e4 LT |
54 | |
55 | static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); | |
56 | static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); | |
57 | static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); | |
58 | static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *); | |
59 | static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *); | |
60 | static void cfi_amdstd_sync (struct mtd_info *); | |
61 | static int cfi_amdstd_suspend (struct mtd_info *); | |
62 | static void cfi_amdstd_resume (struct mtd_info *); | |
63 | static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); | |
64 | ||
65 | static void cfi_amdstd_destroy(struct mtd_info *); | |
66 | ||
67 | struct mtd_info *cfi_cmdset_0002(struct map_info *, int); | |
68 | static struct mtd_info *cfi_amdstd_setup (struct mtd_info *); | |
69 | ||
70 | static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode); | |
71 | static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr); | |
72 | #include "fwh_lock.h" | |
73 | ||
0165508c HS |
74 | static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, size_t len); |
75 | static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, size_t len); | |
76 | ||
1da177e4 LT |
77 | static struct mtd_chip_driver cfi_amdstd_chipdrv = { |
78 | .probe = NULL, /* Not usable directly */ | |
79 | .destroy = cfi_amdstd_destroy, | |
80 | .name = "cfi_cmdset_0002", | |
81 | .module = THIS_MODULE | |
82 | }; | |
83 | ||
84 | ||
85 | /* #define DEBUG_CFI_FEATURES */ | |
86 | ||
87 | ||
88 | #ifdef DEBUG_CFI_FEATURES | |
89 | static void cfi_tell_features(struct cfi_pri_amdstd *extp) | |
90 | { | |
91 | const char* erase_suspend[3] = { | |
92 | "Not supported", "Read only", "Read/write" | |
93 | }; | |
94 | const char* top_bottom[6] = { | |
95 | "No WP", "8x8KiB sectors at top & bottom, no WP", | |
96 | "Bottom boot", "Top boot", | |
97 | "Uniform, Bottom WP", "Uniform, Top WP" | |
98 | }; | |
99 | ||
100 | printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1); | |
1f948b43 | 101 | printk(" Address sensitive unlock: %s\n", |
1da177e4 LT |
102 | (extp->SiliconRevision & 1) ? "Not required" : "Required"); |
103 | ||
104 | if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend)) | |
105 | printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]); | |
106 | else | |
107 | printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend); | |
108 | ||
109 | if (extp->BlkProt == 0) | |
110 | printk(" Block protection: Not supported\n"); | |
111 | else | |
112 | printk(" Block protection: %d sectors per group\n", extp->BlkProt); | |
113 | ||
114 | ||
115 | printk(" Temporary block unprotect: %s\n", | |
116 | extp->TmpBlkUnprotect ? "Supported" : "Not supported"); | |
117 | printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot); | |
118 | printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps); | |
119 | printk(" Burst mode: %s\n", | |
120 | extp->BurstMode ? "Supported" : "Not supported"); | |
121 | if (extp->PageMode == 0) | |
122 | printk(" Page mode: Not supported\n"); | |
123 | else | |
124 | printk(" Page mode: %d word page\n", extp->PageMode << 2); | |
125 | ||
1f948b43 | 126 | printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n", |
1da177e4 | 127 | extp->VppMin >> 4, extp->VppMin & 0xf); |
1f948b43 | 128 | printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n", |
1da177e4 LT |
129 | extp->VppMax >> 4, extp->VppMax & 0xf); |
130 | ||
131 | if (extp->TopBottom < ARRAY_SIZE(top_bottom)) | |
132 | printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]); | |
133 | else | |
134 | printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom); | |
135 | } | |
136 | #endif | |
137 | ||
138 | #ifdef AMD_BOOTLOC_BUG | |
139 | /* Wheee. Bring me the head of someone at AMD. */ | |
140 | static void fixup_amd_bootblock(struct mtd_info *mtd, void* param) | |
141 | { | |
142 | struct map_info *map = mtd->priv; | |
143 | struct cfi_private *cfi = map->fldrv_priv; | |
144 | struct cfi_pri_amdstd *extp = cfi->cmdset_priv; | |
145 | __u8 major = extp->MajorVersion; | |
146 | __u8 minor = extp->MinorVersion; | |
147 | ||
148 | if (((major << 8) | minor) < 0x3131) { | |
149 | /* CFI version 1.0 => don't trust bootloc */ | |
87e92c06 CM |
150 | |
151 | DEBUG(MTD_DEBUG_LEVEL1, | |
152 | "%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n", | |
153 | map->name, cfi->mfr, cfi->id); | |
154 | ||
155 | /* AFAICS all 29LV400 with a bottom boot block have a device ID | |
156 | * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode. | |
157 | * These were badly detected as they have the 0x80 bit set | |
158 | * so treat them as a special case. | |
159 | */ | |
160 | if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) && | |
161 | ||
162 | /* Macronix added CFI to their 2nd generation | |
163 | * MX29LV400C B/T but AFAICS no other 29LV400 (AMD, | |
164 | * Fujitsu, Spansion, EON, ESI and older Macronix) | |
165 | * has CFI. | |
166 | * | |
167 | * Therefore also check the manufacturer. | |
168 | * This reduces the risk of false detection due to | |
169 | * the 8-bit device ID. | |
170 | */ | |
171 | (cfi->mfr == MANUFACTURER_MACRONIX)) { | |
172 | DEBUG(MTD_DEBUG_LEVEL1, | |
173 | "%s: Macronix MX29LV400C with bottom boot block" | |
174 | " detected\n", map->name); | |
175 | extp->TopBottom = 2; /* bottom boot */ | |
176 | } else | |
1da177e4 LT |
177 | if (cfi->id & 0x80) { |
178 | printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id); | |
179 | extp->TopBottom = 3; /* top boot */ | |
180 | } else { | |
181 | extp->TopBottom = 2; /* bottom boot */ | |
182 | } | |
87e92c06 CM |
183 | |
184 | DEBUG(MTD_DEBUG_LEVEL1, | |
185 | "%s: AMD CFI PRI V%c.%c has no boot block field;" | |
186 | " deduced %s from Device ID\n", map->name, major, minor, | |
187 | extp->TopBottom == 2 ? "bottom" : "top"); | |
1da177e4 LT |
188 | } |
189 | } | |
190 | #endif | |
191 | ||
192 | static void fixup_use_write_buffers(struct mtd_info *mtd, void *param) | |
193 | { | |
194 | struct map_info *map = mtd->priv; | |
195 | struct cfi_private *cfi = map->fldrv_priv; | |
196 | if (cfi->cfiq->BufWriteTimeoutTyp) { | |
197 | DEBUG(MTD_DEBUG_LEVEL1, "Using buffer write method\n" ); | |
198 | mtd->write = cfi_amdstd_write_buffers; | |
199 | } | |
200 | } | |
201 | ||
5b0c5c2c HS |
202 | /* Atmel chips don't use the same PRI format as AMD chips */ |
203 | static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param) | |
204 | { | |
205 | struct map_info *map = mtd->priv; | |
206 | struct cfi_private *cfi = map->fldrv_priv; | |
207 | struct cfi_pri_amdstd *extp = cfi->cmdset_priv; | |
208 | struct cfi_pri_atmel atmel_pri; | |
209 | ||
210 | memcpy(&atmel_pri, extp, sizeof(atmel_pri)); | |
de591dac | 211 | memset((char *)extp + 5, 0, sizeof(*extp) - 5); |
5b0c5c2c HS |
212 | |
213 | if (atmel_pri.Features & 0x02) | |
214 | extp->EraseSuspend = 2; | |
215 | ||
216 | if (atmel_pri.BottomBoot) | |
217 | extp->TopBottom = 2; | |
218 | else | |
219 | extp->TopBottom = 3; | |
d10a39d1 HCE |
220 | |
221 | /* burst write mode not supported */ | |
222 | cfi->cfiq->BufWriteTimeoutTyp = 0; | |
223 | cfi->cfiq->BufWriteTimeoutMax = 0; | |
5b0c5c2c HS |
224 | } |
225 | ||
1da177e4 LT |
226 | static void fixup_use_secsi(struct mtd_info *mtd, void *param) |
227 | { | |
228 | /* Setup for chips with a secsi area */ | |
229 | mtd->read_user_prot_reg = cfi_amdstd_secsi_read; | |
230 | mtd->read_fact_prot_reg = cfi_amdstd_secsi_read; | |
231 | } | |
232 | ||
233 | static void fixup_use_erase_chip(struct mtd_info *mtd, void *param) | |
234 | { | |
235 | struct map_info *map = mtd->priv; | |
236 | struct cfi_private *cfi = map->fldrv_priv; | |
237 | if ((cfi->cfiq->NumEraseRegions == 1) && | |
238 | ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) { | |
239 | mtd->erase = cfi_amdstd_erase_chip; | |
240 | } | |
1f948b43 | 241 | |
1da177e4 LT |
242 | } |
243 | ||
0165508c HS |
244 | /* |
245 | * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors | |
246 | * locked by default. | |
247 | */ | |
248 | static void fixup_use_atmel_lock(struct mtd_info *mtd, void *param) | |
249 | { | |
250 | mtd->lock = cfi_atmel_lock; | |
251 | mtd->unlock = cfi_atmel_unlock; | |
e619a75f | 252 | mtd->flags |= MTD_POWERUP_LOCK; |
0165508c HS |
253 | } |
254 | ||
70b07255 TP |
255 | static void fixup_s29gl064n_sectors(struct mtd_info *mtd, void *param) |
256 | { | |
257 | struct map_info *map = mtd->priv; | |
258 | struct cfi_private *cfi = map->fldrv_priv; | |
259 | ||
260 | if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) { | |
261 | cfi->cfiq->EraseRegionInfo[0] |= 0x0040; | |
262 | pr_warning("%s: Bad S29GL064N CFI data, adjust from 64 to 128 sectors\n", mtd->name); | |
263 | } | |
264 | } | |
265 | ||
266 | static void fixup_s29gl032n_sectors(struct mtd_info *mtd, void *param) | |
267 | { | |
268 | struct map_info *map = mtd->priv; | |
269 | struct cfi_private *cfi = map->fldrv_priv; | |
270 | ||
271 | if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) { | |
272 | cfi->cfiq->EraseRegionInfo[1] &= ~0x0040; | |
273 | pr_warning("%s: Bad S29GL032N CFI data, adjust from 127 to 63 sectors\n", mtd->name); | |
274 | } | |
275 | } | |
276 | ||
1da177e4 | 277 | static struct cfi_fixup cfi_fixup_table[] = { |
d10a39d1 | 278 | { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL }, |
1da177e4 LT |
279 | #ifdef AMD_BOOTLOC_BUG |
280 | { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL }, | |
87e92c06 | 281 | { MANUFACTURER_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock, NULL }, |
1da177e4 LT |
282 | #endif |
283 | { CFI_MFR_AMD, 0x0050, fixup_use_secsi, NULL, }, | |
284 | { CFI_MFR_AMD, 0x0053, fixup_use_secsi, NULL, }, | |
285 | { CFI_MFR_AMD, 0x0055, fixup_use_secsi, NULL, }, | |
286 | { CFI_MFR_AMD, 0x0056, fixup_use_secsi, NULL, }, | |
287 | { CFI_MFR_AMD, 0x005C, fixup_use_secsi, NULL, }, | |
288 | { CFI_MFR_AMD, 0x005F, fixup_use_secsi, NULL, }, | |
70b07255 TP |
289 | { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors, NULL, }, |
290 | { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors, NULL, }, | |
291 | { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors, NULL, }, | |
292 | { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors, NULL, }, | |
1da177e4 LT |
293 | #if !FORCE_WORD_WRITE |
294 | { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, }, | |
295 | #endif | |
296 | { 0, 0, NULL, NULL } | |
297 | }; | |
298 | static struct cfi_fixup jedec_fixup_table[] = { | |
299 | { MANUFACTURER_SST, SST49LF004B, fixup_use_fwh_lock, NULL, }, | |
89072ef9 | 300 | { MANUFACTURER_SST, SST49LF040B, fixup_use_fwh_lock, NULL, }, |
fb4a90bf | 301 | { MANUFACTURER_SST, SST49LF008A, fixup_use_fwh_lock, NULL, }, |
1da177e4 LT |
302 | { 0, 0, NULL, NULL } |
303 | }; | |
304 | ||
305 | static struct cfi_fixup fixup_table[] = { | |
306 | /* The CFI vendor ids and the JEDEC vendor IDs appear | |
307 | * to be common. It is like the devices id's are as | |
308 | * well. This table is to pick all cases where | |
309 | * we know that is the case. | |
310 | */ | |
311 | { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip, NULL }, | |
0165508c | 312 | { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock, NULL }, |
1da177e4 LT |
313 | { 0, 0, NULL, NULL } |
314 | }; | |
315 | ||
316 | ||
317 | struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary) | |
318 | { | |
319 | struct cfi_private *cfi = map->fldrv_priv; | |
320 | struct mtd_info *mtd; | |
321 | int i; | |
322 | ||
95b93a0c | 323 | mtd = kzalloc(sizeof(*mtd), GFP_KERNEL); |
1da177e4 LT |
324 | if (!mtd) { |
325 | printk(KERN_WARNING "Failed to allocate memory for MTD device\n"); | |
326 | return NULL; | |
327 | } | |
1da177e4 LT |
328 | mtd->priv = map; |
329 | mtd->type = MTD_NORFLASH; | |
330 | ||
331 | /* Fill in the default mtd operations */ | |
332 | mtd->erase = cfi_amdstd_erase_varsize; | |
333 | mtd->write = cfi_amdstd_write_words; | |
334 | mtd->read = cfi_amdstd_read; | |
335 | mtd->sync = cfi_amdstd_sync; | |
336 | mtd->suspend = cfi_amdstd_suspend; | |
337 | mtd->resume = cfi_amdstd_resume; | |
338 | mtd->flags = MTD_CAP_NORFLASH; | |
339 | mtd->name = map->name; | |
783ed81f | 340 | mtd->writesize = 1; |
1da177e4 LT |
341 | |
342 | if (cfi->cfi_mode==CFI_MODE_CFI){ | |
343 | unsigned char bootloc; | |
1f948b43 | 344 | /* |
1da177e4 LT |
345 | * It's a real CFI chip, not one for which the probe |
346 | * routine faked a CFI structure. So we read the feature | |
347 | * table from it. | |
348 | */ | |
349 | __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR; | |
350 | struct cfi_pri_amdstd *extp; | |
351 | ||
352 | extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu"); | |
353 | if (!extp) { | |
354 | kfree(mtd); | |
355 | return NULL; | |
356 | } | |
357 | ||
d88f977b TP |
358 | if (extp->MajorVersion != '1' || |
359 | (extp->MinorVersion < '0' || extp->MinorVersion > '4')) { | |
360 | printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query " | |
361 | "version %c.%c.\n", extp->MajorVersion, | |
362 | extp->MinorVersion); | |
363 | kfree(extp); | |
364 | kfree(mtd); | |
365 | return NULL; | |
366 | } | |
367 | ||
1da177e4 | 368 | /* Install our own private info structure */ |
1f948b43 | 369 | cfi->cmdset_priv = extp; |
1da177e4 LT |
370 | |
371 | /* Apply cfi device specific fixups */ | |
372 | cfi_fixup(mtd, cfi_fixup_table); | |
373 | ||
374 | #ifdef DEBUG_CFI_FEATURES | |
375 | /* Tell the user about it in lots of lovely detail */ | |
376 | cfi_tell_features(extp); | |
1f948b43 | 377 | #endif |
1da177e4 LT |
378 | |
379 | bootloc = extp->TopBottom; | |
380 | if ((bootloc != 2) && (bootloc != 3)) { | |
381 | printk(KERN_WARNING "%s: CFI does not contain boot " | |
382 | "bank location. Assuming top.\n", map->name); | |
383 | bootloc = 2; | |
384 | } | |
385 | ||
386 | if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) { | |
387 | printk(KERN_WARNING "%s: Swapping erase regions for broken CFI table.\n", map->name); | |
1f948b43 | 388 | |
1da177e4 LT |
389 | for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) { |
390 | int j = (cfi->cfiq->NumEraseRegions-1)-i; | |
391 | __u32 swap; | |
1f948b43 | 392 | |
1da177e4 LT |
393 | swap = cfi->cfiq->EraseRegionInfo[i]; |
394 | cfi->cfiq->EraseRegionInfo[i] = cfi->cfiq->EraseRegionInfo[j]; | |
395 | cfi->cfiq->EraseRegionInfo[j] = swap; | |
396 | } | |
397 | } | |
398 | /* Set the default CFI lock/unlock addresses */ | |
399 | cfi->addr_unlock1 = 0x555; | |
400 | cfi->addr_unlock2 = 0x2aa; | |
401 | /* Modify the unlock address if we are in compatibility mode */ | |
402 | if ( /* x16 in x8 mode */ | |
1f948b43 | 403 | ((cfi->device_type == CFI_DEVICETYPE_X8) && |
de7921f0 BS |
404 | (cfi->cfiq->InterfaceDesc == |
405 | CFI_INTERFACE_X8_BY_X16_ASYNC)) || | |
1da177e4 LT |
406 | /* x32 in x16 mode */ |
407 | ((cfi->device_type == CFI_DEVICETYPE_X16) && | |
de7921f0 BS |
408 | (cfi->cfiq->InterfaceDesc == |
409 | CFI_INTERFACE_X16_BY_X32_ASYNC))) | |
1da177e4 LT |
410 | { |
411 | cfi->addr_unlock1 = 0xaaa; | |
412 | cfi->addr_unlock2 = 0x555; | |
413 | } | |
414 | ||
415 | } /* CFI mode */ | |
416 | else if (cfi->cfi_mode == CFI_MODE_JEDEC) { | |
417 | /* Apply jedec specific fixups */ | |
418 | cfi_fixup(mtd, jedec_fixup_table); | |
419 | } | |
420 | /* Apply generic fixups */ | |
421 | cfi_fixup(mtd, fixup_table); | |
422 | ||
423 | for (i=0; i< cfi->numchips; i++) { | |
424 | cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp; | |
425 | cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp; | |
426 | cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp; | |
83d48091 VS |
427 | cfi->chips[i].ref_point_counter = 0; |
428 | init_waitqueue_head(&(cfi->chips[i].wq)); | |
1f948b43 TG |
429 | } |
430 | ||
1da177e4 | 431 | map->fldrv = &cfi_amdstd_chipdrv; |
1f948b43 | 432 | |
1da177e4 LT |
433 | return cfi_amdstd_setup(mtd); |
434 | } | |
83ea4ef2 | 435 | EXPORT_SYMBOL_GPL(cfi_cmdset_0002); |
1da177e4 LT |
436 | |
437 | static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd) | |
438 | { | |
439 | struct map_info *map = mtd->priv; | |
440 | struct cfi_private *cfi = map->fldrv_priv; | |
441 | unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave; | |
442 | unsigned long offset = 0; | |
443 | int i,j; | |
444 | ||
1f948b43 | 445 | printk(KERN_NOTICE "number of %s chips: %d\n", |
1da177e4 | 446 | (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips); |
1f948b43 | 447 | /* Select the correct geometry setup */ |
1da177e4 LT |
448 | mtd->size = devsize * cfi->numchips; |
449 | ||
450 | mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips; | |
451 | mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info) | |
452 | * mtd->numeraseregions, GFP_KERNEL); | |
1f948b43 | 453 | if (!mtd->eraseregions) { |
1da177e4 LT |
454 | printk(KERN_WARNING "Failed to allocate memory for MTD erase region info\n"); |
455 | goto setup_err; | |
456 | } | |
1f948b43 | 457 | |
1da177e4 LT |
458 | for (i=0; i<cfi->cfiq->NumEraseRegions; i++) { |
459 | unsigned long ernum, ersize; | |
460 | ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave; | |
461 | ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1; | |
1f948b43 | 462 | |
1da177e4 LT |
463 | if (mtd->erasesize < ersize) { |
464 | mtd->erasesize = ersize; | |
465 | } | |
466 | for (j=0; j<cfi->numchips; j++) { | |
467 | mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset; | |
468 | mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize; | |
469 | mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum; | |
470 | } | |
471 | offset += (ersize * ernum); | |
472 | } | |
473 | if (offset != devsize) { | |
474 | /* Argh */ | |
475 | printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize); | |
476 | goto setup_err; | |
477 | } | |
478 | #if 0 | |
479 | // debug | |
480 | for (i=0; i<mtd->numeraseregions;i++){ | |
481 | printk("%d: offset=0x%x,size=0x%x,blocks=%d\n", | |
482 | i,mtd->eraseregions[i].offset, | |
483 | mtd->eraseregions[i].erasesize, | |
484 | mtd->eraseregions[i].numblocks); | |
485 | } | |
486 | #endif | |
487 | ||
488 | /* FIXME: erase-suspend-program is broken. See | |
489 | http://lists.infradead.org/pipermail/linux-mtd/2003-December/009001.html */ | |
490 | printk(KERN_NOTICE "cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.\n"); | |
491 | ||
492 | __module_get(THIS_MODULE); | |
493 | return mtd; | |
494 | ||
495 | setup_err: | |
496 | if(mtd) { | |
fa671646 | 497 | kfree(mtd->eraseregions); |
1da177e4 LT |
498 | kfree(mtd); |
499 | } | |
500 | kfree(cfi->cmdset_priv); | |
501 | kfree(cfi->cfiq); | |
502 | return NULL; | |
503 | } | |
504 | ||
505 | /* | |
506 | * Return true if the chip is ready. | |
507 | * | |
508 | * Ready is one of: read mode, query mode, erase-suspend-read mode (in any | |
509 | * non-suspended sector) and is indicated by no toggle bits toggling. | |
510 | * | |
511 | * Note that anything more complicated than checking if no bits are toggling | |
512 | * (including checking DQ5 for an error status) is tricky to get working | |
513 | * correctly and is therefore not done (particulary with interleaved chips | |
514 | * as each chip must be checked independantly of the others). | |
515 | */ | |
02b15e34 | 516 | static int __xipram chip_ready(struct map_info *map, unsigned long addr) |
1da177e4 LT |
517 | { |
518 | map_word d, t; | |
519 | ||
520 | d = map_read(map, addr); | |
521 | t = map_read(map, addr); | |
522 | ||
523 | return map_word_equal(map, d, t); | |
524 | } | |
525 | ||
fb4a90bf EB |
526 | /* |
527 | * Return true if the chip is ready and has the correct value. | |
528 | * | |
529 | * Ready is one of: read mode, query mode, erase-suspend-read mode (in any | |
530 | * non-suspended sector) and it is indicated by no bits toggling. | |
531 | * | |
532 | * Error are indicated by toggling bits or bits held with the wrong value, | |
533 | * or with bits toggling. | |
534 | * | |
535 | * Note that anything more complicated than checking if no bits are toggling | |
536 | * (including checking DQ5 for an error status) is tricky to get working | |
537 | * correctly and is therefore not done (particulary with interleaved chips | |
538 | * as each chip must be checked independantly of the others). | |
539 | * | |
540 | */ | |
02b15e34 | 541 | static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected) |
fb4a90bf EB |
542 | { |
543 | map_word oldd, curd; | |
544 | ||
545 | oldd = map_read(map, addr); | |
546 | curd = map_read(map, addr); | |
547 | ||
1f948b43 | 548 | return map_word_equal(map, oldd, curd) && |
fb4a90bf EB |
549 | map_word_equal(map, curd, expected); |
550 | } | |
551 | ||
1da177e4 LT |
552 | static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode) |
553 | { | |
554 | DECLARE_WAITQUEUE(wait, current); | |
555 | struct cfi_private *cfi = map->fldrv_priv; | |
556 | unsigned long timeo; | |
557 | struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv; | |
558 | ||
559 | resettime: | |
560 | timeo = jiffies + HZ; | |
561 | retry: | |
562 | switch (chip->state) { | |
563 | ||
564 | case FL_STATUS: | |
565 | for (;;) { | |
566 | if (chip_ready(map, adr)) | |
567 | break; | |
568 | ||
569 | if (time_after(jiffies, timeo)) { | |
570 | printk(KERN_ERR "Waiting for chip to be ready timed out.\n"); | |
02b15e34 | 571 | spin_unlock(chip->mutex); |
1da177e4 LT |
572 | return -EIO; |
573 | } | |
02b15e34 | 574 | spin_unlock(chip->mutex); |
1da177e4 | 575 | cfi_udelay(1); |
02b15e34 | 576 | spin_lock(chip->mutex); |
1da177e4 LT |
577 | /* Someone else might have been playing with it. */ |
578 | goto retry; | |
579 | } | |
1f948b43 | 580 | |
1da177e4 LT |
581 | case FL_READY: |
582 | case FL_CFI_QUERY: | |
583 | case FL_JEDEC_QUERY: | |
584 | return 0; | |
585 | ||
586 | case FL_ERASING: | |
587 | if (mode == FL_WRITING) /* FIXME: Erase-suspend-program appears broken. */ | |
588 | goto sleep; | |
589 | ||
89072ef9 RJ |
590 | if (!( mode == FL_READY |
591 | || mode == FL_POINT | |
1da177e4 LT |
592 | || !cfip |
593 | || (mode == FL_WRITING && (cfip->EraseSuspend & 0x2)) | |
89072ef9 RJ |
594 | || (mode == FL_WRITING && (cfip->EraseSuspend & 0x1) |
595 | ))) | |
1da177e4 LT |
596 | goto sleep; |
597 | ||
598 | /* We could check to see if we're trying to access the sector | |
599 | * that is currently being erased. However, no user will try | |
600 | * anything like that so we just wait for the timeout. */ | |
601 | ||
602 | /* Erase suspend */ | |
603 | /* It's harmless to issue the Erase-Suspend and Erase-Resume | |
604 | * commands when the erase algorithm isn't in progress. */ | |
605 | map_write(map, CMD(0xB0), chip->in_progress_block_addr); | |
606 | chip->oldstate = FL_ERASING; | |
607 | chip->state = FL_ERASE_SUSPENDING; | |
608 | chip->erase_suspended = 1; | |
609 | for (;;) { | |
610 | if (chip_ready(map, adr)) | |
611 | break; | |
612 | ||
613 | if (time_after(jiffies, timeo)) { | |
614 | /* Should have suspended the erase by now. | |
615 | * Send an Erase-Resume command as either | |
616 | * there was an error (so leave the erase | |
617 | * routine to recover from it) or we trying to | |
618 | * use the erase-in-progress sector. */ | |
619 | map_write(map, CMD(0x30), chip->in_progress_block_addr); | |
620 | chip->state = FL_ERASING; | |
621 | chip->oldstate = FL_READY; | |
622 | printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__); | |
623 | return -EIO; | |
624 | } | |
1f948b43 | 625 | |
02b15e34 | 626 | spin_unlock(chip->mutex); |
1da177e4 | 627 | cfi_udelay(1); |
02b15e34 | 628 | spin_lock(chip->mutex); |
1da177e4 LT |
629 | /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING. |
630 | So we can just loop here. */ | |
631 | } | |
632 | chip->state = FL_READY; | |
633 | return 0; | |
634 | ||
02b15e34 TP |
635 | case FL_XIP_WHILE_ERASING: |
636 | if (mode != FL_READY && mode != FL_POINT && | |
637 | (!cfip || !(cfip->EraseSuspend&2))) | |
638 | goto sleep; | |
639 | chip->oldstate = chip->state; | |
640 | chip->state = FL_READY; | |
641 | return 0; | |
642 | ||
1da177e4 LT |
643 | case FL_POINT: |
644 | /* Only if there's no operation suspended... */ | |
645 | if (mode == FL_READY && chip->oldstate == FL_READY) | |
646 | return 0; | |
647 | ||
648 | default: | |
649 | sleep: | |
650 | set_current_state(TASK_UNINTERRUPTIBLE); | |
651 | add_wait_queue(&chip->wq, &wait); | |
02b15e34 | 652 | spin_unlock(chip->mutex); |
1da177e4 LT |
653 | schedule(); |
654 | remove_wait_queue(&chip->wq, &wait); | |
02b15e34 | 655 | spin_lock(chip->mutex); |
1da177e4 LT |
656 | goto resettime; |
657 | } | |
658 | } | |
659 | ||
660 | ||
661 | static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr) | |
662 | { | |
663 | struct cfi_private *cfi = map->fldrv_priv; | |
664 | ||
665 | switch(chip->oldstate) { | |
666 | case FL_ERASING: | |
667 | chip->state = chip->oldstate; | |
668 | map_write(map, CMD(0x30), chip->in_progress_block_addr); | |
669 | chip->oldstate = FL_READY; | |
670 | chip->state = FL_ERASING; | |
671 | break; | |
672 | ||
02b15e34 TP |
673 | case FL_XIP_WHILE_ERASING: |
674 | chip->state = chip->oldstate; | |
675 | chip->oldstate = FL_READY; | |
676 | break; | |
677 | ||
1da177e4 LT |
678 | case FL_READY: |
679 | case FL_STATUS: | |
680 | /* We should really make set_vpp() count, rather than doing this */ | |
681 | DISABLE_VPP(map); | |
682 | break; | |
683 | default: | |
684 | printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate); | |
685 | } | |
686 | wake_up(&chip->wq); | |
687 | } | |
688 | ||
02b15e34 TP |
689 | #ifdef CONFIG_MTD_XIP |
690 | ||
691 | /* | |
692 | * No interrupt what so ever can be serviced while the flash isn't in array | |
693 | * mode. This is ensured by the xip_disable() and xip_enable() functions | |
694 | * enclosing any code path where the flash is known not to be in array mode. | |
695 | * And within a XIP disabled code path, only functions marked with __xipram | |
696 | * may be called and nothing else (it's a good thing to inspect generated | |
697 | * assembly to make sure inline functions were actually inlined and that gcc | |
698 | * didn't emit calls to its own support functions). Also configuring MTD CFI | |
699 | * support to a single buswidth and a single interleave is also recommended. | |
700 | */ | |
f8eb321b | 701 | |
02b15e34 TP |
702 | static void xip_disable(struct map_info *map, struct flchip *chip, |
703 | unsigned long adr) | |
704 | { | |
705 | /* TODO: chips with no XIP use should ignore and return */ | |
706 | (void) map_read(map, adr); /* ensure mmu mapping is up to date */ | |
707 | local_irq_disable(); | |
708 | } | |
709 | ||
710 | static void __xipram xip_enable(struct map_info *map, struct flchip *chip, | |
711 | unsigned long adr) | |
712 | { | |
713 | struct cfi_private *cfi = map->fldrv_priv; | |
714 | ||
715 | if (chip->state != FL_POINT && chip->state != FL_READY) { | |
716 | map_write(map, CMD(0xf0), adr); | |
717 | chip->state = FL_READY; | |
718 | } | |
719 | (void) map_read(map, adr); | |
97f927a4 | 720 | xip_iprefetch(); |
02b15e34 TP |
721 | local_irq_enable(); |
722 | } | |
723 | ||
724 | /* | |
725 | * When a delay is required for the flash operation to complete, the | |
726 | * xip_udelay() function is polling for both the given timeout and pending | |
727 | * (but still masked) hardware interrupts. Whenever there is an interrupt | |
1f948b43 | 728 | * pending then the flash erase operation is suspended, array mode restored |
02b15e34 TP |
729 | * and interrupts unmasked. Task scheduling might also happen at that |
730 | * point. The CPU eventually returns from the interrupt or the call to | |
731 | * schedule() and the suspended flash operation is resumed for the remaining | |
732 | * of the delay period. | |
733 | * | |
734 | * Warning: this function _will_ fool interrupt latency tracing tools. | |
735 | */ | |
736 | ||
737 | static void __xipram xip_udelay(struct map_info *map, struct flchip *chip, | |
738 | unsigned long adr, int usec) | |
739 | { | |
740 | struct cfi_private *cfi = map->fldrv_priv; | |
741 | struct cfi_pri_amdstd *extp = cfi->cmdset_priv; | |
742 | map_word status, OK = CMD(0x80); | |
743 | unsigned long suspended, start = xip_currtime(); | |
744 | flstate_t oldstate; | |
745 | ||
746 | do { | |
747 | cpu_relax(); | |
748 | if (xip_irqpending() && extp && | |
749 | ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) && | |
750 | (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) { | |
751 | /* | |
1f948b43 TG |
752 | * Let's suspend the erase operation when supported. |
753 | * Note that we currently don't try to suspend | |
754 | * interleaved chips if there is already another | |
02b15e34 TP |
755 | * operation suspended (imagine what happens |
756 | * when one chip was already done with the current | |
757 | * operation while another chip suspended it, then | |
758 | * we resume the whole thing at once). Yes, it | |
759 | * can happen! | |
760 | */ | |
761 | map_write(map, CMD(0xb0), adr); | |
762 | usec -= xip_elapsed_since(start); | |
763 | suspended = xip_currtime(); | |
764 | do { | |
765 | if (xip_elapsed_since(suspended) > 100000) { | |
766 | /* | |
767 | * The chip doesn't want to suspend | |
768 | * after waiting for 100 msecs. | |
769 | * This is a critical error but there | |
770 | * is not much we can do here. | |
771 | */ | |
772 | return; | |
773 | } | |
774 | status = map_read(map, adr); | |
775 | } while (!map_word_andequal(map, status, OK, OK)); | |
776 | ||
777 | /* Suspend succeeded */ | |
778 | oldstate = chip->state; | |
779 | if (!map_word_bitsset(map, status, CMD(0x40))) | |
780 | break; | |
781 | chip->state = FL_XIP_WHILE_ERASING; | |
782 | chip->erase_suspended = 1; | |
783 | map_write(map, CMD(0xf0), adr); | |
784 | (void) map_read(map, adr); | |
ca5c23c3 | 785 | xip_iprefetch(); |
02b15e34 TP |
786 | local_irq_enable(); |
787 | spin_unlock(chip->mutex); | |
ca5c23c3 | 788 | xip_iprefetch(); |
02b15e34 TP |
789 | cond_resched(); |
790 | ||
791 | /* | |
792 | * We're back. However someone else might have | |
793 | * decided to go write to the chip if we are in | |
794 | * a suspended erase state. If so let's wait | |
795 | * until it's done. | |
796 | */ | |
797 | spin_lock(chip->mutex); | |
798 | while (chip->state != FL_XIP_WHILE_ERASING) { | |
799 | DECLARE_WAITQUEUE(wait, current); | |
800 | set_current_state(TASK_UNINTERRUPTIBLE); | |
801 | add_wait_queue(&chip->wq, &wait); | |
802 | spin_unlock(chip->mutex); | |
803 | schedule(); | |
804 | remove_wait_queue(&chip->wq, &wait); | |
805 | spin_lock(chip->mutex); | |
806 | } | |
807 | /* Disallow XIP again */ | |
808 | local_irq_disable(); | |
809 | ||
810 | /* Resume the write or erase operation */ | |
811 | map_write(map, CMD(0x30), adr); | |
812 | chip->state = oldstate; | |
813 | start = xip_currtime(); | |
814 | } else if (usec >= 1000000/HZ) { | |
815 | /* | |
816 | * Try to save on CPU power when waiting delay | |
817 | * is at least a system timer tick period. | |
818 | * No need to be extremely accurate here. | |
819 | */ | |
820 | xip_cpu_idle(); | |
821 | } | |
822 | status = map_read(map, adr); | |
823 | } while (!map_word_andequal(map, status, OK, OK) | |
824 | && xip_elapsed_since(start) < usec); | |
825 | } | |
826 | ||
827 | #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec) | |
828 | ||
829 | /* | |
830 | * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while | |
831 | * the flash is actively programming or erasing since we have to poll for | |
832 | * the operation to complete anyway. We can't do that in a generic way with | |
833 | * a XIP setup so do it before the actual flash operation in this case | |
834 | * and stub it out from INVALIDATE_CACHE_UDELAY. | |
835 | */ | |
836 | #define XIP_INVAL_CACHED_RANGE(map, from, size) \ | |
837 | INVALIDATE_CACHED_RANGE(map, from, size) | |
838 | ||
839 | #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \ | |
840 | UDELAY(map, chip, adr, usec) | |
841 | ||
842 | /* | |
843 | * Extra notes: | |
844 | * | |
845 | * Activating this XIP support changes the way the code works a bit. For | |
846 | * example the code to suspend the current process when concurrent access | |
847 | * happens is never executed because xip_udelay() will always return with the | |
848 | * same chip state as it was entered with. This is why there is no care for | |
849 | * the presence of add_wait_queue() or schedule() calls from within a couple | |
850 | * xip_disable()'d areas of code, like in do_erase_oneblock for example. | |
851 | * The queueing and scheduling are always happening within xip_udelay(). | |
852 | * | |
853 | * Similarly, get_chip() and put_chip() just happen to always be executed | |
854 | * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state | |
855 | * is in array mode, therefore never executing many cases therein and not | |
856 | * causing any problem with XIP. | |
857 | */ | |
858 | ||
859 | #else | |
860 | ||
861 | #define xip_disable(map, chip, adr) | |
862 | #define xip_enable(map, chip, adr) | |
863 | #define XIP_INVAL_CACHED_RANGE(x...) | |
864 | ||
865 | #define UDELAY(map, chip, adr, usec) \ | |
866 | do { \ | |
867 | spin_unlock(chip->mutex); \ | |
868 | cfi_udelay(usec); \ | |
869 | spin_lock(chip->mutex); \ | |
870 | } while (0) | |
871 | ||
872 | #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \ | |
873 | do { \ | |
874 | spin_unlock(chip->mutex); \ | |
875 | INVALIDATE_CACHED_RANGE(map, adr, len); \ | |
876 | cfi_udelay(usec); \ | |
877 | spin_lock(chip->mutex); \ | |
878 | } while (0) | |
879 | ||
880 | #endif | |
1da177e4 LT |
881 | |
882 | static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf) | |
883 | { | |
884 | unsigned long cmd_addr; | |
885 | struct cfi_private *cfi = map->fldrv_priv; | |
886 | int ret; | |
887 | ||
888 | adr += chip->start; | |
889 | ||
1f948b43 TG |
890 | /* Ensure cmd read/writes are aligned. */ |
891 | cmd_addr = adr & ~(map_bankwidth(map)-1); | |
1da177e4 | 892 | |
02b15e34 | 893 | spin_lock(chip->mutex); |
1da177e4 LT |
894 | ret = get_chip(map, chip, cmd_addr, FL_READY); |
895 | if (ret) { | |
02b15e34 | 896 | spin_unlock(chip->mutex); |
1da177e4 LT |
897 | return ret; |
898 | } | |
899 | ||
900 | if (chip->state != FL_POINT && chip->state != FL_READY) { | |
901 | map_write(map, CMD(0xf0), cmd_addr); | |
902 | chip->state = FL_READY; | |
903 | } | |
904 | ||
905 | map_copy_from(map, buf, adr, len); | |
906 | ||
907 | put_chip(map, chip, cmd_addr); | |
908 | ||
02b15e34 | 909 | spin_unlock(chip->mutex); |
1da177e4 LT |
910 | return 0; |
911 | } | |
912 | ||
913 | ||
914 | static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) | |
915 | { | |
916 | struct map_info *map = mtd->priv; | |
917 | struct cfi_private *cfi = map->fldrv_priv; | |
918 | unsigned long ofs; | |
919 | int chipnum; | |
920 | int ret = 0; | |
921 | ||
922 | /* ofs: offset within the first chip that the first read should start */ | |
923 | ||
924 | chipnum = (from >> cfi->chipshift); | |
925 | ofs = from - (chipnum << cfi->chipshift); | |
926 | ||
927 | ||
928 | *retlen = 0; | |
929 | ||
930 | while (len) { | |
931 | unsigned long thislen; | |
932 | ||
933 | if (chipnum >= cfi->numchips) | |
934 | break; | |
935 | ||
936 | if ((len + ofs -1) >> cfi->chipshift) | |
937 | thislen = (1<<cfi->chipshift) - ofs; | |
938 | else | |
939 | thislen = len; | |
940 | ||
941 | ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf); | |
942 | if (ret) | |
943 | break; | |
944 | ||
945 | *retlen += thislen; | |
946 | len -= thislen; | |
947 | buf += thislen; | |
948 | ||
949 | ofs = 0; | |
950 | chipnum++; | |
951 | } | |
952 | return ret; | |
953 | } | |
954 | ||
955 | ||
956 | static inline int do_read_secsi_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf) | |
957 | { | |
958 | DECLARE_WAITQUEUE(wait, current); | |
959 | unsigned long timeo = jiffies + HZ; | |
960 | struct cfi_private *cfi = map->fldrv_priv; | |
961 | ||
962 | retry: | |
02b15e34 | 963 | spin_lock(chip->mutex); |
1da177e4 LT |
964 | |
965 | if (chip->state != FL_READY){ | |
966 | #if 0 | |
967 | printk(KERN_DEBUG "Waiting for chip to read, status = %d\n", chip->state); | |
968 | #endif | |
969 | set_current_state(TASK_UNINTERRUPTIBLE); | |
970 | add_wait_queue(&chip->wq, &wait); | |
1f948b43 | 971 | |
02b15e34 | 972 | spin_unlock(chip->mutex); |
1da177e4 LT |
973 | |
974 | schedule(); | |
975 | remove_wait_queue(&chip->wq, &wait); | |
976 | #if 0 | |
977 | if(signal_pending(current)) | |
978 | return -EINTR; | |
979 | #endif | |
980 | timeo = jiffies + HZ; | |
981 | ||
982 | goto retry; | |
1f948b43 | 983 | } |
1da177e4 LT |
984 | |
985 | adr += chip->start; | |
986 | ||
987 | chip->state = FL_READY; | |
988 | ||
989 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
990 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
991 | cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1f948b43 | 992 | |
1da177e4 LT |
993 | map_copy_from(map, buf, adr, len); |
994 | ||
995 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
996 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
997 | cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
998 | cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1f948b43 | 999 | |
1da177e4 | 1000 | wake_up(&chip->wq); |
02b15e34 | 1001 | spin_unlock(chip->mutex); |
1da177e4 LT |
1002 | |
1003 | return 0; | |
1004 | } | |
1005 | ||
1006 | static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) | |
1007 | { | |
1008 | struct map_info *map = mtd->priv; | |
1009 | struct cfi_private *cfi = map->fldrv_priv; | |
1010 | unsigned long ofs; | |
1011 | int chipnum; | |
1012 | int ret = 0; | |
1013 | ||
1014 | ||
1015 | /* ofs: offset within the first chip that the first read should start */ | |
1016 | ||
1017 | /* 8 secsi bytes per chip */ | |
1018 | chipnum=from>>3; | |
1019 | ofs=from & 7; | |
1020 | ||
1021 | ||
1022 | *retlen = 0; | |
1023 | ||
1024 | while (len) { | |
1025 | unsigned long thislen; | |
1026 | ||
1027 | if (chipnum >= cfi->numchips) | |
1028 | break; | |
1029 | ||
1030 | if ((len + ofs -1) >> 3) | |
1031 | thislen = (1<<3) - ofs; | |
1032 | else | |
1033 | thislen = len; | |
1034 | ||
1035 | ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf); | |
1036 | if (ret) | |
1037 | break; | |
1038 | ||
1039 | *retlen += thislen; | |
1040 | len -= thislen; | |
1041 | buf += thislen; | |
1042 | ||
1043 | ofs = 0; | |
1044 | chipnum++; | |
1045 | } | |
1046 | return ret; | |
1047 | } | |
1048 | ||
1049 | ||
02b15e34 | 1050 | static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, unsigned long adr, map_word datum) |
1da177e4 LT |
1051 | { |
1052 | struct cfi_private *cfi = map->fldrv_priv; | |
1053 | unsigned long timeo = jiffies + HZ; | |
1054 | /* | |
1055 | * We use a 1ms + 1 jiffies generic timeout for writes (most devices | |
1056 | * have a max write time of a few hundreds usec). However, we should | |
1057 | * use the maximum timeout value given by the chip at probe time | |
1058 | * instead. Unfortunately, struct flchip does have a field for | |
1059 | * maximum timeout, only for typical which can be far too short | |
1060 | * depending of the conditions. The ' + 1' is to avoid having a | |
1061 | * timeout of 0 jiffies if HZ is smaller than 1000. | |
1062 | */ | |
1063 | unsigned long uWriteTimeout = ( HZ / 1000 ) + 1; | |
1064 | int ret = 0; | |
1065 | map_word oldd; | |
1066 | int retry_cnt = 0; | |
1067 | ||
1068 | adr += chip->start; | |
1069 | ||
02b15e34 | 1070 | spin_lock(chip->mutex); |
1da177e4 LT |
1071 | ret = get_chip(map, chip, adr, FL_WRITING); |
1072 | if (ret) { | |
02b15e34 | 1073 | spin_unlock(chip->mutex); |
1da177e4 LT |
1074 | return ret; |
1075 | } | |
1076 | ||
1077 | DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n", | |
1078 | __func__, adr, datum.x[0] ); | |
1079 | ||
1080 | /* | |
1081 | * Check for a NOP for the case when the datum to write is already | |
1082 | * present - it saves time and works around buggy chips that corrupt | |
1083 | * data at other locations when 0xff is written to a location that | |
1084 | * already contains 0xff. | |
1085 | */ | |
1086 | oldd = map_read(map, adr); | |
1087 | if (map_word_equal(map, oldd, datum)) { | |
1088 | DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): NOP\n", | |
1089 | __func__); | |
1090 | goto op_done; | |
1091 | } | |
1092 | ||
02b15e34 | 1093 | XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map)); |
1da177e4 | 1094 | ENABLE_VPP(map); |
02b15e34 | 1095 | xip_disable(map, chip, adr); |
1da177e4 LT |
1096 | retry: |
1097 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1098 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1099 | cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1100 | map_write(map, datum, adr); | |
1101 | chip->state = FL_WRITING; | |
1102 | ||
02b15e34 TP |
1103 | INVALIDATE_CACHE_UDELAY(map, chip, |
1104 | adr, map_bankwidth(map), | |
1105 | chip->word_write_time); | |
1da177e4 LT |
1106 | |
1107 | /* See comment above for timeout value. */ | |
1f948b43 | 1108 | timeo = jiffies + uWriteTimeout; |
1da177e4 LT |
1109 | for (;;) { |
1110 | if (chip->state != FL_WRITING) { | |
1111 | /* Someone's suspended the write. Sleep */ | |
1112 | DECLARE_WAITQUEUE(wait, current); | |
1113 | ||
1114 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1115 | add_wait_queue(&chip->wq, &wait); | |
02b15e34 | 1116 | spin_unlock(chip->mutex); |
1da177e4 LT |
1117 | schedule(); |
1118 | remove_wait_queue(&chip->wq, &wait); | |
1119 | timeo = jiffies + (HZ / 2); /* FIXME */ | |
02b15e34 | 1120 | spin_lock(chip->mutex); |
1da177e4 LT |
1121 | continue; |
1122 | } | |
1123 | ||
b95f9609 | 1124 | if (time_after(jiffies, timeo) && !chip_ready(map, adr)){ |
02b15e34 | 1125 | xip_enable(map, chip, adr); |
fb4a90bf | 1126 | printk(KERN_WARNING "MTD %s(): software timeout\n", __func__); |
02b15e34 | 1127 | xip_disable(map, chip, adr); |
b95f9609 | 1128 | break; |
fb4a90bf | 1129 | } |
1da177e4 | 1130 | |
b95f9609 KB |
1131 | if (chip_ready(map, adr)) |
1132 | break; | |
1133 | ||
1da177e4 | 1134 | /* Latency issues. Drop the lock, wait a while and retry */ |
02b15e34 | 1135 | UDELAY(map, chip, adr, 1); |
1da177e4 | 1136 | } |
fb4a90bf EB |
1137 | /* Did we succeed? */ |
1138 | if (!chip_good(map, adr, datum)) { | |
1139 | /* reset on all failures. */ | |
1140 | map_write( map, CMD(0xF0), chip->start ); | |
1141 | /* FIXME - should have reset delay before continuing */ | |
1da177e4 | 1142 | |
1f948b43 | 1143 | if (++retry_cnt <= MAX_WORD_RETRIES) |
fb4a90bf | 1144 | goto retry; |
1da177e4 | 1145 | |
fb4a90bf EB |
1146 | ret = -EIO; |
1147 | } | |
02b15e34 | 1148 | xip_enable(map, chip, adr); |
1da177e4 LT |
1149 | op_done: |
1150 | chip->state = FL_READY; | |
1151 | put_chip(map, chip, adr); | |
02b15e34 | 1152 | spin_unlock(chip->mutex); |
1da177e4 LT |
1153 | |
1154 | return ret; | |
1155 | } | |
1156 | ||
1157 | ||
1158 | static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len, | |
1159 | size_t *retlen, const u_char *buf) | |
1160 | { | |
1161 | struct map_info *map = mtd->priv; | |
1162 | struct cfi_private *cfi = map->fldrv_priv; | |
1163 | int ret = 0; | |
1164 | int chipnum; | |
1165 | unsigned long ofs, chipstart; | |
1166 | DECLARE_WAITQUEUE(wait, current); | |
1167 | ||
1168 | *retlen = 0; | |
1169 | if (!len) | |
1170 | return 0; | |
1171 | ||
1172 | chipnum = to >> cfi->chipshift; | |
1173 | ofs = to - (chipnum << cfi->chipshift); | |
1174 | chipstart = cfi->chips[chipnum].start; | |
1175 | ||
1176 | /* If it's not bus-aligned, do the first byte write */ | |
1177 | if (ofs & (map_bankwidth(map)-1)) { | |
1178 | unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1); | |
1179 | int i = ofs - bus_ofs; | |
1180 | int n = 0; | |
1181 | map_word tmp_buf; | |
1182 | ||
1183 | retry: | |
02b15e34 | 1184 | spin_lock(cfi->chips[chipnum].mutex); |
1da177e4 LT |
1185 | |
1186 | if (cfi->chips[chipnum].state != FL_READY) { | |
1187 | #if 0 | |
1188 | printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state); | |
1189 | #endif | |
1190 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1191 | add_wait_queue(&cfi->chips[chipnum].wq, &wait); | |
1192 | ||
02b15e34 | 1193 | spin_unlock(cfi->chips[chipnum].mutex); |
1da177e4 LT |
1194 | |
1195 | schedule(); | |
1196 | remove_wait_queue(&cfi->chips[chipnum].wq, &wait); | |
1197 | #if 0 | |
1198 | if(signal_pending(current)) | |
1199 | return -EINTR; | |
1200 | #endif | |
1201 | goto retry; | |
1202 | } | |
1203 | ||
1204 | /* Load 'tmp_buf' with old contents of flash */ | |
1205 | tmp_buf = map_read(map, bus_ofs+chipstart); | |
1206 | ||
02b15e34 | 1207 | spin_unlock(cfi->chips[chipnum].mutex); |
1da177e4 LT |
1208 | |
1209 | /* Number of bytes to copy from buffer */ | |
1210 | n = min_t(int, len, map_bankwidth(map)-i); | |
1f948b43 | 1211 | |
1da177e4 LT |
1212 | tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n); |
1213 | ||
1f948b43 | 1214 | ret = do_write_oneword(map, &cfi->chips[chipnum], |
1da177e4 | 1215 | bus_ofs, tmp_buf); |
1f948b43 | 1216 | if (ret) |
1da177e4 | 1217 | return ret; |
1f948b43 | 1218 | |
1da177e4 LT |
1219 | ofs += n; |
1220 | buf += n; | |
1221 | (*retlen) += n; | |
1222 | len -= n; | |
1223 | ||
1224 | if (ofs >> cfi->chipshift) { | |
1f948b43 | 1225 | chipnum ++; |
1da177e4 LT |
1226 | ofs = 0; |
1227 | if (chipnum == cfi->numchips) | |
1228 | return 0; | |
1229 | } | |
1230 | } | |
1f948b43 | 1231 | |
1da177e4 LT |
1232 | /* We are now aligned, write as much as possible */ |
1233 | while(len >= map_bankwidth(map)) { | |
1234 | map_word datum; | |
1235 | ||
1236 | datum = map_word_load(map, buf); | |
1237 | ||
1238 | ret = do_write_oneword(map, &cfi->chips[chipnum], | |
1239 | ofs, datum); | |
1240 | if (ret) | |
1241 | return ret; | |
1242 | ||
1243 | ofs += map_bankwidth(map); | |
1244 | buf += map_bankwidth(map); | |
1245 | (*retlen) += map_bankwidth(map); | |
1246 | len -= map_bankwidth(map); | |
1247 | ||
1248 | if (ofs >> cfi->chipshift) { | |
1f948b43 | 1249 | chipnum ++; |
1da177e4 LT |
1250 | ofs = 0; |
1251 | if (chipnum == cfi->numchips) | |
1252 | return 0; | |
1253 | chipstart = cfi->chips[chipnum].start; | |
1254 | } | |
1255 | } | |
1256 | ||
1257 | /* Write the trailing bytes if any */ | |
1258 | if (len & (map_bankwidth(map)-1)) { | |
1259 | map_word tmp_buf; | |
1260 | ||
1261 | retry1: | |
02b15e34 | 1262 | spin_lock(cfi->chips[chipnum].mutex); |
1da177e4 LT |
1263 | |
1264 | if (cfi->chips[chipnum].state != FL_READY) { | |
1265 | #if 0 | |
1266 | printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state); | |
1267 | #endif | |
1268 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1269 | add_wait_queue(&cfi->chips[chipnum].wq, &wait); | |
1270 | ||
02b15e34 | 1271 | spin_unlock(cfi->chips[chipnum].mutex); |
1da177e4 LT |
1272 | |
1273 | schedule(); | |
1274 | remove_wait_queue(&cfi->chips[chipnum].wq, &wait); | |
1275 | #if 0 | |
1276 | if(signal_pending(current)) | |
1277 | return -EINTR; | |
1278 | #endif | |
1279 | goto retry1; | |
1280 | } | |
1281 | ||
1282 | tmp_buf = map_read(map, ofs + chipstart); | |
1283 | ||
02b15e34 | 1284 | spin_unlock(cfi->chips[chipnum].mutex); |
1da177e4 LT |
1285 | |
1286 | tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len); | |
1f948b43 TG |
1287 | |
1288 | ret = do_write_oneword(map, &cfi->chips[chipnum], | |
1da177e4 | 1289 | ofs, tmp_buf); |
1f948b43 | 1290 | if (ret) |
1da177e4 | 1291 | return ret; |
1f948b43 | 1292 | |
1da177e4 LT |
1293 | (*retlen) += len; |
1294 | } | |
1295 | ||
1296 | return 0; | |
1297 | } | |
1298 | ||
1299 | ||
1300 | /* | |
1301 | * FIXME: interleaved mode not tested, and probably not supported! | |
1302 | */ | |
02b15e34 | 1303 | static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip, |
1f948b43 | 1304 | unsigned long adr, const u_char *buf, |
02b15e34 | 1305 | int len) |
1da177e4 LT |
1306 | { |
1307 | struct cfi_private *cfi = map->fldrv_priv; | |
1308 | unsigned long timeo = jiffies + HZ; | |
1309 | /* see comments in do_write_oneword() regarding uWriteTimeo. */ | |
1310 | unsigned long uWriteTimeout = ( HZ / 1000 ) + 1; | |
1311 | int ret = -EIO; | |
1312 | unsigned long cmd_adr; | |
1313 | int z, words; | |
1314 | map_word datum; | |
1315 | ||
1316 | adr += chip->start; | |
1317 | cmd_adr = adr; | |
1318 | ||
02b15e34 | 1319 | spin_lock(chip->mutex); |
1da177e4 LT |
1320 | ret = get_chip(map, chip, adr, FL_WRITING); |
1321 | if (ret) { | |
02b15e34 | 1322 | spin_unlock(chip->mutex); |
1da177e4 LT |
1323 | return ret; |
1324 | } | |
1325 | ||
1326 | datum = map_word_load(map, buf); | |
1327 | ||
1328 | DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n", | |
1329 | __func__, adr, datum.x[0] ); | |
1330 | ||
02b15e34 | 1331 | XIP_INVAL_CACHED_RANGE(map, adr, len); |
1da177e4 | 1332 | ENABLE_VPP(map); |
02b15e34 | 1333 | xip_disable(map, chip, cmd_adr); |
1f948b43 | 1334 | |
1da177e4 LT |
1335 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); |
1336 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1337 | //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1338 | ||
1339 | /* Write Buffer Load */ | |
1340 | map_write(map, CMD(0x25), cmd_adr); | |
1341 | ||
1342 | chip->state = FL_WRITING_TO_BUFFER; | |
1343 | ||
1344 | /* Write length of data to come */ | |
1345 | words = len / map_bankwidth(map); | |
1346 | map_write(map, CMD(words - 1), cmd_adr); | |
1347 | /* Write data */ | |
1348 | z = 0; | |
1349 | while(z < words * map_bankwidth(map)) { | |
1350 | datum = map_word_load(map, buf); | |
1351 | map_write(map, datum, adr + z); | |
1352 | ||
1353 | z += map_bankwidth(map); | |
1354 | buf += map_bankwidth(map); | |
1355 | } | |
1356 | z -= map_bankwidth(map); | |
1357 | ||
1358 | adr += z; | |
1359 | ||
1360 | /* Write Buffer Program Confirm: GO GO GO */ | |
1361 | map_write(map, CMD(0x29), cmd_adr); | |
1362 | chip->state = FL_WRITING; | |
1363 | ||
02b15e34 TP |
1364 | INVALIDATE_CACHE_UDELAY(map, chip, |
1365 | adr, map_bankwidth(map), | |
1366 | chip->word_write_time); | |
1da177e4 | 1367 | |
1f948b43 TG |
1368 | timeo = jiffies + uWriteTimeout; |
1369 | ||
1da177e4 LT |
1370 | for (;;) { |
1371 | if (chip->state != FL_WRITING) { | |
1372 | /* Someone's suspended the write. Sleep */ | |
1373 | DECLARE_WAITQUEUE(wait, current); | |
1374 | ||
1375 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1376 | add_wait_queue(&chip->wq, &wait); | |
02b15e34 | 1377 | spin_unlock(chip->mutex); |
1da177e4 LT |
1378 | schedule(); |
1379 | remove_wait_queue(&chip->wq, &wait); | |
1380 | timeo = jiffies + (HZ / 2); /* FIXME */ | |
02b15e34 | 1381 | spin_lock(chip->mutex); |
1da177e4 LT |
1382 | continue; |
1383 | } | |
1384 | ||
b95f9609 KB |
1385 | if (time_after(jiffies, timeo) && !chip_ready(map, adr)) |
1386 | break; | |
1387 | ||
02b15e34 TP |
1388 | if (chip_ready(map, adr)) { |
1389 | xip_enable(map, chip, adr); | |
1da177e4 | 1390 | goto op_done; |
02b15e34 | 1391 | } |
1da177e4 LT |
1392 | |
1393 | /* Latency issues. Drop the lock, wait a while and retry */ | |
02b15e34 | 1394 | UDELAY(map, chip, adr, 1); |
1da177e4 LT |
1395 | } |
1396 | ||
1da177e4 LT |
1397 | /* reset on all failures. */ |
1398 | map_write( map, CMD(0xF0), chip->start ); | |
02b15e34 | 1399 | xip_enable(map, chip, adr); |
1da177e4 LT |
1400 | /* FIXME - should have reset delay before continuing */ |
1401 | ||
02b15e34 TP |
1402 | printk(KERN_WARNING "MTD %s(): software timeout\n", |
1403 | __func__ ); | |
1404 | ||
1da177e4 LT |
1405 | ret = -EIO; |
1406 | op_done: | |
1407 | chip->state = FL_READY; | |
1408 | put_chip(map, chip, adr); | |
02b15e34 | 1409 | spin_unlock(chip->mutex); |
1da177e4 LT |
1410 | |
1411 | return ret; | |
1412 | } | |
1413 | ||
1414 | ||
1415 | static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len, | |
1416 | size_t *retlen, const u_char *buf) | |
1417 | { | |
1418 | struct map_info *map = mtd->priv; | |
1419 | struct cfi_private *cfi = map->fldrv_priv; | |
1420 | int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize; | |
1421 | int ret = 0; | |
1422 | int chipnum; | |
1423 | unsigned long ofs; | |
1424 | ||
1425 | *retlen = 0; | |
1426 | if (!len) | |
1427 | return 0; | |
1428 | ||
1429 | chipnum = to >> cfi->chipshift; | |
1430 | ofs = to - (chipnum << cfi->chipshift); | |
1431 | ||
1432 | /* If it's not bus-aligned, do the first word write */ | |
1433 | if (ofs & (map_bankwidth(map)-1)) { | |
1434 | size_t local_len = (-ofs)&(map_bankwidth(map)-1); | |
1435 | if (local_len > len) | |
1436 | local_len = len; | |
1437 | ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift), | |
1438 | local_len, retlen, buf); | |
1439 | if (ret) | |
1440 | return ret; | |
1441 | ofs += local_len; | |
1442 | buf += local_len; | |
1443 | len -= local_len; | |
1444 | ||
1445 | if (ofs >> cfi->chipshift) { | |
1446 | chipnum ++; | |
1447 | ofs = 0; | |
1448 | if (chipnum == cfi->numchips) | |
1449 | return 0; | |
1450 | } | |
1451 | } | |
1452 | ||
1453 | /* Write buffer is worth it only if more than one word to write... */ | |
1454 | while (len >= map_bankwidth(map) * 2) { | |
1455 | /* We must not cross write block boundaries */ | |
1456 | int size = wbufsize - (ofs & (wbufsize-1)); | |
1457 | ||
1458 | if (size > len) | |
1459 | size = len; | |
1460 | if (size % map_bankwidth(map)) | |
1461 | size -= size % map_bankwidth(map); | |
1462 | ||
1f948b43 | 1463 | ret = do_write_buffer(map, &cfi->chips[chipnum], |
1da177e4 LT |
1464 | ofs, buf, size); |
1465 | if (ret) | |
1466 | return ret; | |
1467 | ||
1468 | ofs += size; | |
1469 | buf += size; | |
1470 | (*retlen) += size; | |
1471 | len -= size; | |
1472 | ||
1473 | if (ofs >> cfi->chipshift) { | |
1f948b43 | 1474 | chipnum ++; |
1da177e4 LT |
1475 | ofs = 0; |
1476 | if (chipnum == cfi->numchips) | |
1477 | return 0; | |
1478 | } | |
1479 | } | |
1480 | ||
1481 | if (len) { | |
1482 | size_t retlen_dregs = 0; | |
1483 | ||
1484 | ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift), | |
1485 | len, &retlen_dregs, buf); | |
1486 | ||
1487 | *retlen += retlen_dregs; | |
1488 | return ret; | |
1489 | } | |
1490 | ||
1491 | return 0; | |
1492 | } | |
1493 | ||
1494 | ||
1495 | /* | |
1496 | * Handle devices with one erase region, that only implement | |
1497 | * the chip erase command. | |
1498 | */ | |
02b15e34 | 1499 | static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip) |
1da177e4 LT |
1500 | { |
1501 | struct cfi_private *cfi = map->fldrv_priv; | |
1502 | unsigned long timeo = jiffies + HZ; | |
1503 | unsigned long int adr; | |
1504 | DECLARE_WAITQUEUE(wait, current); | |
1505 | int ret = 0; | |
1506 | ||
1507 | adr = cfi->addr_unlock1; | |
1508 | ||
02b15e34 | 1509 | spin_lock(chip->mutex); |
1da177e4 LT |
1510 | ret = get_chip(map, chip, adr, FL_WRITING); |
1511 | if (ret) { | |
02b15e34 | 1512 | spin_unlock(chip->mutex); |
1da177e4 LT |
1513 | return ret; |
1514 | } | |
1515 | ||
1516 | DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n", | |
1517 | __func__, chip->start ); | |
1518 | ||
02b15e34 | 1519 | XIP_INVAL_CACHED_RANGE(map, adr, map->size); |
1da177e4 | 1520 | ENABLE_VPP(map); |
02b15e34 TP |
1521 | xip_disable(map, chip, adr); |
1522 | ||
1da177e4 LT |
1523 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); |
1524 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1525 | cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1526 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1527 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1528 | cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1529 | ||
1530 | chip->state = FL_ERASING; | |
1531 | chip->erase_suspended = 0; | |
1532 | chip->in_progress_block_addr = adr; | |
1533 | ||
02b15e34 TP |
1534 | INVALIDATE_CACHE_UDELAY(map, chip, |
1535 | adr, map->size, | |
1536 | chip->erase_time*500); | |
1da177e4 LT |
1537 | |
1538 | timeo = jiffies + (HZ*20); | |
1539 | ||
1540 | for (;;) { | |
1541 | if (chip->state != FL_ERASING) { | |
1542 | /* Someone's suspended the erase. Sleep */ | |
1543 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1544 | add_wait_queue(&chip->wq, &wait); | |
02b15e34 | 1545 | spin_unlock(chip->mutex); |
1da177e4 LT |
1546 | schedule(); |
1547 | remove_wait_queue(&chip->wq, &wait); | |
02b15e34 | 1548 | spin_lock(chip->mutex); |
1da177e4 LT |
1549 | continue; |
1550 | } | |
1551 | if (chip->erase_suspended) { | |
1552 | /* This erase was suspended and resumed. | |
1553 | Adjust the timeout */ | |
1554 | timeo = jiffies + (HZ*20); /* FIXME */ | |
1555 | chip->erase_suspended = 0; | |
1556 | } | |
1557 | ||
1558 | if (chip_ready(map, adr)) | |
fb4a90bf | 1559 | break; |
1da177e4 | 1560 | |
fb4a90bf EB |
1561 | if (time_after(jiffies, timeo)) { |
1562 | printk(KERN_WARNING "MTD %s(): software timeout\n", | |
1563 | __func__ ); | |
1da177e4 | 1564 | break; |
fb4a90bf | 1565 | } |
1da177e4 LT |
1566 | |
1567 | /* Latency issues. Drop the lock, wait a while and retry */ | |
02b15e34 | 1568 | UDELAY(map, chip, adr, 1000000/HZ); |
1da177e4 | 1569 | } |
fb4a90bf EB |
1570 | /* Did we succeed? */ |
1571 | if (!chip_good(map, adr, map_word_ff(map))) { | |
1572 | /* reset on all failures. */ | |
1573 | map_write( map, CMD(0xF0), chip->start ); | |
1574 | /* FIXME - should have reset delay before continuing */ | |
1da177e4 | 1575 | |
fb4a90bf EB |
1576 | ret = -EIO; |
1577 | } | |
1da177e4 | 1578 | |
1da177e4 | 1579 | chip->state = FL_READY; |
02b15e34 | 1580 | xip_enable(map, chip, adr); |
1da177e4 | 1581 | put_chip(map, chip, adr); |
02b15e34 | 1582 | spin_unlock(chip->mutex); |
1da177e4 LT |
1583 | |
1584 | return ret; | |
1585 | } | |
1586 | ||
1587 | ||
02b15e34 | 1588 | static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk) |
1da177e4 LT |
1589 | { |
1590 | struct cfi_private *cfi = map->fldrv_priv; | |
1591 | unsigned long timeo = jiffies + HZ; | |
1592 | DECLARE_WAITQUEUE(wait, current); | |
1593 | int ret = 0; | |
1594 | ||
1595 | adr += chip->start; | |
1596 | ||
02b15e34 | 1597 | spin_lock(chip->mutex); |
1da177e4 LT |
1598 | ret = get_chip(map, chip, adr, FL_ERASING); |
1599 | if (ret) { | |
02b15e34 | 1600 | spin_unlock(chip->mutex); |
1da177e4 LT |
1601 | return ret; |
1602 | } | |
1603 | ||
1604 | DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n", | |
1605 | __func__, adr ); | |
1606 | ||
02b15e34 | 1607 | XIP_INVAL_CACHED_RANGE(map, adr, len); |
1da177e4 | 1608 | ENABLE_VPP(map); |
02b15e34 TP |
1609 | xip_disable(map, chip, adr); |
1610 | ||
1da177e4 LT |
1611 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); |
1612 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1613 | cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1614 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); | |
1615 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); | |
1616 | map_write(map, CMD(0x30), adr); | |
1617 | ||
1618 | chip->state = FL_ERASING; | |
1619 | chip->erase_suspended = 0; | |
1620 | chip->in_progress_block_addr = adr; | |
02b15e34 TP |
1621 | |
1622 | INVALIDATE_CACHE_UDELAY(map, chip, | |
1623 | adr, len, | |
1624 | chip->erase_time*500); | |
1da177e4 LT |
1625 | |
1626 | timeo = jiffies + (HZ*20); | |
1627 | ||
1628 | for (;;) { | |
1629 | if (chip->state != FL_ERASING) { | |
1630 | /* Someone's suspended the erase. Sleep */ | |
1631 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1632 | add_wait_queue(&chip->wq, &wait); | |
02b15e34 | 1633 | spin_unlock(chip->mutex); |
1da177e4 LT |
1634 | schedule(); |
1635 | remove_wait_queue(&chip->wq, &wait); | |
02b15e34 | 1636 | spin_lock(chip->mutex); |
1da177e4 LT |
1637 | continue; |
1638 | } | |
1639 | if (chip->erase_suspended) { | |
1640 | /* This erase was suspended and resumed. | |
1641 | Adjust the timeout */ | |
1642 | timeo = jiffies + (HZ*20); /* FIXME */ | |
1643 | chip->erase_suspended = 0; | |
1644 | } | |
1645 | ||
02b15e34 TP |
1646 | if (chip_ready(map, adr)) { |
1647 | xip_enable(map, chip, adr); | |
fb4a90bf | 1648 | break; |
02b15e34 | 1649 | } |
1da177e4 | 1650 | |
fb4a90bf | 1651 | if (time_after(jiffies, timeo)) { |
02b15e34 | 1652 | xip_enable(map, chip, adr); |
fb4a90bf EB |
1653 | printk(KERN_WARNING "MTD %s(): software timeout\n", |
1654 | __func__ ); | |
1da177e4 | 1655 | break; |
fb4a90bf | 1656 | } |
1da177e4 LT |
1657 | |
1658 | /* Latency issues. Drop the lock, wait a while and retry */ | |
02b15e34 | 1659 | UDELAY(map, chip, adr, 1000000/HZ); |
1da177e4 | 1660 | } |
fb4a90bf | 1661 | /* Did we succeed? */ |
22fd9a87 | 1662 | if (!chip_good(map, adr, map_word_ff(map))) { |
fb4a90bf EB |
1663 | /* reset on all failures. */ |
1664 | map_write( map, CMD(0xF0), chip->start ); | |
1665 | /* FIXME - should have reset delay before continuing */ | |
1666 | ||
1667 | ret = -EIO; | |
1668 | } | |
1da177e4 | 1669 | |
1da177e4 LT |
1670 | chip->state = FL_READY; |
1671 | put_chip(map, chip, adr); | |
02b15e34 | 1672 | spin_unlock(chip->mutex); |
1da177e4 LT |
1673 | return ret; |
1674 | } | |
1675 | ||
1676 | ||
ce0f33ad | 1677 | static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 LT |
1678 | { |
1679 | unsigned long ofs, len; | |
1680 | int ret; | |
1681 | ||
1682 | ofs = instr->addr; | |
1683 | len = instr->len; | |
1684 | ||
1685 | ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL); | |
1686 | if (ret) | |
1687 | return ret; | |
1688 | ||
1689 | instr->state = MTD_ERASE_DONE; | |
1690 | mtd_erase_callback(instr); | |
1f948b43 | 1691 | |
1da177e4 LT |
1692 | return 0; |
1693 | } | |
1694 | ||
1695 | ||
1696 | static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr) | |
1697 | { | |
1698 | struct map_info *map = mtd->priv; | |
1699 | struct cfi_private *cfi = map->fldrv_priv; | |
1700 | int ret = 0; | |
1701 | ||
1702 | if (instr->addr != 0) | |
1703 | return -EINVAL; | |
1704 | ||
1705 | if (instr->len != mtd->size) | |
1706 | return -EINVAL; | |
1707 | ||
1708 | ret = do_erase_chip(map, &cfi->chips[0]); | |
1709 | if (ret) | |
1710 | return ret; | |
1711 | ||
1712 | instr->state = MTD_ERASE_DONE; | |
1713 | mtd_erase_callback(instr); | |
1f948b43 | 1714 | |
1da177e4 LT |
1715 | return 0; |
1716 | } | |
1717 | ||
0165508c HS |
1718 | static int do_atmel_lock(struct map_info *map, struct flchip *chip, |
1719 | unsigned long adr, int len, void *thunk) | |
1720 | { | |
1721 | struct cfi_private *cfi = map->fldrv_priv; | |
1722 | int ret; | |
1723 | ||
1724 | spin_lock(chip->mutex); | |
1725 | ret = get_chip(map, chip, adr + chip->start, FL_LOCKING); | |
1726 | if (ret) | |
1727 | goto out_unlock; | |
1728 | chip->state = FL_LOCKING; | |
1729 | ||
1730 | DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n", | |
1731 | __func__, adr, len); | |
1732 | ||
1733 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, | |
1734 | cfi->device_type, NULL); | |
1735 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, | |
1736 | cfi->device_type, NULL); | |
1737 | cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, | |
1738 | cfi->device_type, NULL); | |
1739 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, | |
1740 | cfi->device_type, NULL); | |
1741 | cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, | |
1742 | cfi->device_type, NULL); | |
1743 | map_write(map, CMD(0x40), chip->start + adr); | |
1744 | ||
1745 | chip->state = FL_READY; | |
1746 | put_chip(map, chip, adr + chip->start); | |
1747 | ret = 0; | |
1748 | ||
1749 | out_unlock: | |
1750 | spin_unlock(chip->mutex); | |
1751 | return ret; | |
1752 | } | |
1753 | ||
1754 | static int do_atmel_unlock(struct map_info *map, struct flchip *chip, | |
1755 | unsigned long adr, int len, void *thunk) | |
1756 | { | |
1757 | struct cfi_private *cfi = map->fldrv_priv; | |
1758 | int ret; | |
1759 | ||
1760 | spin_lock(chip->mutex); | |
1761 | ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING); | |
1762 | if (ret) | |
1763 | goto out_unlock; | |
1764 | chip->state = FL_UNLOCKING; | |
1765 | ||
1766 | DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n", | |
1767 | __func__, adr, len); | |
1768 | ||
1769 | cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, | |
1770 | cfi->device_type, NULL); | |
1771 | map_write(map, CMD(0x70), adr); | |
1772 | ||
1773 | chip->state = FL_READY; | |
1774 | put_chip(map, chip, adr + chip->start); | |
1775 | ret = 0; | |
1776 | ||
1777 | out_unlock: | |
1778 | spin_unlock(chip->mutex); | |
1779 | return ret; | |
1780 | } | |
1781 | ||
1782 | static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, size_t len) | |
1783 | { | |
1784 | return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL); | |
1785 | } | |
1786 | ||
1787 | static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) | |
1788 | { | |
1789 | return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL); | |
1790 | } | |
1791 | ||
1da177e4 LT |
1792 | |
1793 | static void cfi_amdstd_sync (struct mtd_info *mtd) | |
1794 | { | |
1795 | struct map_info *map = mtd->priv; | |
1796 | struct cfi_private *cfi = map->fldrv_priv; | |
1797 | int i; | |
1798 | struct flchip *chip; | |
1799 | int ret = 0; | |
1800 | DECLARE_WAITQUEUE(wait, current); | |
1801 | ||
1802 | for (i=0; !ret && i<cfi->numchips; i++) { | |
1803 | chip = &cfi->chips[i]; | |
1804 | ||
1805 | retry: | |
02b15e34 | 1806 | spin_lock(chip->mutex); |
1da177e4 LT |
1807 | |
1808 | switch(chip->state) { | |
1809 | case FL_READY: | |
1810 | case FL_STATUS: | |
1811 | case FL_CFI_QUERY: | |
1812 | case FL_JEDEC_QUERY: | |
1813 | chip->oldstate = chip->state; | |
1814 | chip->state = FL_SYNCING; | |
1f948b43 | 1815 | /* No need to wake_up() on this state change - |
1da177e4 LT |
1816 | * as the whole point is that nobody can do anything |
1817 | * with the chip now anyway. | |
1818 | */ | |
1819 | case FL_SYNCING: | |
02b15e34 | 1820 | spin_unlock(chip->mutex); |
1da177e4 LT |
1821 | break; |
1822 | ||
1823 | default: | |
1824 | /* Not an idle state */ | |
f8e30e44 | 1825 | set_current_state(TASK_UNINTERRUPTIBLE); |
1da177e4 | 1826 | add_wait_queue(&chip->wq, &wait); |
1f948b43 | 1827 | |
02b15e34 | 1828 | spin_unlock(chip->mutex); |
1da177e4 LT |
1829 | |
1830 | schedule(); | |
1831 | ||
1832 | remove_wait_queue(&chip->wq, &wait); | |
1f948b43 | 1833 | |
1da177e4 LT |
1834 | goto retry; |
1835 | } | |
1836 | } | |
1837 | ||
1838 | /* Unlock the chips again */ | |
1839 | ||
1840 | for (i--; i >=0; i--) { | |
1841 | chip = &cfi->chips[i]; | |
1842 | ||
02b15e34 | 1843 | spin_lock(chip->mutex); |
1f948b43 | 1844 | |
1da177e4 LT |
1845 | if (chip->state == FL_SYNCING) { |
1846 | chip->state = chip->oldstate; | |
1847 | wake_up(&chip->wq); | |
1848 | } | |
02b15e34 | 1849 | spin_unlock(chip->mutex); |
1da177e4 LT |
1850 | } |
1851 | } | |
1852 | ||
1853 | ||
1854 | static int cfi_amdstd_suspend(struct mtd_info *mtd) | |
1855 | { | |
1856 | struct map_info *map = mtd->priv; | |
1857 | struct cfi_private *cfi = map->fldrv_priv; | |
1858 | int i; | |
1859 | struct flchip *chip; | |
1860 | int ret = 0; | |
1861 | ||
1862 | for (i=0; !ret && i<cfi->numchips; i++) { | |
1863 | chip = &cfi->chips[i]; | |
1864 | ||
02b15e34 | 1865 | spin_lock(chip->mutex); |
1da177e4 LT |
1866 | |
1867 | switch(chip->state) { | |
1868 | case FL_READY: | |
1869 | case FL_STATUS: | |
1870 | case FL_CFI_QUERY: | |
1871 | case FL_JEDEC_QUERY: | |
1872 | chip->oldstate = chip->state; | |
1873 | chip->state = FL_PM_SUSPENDED; | |
1f948b43 | 1874 | /* No need to wake_up() on this state change - |
1da177e4 LT |
1875 | * as the whole point is that nobody can do anything |
1876 | * with the chip now anyway. | |
1877 | */ | |
1878 | case FL_PM_SUSPENDED: | |
1879 | break; | |
1880 | ||
1881 | default: | |
1882 | ret = -EAGAIN; | |
1883 | break; | |
1884 | } | |
02b15e34 | 1885 | spin_unlock(chip->mutex); |
1da177e4 LT |
1886 | } |
1887 | ||
1888 | /* Unlock the chips again */ | |
1889 | ||
1890 | if (ret) { | |
1891 | for (i--; i >=0; i--) { | |
1892 | chip = &cfi->chips[i]; | |
1893 | ||
02b15e34 | 1894 | spin_lock(chip->mutex); |
1f948b43 | 1895 | |
1da177e4 LT |
1896 | if (chip->state == FL_PM_SUSPENDED) { |
1897 | chip->state = chip->oldstate; | |
1898 | wake_up(&chip->wq); | |
1899 | } | |
02b15e34 | 1900 | spin_unlock(chip->mutex); |
1da177e4 LT |
1901 | } |
1902 | } | |
1f948b43 | 1903 | |
1da177e4 LT |
1904 | return ret; |
1905 | } | |
1906 | ||
1907 | ||
1908 | static void cfi_amdstd_resume(struct mtd_info *mtd) | |
1909 | { | |
1910 | struct map_info *map = mtd->priv; | |
1911 | struct cfi_private *cfi = map->fldrv_priv; | |
1912 | int i; | |
1913 | struct flchip *chip; | |
1914 | ||
1915 | for (i=0; i<cfi->numchips; i++) { | |
1f948b43 | 1916 | |
1da177e4 LT |
1917 | chip = &cfi->chips[i]; |
1918 | ||
02b15e34 | 1919 | spin_lock(chip->mutex); |
1f948b43 | 1920 | |
1da177e4 LT |
1921 | if (chip->state == FL_PM_SUSPENDED) { |
1922 | chip->state = FL_READY; | |
1923 | map_write(map, CMD(0xF0), chip->start); | |
1924 | wake_up(&chip->wq); | |
1925 | } | |
1926 | else | |
1927 | printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n"); | |
1928 | ||
02b15e34 | 1929 | spin_unlock(chip->mutex); |
1da177e4 LT |
1930 | } |
1931 | } | |
1932 | ||
1933 | static void cfi_amdstd_destroy(struct mtd_info *mtd) | |
1934 | { | |
1935 | struct map_info *map = mtd->priv; | |
1936 | struct cfi_private *cfi = map->fldrv_priv; | |
fa671646 | 1937 | |
1da177e4 LT |
1938 | kfree(cfi->cmdset_priv); |
1939 | kfree(cfi->cfiq); | |
1940 | kfree(cfi); | |
1941 | kfree(mtd->eraseregions); | |
1942 | } | |
1943 | ||
1da177e4 LT |
1944 | MODULE_LICENSE("GPL"); |
1945 | MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al."); | |
1946 | MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips"); |