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Commit | Line | Data |
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2f9f7628 | 1 | /* |
fa0a8c71 | 2 | * MTD SPI driver for ST M25Pxx (and similar) serial flash chips |
2f9f7628 ML |
3 | * |
4 | * Author: Mike Lavender, mike@steroidmicros.com | |
5 | * | |
6 | * Copyright (c) 2005, Intec Automation Inc. | |
7 | * | |
8 | * Some parts are based on lart.c by Abraham Van Der Merwe | |
9 | * | |
10 | * Cleaned up and generalized based on mtd_dataflash.c | |
11 | * | |
12 | * This code is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
9d2c4f3f AV |
19 | #include <linux/err.h> |
20 | #include <linux/errno.h> | |
2f9f7628 ML |
21 | #include <linux/module.h> |
22 | #include <linux/device.h> | |
23 | #include <linux/interrupt.h> | |
7d5230ea | 24 | #include <linux/mutex.h> |
d85316ac | 25 | #include <linux/math64.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
d43c36dc | 27 | #include <linux/sched.h> |
b34bc037 | 28 | #include <linux/mod_devicetable.h> |
7d5230ea | 29 | |
2f9f7628 ML |
30 | #include <linux/mtd/mtd.h> |
31 | #include <linux/mtd/partitions.h> | |
7d5230ea | 32 | |
2f9f7628 ML |
33 | #include <linux/spi/spi.h> |
34 | #include <linux/spi/flash.h> | |
35 | ||
2f9f7628 | 36 | /* Flash opcodes. */ |
fa0a8c71 DB |
37 | #define OPCODE_WREN 0x06 /* Write enable */ |
38 | #define OPCODE_RDSR 0x05 /* Read status register */ | |
72289824 | 39 | #define OPCODE_WRSR 0x01 /* Write status register 1 byte */ |
2230b76b | 40 | #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ |
fa0a8c71 DB |
41 | #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ |
42 | #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ | |
7854643a | 43 | #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ |
02d087db | 44 | #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ |
7854643a | 45 | #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ |
02d087db | 46 | #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ |
2f9f7628 ML |
47 | #define OPCODE_RDID 0x9f /* Read JEDEC ID */ |
48 | ||
49aac4ae GY |
49 | /* Used for SST flashes only. */ |
50 | #define OPCODE_BP 0x02 /* Byte program */ | |
51 | #define OPCODE_WRDI 0x04 /* Write disable */ | |
52 | #define OPCODE_AAI_WP 0xad /* Auto address increment word program */ | |
53 | ||
4b7f7422 KC |
54 | /* Used for Macronix flashes only. */ |
55 | #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */ | |
56 | #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */ | |
57 | ||
2f9f7628 ML |
58 | /* Status Register bits. */ |
59 | #define SR_WIP 1 /* Write in progress */ | |
60 | #define SR_WEL 2 /* Write enable latch */ | |
fa0a8c71 | 61 | /* meaning of other SR_* bits may differ between vendors */ |
2f9f7628 ML |
62 | #define SR_BP0 4 /* Block protect 0 */ |
63 | #define SR_BP1 8 /* Block protect 1 */ | |
64 | #define SR_BP2 0x10 /* Block protect 2 */ | |
65 | #define SR_SRWD 0x80 /* SR write protect */ | |
66 | ||
67 | /* Define max times to check status register before we give up. */ | |
89bb871e | 68 | #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */ |
4b7f7422 | 69 | #define MAX_CMD_SIZE 5 |
2f9f7628 | 70 | |
2230b76b BW |
71 | #ifdef CONFIG_M25PXX_USE_FAST_READ |
72 | #define OPCODE_READ OPCODE_FAST_READ | |
73 | #define FAST_READ_DUMMY_BYTE 1 | |
74 | #else | |
75 | #define OPCODE_READ OPCODE_NORM_READ | |
76 | #define FAST_READ_DUMMY_BYTE 0 | |
77 | #endif | |
2f9f7628 | 78 | |
2f9f7628 ML |
79 | /****************************************************************************/ |
80 | ||
81 | struct m25p { | |
82 | struct spi_device *spi; | |
7d5230ea | 83 | struct mutex lock; |
2f9f7628 | 84 | struct mtd_info mtd; |
fa0a8c71 | 85 | unsigned partitioned:1; |
837479d2 AV |
86 | u16 page_size; |
87 | u16 addr_width; | |
fa0a8c71 | 88 | u8 erase_opcode; |
61c3506c | 89 | u8 *command; |
2f9f7628 ML |
90 | }; |
91 | ||
92 | static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd) | |
93 | { | |
94 | return container_of(mtd, struct m25p, mtd); | |
95 | } | |
96 | ||
97 | /****************************************************************************/ | |
98 | ||
99 | /* | |
100 | * Internal helper functions | |
101 | */ | |
102 | ||
103 | /* | |
104 | * Read the status register, returning its value in the location | |
105 | * Return the status register value. | |
106 | * Returns negative if error occurred. | |
107 | */ | |
108 | static int read_sr(struct m25p *flash) | |
109 | { | |
110 | ssize_t retval; | |
111 | u8 code = OPCODE_RDSR; | |
112 | u8 val; | |
113 | ||
114 | retval = spi_write_then_read(flash->spi, &code, 1, &val, 1); | |
115 | ||
116 | if (retval < 0) { | |
117 | dev_err(&flash->spi->dev, "error %d reading SR\n", | |
118 | (int) retval); | |
119 | return retval; | |
120 | } | |
121 | ||
122 | return val; | |
123 | } | |
124 | ||
72289824 MH |
125 | /* |
126 | * Write status register 1 byte | |
127 | * Returns negative if error occurred. | |
128 | */ | |
129 | static int write_sr(struct m25p *flash, u8 val) | |
130 | { | |
131 | flash->command[0] = OPCODE_WRSR; | |
132 | flash->command[1] = val; | |
133 | ||
134 | return spi_write(flash->spi, flash->command, 2); | |
135 | } | |
2f9f7628 ML |
136 | |
137 | /* | |
138 | * Set write enable latch with Write Enable command. | |
139 | * Returns negative if error occurred. | |
140 | */ | |
141 | static inline int write_enable(struct m25p *flash) | |
142 | { | |
143 | u8 code = OPCODE_WREN; | |
144 | ||
8a1a6272 | 145 | return spi_write_then_read(flash->spi, &code, 1, NULL, 0); |
2f9f7628 ML |
146 | } |
147 | ||
49aac4ae GY |
148 | /* |
149 | * Send write disble instruction to the chip. | |
150 | */ | |
151 | static inline int write_disable(struct m25p *flash) | |
152 | { | |
153 | u8 code = OPCODE_WRDI; | |
154 | ||
155 | return spi_write_then_read(flash->spi, &code, 1, NULL, 0); | |
156 | } | |
2f9f7628 | 157 | |
4b7f7422 KC |
158 | /* |
159 | * Enable/disable 4-byte addressing mode. | |
160 | */ | |
161 | static inline int set_4byte(struct m25p *flash, int enable) | |
162 | { | |
163 | u8 code = enable ? OPCODE_EN4B : OPCODE_EX4B; | |
164 | ||
165 | return spi_write_then_read(flash->spi, &code, 1, NULL, 0); | |
166 | } | |
167 | ||
2f9f7628 ML |
168 | /* |
169 | * Service routine to read status register until ready, or timeout occurs. | |
170 | * Returns non-zero if error. | |
171 | */ | |
172 | static int wait_till_ready(struct m25p *flash) | |
173 | { | |
cd1a6de7 | 174 | unsigned long deadline; |
2f9f7628 ML |
175 | int sr; |
176 | ||
cd1a6de7 PH |
177 | deadline = jiffies + MAX_READY_WAIT_JIFFIES; |
178 | ||
179 | do { | |
2f9f7628 ML |
180 | if ((sr = read_sr(flash)) < 0) |
181 | break; | |
182 | else if (!(sr & SR_WIP)) | |
183 | return 0; | |
184 | ||
cd1a6de7 PH |
185 | cond_resched(); |
186 | ||
187 | } while (!time_after_eq(jiffies, deadline)); | |
2f9f7628 ML |
188 | |
189 | return 1; | |
190 | } | |
191 | ||
faff3750 CG |
192 | /* |
193 | * Erase the whole flash memory | |
194 | * | |
195 | * Returns 0 if successful, non-zero otherwise. | |
196 | */ | |
7854643a | 197 | static int erase_chip(struct m25p *flash) |
faff3750 | 198 | { |
d85316ac | 199 | DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %lldKiB\n", |
160bbab3 KS |
200 | dev_name(&flash->spi->dev), __func__, |
201 | (long long)(flash->mtd.size >> 10)); | |
faff3750 CG |
202 | |
203 | /* Wait until finished previous write command. */ | |
204 | if (wait_till_ready(flash)) | |
205 | return 1; | |
206 | ||
207 | /* Send write enable, then erase commands. */ | |
208 | write_enable(flash); | |
209 | ||
210 | /* Set up command buffer. */ | |
7854643a | 211 | flash->command[0] = OPCODE_CHIP_ERASE; |
faff3750 CG |
212 | |
213 | spi_write(flash->spi, flash->command, 1); | |
214 | ||
215 | return 0; | |
216 | } | |
2f9f7628 | 217 | |
837479d2 AV |
218 | static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd) |
219 | { | |
220 | /* opcode is in cmd[0] */ | |
221 | cmd[1] = addr >> (flash->addr_width * 8 - 8); | |
222 | cmd[2] = addr >> (flash->addr_width * 8 - 16); | |
223 | cmd[3] = addr >> (flash->addr_width * 8 - 24); | |
4b7f7422 | 224 | cmd[4] = addr >> (flash->addr_width * 8 - 32); |
837479d2 AV |
225 | } |
226 | ||
227 | static int m25p_cmdsz(struct m25p *flash) | |
228 | { | |
229 | return 1 + flash->addr_width; | |
230 | } | |
231 | ||
2f9f7628 ML |
232 | /* |
233 | * Erase one sector of flash memory at offset ``offset'' which is any | |
234 | * address within the sector which should be erased. | |
235 | * | |
236 | * Returns 0 if successful, non-zero otherwise. | |
237 | */ | |
238 | static int erase_sector(struct m25p *flash, u32 offset) | |
239 | { | |
02d087db | 240 | DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %dKiB at 0x%08x\n", |
160bbab3 | 241 | dev_name(&flash->spi->dev), __func__, |
fa0a8c71 | 242 | flash->mtd.erasesize / 1024, offset); |
2f9f7628 ML |
243 | |
244 | /* Wait until finished previous write command. */ | |
245 | if (wait_till_ready(flash)) | |
246 | return 1; | |
247 | ||
248 | /* Send write enable, then erase commands. */ | |
249 | write_enable(flash); | |
250 | ||
251 | /* Set up command buffer. */ | |
fa0a8c71 | 252 | flash->command[0] = flash->erase_opcode; |
837479d2 | 253 | m25p_addr2cmd(flash, offset, flash->command); |
2f9f7628 | 254 | |
837479d2 | 255 | spi_write(flash->spi, flash->command, m25p_cmdsz(flash)); |
2f9f7628 ML |
256 | |
257 | return 0; | |
258 | } | |
259 | ||
260 | /****************************************************************************/ | |
261 | ||
262 | /* | |
263 | * MTD implementation | |
264 | */ | |
265 | ||
266 | /* | |
267 | * Erase an address range on the flash chip. The address range may extend | |
268 | * one or more erase sectors. Return an error is there is a problem erasing. | |
269 | */ | |
270 | static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr) | |
271 | { | |
272 | struct m25p *flash = mtd_to_m25p(mtd); | |
273 | u32 addr,len; | |
d85316ac | 274 | uint32_t rem; |
2f9f7628 | 275 | |
d85316ac | 276 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%llx, len %lld\n", |
160bbab3 KS |
277 | dev_name(&flash->spi->dev), __func__, "at", |
278 | (long long)instr->addr, (long long)instr->len); | |
2f9f7628 ML |
279 | |
280 | /* sanity checks */ | |
281 | if (instr->addr + instr->len > flash->mtd.size) | |
282 | return -EINVAL; | |
d85316ac AB |
283 | div_u64_rem(instr->len, mtd->erasesize, &rem); |
284 | if (rem) | |
2f9f7628 | 285 | return -EINVAL; |
2f9f7628 ML |
286 | |
287 | addr = instr->addr; | |
288 | len = instr->len; | |
289 | ||
7d5230ea | 290 | mutex_lock(&flash->lock); |
2f9f7628 | 291 | |
7854643a | 292 | /* whole-chip erase? */ |
3f33b0aa SF |
293 | if (len == flash->mtd.size) { |
294 | if (erase_chip(flash)) { | |
295 | instr->state = MTD_ERASE_FAILED; | |
296 | mutex_unlock(&flash->lock); | |
297 | return -EIO; | |
298 | } | |
7854643a CG |
299 | |
300 | /* REVISIT in some cases we could speed up erasing large regions | |
301 | * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up | |
302 | * to use "small sector erase", but that's not always optimal. | |
303 | */ | |
304 | ||
305 | /* "sector"-at-a-time erase */ | |
faff3750 CG |
306 | } else { |
307 | while (len) { | |
308 | if (erase_sector(flash, addr)) { | |
309 | instr->state = MTD_ERASE_FAILED; | |
310 | mutex_unlock(&flash->lock); | |
311 | return -EIO; | |
312 | } | |
313 | ||
314 | addr += mtd->erasesize; | |
315 | len -= mtd->erasesize; | |
2f9f7628 | 316 | } |
2f9f7628 ML |
317 | } |
318 | ||
7d5230ea | 319 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
320 | |
321 | instr->state = MTD_ERASE_DONE; | |
322 | mtd_erase_callback(instr); | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
327 | /* | |
328 | * Read an address range from the flash chip. The address range | |
329 | * may be any size provided it is within the physical boundaries. | |
330 | */ | |
331 | static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len, | |
332 | size_t *retlen, u_char *buf) | |
333 | { | |
334 | struct m25p *flash = mtd_to_m25p(mtd); | |
335 | struct spi_transfer t[2]; | |
336 | struct spi_message m; | |
337 | ||
338 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n", | |
160bbab3 | 339 | dev_name(&flash->spi->dev), __func__, "from", |
2f9f7628 ML |
340 | (u32)from, len); |
341 | ||
342 | /* sanity checks */ | |
343 | if (!len) | |
344 | return 0; | |
345 | ||
346 | if (from + len > flash->mtd.size) | |
347 | return -EINVAL; | |
348 | ||
8275c642 VW |
349 | spi_message_init(&m); |
350 | memset(t, 0, (sizeof t)); | |
351 | ||
2230b76b BW |
352 | /* NOTE: |
353 | * OPCODE_FAST_READ (if available) is faster. | |
354 | * Should add 1 byte DUMMY_BYTE. | |
355 | */ | |
8275c642 | 356 | t[0].tx_buf = flash->command; |
837479d2 | 357 | t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE; |
8275c642 VW |
358 | spi_message_add_tail(&t[0], &m); |
359 | ||
360 | t[1].rx_buf = buf; | |
361 | t[1].len = len; | |
362 | spi_message_add_tail(&t[1], &m); | |
363 | ||
364 | /* Byte count starts at zero. */ | |
b06cd21e | 365 | *retlen = 0; |
8275c642 | 366 | |
7d5230ea | 367 | mutex_lock(&flash->lock); |
2f9f7628 ML |
368 | |
369 | /* Wait till previous write/erase is done. */ | |
370 | if (wait_till_ready(flash)) { | |
371 | /* REVISIT status return?? */ | |
7d5230ea | 372 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
373 | return 1; |
374 | } | |
375 | ||
fa0a8c71 DB |
376 | /* FIXME switch to OPCODE_FAST_READ. It's required for higher |
377 | * clocks; and at this writing, every chip this driver handles | |
378 | * supports that opcode. | |
379 | */ | |
2f9f7628 ML |
380 | |
381 | /* Set up the write data buffer. */ | |
382 | flash->command[0] = OPCODE_READ; | |
837479d2 | 383 | m25p_addr2cmd(flash, from, flash->command); |
2f9f7628 | 384 | |
2f9f7628 ML |
385 | spi_sync(flash->spi, &m); |
386 | ||
837479d2 | 387 | *retlen = m.actual_length - m25p_cmdsz(flash) - FAST_READ_DUMMY_BYTE; |
2f9f7628 | 388 | |
7d5230ea | 389 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
390 | |
391 | return 0; | |
392 | } | |
393 | ||
394 | /* | |
395 | * Write an address range to the flash chip. Data must be written in | |
396 | * FLASH_PAGESIZE chunks. The address range may be any size provided | |
397 | * it is within the physical boundaries. | |
398 | */ | |
399 | static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len, | |
400 | size_t *retlen, const u_char *buf) | |
401 | { | |
402 | struct m25p *flash = mtd_to_m25p(mtd); | |
403 | u32 page_offset, page_size; | |
404 | struct spi_transfer t[2]; | |
405 | struct spi_message m; | |
406 | ||
407 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n", | |
160bbab3 | 408 | dev_name(&flash->spi->dev), __func__, "to", |
2f9f7628 ML |
409 | (u32)to, len); |
410 | ||
b06cd21e | 411 | *retlen = 0; |
2f9f7628 ML |
412 | |
413 | /* sanity checks */ | |
414 | if (!len) | |
415 | return(0); | |
416 | ||
417 | if (to + len > flash->mtd.size) | |
418 | return -EINVAL; | |
419 | ||
8275c642 VW |
420 | spi_message_init(&m); |
421 | memset(t, 0, (sizeof t)); | |
422 | ||
423 | t[0].tx_buf = flash->command; | |
837479d2 | 424 | t[0].len = m25p_cmdsz(flash); |
8275c642 VW |
425 | spi_message_add_tail(&t[0], &m); |
426 | ||
427 | t[1].tx_buf = buf; | |
428 | spi_message_add_tail(&t[1], &m); | |
429 | ||
7d5230ea | 430 | mutex_lock(&flash->lock); |
2f9f7628 ML |
431 | |
432 | /* Wait until finished previous write command. */ | |
bc018863 CG |
433 | if (wait_till_ready(flash)) { |
434 | mutex_unlock(&flash->lock); | |
2f9f7628 | 435 | return 1; |
bc018863 | 436 | } |
2f9f7628 ML |
437 | |
438 | write_enable(flash); | |
439 | ||
2f9f7628 ML |
440 | /* Set up the opcode in the write buffer. */ |
441 | flash->command[0] = OPCODE_PP; | |
837479d2 | 442 | m25p_addr2cmd(flash, to, flash->command); |
2f9f7628 | 443 | |
837479d2 | 444 | page_offset = to & (flash->page_size - 1); |
2f9f7628 ML |
445 | |
446 | /* do all the bytes fit onto one page? */ | |
837479d2 | 447 | if (page_offset + len <= flash->page_size) { |
2f9f7628 ML |
448 | t[1].len = len; |
449 | ||
450 | spi_sync(flash->spi, &m); | |
451 | ||
837479d2 | 452 | *retlen = m.actual_length - m25p_cmdsz(flash); |
2f9f7628 ML |
453 | } else { |
454 | u32 i; | |
455 | ||
456 | /* the size of data remaining on the first page */ | |
837479d2 | 457 | page_size = flash->page_size - page_offset; |
2f9f7628 | 458 | |
2f9f7628 ML |
459 | t[1].len = page_size; |
460 | spi_sync(flash->spi, &m); | |
461 | ||
837479d2 | 462 | *retlen = m.actual_length - m25p_cmdsz(flash); |
2f9f7628 | 463 | |
837479d2 | 464 | /* write everything in flash->page_size chunks */ |
2f9f7628 ML |
465 | for (i = page_size; i < len; i += page_size) { |
466 | page_size = len - i; | |
837479d2 AV |
467 | if (page_size > flash->page_size) |
468 | page_size = flash->page_size; | |
2f9f7628 ML |
469 | |
470 | /* write the next page to flash */ | |
837479d2 | 471 | m25p_addr2cmd(flash, to + i, flash->command); |
2f9f7628 ML |
472 | |
473 | t[1].tx_buf = buf + i; | |
474 | t[1].len = page_size; | |
475 | ||
476 | wait_till_ready(flash); | |
477 | ||
478 | write_enable(flash); | |
479 | ||
480 | spi_sync(flash->spi, &m); | |
481 | ||
b06cd21e | 482 | *retlen += m.actual_length - m25p_cmdsz(flash); |
7d5230ea DB |
483 | } |
484 | } | |
2f9f7628 | 485 | |
7d5230ea | 486 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
487 | |
488 | return 0; | |
489 | } | |
490 | ||
49aac4ae GY |
491 | static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, |
492 | size_t *retlen, const u_char *buf) | |
493 | { | |
494 | struct m25p *flash = mtd_to_m25p(mtd); | |
495 | struct spi_transfer t[2]; | |
496 | struct spi_message m; | |
497 | size_t actual; | |
498 | int cmd_sz, ret; | |
499 | ||
dcf12463 NF |
500 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n", |
501 | dev_name(&flash->spi->dev), __func__, "to", | |
502 | (u32)to, len); | |
503 | ||
b06cd21e | 504 | *retlen = 0; |
49aac4ae GY |
505 | |
506 | /* sanity checks */ | |
507 | if (!len) | |
508 | return 0; | |
509 | ||
510 | if (to + len > flash->mtd.size) | |
511 | return -EINVAL; | |
512 | ||
513 | spi_message_init(&m); | |
514 | memset(t, 0, (sizeof t)); | |
515 | ||
516 | t[0].tx_buf = flash->command; | |
837479d2 | 517 | t[0].len = m25p_cmdsz(flash); |
49aac4ae GY |
518 | spi_message_add_tail(&t[0], &m); |
519 | ||
520 | t[1].tx_buf = buf; | |
521 | spi_message_add_tail(&t[1], &m); | |
522 | ||
523 | mutex_lock(&flash->lock); | |
524 | ||
525 | /* Wait until finished previous write command. */ | |
526 | ret = wait_till_ready(flash); | |
527 | if (ret) | |
528 | goto time_out; | |
529 | ||
530 | write_enable(flash); | |
531 | ||
532 | actual = to % 2; | |
533 | /* Start write from odd address. */ | |
534 | if (actual) { | |
535 | flash->command[0] = OPCODE_BP; | |
837479d2 | 536 | m25p_addr2cmd(flash, to, flash->command); |
49aac4ae GY |
537 | |
538 | /* write one byte. */ | |
539 | t[1].len = 1; | |
540 | spi_sync(flash->spi, &m); | |
541 | ret = wait_till_ready(flash); | |
542 | if (ret) | |
543 | goto time_out; | |
837479d2 | 544 | *retlen += m.actual_length - m25p_cmdsz(flash); |
49aac4ae GY |
545 | } |
546 | to += actual; | |
547 | ||
548 | flash->command[0] = OPCODE_AAI_WP; | |
837479d2 | 549 | m25p_addr2cmd(flash, to, flash->command); |
49aac4ae GY |
550 | |
551 | /* Write out most of the data here. */ | |
837479d2 | 552 | cmd_sz = m25p_cmdsz(flash); |
49aac4ae GY |
553 | for (; actual < len - 1; actual += 2) { |
554 | t[0].len = cmd_sz; | |
555 | /* write two bytes. */ | |
556 | t[1].len = 2; | |
557 | t[1].tx_buf = buf + actual; | |
558 | ||
559 | spi_sync(flash->spi, &m); | |
560 | ret = wait_till_ready(flash); | |
561 | if (ret) | |
562 | goto time_out; | |
563 | *retlen += m.actual_length - cmd_sz; | |
564 | cmd_sz = 1; | |
565 | to += 2; | |
566 | } | |
567 | write_disable(flash); | |
568 | ret = wait_till_ready(flash); | |
569 | if (ret) | |
570 | goto time_out; | |
571 | ||
572 | /* Write out trailing byte if it exists. */ | |
573 | if (actual != len) { | |
574 | write_enable(flash); | |
575 | flash->command[0] = OPCODE_BP; | |
837479d2 AV |
576 | m25p_addr2cmd(flash, to, flash->command); |
577 | t[0].len = m25p_cmdsz(flash); | |
49aac4ae GY |
578 | t[1].len = 1; |
579 | t[1].tx_buf = buf + actual; | |
580 | ||
581 | spi_sync(flash->spi, &m); | |
582 | ret = wait_till_ready(flash); | |
583 | if (ret) | |
584 | goto time_out; | |
837479d2 | 585 | *retlen += m.actual_length - m25p_cmdsz(flash); |
49aac4ae GY |
586 | write_disable(flash); |
587 | } | |
588 | ||
589 | time_out: | |
590 | mutex_unlock(&flash->lock); | |
591 | return ret; | |
592 | } | |
2f9f7628 ML |
593 | |
594 | /****************************************************************************/ | |
595 | ||
596 | /* | |
597 | * SPI device driver setup and teardown | |
598 | */ | |
599 | ||
600 | struct flash_info { | |
fa0a8c71 DB |
601 | /* JEDEC id zero means "no ID" (most older chips); otherwise it has |
602 | * a high byte of zero plus three data bytes: the manufacturer id, | |
603 | * then a two byte device id. | |
604 | */ | |
605 | u32 jedec_id; | |
d0e8c47c | 606 | u16 ext_id; |
fa0a8c71 DB |
607 | |
608 | /* The size listed here is what works with OPCODE_SE, which isn't | |
609 | * necessarily called a "sector" by the vendor. | |
610 | */ | |
2f9f7628 | 611 | unsigned sector_size; |
fa0a8c71 DB |
612 | u16 n_sectors; |
613 | ||
837479d2 AV |
614 | u16 page_size; |
615 | u16 addr_width; | |
616 | ||
fa0a8c71 DB |
617 | u16 flags; |
618 | #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */ | |
837479d2 | 619 | #define M25P_NO_ERASE 0x02 /* No erase command needed */ |
2f9f7628 ML |
620 | }; |
621 | ||
b34bc037 AV |
622 | #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
623 | ((kernel_ulong_t)&(struct flash_info) { \ | |
624 | .jedec_id = (_jedec_id), \ | |
625 | .ext_id = (_ext_id), \ | |
626 | .sector_size = (_sector_size), \ | |
627 | .n_sectors = (_n_sectors), \ | |
837479d2 | 628 | .page_size = 256, \ |
b34bc037 AV |
629 | .flags = (_flags), \ |
630 | }) | |
fa0a8c71 | 631 | |
837479d2 AV |
632 | #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width) \ |
633 | ((kernel_ulong_t)&(struct flash_info) { \ | |
634 | .sector_size = (_sector_size), \ | |
635 | .n_sectors = (_n_sectors), \ | |
636 | .page_size = (_page_size), \ | |
637 | .addr_width = (_addr_width), \ | |
638 | .flags = M25P_NO_ERASE, \ | |
639 | }) | |
fa0a8c71 DB |
640 | |
641 | /* NOTE: double check command sets and memory organization when you add | |
642 | * more flash chips. This current list focusses on newer chips, which | |
643 | * have been converging on command sets which including JEDEC ID. | |
644 | */ | |
b34bc037 | 645 | static const struct spi_device_id m25p_ids[] = { |
fa0a8c71 | 646 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ |
b34bc037 AV |
647 | { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, |
648 | { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, | |
fa0a8c71 | 649 | |
b34bc037 AV |
650 | { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, |
651 | { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, | |
fa0a8c71 | 652 | |
b34bc037 AV |
653 | { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, |
654 | { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, | |
655 | { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) }, | |
8fffed8c | 656 | { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, |
fa0a8c71 | 657 | |
37a23c20 GJ |
658 | /* EON -- en25xxx */ |
659 | { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, | |
60845e72 GJ |
660 | { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, |
661 | { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, | |
662 | ||
f80e521c GJ |
663 | /* Intel/Numonyx -- xxxs33b */ |
664 | { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, | |
665 | { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, | |
666 | { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, | |
667 | ||
ab1ff210 | 668 | /* Macronix */ |
df0094d7 | 669 | { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, |
6175f4a1 | 670 | { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, |
b34bc037 AV |
671 | { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) }, |
672 | { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) }, | |
673 | { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, | |
674 | { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, | |
4b7f7422 | 675 | { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) }, |
ac622f58 | 676 | { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, |
ab1ff210 | 677 | |
fa0a8c71 DB |
678 | /* Spansion -- single (large) sector size only, at least |
679 | * for the chips listed here (without boot sectors). | |
680 | */ | |
b34bc037 AV |
681 | { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, |
682 | { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, | |
683 | { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, | |
684 | { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, | |
d86fbdb8 | 685 | { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SECT_4K) }, |
b34bc037 AV |
686 | { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, |
687 | { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, | |
688 | { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, | |
689 | { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) }, | |
690 | { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) }, | |
f2df1ae3 GH |
691 | { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) }, |
692 | { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, | |
fa0a8c71 DB |
693 | |
694 | /* SST -- large erase sizes are "overlays", "sectors" are 4K */ | |
b34bc037 AV |
695 | { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K) }, |
696 | { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K) }, | |
697 | { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K) }, | |
698 | { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K) }, | |
699 | { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K) }, | |
700 | { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K) }, | |
701 | { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K) }, | |
702 | { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K) }, | |
fa0a8c71 DB |
703 | |
704 | /* ST Microelectronics -- newer production may have feature updates */ | |
b34bc037 AV |
705 | { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, |
706 | { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, | |
707 | { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, | |
708 | { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, | |
709 | { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, | |
710 | { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, | |
711 | { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, | |
712 | { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, | |
713 | { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, | |
714 | ||
f7b00090 AV |
715 | { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) }, |
716 | { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) }, | |
717 | { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) }, | |
718 | { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) }, | |
719 | { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) }, | |
720 | { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) }, | |
721 | { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) }, | |
722 | { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) }, | |
723 | { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) }, | |
724 | ||
b34bc037 AV |
725 | { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) }, |
726 | { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) }, | |
727 | { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) }, | |
728 | ||
729 | { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) }, | |
730 | { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, | |
fa0a8c71 | 731 | |
d8f90b2c YS |
732 | { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, |
733 | ||
02d087db | 734 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ |
b34bc037 AV |
735 | { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, |
736 | { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, | |
737 | { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, | |
738 | { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, | |
739 | { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, | |
740 | { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, | |
0af18d27 | 741 | { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, |
b34bc037 | 742 | { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, |
d2ac467a | 743 | { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, |
837479d2 AV |
744 | |
745 | /* Catalyst / On Semiconductor -- non-JEDEC */ | |
746 | { "cat25c11", CAT25_INFO( 16, 8, 16, 1) }, | |
747 | { "cat25c03", CAT25_INFO( 32, 8, 16, 2) }, | |
748 | { "cat25c09", CAT25_INFO( 128, 8, 32, 2) }, | |
749 | { "cat25c17", CAT25_INFO( 256, 8, 32, 2) }, | |
750 | { "cat25128", CAT25_INFO(2048, 8, 64, 2) }, | |
b34bc037 | 751 | { }, |
2f9f7628 | 752 | }; |
b34bc037 | 753 | MODULE_DEVICE_TABLE(spi, m25p_ids); |
2f9f7628 | 754 | |
b34bc037 | 755 | static const struct spi_device_id *__devinit jedec_probe(struct spi_device *spi) |
fa0a8c71 DB |
756 | { |
757 | int tmp; | |
758 | u8 code = OPCODE_RDID; | |
daa84735 | 759 | u8 id[5]; |
fa0a8c71 | 760 | u32 jedec; |
d0e8c47c | 761 | u16 ext_jedec; |
fa0a8c71 DB |
762 | struct flash_info *info; |
763 | ||
764 | /* JEDEC also defines an optional "extended device information" | |
765 | * string for after vendor-specific data, after the three bytes | |
766 | * we use here. Supporting some chips might require using it. | |
767 | */ | |
daa84735 | 768 | tmp = spi_write_then_read(spi, &code, 1, id, 5); |
fa0a8c71 DB |
769 | if (tmp < 0) { |
770 | DEBUG(MTD_DEBUG_LEVEL0, "%s: error %d reading JEDEC ID\n", | |
160bbab3 | 771 | dev_name(&spi->dev), tmp); |
9d2c4f3f | 772 | return ERR_PTR(tmp); |
fa0a8c71 DB |
773 | } |
774 | jedec = id[0]; | |
775 | jedec = jedec << 8; | |
776 | jedec |= id[1]; | |
777 | jedec = jedec << 8; | |
778 | jedec |= id[2]; | |
779 | ||
d0e8c47c CG |
780 | ext_jedec = id[3] << 8 | id[4]; |
781 | ||
b34bc037 AV |
782 | for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) { |
783 | info = (void *)m25p_ids[tmp].driver_data; | |
a3d3f73c | 784 | if (info->jedec_id == jedec) { |
9168ab86 | 785 | if (info->ext_id != 0 && info->ext_id != ext_jedec) |
d0e8c47c | 786 | continue; |
b34bc037 | 787 | return &m25p_ids[tmp]; |
a3d3f73c | 788 | } |
fa0a8c71 | 789 | } |
f0dff9bd | 790 | dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec); |
9d2c4f3f | 791 | return ERR_PTR(-ENODEV); |
fa0a8c71 DB |
792 | } |
793 | ||
794 | ||
2f9f7628 ML |
795 | /* |
796 | * board specific setup should have ensured the SPI clock used here | |
797 | * matches what the READ command supports, at least until this driver | |
798 | * understands FAST_READ (for clocks over 25 MHz). | |
799 | */ | |
800 | static int __devinit m25p_probe(struct spi_device *spi) | |
801 | { | |
18c6182b | 802 | const struct spi_device_id *id = spi_get_device_id(spi); |
2f9f7628 ML |
803 | struct flash_platform_data *data; |
804 | struct m25p *flash; | |
805 | struct flash_info *info; | |
806 | unsigned i; | |
807 | ||
808 | /* Platform data helps sort out which chip type we have, as | |
fa0a8c71 DB |
809 | * well as how this board partitions it. If we don't have |
810 | * a chip ID, try the JEDEC id commands; they'll work for most | |
811 | * newer chips, even if we don't recognize the particular chip. | |
2f9f7628 ML |
812 | */ |
813 | data = spi->dev.platform_data; | |
fa0a8c71 | 814 | if (data && data->type) { |
18c6182b | 815 | const struct spi_device_id *plat_id; |
2f9f7628 | 816 | |
b34bc037 | 817 | for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) { |
18c6182b AV |
818 | plat_id = &m25p_ids[i]; |
819 | if (strcmp(data->type, plat_id->name)) | |
b34bc037 AV |
820 | continue; |
821 | break; | |
fa0a8c71 | 822 | } |
fa0a8c71 | 823 | |
f78ec6b2 | 824 | if (i < ARRAY_SIZE(m25p_ids) - 1) |
18c6182b AV |
825 | id = plat_id; |
826 | else | |
827 | dev_warn(&spi->dev, "unrecognized id %s\n", data->type); | |
b34bc037 | 828 | } |
fa0a8c71 | 829 | |
18c6182b AV |
830 | info = (void *)id->driver_data; |
831 | ||
832 | if (info->jedec_id) { | |
833 | const struct spi_device_id *jid; | |
834 | ||
835 | jid = jedec_probe(spi); | |
9d2c4f3f AV |
836 | if (IS_ERR(jid)) { |
837 | return PTR_ERR(jid); | |
18c6182b AV |
838 | } else if (jid != id) { |
839 | /* | |
840 | * JEDEC knows better, so overwrite platform ID. We | |
841 | * can't trust partitions any longer, but we'll let | |
842 | * mtd apply them anyway, since some partitions may be | |
843 | * marked read-only, and we don't want to lose that | |
844 | * information, even if it's not 100% accurate. | |
845 | */ | |
846 | dev_warn(&spi->dev, "found %s, expected %s\n", | |
847 | jid->name, id->name); | |
848 | id = jid; | |
849 | info = (void *)jid->driver_data; | |
850 | } | |
851 | } | |
2f9f7628 | 852 | |
e94b1766 | 853 | flash = kzalloc(sizeof *flash, GFP_KERNEL); |
2f9f7628 ML |
854 | if (!flash) |
855 | return -ENOMEM; | |
837479d2 | 856 | flash->command = kmalloc(MAX_CMD_SIZE + FAST_READ_DUMMY_BYTE, GFP_KERNEL); |
61c3506c JS |
857 | if (!flash->command) { |
858 | kfree(flash); | |
859 | return -ENOMEM; | |
860 | } | |
2f9f7628 ML |
861 | |
862 | flash->spi = spi; | |
7d5230ea | 863 | mutex_init(&flash->lock); |
2f9f7628 ML |
864 | dev_set_drvdata(&spi->dev, flash); |
865 | ||
72289824 | 866 | /* |
f80e521c | 867 | * Atmel, SST and Intel/Numonyx serial flash tend to power |
ea60658a | 868 | * up with the software protection bits set |
72289824 MH |
869 | */ |
870 | ||
ea60658a | 871 | if (info->jedec_id >> 16 == 0x1f || |
f80e521c | 872 | info->jedec_id >> 16 == 0x89 || |
ea60658a | 873 | info->jedec_id >> 16 == 0xbf) { |
72289824 MH |
874 | write_enable(flash); |
875 | write_sr(flash, 0); | |
876 | } | |
877 | ||
fa0a8c71 | 878 | if (data && data->name) |
2f9f7628 ML |
879 | flash->mtd.name = data->name; |
880 | else | |
160bbab3 | 881 | flash->mtd.name = dev_name(&spi->dev); |
2f9f7628 ML |
882 | |
883 | flash->mtd.type = MTD_NORFLASH; | |
783ed81f | 884 | flash->mtd.writesize = 1; |
2f9f7628 ML |
885 | flash->mtd.flags = MTD_CAP_NORFLASH; |
886 | flash->mtd.size = info->sector_size * info->n_sectors; | |
2f9f7628 ML |
887 | flash->mtd.erase = m25p80_erase; |
888 | flash->mtd.read = m25p80_read; | |
49aac4ae GY |
889 | |
890 | /* sst flash chips use AAI word program */ | |
891 | if (info->jedec_id >> 16 == 0xbf) | |
892 | flash->mtd.write = sst_write; | |
893 | else | |
894 | flash->mtd.write = m25p80_write; | |
2f9f7628 | 895 | |
fa0a8c71 DB |
896 | /* prefer "small sector" erase if possible */ |
897 | if (info->flags & SECT_4K) { | |
898 | flash->erase_opcode = OPCODE_BE_4K; | |
899 | flash->mtd.erasesize = 4096; | |
900 | } else { | |
901 | flash->erase_opcode = OPCODE_SE; | |
902 | flash->mtd.erasesize = info->sector_size; | |
903 | } | |
904 | ||
837479d2 AV |
905 | if (info->flags & M25P_NO_ERASE) |
906 | flash->mtd.flags |= MTD_NO_ERASE; | |
907 | ||
87f39f04 | 908 | flash->mtd.dev.parent = &spi->dev; |
837479d2 | 909 | flash->page_size = info->page_size; |
4b7f7422 KC |
910 | |
911 | if (info->addr_width) | |
912 | flash->addr_width = info->addr_width; | |
913 | else { | |
914 | /* enable 4-byte addressing if the device exceeds 16MiB */ | |
915 | if (flash->mtd.size > 0x1000000) { | |
916 | flash->addr_width = 4; | |
917 | set_4byte(flash, 1); | |
918 | } else | |
919 | flash->addr_width = 3; | |
920 | } | |
87f39f04 | 921 | |
b34bc037 | 922 | dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name, |
d85316ac | 923 | (long long)flash->mtd.size >> 10); |
2f9f7628 ML |
924 | |
925 | DEBUG(MTD_DEBUG_LEVEL2, | |
d85316ac | 926 | "mtd .name = %s, .size = 0x%llx (%lldMiB) " |
02d087db | 927 | ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", |
2f9f7628 | 928 | flash->mtd.name, |
d85316ac | 929 | (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20), |
2f9f7628 ML |
930 | flash->mtd.erasesize, flash->mtd.erasesize / 1024, |
931 | flash->mtd.numeraseregions); | |
932 | ||
933 | if (flash->mtd.numeraseregions) | |
934 | for (i = 0; i < flash->mtd.numeraseregions; i++) | |
935 | DEBUG(MTD_DEBUG_LEVEL2, | |
d85316ac | 936 | "mtd.eraseregions[%d] = { .offset = 0x%llx, " |
02d087db | 937 | ".erasesize = 0x%.8x (%uKiB), " |
2f9f7628 | 938 | ".numblocks = %d }\n", |
d85316ac | 939 | i, (long long)flash->mtd.eraseregions[i].offset, |
2f9f7628 ML |
940 | flash->mtd.eraseregions[i].erasesize, |
941 | flash->mtd.eraseregions[i].erasesize / 1024, | |
942 | flash->mtd.eraseregions[i].numblocks); | |
943 | ||
944 | ||
945 | /* partitions should match sector boundaries; and it may be good to | |
946 | * use readonly partitions for writeprotected sectors (BP2..BP0). | |
947 | */ | |
948 | if (mtd_has_partitions()) { | |
949 | struct mtd_partition *parts = NULL; | |
950 | int nr_parts = 0; | |
951 | ||
a4b6d516 DB |
952 | if (mtd_has_cmdlinepart()) { |
953 | static const char *part_probes[] | |
954 | = { "cmdlinepart", NULL, }; | |
2f9f7628 | 955 | |
a4b6d516 DB |
956 | nr_parts = parse_mtd_partitions(&flash->mtd, |
957 | part_probes, &parts, 0); | |
958 | } | |
2f9f7628 ML |
959 | |
960 | if (nr_parts <= 0 && data && data->parts) { | |
961 | parts = data->parts; | |
962 | nr_parts = data->nr_parts; | |
963 | } | |
964 | ||
40847437 | 965 | #ifdef CONFIG_MTD_OF_PARTS |
97ff46cb MH |
966 | if (nr_parts <= 0 && spi->dev.of_node) { |
967 | nr_parts = of_mtd_parse_partitions(&spi->dev, | |
968 | spi->dev.of_node, &parts); | |
969 | } | |
970 | #endif | |
971 | ||
2f9f7628 | 972 | if (nr_parts > 0) { |
fa0a8c71 | 973 | for (i = 0; i < nr_parts; i++) { |
2f9f7628 | 974 | DEBUG(MTD_DEBUG_LEVEL2, "partitions[%d] = " |
d85316ac AB |
975 | "{.name = %s, .offset = 0x%llx, " |
976 | ".size = 0x%llx (%lldKiB) }\n", | |
fa0a8c71 | 977 | i, parts[i].name, |
d85316ac AB |
978 | (long long)parts[i].offset, |
979 | (long long)parts[i].size, | |
980 | (long long)(parts[i].size >> 10)); | |
2f9f7628 ML |
981 | } |
982 | flash->partitioned = 1; | |
983 | return add_mtd_partitions(&flash->mtd, parts, nr_parts); | |
984 | } | |
edcb3b14 | 985 | } else if (data && data->nr_parts) |
2f9f7628 ML |
986 | dev_warn(&spi->dev, "ignoring %d default partitions on %s\n", |
987 | data->nr_parts, data->name); | |
988 | ||
989 | return add_mtd_device(&flash->mtd) == 1 ? -ENODEV : 0; | |
990 | } | |
991 | ||
992 | ||
993 | static int __devexit m25p_remove(struct spi_device *spi) | |
994 | { | |
995 | struct m25p *flash = dev_get_drvdata(&spi->dev); | |
996 | int status; | |
997 | ||
998 | /* Clean up MTD stuff. */ | |
999 | if (mtd_has_partitions() && flash->partitioned) | |
1000 | status = del_mtd_partitions(&flash->mtd); | |
1001 | else | |
1002 | status = del_mtd_device(&flash->mtd); | |
61c3506c JS |
1003 | if (status == 0) { |
1004 | kfree(flash->command); | |
2f9f7628 | 1005 | kfree(flash); |
61c3506c | 1006 | } |
2f9f7628 ML |
1007 | return 0; |
1008 | } | |
1009 | ||
1010 | ||
1011 | static struct spi_driver m25p80_driver = { | |
1012 | .driver = { | |
1013 | .name = "m25p80", | |
1014 | .bus = &spi_bus_type, | |
1015 | .owner = THIS_MODULE, | |
1016 | }, | |
b34bc037 | 1017 | .id_table = m25p_ids, |
2f9f7628 ML |
1018 | .probe = m25p_probe, |
1019 | .remove = __devexit_p(m25p_remove), | |
fa0a8c71 DB |
1020 | |
1021 | /* REVISIT: many of these chips have deep power-down modes, which | |
1022 | * should clearly be entered on suspend() to minimize power use. | |
1023 | * And also when they're otherwise idle... | |
1024 | */ | |
2f9f7628 ML |
1025 | }; |
1026 | ||
1027 | ||
627df23c | 1028 | static int __init m25p80_init(void) |
2f9f7628 ML |
1029 | { |
1030 | return spi_register_driver(&m25p80_driver); | |
1031 | } | |
1032 | ||
1033 | ||
627df23c | 1034 | static void __exit m25p80_exit(void) |
2f9f7628 ML |
1035 | { |
1036 | spi_unregister_driver(&m25p80_driver); | |
1037 | } | |
1038 | ||
1039 | ||
1040 | module_init(m25p80_init); | |
1041 | module_exit(m25p80_exit); | |
1042 | ||
1043 | MODULE_LICENSE("GPL"); | |
1044 | MODULE_AUTHOR("Mike Lavender"); | |
1045 | MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips"); |