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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PMC551 PCI Mezzanine Ram Device |
3 | * | |
4 | * Author: | |
cdf0a7d1 JS |
5 | * Mark Ferrell <mferrell@mvista.com> |
6 | * Copyright 1999,2000 Nortel Networks | |
1da177e4 LT |
7 | * |
8 | * License: | |
cdf0a7d1 JS |
9 | * As part of this driver was derived from the slram.c driver it |
10 | * falls under the same license, which is GNU General Public | |
11 | * License v2 | |
1da177e4 LT |
12 | * |
13 | * Description: | |
cdf0a7d1 JS |
14 | * This driver is intended to support the PMC551 PCI Ram device |
15 | * from Ramix Inc. The PMC551 is a PMC Mezzanine module for | |
16 | * cPCI embedded systems. The device contains a single SROM | |
17 | * that initially programs the V370PDC chipset onboard the | |
18 | * device, and various banks of DRAM/SDRAM onboard. This driver | |
19 | * implements this PCI Ram device as an MTD (Memory Technology | |
20 | * Device) so that it can be used to hold a file system, or for | |
21 | * added swap space in embedded systems. Since the memory on | |
22 | * this board isn't as fast as main memory we do not try to hook | |
23 | * it into main memory as that would simply reduce performance | |
24 | * on the system. Using it as a block device allows us to use | |
25 | * it as high speed swap or for a high speed disk device of some | |
26 | * sort. Which becomes very useful on diskless systems in the | |
27 | * embedded market I might add. | |
e5580fbe | 28 | * |
1da177e4 | 29 | * Notes: |
cdf0a7d1 | 30 | * Due to what I assume is more buggy SROM, the 64M PMC551 I |
8e0aedc5 DW |
31 | * have available claims that all 4 of its DRAM banks have 64MiB |
32 | * of ram configured (making a grand total of 256MiB onboard). | |
cdf0a7d1 JS |
33 | * This is slightly annoying since the BAR0 size reflects the |
34 | * aperture size, not the dram size, and the V370PDC supplies no | |
35 | * other method for memory size discovery. This problem is | |
36 | * mostly only relevant when compiled as a module, as the | |
025dfdaf | 37 | * unloading of the module with an aperture size smaller than |
cdf0a7d1 JS |
38 | * the ram will cause the driver to detect the onboard memory |
39 | * size to be equal to the aperture size when the module is | |
40 | * reloaded. Soooo, to help, the module supports an msize | |
41 | * option to allow the specification of the onboard memory, and | |
42 | * an asize option, to allow the specification of the aperture | |
43 | * size. The aperture must be equal to or less then the memory | |
44 | * size, the driver will correct this if you screw it up. This | |
45 | * problem is not relevant for compiled in drivers as compiled | |
46 | * in drivers only init once. | |
1da177e4 LT |
47 | * |
48 | * Credits: | |
cdf0a7d1 JS |
49 | * Saeed Karamooz <saeed@ramix.com> of Ramix INC. for the |
50 | * initial example code of how to initialize this device and for | |
51 | * help with questions I had concerning operation of the device. | |
1da177e4 | 52 | * |
cdf0a7d1 JS |
53 | * Most of the MTD code for this driver was originally written |
54 | * for the slram.o module in the MTD drivers package which | |
55 | * allows the mapping of system memory into an MTD device. | |
56 | * Since the PMC551 memory module is accessed in the same | |
57 | * fashion as system memory, the slram.c code became a very nice | |
58 | * fit to the needs of this driver. All we added was PCI | |
59 | * detection/initialization to the driver and automatically figure | |
60 | * out the size via the PCI detection.o, later changes by Corey | |
61 | * Minyard set up the card to utilize a 1M sliding apature. | |
1da177e4 | 62 | * |
cdf0a7d1 JS |
63 | * Corey Minyard <minyard@nortelnetworks.com> |
64 | * * Modified driver to utilize a sliding aperture instead of | |
65 | * mapping all memory into kernel space which turned out to | |
66 | * be very wasteful. | |
67 | * * Located a bug in the SROM's initialization sequence that | |
68 | * made the memory unusable, added a fix to code to touch up | |
69 | * the DRAM some. | |
1da177e4 | 70 | * |
8e0aedc5 | 71 | * Bugs/FIXMEs: |
cdf0a7d1 JS |
72 | * * MUST fix the init function to not spin on a register |
73 | * waiting for it to set .. this does not safely handle busted | |
74 | * devices that never reset the register correctly which will | |
75 | * cause the system to hang w/ a reboot being the only chance at | |
76 | * recover. [sort of fixed, could be better] | |
77 | * * Add I2C handling of the SROM so we can read the SROM's information | |
78 | * about the aperture size. This should always accurately reflect the | |
79 | * onboard memory size. | |
80 | * * Comb the init routine. It's still a bit cludgy on a few things. | |
1da177e4 LT |
81 | */ |
82 | ||
1da177e4 LT |
83 | #include <linux/kernel.h> |
84 | #include <linux/module.h> | |
85 | #include <asm/uaccess.h> | |
86 | #include <linux/types.h> | |
1da177e4 LT |
87 | #include <linux/init.h> |
88 | #include <linux/ptrace.h> | |
89 | #include <linux/slab.h> | |
90 | #include <linux/string.h> | |
91 | #include <linux/timer.h> | |
92 | #include <linux/major.h> | |
93 | #include <linux/fs.h> | |
94 | #include <linux/ioctl.h> | |
95 | #include <asm/io.h> | |
1da177e4 | 96 | #include <linux/pci.h> |
1da177e4 | 97 | #include <linux/mtd/mtd.h> |
c3faac4a AB |
98 | |
99 | #define PMC551_VERSION \ | |
100 | "Ramix PMC551 PCI Mezzanine Ram Driver. (C) 1999,2000 Nortel Networks.\n" | |
101 | ||
102 | #define PCI_VENDOR_ID_V3_SEMI 0x11b0 | |
103 | #define PCI_DEVICE_ID_V3_SEMI_V370PDC 0x0200 | |
104 | ||
105 | #define PMC551_PCI_MEM_MAP0 0x50 | |
106 | #define PMC551_PCI_MEM_MAP1 0x54 | |
107 | #define PMC551_PCI_MEM_MAP_MAP_ADDR_MASK 0x3ff00000 | |
108 | #define PMC551_PCI_MEM_MAP_APERTURE_MASK 0x000000f0 | |
109 | #define PMC551_PCI_MEM_MAP_REG_EN 0x00000002 | |
110 | #define PMC551_PCI_MEM_MAP_ENABLE 0x00000001 | |
111 | ||
112 | #define PMC551_SDRAM_MA 0x60 | |
113 | #define PMC551_SDRAM_CMD 0x62 | |
114 | #define PMC551_DRAM_CFG 0x64 | |
115 | #define PMC551_SYS_CTRL_REG 0x78 | |
116 | ||
117 | #define PMC551_DRAM_BLK0 0x68 | |
118 | #define PMC551_DRAM_BLK1 0x6c | |
119 | #define PMC551_DRAM_BLK2 0x70 | |
120 | #define PMC551_DRAM_BLK3 0x74 | |
121 | #define PMC551_DRAM_BLK_GET_SIZE(x) (524288 << ((x >> 4) & 0x0f)) | |
122 | #define PMC551_DRAM_BLK_SET_COL_MUX(x, v) (((x) & ~0x00007000) | (((v) & 0x7) << 12)) | |
123 | #define PMC551_DRAM_BLK_SET_ROW_MUX(x, v) (((x) & ~0x00000f00) | (((v) & 0xf) << 8)) | |
124 | ||
125 | struct mypriv { | |
126 | struct pci_dev *dev; | |
127 | u_char *start; | |
128 | u32 base_map0; | |
129 | u32 curr_map0; | |
130 | u32 asize; | |
131 | struct mtd_info *nextpmc551; | |
132 | }; | |
1da177e4 LT |
133 | |
134 | static struct mtd_info *pmc551list; | |
135 | ||
c3faac4a AB |
136 | static int pmc551_point(struct mtd_info *mtd, loff_t from, size_t len, |
137 | size_t *retlen, void **virt, resource_size_t *phys); | |
138 | ||
cdf0a7d1 | 139 | static int pmc551_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 140 | { |
cdf0a7d1 JS |
141 | struct mypriv *priv = mtd->priv; |
142 | u32 soff_hi, soff_lo; /* start address offset hi/lo */ | |
143 | u32 eoff_hi, eoff_lo; /* end address offset hi/lo */ | |
144 | unsigned long end; | |
1da177e4 LT |
145 | u_char *ptr; |
146 | size_t retlen; | |
147 | ||
148 | #ifdef CONFIG_MTD_PMC551_DEBUG | |
cdf0a7d1 JS |
149 | printk(KERN_DEBUG "pmc551_erase(pos:%ld, len:%ld)\n", (long)instr->addr, |
150 | (long)instr->len); | |
1da177e4 LT |
151 | #endif |
152 | ||
cdf0a7d1 | 153 | end = instr->addr + instr->len - 1; |
cdf0a7d1 JS |
154 | eoff_hi = end & ~(priv->asize - 1); |
155 | soff_hi = instr->addr & ~(priv->asize - 1); | |
156 | eoff_lo = end & (priv->asize - 1); | |
157 | soff_lo = instr->addr & (priv->asize - 1); | |
158 | ||
a98889f3 JH |
159 | pmc551_point(mtd, instr->addr, instr->len, &retlen, |
160 | (void **)&ptr, NULL); | |
cdf0a7d1 JS |
161 | |
162 | if (soff_hi == eoff_hi || mtd->size == priv->asize) { | |
163 | /* The whole thing fits within one access, so just one shot | |
164 | will do it. */ | |
165 | memset(ptr, 0xff, instr->len); | |
166 | } else { | |
167 | /* We have to do multiple writes to get all the data | |
168 | written. */ | |
169 | while (soff_hi != eoff_hi) { | |
1da177e4 | 170 | #ifdef CONFIG_MTD_PMC551_DEBUG |
cdf0a7d1 JS |
171 | printk(KERN_DEBUG "pmc551_erase() soff_hi: %ld, " |
172 | "eoff_hi: %ld\n", (long)soff_hi, (long)eoff_hi); | |
1da177e4 | 173 | #endif |
cdf0a7d1 JS |
174 | memset(ptr, 0xff, priv->asize); |
175 | if (soff_hi + priv->asize >= mtd->size) { | |
176 | goto out; | |
177 | } | |
178 | soff_hi += priv->asize; | |
179 | pmc551_point(mtd, (priv->base_map0 | soff_hi), | |
a98889f3 JH |
180 | priv->asize, &retlen, |
181 | (void **)&ptr, NULL); | |
cdf0a7d1 JS |
182 | } |
183 | memset(ptr, 0xff, eoff_lo); | |
184 | } | |
185 | ||
186 | out: | |
1da177e4 LT |
187 | instr->state = MTD_ERASE_DONE; |
188 | #ifdef CONFIG_MTD_PMC551_DEBUG | |
189 | printk(KERN_DEBUG "pmc551_erase() done\n"); | |
190 | #endif | |
191 | ||
cdf0a7d1 JS |
192 | mtd_erase_callback(instr); |
193 | return 0; | |
1da177e4 LT |
194 | } |
195 | ||
cdf0a7d1 | 196 | static int pmc551_point(struct mtd_info *mtd, loff_t from, size_t len, |
a98889f3 | 197 | size_t *retlen, void **virt, resource_size_t *phys) |
1da177e4 | 198 | { |
cdf0a7d1 JS |
199 | struct mypriv *priv = mtd->priv; |
200 | u32 soff_hi; | |
201 | u32 soff_lo; | |
1da177e4 LT |
202 | |
203 | #ifdef CONFIG_MTD_PMC551_DEBUG | |
204 | printk(KERN_DEBUG "pmc551_point(%ld, %ld)\n", (long)from, (long)len); | |
205 | #endif | |
206 | ||
cdf0a7d1 JS |
207 | soff_hi = from & ~(priv->asize - 1); |
208 | soff_lo = from & (priv->asize - 1); | |
1da177e4 LT |
209 | |
210 | /* Cheap hack optimization */ | |
cdf0a7d1 JS |
211 | if (priv->curr_map0 != from) { |
212 | pci_write_config_dword(priv->dev, PMC551_PCI_MEM_MAP0, | |
213 | (priv->base_map0 | soff_hi)); | |
1da177e4 LT |
214 | priv->curr_map0 = soff_hi; |
215 | } | |
216 | ||
a98889f3 | 217 | *virt = priv->start + soff_lo; |
1da177e4 LT |
218 | *retlen = len; |
219 | return 0; | |
220 | } | |
221 | ||
5e4e6e3f | 222 | static int pmc551_unpoint(struct mtd_info *mtd, loff_t from, size_t len) |
1da177e4 LT |
223 | { |
224 | #ifdef CONFIG_MTD_PMC551_DEBUG | |
225 | printk(KERN_DEBUG "pmc551_unpoint()\n"); | |
226 | #endif | |
5e4e6e3f | 227 | return 0; |
1da177e4 LT |
228 | } |
229 | ||
cdf0a7d1 JS |
230 | static int pmc551_read(struct mtd_info *mtd, loff_t from, size_t len, |
231 | size_t * retlen, u_char * buf) | |
1da177e4 | 232 | { |
cdf0a7d1 JS |
233 | struct mypriv *priv = mtd->priv; |
234 | u32 soff_hi, soff_lo; /* start address offset hi/lo */ | |
235 | u32 eoff_hi, eoff_lo; /* end address offset hi/lo */ | |
236 | unsigned long end; | |
1da177e4 | 237 | u_char *ptr; |
cdf0a7d1 | 238 | u_char *copyto = buf; |
1da177e4 LT |
239 | |
240 | #ifdef CONFIG_MTD_PMC551_DEBUG | |
cdf0a7d1 JS |
241 | printk(KERN_DEBUG "pmc551_read(pos:%ld, len:%ld) asize: %ld\n", |
242 | (long)from, (long)len, (long)priv->asize); | |
1da177e4 LT |
243 | #endif |
244 | ||
cdf0a7d1 | 245 | end = from + len - 1; |
cdf0a7d1 JS |
246 | soff_hi = from & ~(priv->asize - 1); |
247 | eoff_hi = end & ~(priv->asize - 1); | |
248 | soff_lo = from & (priv->asize - 1); | |
249 | eoff_lo = end & (priv->asize - 1); | |
250 | ||
a98889f3 | 251 | pmc551_point(mtd, from, len, retlen, (void **)&ptr, NULL); |
cdf0a7d1 JS |
252 | |
253 | if (soff_hi == eoff_hi) { | |
254 | /* The whole thing fits within one access, so just one shot | |
255 | will do it. */ | |
256 | memcpy(copyto, ptr, len); | |
257 | copyto += len; | |
258 | } else { | |
259 | /* We have to do multiple writes to get all the data | |
260 | written. */ | |
261 | while (soff_hi != eoff_hi) { | |
1da177e4 | 262 | #ifdef CONFIG_MTD_PMC551_DEBUG |
cdf0a7d1 JS |
263 | printk(KERN_DEBUG "pmc551_read() soff_hi: %ld, " |
264 | "eoff_hi: %ld\n", (long)soff_hi, (long)eoff_hi); | |
1da177e4 | 265 | #endif |
cdf0a7d1 JS |
266 | memcpy(copyto, ptr, priv->asize); |
267 | copyto += priv->asize; | |
268 | if (soff_hi + priv->asize >= mtd->size) { | |
269 | goto out; | |
270 | } | |
271 | soff_hi += priv->asize; | |
a98889f3 JH |
272 | pmc551_point(mtd, soff_hi, priv->asize, retlen, |
273 | (void **)&ptr, NULL); | |
cdf0a7d1 JS |
274 | } |
275 | memcpy(copyto, ptr, eoff_lo); | |
276 | copyto += eoff_lo; | |
277 | } | |
278 | ||
279 | out: | |
1da177e4 LT |
280 | #ifdef CONFIG_MTD_PMC551_DEBUG |
281 | printk(KERN_DEBUG "pmc551_read() done\n"); | |
282 | #endif | |
cdf0a7d1 JS |
283 | *retlen = copyto - buf; |
284 | return 0; | |
1da177e4 LT |
285 | } |
286 | ||
cdf0a7d1 JS |
287 | static int pmc551_write(struct mtd_info *mtd, loff_t to, size_t len, |
288 | size_t * retlen, const u_char * buf) | |
1da177e4 | 289 | { |
cdf0a7d1 JS |
290 | struct mypriv *priv = mtd->priv; |
291 | u32 soff_hi, soff_lo; /* start address offset hi/lo */ | |
292 | u32 eoff_hi, eoff_lo; /* end address offset hi/lo */ | |
293 | unsigned long end; | |
1da177e4 | 294 | u_char *ptr; |
cdf0a7d1 | 295 | const u_char *copyfrom = buf; |
1da177e4 LT |
296 | |
297 | #ifdef CONFIG_MTD_PMC551_DEBUG | |
cdf0a7d1 JS |
298 | printk(KERN_DEBUG "pmc551_write(pos:%ld, len:%ld) asize:%ld\n", |
299 | (long)to, (long)len, (long)priv->asize); | |
1da177e4 LT |
300 | #endif |
301 | ||
cdf0a7d1 | 302 | end = to + len - 1; |
cdf0a7d1 JS |
303 | soff_hi = to & ~(priv->asize - 1); |
304 | eoff_hi = end & ~(priv->asize - 1); | |
305 | soff_lo = to & (priv->asize - 1); | |
306 | eoff_lo = end & (priv->asize - 1); | |
307 | ||
a98889f3 | 308 | pmc551_point(mtd, to, len, retlen, (void **)&ptr, NULL); |
cdf0a7d1 JS |
309 | |
310 | if (soff_hi == eoff_hi) { | |
311 | /* The whole thing fits within one access, so just one shot | |
312 | will do it. */ | |
313 | memcpy(ptr, copyfrom, len); | |
314 | copyfrom += len; | |
315 | } else { | |
316 | /* We have to do multiple writes to get all the data | |
317 | written. */ | |
318 | while (soff_hi != eoff_hi) { | |
1da177e4 | 319 | #ifdef CONFIG_MTD_PMC551_DEBUG |
cdf0a7d1 JS |
320 | printk(KERN_DEBUG "pmc551_write() soff_hi: %ld, " |
321 | "eoff_hi: %ld\n", (long)soff_hi, (long)eoff_hi); | |
1da177e4 | 322 | #endif |
cdf0a7d1 JS |
323 | memcpy(ptr, copyfrom, priv->asize); |
324 | copyfrom += priv->asize; | |
325 | if (soff_hi >= mtd->size) { | |
326 | goto out; | |
327 | } | |
328 | soff_hi += priv->asize; | |
a98889f3 JH |
329 | pmc551_point(mtd, soff_hi, priv->asize, retlen, |
330 | (void **)&ptr, NULL); | |
cdf0a7d1 JS |
331 | } |
332 | memcpy(ptr, copyfrom, eoff_lo); | |
333 | copyfrom += eoff_lo; | |
334 | } | |
335 | ||
336 | out: | |
1da177e4 LT |
337 | #ifdef CONFIG_MTD_PMC551_DEBUG |
338 | printk(KERN_DEBUG "pmc551_write() done\n"); | |
339 | #endif | |
cdf0a7d1 JS |
340 | *retlen = copyfrom - buf; |
341 | return 0; | |
1da177e4 LT |
342 | } |
343 | ||
344 | /* | |
345 | * Fixup routines for the V370PDC | |
346 | * PCI device ID 0x020011b0 | |
347 | * | |
25985edc | 348 | * This function basically kick starts the DRAM oboard the card and gets it |
1da177e4 LT |
349 | * ready to be used. Before this is done the device reads VERY erratic, so |
350 | * much that it can crash the Linux 2.2.x series kernels when a user cat's | |
351 | * /proc/pci .. though that is mainly a kernel bug in handling the PCI DEVSEL | |
352 | * register. FIXME: stop spinning on registers .. must implement a timeout | |
353 | * mechanism | |
354 | * returns the size of the memory region found. | |
355 | */ | |
2ff5e153 | 356 | static int fixup_pmc551(struct pci_dev *dev) |
1da177e4 LT |
357 | { |
358 | #ifdef CONFIG_MTD_PMC551_BUGFIX | |
cdf0a7d1 | 359 | u32 dram_data; |
1da177e4 | 360 | #endif |
cdf0a7d1 JS |
361 | u32 size, dcmd, cfg, dtmp; |
362 | u16 cmd, tmp, i; | |
1da177e4 LT |
363 | u8 bcmd, counter; |
364 | ||
cdf0a7d1 JS |
365 | /* Sanity Check */ |
366 | if (!dev) { | |
367 | return -ENODEV; | |
368 | } | |
1da177e4 LT |
369 | |
370 | /* | |
371 | * Attempt to reset the card | |
372 | * FIXME: Stop Spinning registers | |
373 | */ | |
cdf0a7d1 | 374 | counter = 0; |
1da177e4 | 375 | /* unlock registers */ |
cdf0a7d1 | 376 | pci_write_config_byte(dev, PMC551_SYS_CTRL_REG, 0xA5); |
1da177e4 | 377 | /* read in old data */ |
cdf0a7d1 | 378 | pci_read_config_byte(dev, PMC551_SYS_CTRL_REG, &bcmd); |
1da177e4 | 379 | /* bang the reset line up and down for a few */ |
cdf0a7d1 JS |
380 | for (i = 0; i < 10; i++) { |
381 | counter = 0; | |
1da177e4 | 382 | bcmd &= ~0x80; |
cdf0a7d1 | 383 | while (counter++ < 100) { |
1da177e4 LT |
384 | pci_write_config_byte(dev, PMC551_SYS_CTRL_REG, bcmd); |
385 | } | |
cdf0a7d1 | 386 | counter = 0; |
1da177e4 | 387 | bcmd |= 0x80; |
cdf0a7d1 | 388 | while (counter++ < 100) { |
1da177e4 LT |
389 | pci_write_config_byte(dev, PMC551_SYS_CTRL_REG, bcmd); |
390 | } | |
391 | } | |
cdf0a7d1 | 392 | bcmd |= (0x40 | 0x20); |
1da177e4 LT |
393 | pci_write_config_byte(dev, PMC551_SYS_CTRL_REG, bcmd); |
394 | ||
cdf0a7d1 | 395 | /* |
1da177e4 LT |
396 | * Take care and turn off the memory on the device while we |
397 | * tweak the configurations | |
398 | */ | |
cdf0a7d1 JS |
399 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
400 | tmp = cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY); | |
401 | pci_write_config_word(dev, PCI_COMMAND, tmp); | |
1da177e4 LT |
402 | |
403 | /* | |
404 | * Disable existing aperture before probing memory size | |
405 | */ | |
406 | pci_read_config_dword(dev, PMC551_PCI_MEM_MAP0, &dcmd); | |
cdf0a7d1 | 407 | dtmp = (dcmd | PMC551_PCI_MEM_MAP_ENABLE | PMC551_PCI_MEM_MAP_REG_EN); |
1da177e4 LT |
408 | pci_write_config_dword(dev, PMC551_PCI_MEM_MAP0, dtmp); |
409 | /* | |
410 | * Grab old BAR0 config so that we can figure out memory size | |
411 | * This is another bit of kludge going on. The reason for the | |
412 | * redundancy is I am hoping to retain the original configuration | |
e5580fbe | 413 | * previously assigned to the card by the BIOS or some previous |
1da177e4 LT |
414 | * fixup routine in the kernel. So we read the old config into cfg, |
415 | * then write all 1's to the memory space, read back the result into | |
416 | * "size", and then write back all the old config. | |
417 | */ | |
cdf0a7d1 | 418 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &cfg); |
1da177e4 | 419 | #ifndef CONFIG_MTD_PMC551_BUGFIX |
cdf0a7d1 JS |
420 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, ~0); |
421 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &size); | |
422 | size = (size & PCI_BASE_ADDRESS_MEM_MASK); | |
423 | size &= ~(size - 1); | |
424 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, cfg); | |
1da177e4 | 425 | #else |
cdf0a7d1 JS |
426 | /* |
427 | * Get the size of the memory by reading all the DRAM size values | |
428 | * and adding them up. | |
429 | * | |
430 | * KLUDGE ALERT: the boards we are using have invalid column and | |
431 | * row mux values. We fix them here, but this will break other | |
432 | * memory configurations. | |
433 | */ | |
434 | pci_read_config_dword(dev, PMC551_DRAM_BLK0, &dram_data); | |
435 | size = PMC551_DRAM_BLK_GET_SIZE(dram_data); | |
436 | dram_data = PMC551_DRAM_BLK_SET_COL_MUX(dram_data, 0x5); | |
437 | dram_data = PMC551_DRAM_BLK_SET_ROW_MUX(dram_data, 0x9); | |
438 | pci_write_config_dword(dev, PMC551_DRAM_BLK0, dram_data); | |
439 | ||
440 | pci_read_config_dword(dev, PMC551_DRAM_BLK1, &dram_data); | |
441 | size += PMC551_DRAM_BLK_GET_SIZE(dram_data); | |
442 | dram_data = PMC551_DRAM_BLK_SET_COL_MUX(dram_data, 0x5); | |
443 | dram_data = PMC551_DRAM_BLK_SET_ROW_MUX(dram_data, 0x9); | |
444 | pci_write_config_dword(dev, PMC551_DRAM_BLK1, dram_data); | |
445 | ||
446 | pci_read_config_dword(dev, PMC551_DRAM_BLK2, &dram_data); | |
447 | size += PMC551_DRAM_BLK_GET_SIZE(dram_data); | |
448 | dram_data = PMC551_DRAM_BLK_SET_COL_MUX(dram_data, 0x5); | |
449 | dram_data = PMC551_DRAM_BLK_SET_ROW_MUX(dram_data, 0x9); | |
450 | pci_write_config_dword(dev, PMC551_DRAM_BLK2, dram_data); | |
451 | ||
452 | pci_read_config_dword(dev, PMC551_DRAM_BLK3, &dram_data); | |
453 | size += PMC551_DRAM_BLK_GET_SIZE(dram_data); | |
454 | dram_data = PMC551_DRAM_BLK_SET_COL_MUX(dram_data, 0x5); | |
455 | dram_data = PMC551_DRAM_BLK_SET_ROW_MUX(dram_data, 0x9); | |
456 | pci_write_config_dword(dev, PMC551_DRAM_BLK3, dram_data); | |
457 | ||
458 | /* | |
459 | * Oops .. something went wrong | |
460 | */ | |
461 | if ((size &= PCI_BASE_ADDRESS_MEM_MASK) == 0) { | |
462 | return -ENODEV; | |
1da177e4 | 463 | } |
cdf0a7d1 | 464 | #endif /* CONFIG_MTD_PMC551_BUGFIX */ |
1da177e4 | 465 | |
cdf0a7d1 JS |
466 | if ((cfg & PCI_BASE_ADDRESS_SPACE) != PCI_BASE_ADDRESS_SPACE_MEMORY) { |
467 | return -ENODEV; | |
468 | } | |
469 | ||
470 | /* | |
471 | * Precharge Dram | |
472 | */ | |
473 | pci_write_config_word(dev, PMC551_SDRAM_MA, 0x0400); | |
474 | pci_write_config_word(dev, PMC551_SDRAM_CMD, 0x00bf); | |
475 | ||
476 | /* | |
477 | * Wait until command has gone through | |
478 | * FIXME: register spinning issue | |
479 | */ | |
480 | do { | |
481 | pci_read_config_word(dev, PMC551_SDRAM_CMD, &cmd); | |
482 | if (counter++ > 100) | |
483 | break; | |
484 | } while ((PCI_COMMAND_IO) & cmd); | |
485 | ||
486 | /* | |
e5580fbe | 487 | * Turn on auto refresh |
1da177e4 LT |
488 | * The loop is taken directly from Ramix's example code. I assume that |
489 | * this must be held high for some duration of time, but I can find no | |
490 | * documentation refrencing the reasons why. | |
cdf0a7d1 JS |
491 | */ |
492 | for (i = 1; i <= 8; i++) { | |
493 | pci_write_config_word(dev, PMC551_SDRAM_CMD, 0x0df); | |
494 | ||
495 | /* | |
496 | * Make certain command has gone through | |
497 | * FIXME: register spinning issue | |
498 | */ | |
499 | counter = 0; | |
500 | do { | |
501 | pci_read_config_word(dev, PMC551_SDRAM_CMD, &cmd); | |
502 | if (counter++ > 100) | |
503 | break; | |
504 | } while ((PCI_COMMAND_IO) & cmd); | |
505 | } | |
506 | ||
507 | pci_write_config_word(dev, PMC551_SDRAM_MA, 0x0020); | |
508 | pci_write_config_word(dev, PMC551_SDRAM_CMD, 0x0ff); | |
509 | ||
510 | /* | |
511 | * Wait until command completes | |
512 | * FIXME: register spinning issue | |
513 | */ | |
514 | counter = 0; | |
515 | do { | |
516 | pci_read_config_word(dev, PMC551_SDRAM_CMD, &cmd); | |
517 | if (counter++ > 100) | |
518 | break; | |
519 | } while ((PCI_COMMAND_IO) & cmd); | |
520 | ||
521 | pci_read_config_dword(dev, PMC551_DRAM_CFG, &dcmd); | |
522 | dcmd |= 0x02000000; | |
523 | pci_write_config_dword(dev, PMC551_DRAM_CFG, dcmd); | |
524 | ||
525 | /* | |
526 | * Check to make certain fast back-to-back, if not | |
527 | * then set it so | |
528 | */ | |
529 | pci_read_config_word(dev, PCI_STATUS, &cmd); | |
530 | if ((cmd & PCI_COMMAND_FAST_BACK) == 0) { | |
531 | cmd |= PCI_COMMAND_FAST_BACK; | |
532 | pci_write_config_word(dev, PCI_STATUS, cmd); | |
533 | } | |
534 | ||
535 | /* | |
536 | * Check to make certain the DEVSEL is set correctly, this device | |
25985edc | 537 | * has a tendency to assert DEVSEL and TRDY when a write is performed |
cdf0a7d1 JS |
538 | * to the memory when memory is read-only |
539 | */ | |
540 | if ((cmd & PCI_STATUS_DEVSEL_MASK) != 0x0) { | |
541 | cmd &= ~PCI_STATUS_DEVSEL_MASK; | |
542 | pci_write_config_word(dev, PCI_STATUS, cmd); | |
543 | } | |
544 | /* | |
545 | * Set to be prefetchable and put everything back based on old cfg. | |
1da177e4 LT |
546 | * it's possible that the reset of the V370PDC nuked the original |
547 | * setup | |
cdf0a7d1 | 548 | */ |
1da177e4 | 549 | /* |
cdf0a7d1 JS |
550 | cfg |= PCI_BASE_ADDRESS_MEM_PREFETCH; |
551 | pci_write_config_dword( dev, PCI_BASE_ADDRESS_0, cfg ); | |
552 | */ | |
553 | ||
554 | /* | |
555 | * Turn PCI memory and I/O bus access back on | |
556 | */ | |
557 | pci_write_config_word(dev, PCI_COMMAND, | |
558 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); | |
1da177e4 | 559 | #ifdef CONFIG_MTD_PMC551_DEBUG |
cdf0a7d1 JS |
560 | /* |
561 | * Some screen fun | |
562 | */ | |
8e0aedc5 | 563 | printk(KERN_DEBUG "pmc551: %d%sB (0x%x) of %sprefetchable memory at " |
cdf0a7d1 JS |
564 | "0x%llx\n", (size < 1024) ? size : (size < 1048576) ? |
565 | size >> 10 : size >> 20, | |
8e0aedc5 | 566 | (size < 1024) ? "" : (size < 1048576) ? "Ki" : "Mi", size, |
cdf0a7d1 | 567 | ((dcmd & (0x1 << 3)) == 0) ? "non-" : "", |
98aacdfd | 568 | (unsigned long long)pci_resource_start(dev, 0)); |
cdf0a7d1 JS |
569 | |
570 | /* | |
571 | * Check to see the state of the memory | |
572 | */ | |
573 | pci_read_config_dword(dev, PMC551_DRAM_BLK0, &dcmd); | |
574 | printk(KERN_DEBUG "pmc551: DRAM_BLK0 Flags: %s,%s\n" | |
575 | "pmc551: DRAM_BLK0 Size: %d at %d\n" | |
576 | "pmc551: DRAM_BLK0 Row MUX: %d, Col MUX: %d\n", | |
577 | (((0x1 << 1) & dcmd) == 0) ? "RW" : "RO", | |
578 | (((0x1 << 0) & dcmd) == 0) ? "Off" : "On", | |
579 | PMC551_DRAM_BLK_GET_SIZE(dcmd), | |
580 | ((dcmd >> 20) & 0x7FF), ((dcmd >> 13) & 0x7), | |
581 | ((dcmd >> 9) & 0xF)); | |
582 | ||
583 | pci_read_config_dword(dev, PMC551_DRAM_BLK1, &dcmd); | |
584 | printk(KERN_DEBUG "pmc551: DRAM_BLK1 Flags: %s,%s\n" | |
585 | "pmc551: DRAM_BLK1 Size: %d at %d\n" | |
586 | "pmc551: DRAM_BLK1 Row MUX: %d, Col MUX: %d\n", | |
587 | (((0x1 << 1) & dcmd) == 0) ? "RW" : "RO", | |
588 | (((0x1 << 0) & dcmd) == 0) ? "Off" : "On", | |
589 | PMC551_DRAM_BLK_GET_SIZE(dcmd), | |
590 | ((dcmd >> 20) & 0x7FF), ((dcmd >> 13) & 0x7), | |
591 | ((dcmd >> 9) & 0xF)); | |
592 | ||
593 | pci_read_config_dword(dev, PMC551_DRAM_BLK2, &dcmd); | |
594 | printk(KERN_DEBUG "pmc551: DRAM_BLK2 Flags: %s,%s\n" | |
595 | "pmc551: DRAM_BLK2 Size: %d at %d\n" | |
596 | "pmc551: DRAM_BLK2 Row MUX: %d, Col MUX: %d\n", | |
597 | (((0x1 << 1) & dcmd) == 0) ? "RW" : "RO", | |
598 | (((0x1 << 0) & dcmd) == 0) ? "Off" : "On", | |
599 | PMC551_DRAM_BLK_GET_SIZE(dcmd), | |
600 | ((dcmd >> 20) & 0x7FF), ((dcmd >> 13) & 0x7), | |
601 | ((dcmd >> 9) & 0xF)); | |
602 | ||
603 | pci_read_config_dword(dev, PMC551_DRAM_BLK3, &dcmd); | |
604 | printk(KERN_DEBUG "pmc551: DRAM_BLK3 Flags: %s,%s\n" | |
605 | "pmc551: DRAM_BLK3 Size: %d at %d\n" | |
606 | "pmc551: DRAM_BLK3 Row MUX: %d, Col MUX: %d\n", | |
607 | (((0x1 << 1) & dcmd) == 0) ? "RW" : "RO", | |
608 | (((0x1 << 0) & dcmd) == 0) ? "Off" : "On", | |
609 | PMC551_DRAM_BLK_GET_SIZE(dcmd), | |
610 | ((dcmd >> 20) & 0x7FF), ((dcmd >> 13) & 0x7), | |
611 | ((dcmd >> 9) & 0xF)); | |
612 | ||
613 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
614 | printk(KERN_DEBUG "pmc551: Memory Access %s\n", | |
615 | (((0x1 << 1) & cmd) == 0) ? "off" : "on"); | |
616 | printk(KERN_DEBUG "pmc551: I/O Access %s\n", | |
617 | (((0x1 << 0) & cmd) == 0) ? "off" : "on"); | |
618 | ||
619 | pci_read_config_word(dev, PCI_STATUS, &cmd); | |
620 | printk(KERN_DEBUG "pmc551: Devsel %s\n", | |
621 | ((PCI_STATUS_DEVSEL_MASK & cmd) == 0x000) ? "Fast" : | |
622 | ((PCI_STATUS_DEVSEL_MASK & cmd) == 0x200) ? "Medium" : | |
623 | ((PCI_STATUS_DEVSEL_MASK & cmd) == 0x400) ? "Slow" : "Invalid"); | |
624 | ||
625 | printk(KERN_DEBUG "pmc551: %sFast Back-to-Back\n", | |
626 | ((PCI_COMMAND_FAST_BACK & cmd) == 0) ? "Not " : ""); | |
627 | ||
628 | pci_read_config_byte(dev, PMC551_SYS_CTRL_REG, &bcmd); | |
629 | printk(KERN_DEBUG "pmc551: EEPROM is under %s control\n" | |
630 | "pmc551: System Control Register is %slocked to PCI access\n" | |
631 | "pmc551: System Control Register is %slocked to EEPROM access\n", | |
632 | (bcmd & 0x1) ? "software" : "hardware", | |
633 | (bcmd & 0x20) ? "" : "un", (bcmd & 0x40) ? "" : "un"); | |
1da177e4 | 634 | #endif |
cdf0a7d1 | 635 | return size; |
1da177e4 LT |
636 | } |
637 | ||
638 | /* | |
639 | * Kernel version specific module stuffages | |
640 | */ | |
641 | ||
1da177e4 LT |
642 | MODULE_LICENSE("GPL"); |
643 | MODULE_AUTHOR("Mark Ferrell <mferrell@mvista.com>"); | |
644 | MODULE_DESCRIPTION(PMC551_VERSION); | |
645 | ||
646 | /* | |
647 | * Stuff these outside the ifdef so as to not bust compiled in driver support | |
648 | */ | |
cdf0a7d1 | 649 | static int msize = 0; |
cdf0a7d1 | 650 | static int asize = 0; |
1da177e4 LT |
651 | |
652 | module_param(msize, int, 0); | |
8e0aedc5 | 653 | MODULE_PARM_DESC(msize, "memory size in MiB [1 - 1024]"); |
1da177e4 LT |
654 | module_param(asize, int, 0); |
655 | MODULE_PARM_DESC(asize, "aperture size, must be <= memsize [1-1024]"); | |
656 | ||
657 | /* | |
658 | * PMC551 Card Initialization | |
659 | */ | |
660 | static int __init init_pmc551(void) | |
661 | { | |
cdf0a7d1 JS |
662 | struct pci_dev *PCI_Device = NULL; |
663 | struct mypriv *priv; | |
24c15496 | 664 | int found = 0; |
cdf0a7d1 | 665 | struct mtd_info *mtd; |
2ff5e153 | 666 | int length = 0; |
cdf0a7d1 JS |
667 | |
668 | if (msize) { | |
669 | msize = (1 << (ffs(msize) - 1)) << 20; | |
670 | if (msize > (1 << 30)) { | |
671 | printk(KERN_NOTICE "pmc551: Invalid memory size [%d]\n", | |
672 | msize); | |
1da177e4 LT |
673 | return -EINVAL; |
674 | } | |
675 | } | |
676 | ||
cdf0a7d1 JS |
677 | if (asize) { |
678 | asize = (1 << (ffs(asize) - 1)) << 20; | |
679 | if (asize > (1 << 30)) { | |
680 | printk(KERN_NOTICE "pmc551: Invalid aperture size " | |
681 | "[%d]\n", asize); | |
1da177e4 LT |
682 | return -EINVAL; |
683 | } | |
684 | } | |
685 | ||
cdf0a7d1 JS |
686 | printk(KERN_INFO PMC551_VERSION); |
687 | ||
688 | /* | |
689 | * PCU-bus chipset probe. | |
690 | */ | |
24c15496 | 691 | for (;;) { |
cdf0a7d1 JS |
692 | |
693 | if ((PCI_Device = pci_get_device(PCI_VENDOR_ID_V3_SEMI, | |
694 | PCI_DEVICE_ID_V3_SEMI_V370PDC, | |
695 | PCI_Device)) == NULL) { | |
696 | break; | |
697 | } | |
698 | ||
699 | printk(KERN_NOTICE "pmc551: Found PCI V370PDC at 0x%llx\n", | |
98aacdfd | 700 | (unsigned long long)pci_resource_start(PCI_Device, 0)); |
cdf0a7d1 JS |
701 | |
702 | /* | |
703 | * The PMC551 device acts VERY weird if you don't init it | |
704 | * first. i.e. it will not correctly report devsel. If for | |
705 | * some reason the sdram is in a wrote-protected state the | |
706 | * device will DEVSEL when it is written to causing problems | |
707 | * with the oldproc.c driver in | |
708 | * some kernels (2.2.*) | |
709 | */ | |
710 | if ((length = fixup_pmc551(PCI_Device)) <= 0) { | |
711 | printk(KERN_NOTICE "pmc551: Cannot init SDRAM\n"); | |
712 | break; | |
713 | } | |
1da177e4 LT |
714 | |
715 | /* | |
716 | * This is needed until the driver is capable of reading the | |
717 | * onboard I2C SROM to discover the "real" memory size. | |
718 | */ | |
cdf0a7d1 | 719 | if (msize) { |
1da177e4 | 720 | length = msize; |
cdf0a7d1 JS |
721 | printk(KERN_NOTICE "pmc551: Using specified memory " |
722 | "size 0x%x\n", length); | |
1da177e4 LT |
723 | } else { |
724 | msize = length; | |
725 | } | |
726 | ||
7fefb924 | 727 | mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL); |
c00cb1b7 | 728 | if (!mtd) |
cdf0a7d1 | 729 | break; |
cdf0a7d1 | 730 | |
7fefb924 | 731 | priv = kzalloc(sizeof(struct mypriv), GFP_KERNEL); |
cdf0a7d1 | 732 | if (!priv) { |
cdf0a7d1 JS |
733 | kfree(mtd); |
734 | break; | |
735 | } | |
cdf0a7d1 JS |
736 | mtd->priv = priv; |
737 | priv->dev = PCI_Device; | |
738 | ||
739 | if (asize > length) { | |
740 | printk(KERN_NOTICE "pmc551: reducing aperture size to " | |
741 | "fit %dM\n", length >> 20); | |
1da177e4 LT |
742 | priv->asize = asize = length; |
743 | } else if (asize == 0 || asize == length) { | |
cdf0a7d1 JS |
744 | printk(KERN_NOTICE "pmc551: Using existing aperture " |
745 | "size %dM\n", length >> 20); | |
1da177e4 LT |
746 | priv->asize = asize = length; |
747 | } else { | |
cdf0a7d1 JS |
748 | printk(KERN_NOTICE "pmc551: Using specified aperture " |
749 | "size %dM\n", asize >> 20); | |
1da177e4 LT |
750 | priv->asize = asize; |
751 | } | |
98aacdfd | 752 | priv->start = pci_iomap(PCI_Device, 0, priv->asize); |
e5580fbe | 753 | |
1da177e4 LT |
754 | if (!priv->start) { |
755 | printk(KERN_NOTICE "pmc551: Unable to map IO space\n"); | |
cdf0a7d1 JS |
756 | kfree(mtd->priv); |
757 | kfree(mtd); | |
1da177e4 LT |
758 | break; |
759 | } | |
1da177e4 | 760 | #ifdef CONFIG_MTD_PMC551_DEBUG |
cdf0a7d1 JS |
761 | printk(KERN_DEBUG "pmc551: setting aperture to %d\n", |
762 | ffs(priv->asize >> 20) - 1); | |
1da177e4 LT |
763 | #endif |
764 | ||
cdf0a7d1 JS |
765 | priv->base_map0 = (PMC551_PCI_MEM_MAP_REG_EN |
766 | | PMC551_PCI_MEM_MAP_ENABLE | |
767 | | (ffs(priv->asize >> 20) - 1) << 4); | |
768 | priv->curr_map0 = priv->base_map0; | |
769 | pci_write_config_dword(priv->dev, PMC551_PCI_MEM_MAP0, | |
770 | priv->curr_map0); | |
1da177e4 LT |
771 | |
772 | #ifdef CONFIG_MTD_PMC551_DEBUG | |
cdf0a7d1 JS |
773 | printk(KERN_DEBUG "pmc551: aperture set to %d\n", |
774 | (priv->base_map0 & 0xF0) >> 4); | |
1da177e4 LT |
775 | #endif |
776 | ||
cdf0a7d1 JS |
777 | mtd->size = msize; |
778 | mtd->flags = MTD_CAP_RAM; | |
3c3c10bb AB |
779 | mtd->_erase = pmc551_erase; |
780 | mtd->_read = pmc551_read; | |
781 | mtd->_write = pmc551_write; | |
782 | mtd->_point = pmc551_point; | |
783 | mtd->_unpoint = pmc551_unpoint; | |
cdf0a7d1 JS |
784 | mtd->type = MTD_RAM; |
785 | mtd->name = "PMC551 RAM board"; | |
786 | mtd->erasesize = 0x10000; | |
787 | mtd->writesize = 1; | |
788 | mtd->owner = THIS_MODULE; | |
789 | ||
ee0e87b1 | 790 | if (mtd_device_register(mtd, NULL, 0)) { |
8e0aedc5 | 791 | printk(KERN_NOTICE "pmc551: Failed to register new device\n"); |
98aacdfd | 792 | pci_iounmap(PCI_Device, priv->start); |
cdf0a7d1 JS |
793 | kfree(mtd->priv); |
794 | kfree(mtd); | |
795 | break; | |
796 | } | |
797 | ||
ee0e87b1 | 798 | /* Keep a reference as the mtd_device_register worked */ |
cdf0a7d1 JS |
799 | pci_dev_get(PCI_Device); |
800 | ||
801 | printk(KERN_NOTICE "Registered pmc551 memory device.\n"); | |
8e0aedc5 | 802 | printk(KERN_NOTICE "Mapped %dMiB of memory from 0x%p to 0x%p\n", |
cdf0a7d1 JS |
803 | priv->asize >> 20, |
804 | priv->start, priv->start + priv->asize); | |
8e0aedc5 | 805 | printk(KERN_NOTICE "Total memory is %d%sB\n", |
cdf0a7d1 JS |
806 | (length < 1024) ? length : |
807 | (length < 1048576) ? length >> 10 : length >> 20, | |
8e0aedc5 | 808 | (length < 1024) ? "" : (length < 1048576) ? "Ki" : "Mi"); |
1da177e4 LT |
809 | priv->nextpmc551 = pmc551list; |
810 | pmc551list = mtd; | |
811 | found++; | |
cdf0a7d1 | 812 | } |
1da177e4 | 813 | |
cdf0a7d1 JS |
814 | /* Exited early, reference left over */ |
815 | if (PCI_Device) | |
816 | pci_dev_put(PCI_Device); | |
dd8e9ed6 | 817 | |
cdf0a7d1 JS |
818 | if (!pmc551list) { |
819 | printk(KERN_NOTICE "pmc551: not detected\n"); | |
820 | return -ENODEV; | |
821 | } else { | |
1da177e4 | 822 | printk(KERN_NOTICE "pmc551: %d pmc551 devices loaded\n", found); |
cdf0a7d1 | 823 | return 0; |
1da177e4 LT |
824 | } |
825 | } | |
826 | ||
827 | /* | |
828 | * PMC551 Card Cleanup | |
829 | */ | |
830 | static void __exit cleanup_pmc551(void) | |
831 | { | |
cdf0a7d1 JS |
832 | int found = 0; |
833 | struct mtd_info *mtd; | |
1da177e4 LT |
834 | struct mypriv *priv; |
835 | ||
cdf0a7d1 | 836 | while ((mtd = pmc551list)) { |
1da177e4 LT |
837 | priv = mtd->priv; |
838 | pmc551list = priv->nextpmc551; | |
e5580fbe | 839 | |
cdf0a7d1 | 840 | if (priv->start) { |
8e0aedc5 | 841 | printk(KERN_DEBUG "pmc551: unmapping %dMiB starting at " |
cdf0a7d1 | 842 | "0x%p\n", priv->asize >> 20, priv->start); |
98aacdfd | 843 | pci_iounmap(priv->dev, priv->start); |
1da177e4 | 844 | } |
dd8e9ed6 | 845 | pci_dev_put(priv->dev); |
e5580fbe | 846 | |
cdf0a7d1 | 847 | kfree(mtd->priv); |
ee0e87b1 | 848 | mtd_device_unregister(mtd); |
cdf0a7d1 | 849 | kfree(mtd); |
1da177e4 LT |
850 | found++; |
851 | } | |
852 | ||
853 | printk(KERN_NOTICE "pmc551: %d pmc551 devices unloaded\n", found); | |
854 | } | |
855 | ||
856 | module_init(init_pmc551); | |
857 | module_exit(cleanup_pmc551); |