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Commit | Line | Data |
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90afffc8 DO |
1 | /* |
2 | * ck804xrom.c | |
3 | * | |
4 | * Normal mappings of chips in physical memory | |
5 | * | |
6 | * Dave Olsen <dolsen@lnxi.com> | |
7 | * Ryan Jackson <rjackson@lnxi.com> | |
8 | */ | |
9 | ||
10 | #include <linux/module.h> | |
11 | #include <linux/types.h> | |
90afffc8 DO |
12 | #include <linux/kernel.h> |
13 | #include <linux/init.h> | |
14 | #include <asm/io.h> | |
15 | #include <linux/mtd/mtd.h> | |
16 | #include <linux/mtd/map.h> | |
17 | #include <linux/mtd/cfi.h> | |
18 | #include <linux/mtd/flashchip.h> | |
19 | #include <linux/pci.h> | |
20 | #include <linux/pci_ids.h> | |
21 | #include <linux/list.h> | |
22 | ||
23 | ||
24 | #define MOD_NAME KBUILD_BASENAME | |
25 | ||
26 | #define ADDRESS_NAME_LEN 18 | |
27 | ||
c9ac5977 | 28 | #define ROM_PROBE_STEP_SIZE (64*1024) |
90afffc8 | 29 | |
c3f08b35 CDH |
30 | #define DEV_CK804 1 |
31 | #define DEV_MCP55 2 | |
32 | ||
90afffc8 DO |
33 | struct ck804xrom_window { |
34 | void __iomem *virt; | |
35 | unsigned long phys; | |
36 | unsigned long size; | |
37 | struct list_head maps; | |
38 | struct resource rsrc; | |
39 | struct pci_dev *pdev; | |
40 | }; | |
41 | ||
42 | struct ck804xrom_map_info { | |
43 | struct list_head list; | |
44 | struct map_info map; | |
45 | struct mtd_info *mtd; | |
46 | struct resource rsrc; | |
47 | char map_name[sizeof(MOD_NAME) + 2 + ADDRESS_NAME_LEN]; | |
48 | }; | |
49 | ||
c3f08b35 CDH |
50 | /* |
51 | * The following applies to ck804 only: | |
52 | * The 2 bits controlling the window size are often set to allow reading | |
90afffc8 DO |
53 | * the BIOS, but too small to allow writing, since the lock registers are |
54 | * 4MiB lower in the address space than the data. | |
55 | * | |
56 | * This is intended to prevent flashing the bios, perhaps accidentally. | |
57 | * | |
58 | * This parameter allows the normal driver to override the BIOS settings. | |
59 | * | |
60 | * The bits are 6 and 7. If both bits are set, it is a 5MiB window. | |
61 | * If only the 7 Bit is set, it is a 4MiB window. Otherwise, a | |
62 | * 64KiB window. | |
63 | * | |
c3f08b35 CDH |
64 | * The following applies to mcp55 only: |
65 | * The 15 bits controlling the window size are distributed as follows: | |
66 | * byte @0x88: bit 0..7 | |
67 | * byte @0x8c: bit 8..15 | |
68 | * word @0x90: bit 16..30 | |
69 | * If all bits are enabled, we have a 16? MiB window | |
70 | * Please set win_size_bits to 0x7fffffff if you actually want to do something | |
90afffc8 DO |
71 | */ |
72 | static uint win_size_bits = 0; | |
73 | module_param(win_size_bits, uint, 0); | |
c3f08b35 | 74 | MODULE_PARM_DESC(win_size_bits, "ROM window size bits override, normally set by BIOS."); |
90afffc8 DO |
75 | |
76 | static struct ck804xrom_window ck804xrom_window = { | |
77 | .maps = LIST_HEAD_INIT(ck804xrom_window.maps), | |
78 | }; | |
79 | ||
80 | static void ck804xrom_cleanup(struct ck804xrom_window *window) | |
81 | { | |
82 | struct ck804xrom_map_info *map, *scratch; | |
83 | u8 byte; | |
84 | ||
85 | if (window->pdev) { | |
86 | /* Disable writes through the rom window */ | |
87 | pci_read_config_byte(window->pdev, 0x6d, &byte); | |
88 | pci_write_config_byte(window->pdev, 0x6d, byte & ~1); | |
89 | } | |
90 | ||
91 | /* Free all of the mtd devices */ | |
92 | list_for_each_entry_safe(map, scratch, &window->maps, list) { | |
93 | if (map->rsrc.parent) | |
94 | release_resource(&map->rsrc); | |
95 | ||
96 | del_mtd_device(map->mtd); | |
97 | map_destroy(map->mtd); | |
98 | list_del(&map->list); | |
99 | kfree(map); | |
100 | } | |
101 | if (window->rsrc.parent) | |
102 | release_resource(&window->rsrc); | |
103 | ||
104 | if (window->virt) { | |
105 | iounmap(window->virt); | |
106 | window->virt = NULL; | |
107 | window->phys = 0; | |
108 | window->size = 0; | |
109 | } | |
110 | pci_dev_put(window->pdev); | |
111 | } | |
112 | ||
113 | ||
114 | static int __devinit ck804xrom_init_one (struct pci_dev *pdev, | |
c3f08b35 | 115 | const struct pci_device_id *ent) |
90afffc8 DO |
116 | { |
117 | static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL }; | |
118 | u8 byte; | |
c3f08b35 | 119 | u16 word; |
90afffc8 DO |
120 | struct ck804xrom_window *window = &ck804xrom_window; |
121 | struct ck804xrom_map_info *map = NULL; | |
122 | unsigned long map_top; | |
123 | ||
124 | /* Remember the pci dev I find the window in */ | |
125 | window->pdev = pci_dev_get(pdev); | |
126 | ||
c3f08b35 CDH |
127 | switch (ent->driver_data) { |
128 | case DEV_CK804: | |
129 | /* Enable the selected rom window. This is often incorrectly | |
130 | * set up by the BIOS, and the 4MiB offset for the lock registers | |
131 | * requires the full 5MiB of window space. | |
132 | * | |
133 | * This 'write, then read' approach leaves the bits for | |
134 | * other uses of the hardware info. | |
135 | */ | |
136 | pci_read_config_byte(pdev, 0x88, &byte); | |
137 | pci_write_config_byte(pdev, 0x88, byte | win_size_bits ); | |
138 | ||
139 | /* Assume the rom window is properly setup, and find it's size */ | |
140 | pci_read_config_byte(pdev, 0x88, &byte); | |
141 | ||
142 | if ((byte & ((1<<7)|(1<<6))) == ((1<<7)|(1<<6))) | |
143 | window->phys = 0xffb00000; /* 5MiB */ | |
144 | else if ((byte & (1<<7)) == (1<<7)) | |
145 | window->phys = 0xffc00000; /* 4MiB */ | |
146 | else | |
147 | window->phys = 0xffff0000; /* 64KiB */ | |
148 | break; | |
149 | ||
150 | case DEV_MCP55: | |
151 | pci_read_config_byte(pdev, 0x88, &byte); | |
152 | pci_write_config_byte(pdev, 0x88, byte | (win_size_bits & 0xff)); | |
153 | ||
154 | pci_read_config_byte(pdev, 0x8c, &byte); | |
155 | pci_write_config_byte(pdev, 0x8c, byte | ((win_size_bits & 0xff00) >> 8)); | |
156 | ||
157 | pci_read_config_word(pdev, 0x90, &word); | |
158 | pci_write_config_word(pdev, 0x90, word | ((win_size_bits & 0x7fff0000) >> 16)); | |
159 | ||
160 | window->phys = 0xff000000; /* 16MiB, hardcoded for now */ | |
161 | break; | |
162 | } | |
90afffc8 DO |
163 | |
164 | window->size = 0xffffffffUL - window->phys + 1UL; | |
165 | ||
166 | /* | |
167 | * Try to reserve the window mem region. If this fails then | |
168 | * it is likely due to a fragment of the window being | |
169 | * "reserved" by the BIOS. In the case that the | |
170 | * request_mem_region() fails then once the rom size is | |
171 | * discovered we will try to reserve the unreserved fragment. | |
172 | */ | |
173 | window->rsrc.name = MOD_NAME; | |
174 | window->rsrc.start = window->phys; | |
175 | window->rsrc.end = window->phys + window->size - 1; | |
176 | window->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
177 | if (request_resource(&iomem_resource, &window->rsrc)) { | |
178 | window->rsrc.parent = NULL; | |
179 | printk(KERN_ERR MOD_NAME | |
180 | " %s(): Unable to register resource" | |
181 | " 0x%.016llx-0x%.016llx - kernel bug?\n", | |
182 | __func__, | |
183 | (unsigned long long)window->rsrc.start, | |
184 | (unsigned long long)window->rsrc.end); | |
185 | } | |
186 | ||
187 | ||
188 | /* Enable writes through the rom window */ | |
189 | pci_read_config_byte(pdev, 0x6d, &byte); | |
190 | pci_write_config_byte(pdev, 0x6d, byte | 1); | |
191 | ||
192 | /* FIXME handle registers 0x80 - 0x8C the bios region locks */ | |
193 | ||
194 | /* For write accesses caches are useless */ | |
195 | window->virt = ioremap_nocache(window->phys, window->size); | |
196 | if (!window->virt) { | |
197 | printk(KERN_ERR MOD_NAME ": ioremap(%08lx, %08lx) failed\n", | |
198 | window->phys, window->size); | |
199 | goto out; | |
200 | } | |
201 | ||
202 | /* Get the first address to look for a rom chip at */ | |
203 | map_top = window->phys; | |
204 | #if 1 | |
205 | /* The probe sequence run over the firmware hub lock | |
206 | * registers sets them to 0x7 (no access). | |
207 | * Probe at most the last 4MiB of the address space. | |
208 | */ | |
209 | if (map_top < 0xffc00000) | |
210 | map_top = 0xffc00000; | |
211 | #endif | |
212 | /* Loop through and look for rom chips. Since we don't know the | |
213 | * starting address for each chip, probe every ROM_PROBE_STEP_SIZE | |
214 | * bytes from the starting address of the window. | |
215 | */ | |
216 | while((map_top - 1) < 0xffffffffUL) { | |
217 | struct cfi_private *cfi; | |
218 | unsigned long offset; | |
219 | int i; | |
220 | ||
221 | if (!map) | |
222 | map = kmalloc(sizeof(*map), GFP_KERNEL); | |
223 | ||
224 | if (!map) { | |
225 | printk(KERN_ERR MOD_NAME ": kmalloc failed"); | |
226 | goto out; | |
227 | } | |
228 | memset(map, 0, sizeof(*map)); | |
229 | INIT_LIST_HEAD(&map->list); | |
230 | map->map.name = map->map_name; | |
231 | map->map.phys = map_top; | |
232 | offset = map_top - window->phys; | |
233 | map->map.virt = (void __iomem *) | |
234 | (((unsigned long)(window->virt)) + offset); | |
235 | map->map.size = 0xffffffffUL - map_top + 1UL; | |
236 | /* Set the name of the map to the address I am trying */ | |
65af0714 AM |
237 | sprintf(map->map_name, "%s @%08Lx", |
238 | MOD_NAME, (unsigned long long)map->map.phys); | |
90afffc8 DO |
239 | |
240 | /* There is no generic VPP support */ | |
241 | for(map->map.bankwidth = 32; map->map.bankwidth; | |
242 | map->map.bankwidth >>= 1) | |
243 | { | |
244 | char **probe_type; | |
245 | /* Skip bankwidths that are not supported */ | |
246 | if (!map_bankwidth_supported(map->map.bankwidth)) | |
247 | continue; | |
248 | ||
249 | /* Setup the map methods */ | |
250 | simple_map_init(&map->map); | |
251 | ||
252 | /* Try all of the probe methods */ | |
253 | probe_type = rom_probe_types; | |
254 | for(; *probe_type; probe_type++) { | |
255 | map->mtd = do_map_probe(*probe_type, &map->map); | |
256 | if (map->mtd) | |
257 | goto found; | |
258 | } | |
259 | } | |
260 | map_top += ROM_PROBE_STEP_SIZE; | |
261 | continue; | |
262 | found: | |
263 | /* Trim the size if we are larger than the map */ | |
264 | if (map->mtd->size > map->map.size) { | |
265 | printk(KERN_WARNING MOD_NAME | |
69423d99 AH |
266 | " rom(%llu) larger than window(%lu). fixing...\n", |
267 | (unsigned long long)map->mtd->size, map->map.size); | |
90afffc8 DO |
268 | map->mtd->size = map->map.size; |
269 | } | |
270 | if (window->rsrc.parent) { | |
271 | /* | |
272 | * Registering the MTD device in iomem may not be possible | |
273 | * if there is a BIOS "reserved" and BUSY range. If this | |
274 | * fails then continue anyway. | |
275 | */ | |
276 | map->rsrc.name = map->map_name; | |
277 | map->rsrc.start = map->map.phys; | |
278 | map->rsrc.end = map->map.phys + map->mtd->size - 1; | |
279 | map->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
280 | if (request_resource(&window->rsrc, &map->rsrc)) { | |
281 | printk(KERN_ERR MOD_NAME | |
282 | ": cannot reserve MTD resource\n"); | |
283 | map->rsrc.parent = NULL; | |
284 | } | |
285 | } | |
286 | ||
287 | /* Make the whole region visible in the map */ | |
288 | map->map.virt = window->virt; | |
289 | map->map.phys = window->phys; | |
290 | cfi = map->map.fldrv_priv; | |
291 | for(i = 0; i < cfi->numchips; i++) | |
292 | cfi->chips[i].start += offset; | |
293 | ||
294 | /* Now that the mtd devices is complete claim and export it */ | |
295 | map->mtd->owner = THIS_MODULE; | |
296 | if (add_mtd_device(map->mtd)) { | |
297 | map_destroy(map->mtd); | |
298 | map->mtd = NULL; | |
299 | goto out; | |
300 | } | |
301 | ||
302 | ||
303 | /* Calculate the new value of map_top */ | |
304 | map_top += map->mtd->size; | |
305 | ||
306 | /* File away the map structure */ | |
307 | list_add(&map->list, &window->maps); | |
308 | map = NULL; | |
309 | } | |
310 | ||
311 | out: | |
312 | /* Free any left over map structures */ | |
313 | if (map) | |
314 | kfree(map); | |
315 | ||
316 | /* See if I have any map structures */ | |
317 | if (list_empty(&window->maps)) { | |
318 | ck804xrom_cleanup(window); | |
319 | return -ENODEV; | |
320 | } | |
321 | return 0; | |
322 | } | |
323 | ||
324 | ||
325 | static void __devexit ck804xrom_remove_one (struct pci_dev *pdev) | |
326 | { | |
327 | struct ck804xrom_window *window = &ck804xrom_window; | |
328 | ||
329 | ck804xrom_cleanup(window); | |
330 | } | |
331 | ||
332 | static struct pci_device_id ck804xrom_pci_tbl[] = { | |
edb2301f DW |
333 | { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0051), .driver_data = DEV_CK804 }, |
334 | { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0360), .driver_data = DEV_MCP55 }, | |
335 | { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0361), .driver_data = DEV_MCP55 }, | |
336 | { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0362), .driver_data = DEV_MCP55 }, | |
337 | { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0363), .driver_data = DEV_MCP55 }, | |
338 | { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0364), .driver_data = DEV_MCP55 }, | |
339 | { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0365), .driver_data = DEV_MCP55 }, | |
340 | { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0366), .driver_data = DEV_MCP55 }, | |
341 | { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0367), .driver_data = DEV_MCP55 }, | |
90afffc8 DO |
342 | { 0, } |
343 | }; | |
344 | ||
b50be33e | 345 | #if 0 |
90afffc8 DO |
346 | MODULE_DEVICE_TABLE(pci, ck804xrom_pci_tbl); |
347 | ||
90afffc8 DO |
348 | static struct pci_driver ck804xrom_driver = { |
349 | .name = MOD_NAME, | |
350 | .id_table = ck804xrom_pci_tbl, | |
351 | .probe = ck804xrom_init_one, | |
352 | .remove = ck804xrom_remove_one, | |
353 | }; | |
354 | #endif | |
355 | ||
356 | static int __init init_ck804xrom(void) | |
357 | { | |
358 | struct pci_dev *pdev; | |
359 | struct pci_device_id *id; | |
360 | int retVal; | |
361 | pdev = NULL; | |
362 | ||
363 | for(id = ck804xrom_pci_tbl; id->vendor; id++) { | |
c033a7e3 | 364 | pdev = pci_get_device(id->vendor, id->device, NULL); |
90afffc8 DO |
365 | if (pdev) |
366 | break; | |
367 | } | |
368 | if (pdev) { | |
c3f08b35 | 369 | retVal = ck804xrom_init_one(pdev, id); |
90afffc8 DO |
370 | pci_dev_put(pdev); |
371 | return retVal; | |
372 | } | |
373 | return -ENXIO; | |
374 | #if 0 | |
28b57cdd | 375 | return pci_register_driver(&ck804xrom_driver); |
90afffc8 DO |
376 | #endif |
377 | } | |
378 | ||
379 | static void __exit cleanup_ck804xrom(void) | |
380 | { | |
381 | ck804xrom_remove_one(ck804xrom_window.pdev); | |
382 | } | |
383 | ||
384 | module_init(init_ck804xrom); | |
385 | module_exit(cleanup_ck804xrom); | |
386 | ||
387 | MODULE_LICENSE("GPL"); | |
388 | MODULE_AUTHOR("Eric Biederman <ebiederman@lnxi.com>, Dave Olsen <dolsen@lnxi.com>"); | |
389 | MODULE_DESCRIPTION("MTD map driver for BIOS chips on the Nvidia ck804 southbridge"); | |
390 |