[mirror_ubuntu-artful-kernel.git] / drivers / mtd / nand / ams-delta.c

/*
 *  drivers/mtd/nand/ams-delta.c
 *
 *  Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
 *
 *  Derived from drivers/mtd/toto.c
 *  Converted to platform driver by Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
 *  Partially stolen from drivers/mtd/nand/plat_nand.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  Overview:
 *   This is a device driver for the NAND flash device found on the
 *   Amstrad E3 (Delta).
 */

#include <linux/slab.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/gpio.h>
#include <linux/platform_data/gpio-omap.h>

#include <asm/io.h>
#include <asm/sizes.h>

#include <plat/board-ams-delta.h>

#include <mach/hardware.h>

/*
 * MTD structure for E3 (Delta)
 */
static struct mtd_info *ams_delta_mtd = NULL;

/*
 * Define partitions for flash devices
 */

static struct mtd_partition partition_info[] = {
	{ .name		= "Kernel",
	  .offset	= 0,
	  .size		= 3 * SZ_1M + SZ_512K },
	{ .name		= "u-boot",
	  .offset	= 3 * SZ_1M + SZ_512K,
	  .size		= SZ_256K },
	{ .name		= "u-boot params",
	  .offset	= 3 * SZ_1M + SZ_512K + SZ_256K,
	  .size		= SZ_256K },
	{ .name		= "Amstrad LDR",
	  .offset	= 4 * SZ_1M,
	  .size		= SZ_256K },
	{ .name		= "File system",
	  .offset	= 4 * SZ_1M + 1 * SZ_256K,
	  .size		= 27 * SZ_1M },
	{ .name		= "PBL reserved",
	  .offset	= 32 * SZ_1M - 3 * SZ_256K,
	  .size		=  3 * SZ_256K },
};

static void ams_delta_write_byte(struct mtd_info *mtd, u_char byte)
{
	struct nand_chip *this = mtd->priv;
	void __iomem *io_base = this->priv;

	writew(0, io_base + OMAP_MPUIO_IO_CNTL);
	writew(byte, this->IO_ADDR_W);
	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 0);
	ndelay(40);
	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 1);
}

static u_char ams_delta_read_byte(struct mtd_info *mtd)
{
	u_char res;
	struct nand_chip *this = mtd->priv;
	void __iomem *io_base = this->priv;

	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 0);
	ndelay(40);
	writew(~0, io_base + OMAP_MPUIO_IO_CNTL);
	res = readw(this->IO_ADDR_R);
	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 1);

	return res;
}

static void ams_delta_write_buf(struct mtd_info *mtd, const u_char *buf,
				int len)
{
	int i;

	for (i=0; i<len; i++)
		ams_delta_write_byte(mtd, buf[i]);
}

static void ams_delta_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
	int i;

	for (i=0; i<len; i++)
		buf[i] = ams_delta_read_byte(mtd);
}

static int ams_delta_verify_buf(struct mtd_info *mtd, const u_char *buf,
				int len)
{
	int i;

	for (i=0; i<len; i++)
		if (buf[i] != ams_delta_read_byte(mtd))
			return -EFAULT;

	return 0;
}

/*
 * Command control function
 *
 * ctrl:
 * NAND_NCE: bit 0 -> bit 2
 * NAND_CLE: bit 1 -> bit 7
 * NAND_ALE: bit 2 -> bit 6
 */
static void ams_delta_hwcontrol(struct mtd_info *mtd, int cmd,
				unsigned int ctrl)
{

	if (ctrl & NAND_CTRL_CHANGE) {
		gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NCE,
				(ctrl & NAND_NCE) == 0);
		gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_CLE,
				(ctrl & NAND_CLE) != 0);
		gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_ALE,
				(ctrl & NAND_ALE) != 0);
	}

	if (cmd != NAND_CMD_NONE)
		ams_delta_write_byte(mtd, cmd);
}

static int ams_delta_nand_ready(struct mtd_info *mtd)
{
	return gpio_get_value(AMS_DELTA_GPIO_PIN_NAND_RB);
}

static const struct gpio _mandatory_gpio[] = {
	{
		.gpio	= AMS_DELTA_GPIO_PIN_NAND_NCE,
		.flags	= GPIOF_OUT_INIT_HIGH,
		.label	= "nand_nce",
	},
	{
		.gpio	= AMS_DELTA_GPIO_PIN_NAND_NRE,
		.flags	= GPIOF_OUT_INIT_HIGH,
		.label	= "nand_nre",
	},
	{
		.gpio	= AMS_DELTA_GPIO_PIN_NAND_NWP,
		.flags	= GPIOF_OUT_INIT_HIGH,
		.label	= "nand_nwp",
	},
	{
		.gpio	= AMS_DELTA_GPIO_PIN_NAND_NWE,
		.flags	= GPIOF_OUT_INIT_HIGH,
		.label	= "nand_nwe",
	},
	{
		.gpio	= AMS_DELTA_GPIO_PIN_NAND_ALE,
		.flags	= GPIOF_OUT_INIT_LOW,
		.label	= "nand_ale",
	},
	{
		.gpio	= AMS_DELTA_GPIO_PIN_NAND_CLE,
		.flags	= GPIOF_OUT_INIT_LOW,
		.label	= "nand_cle",
	},
};

/*
 * Main initialization routine
 */
static int __devinit ams_delta_init(struct platform_device *pdev)
{
	struct nand_chip *this;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	void __iomem *io_base;
	int err = 0;

	if (!res)
		return -ENXIO;

	/* Allocate memory for MTD device structure and private data */
	ams_delta_mtd = kmalloc(sizeof(struct mtd_info) +
				sizeof(struct nand_chip), GFP_KERNEL);
	if (!ams_delta_mtd) {
		printk (KERN_WARNING "Unable to allocate E3 NAND MTD device structure.\n");
		err = -ENOMEM;
		goto out;
	}

	ams_delta_mtd->owner = THIS_MODULE;

	/* Get pointer to private data */
	this = (struct nand_chip *) (&ams_delta_mtd[1]);

	/* Initialize structures */
	memset(ams_delta_mtd, 0, sizeof(struct mtd_info));
	memset(this, 0, sizeof(struct nand_chip));

	/* Link the private data with the MTD structure */
	ams_delta_mtd->priv = this;

	/*
	 * Don't try to request the memory region from here,
	 * it should have been already requested from the
	 * gpio-omap driver and requesting it again would fail.
	 */

	io_base = ioremap(res->start, resource_size(res));
	if (io_base == NULL) {
		dev_err(&pdev->dev, "ioremap failed\n");
		err = -EIO;
		goto out_free;
	}

	this->priv = io_base;

	/* Set address of NAND IO lines */
	this->IO_ADDR_R = io_base + OMAP_MPUIO_INPUT_LATCH;
	this->IO_ADDR_W = io_base + OMAP_MPUIO_OUTPUT;
	this->read_byte = ams_delta_read_byte;
	this->write_buf = ams_delta_write_buf;
	this->read_buf = ams_delta_read_buf;
	this->verify_buf = ams_delta_verify_buf;
	this->cmd_ctrl = ams_delta_hwcontrol;
	if (gpio_request(AMS_DELTA_GPIO_PIN_NAND_RB, "nand_rdy") == 0) {
		this->dev_ready = ams_delta_nand_ready;
	} else {
		this->dev_ready = NULL;
		printk(KERN_NOTICE "Couldn't request gpio for Delta NAND ready.\n");
	}
	/* 25 us command delay time */
	this->chip_delay = 30;
	this->ecc.mode = NAND_ECC_SOFT;

	platform_set_drvdata(pdev, io_base);

	/* Set chip enabled, but  */
	err = gpio_request_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
	if (err)
		goto out_gpio;

	/* Scan to find existence of the device */
	if (nand_scan(ams_delta_mtd, 1)) {
		err = -ENXIO;
		goto out_mtd;
	}

	/* Register the partitions */
	mtd_device_register(ams_delta_mtd, partition_info,
			    ARRAY_SIZE(partition_info));

	goto out;

 out_mtd:
	gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
out_gpio:
	platform_set_drvdata(pdev, NULL);
	gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB);
	iounmap(io_base);
out_free:
	kfree(ams_delta_mtd);
 out:
	return err;
}

/*
 * Clean up routine
 */
static int __devexit ams_delta_cleanup(struct platform_device *pdev)
{
	void __iomem *io_base = platform_get_drvdata(pdev);

	/* Release resources, unregister device */
	nand_release(ams_delta_mtd);

	gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
	gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB);
	iounmap(io_base);

	/* Free the MTD device structure */
	kfree(ams_delta_mtd);

	return 0;
}

static struct platform_driver ams_delta_nand_driver = {
	.probe		= ams_delta_init,
	.remove		= __devexit_p(ams_delta_cleanup),
	.driver		= {
		.name	= "ams-delta-nand",
		.owner	= THIS_MODULE,
	},
};

module_platform_driver(ams_delta_nand_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Jonathan McDowell <noodles@earth.li>");
MODULE_DESCRIPTION("Glue layer for NAND flash on Amstrad E3 (Delta)");
Commit	Line	Data
3d12c0c7 JM	1	/*
	2	* drivers/mtd/nand/ams-delta.c
	3	*
	4	* Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
	5	*
	6	* Derived from drivers/mtd/toto.c
7e95d1f1	7	* Converted to platform driver by Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
eaca491f	8	* Partially stolen from drivers/mtd/nand/plat_nand.c
3d12c0c7 JM	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* Overview:
	15	* This is a device driver for the NAND flash device found on the
	16	* Amstrad E3 (Delta).
	17	*/
	18
	19	#include <linux/slab.h>
	20	#include <linux/init.h>
	21	#include <linux/module.h>
	22	#include <linux/delay.h>
	23	#include <linux/mtd/mtd.h>
	24	#include <linux/mtd/nand.h>
	25	#include <linux/mtd/partitions.h>
4b25408f TL	26	#include <linux/gpio.h>
	27	#include <linux/platform_data/gpio-omap.h>
	28
3d12c0c7	29	#include <asm/io.h>
3d12c0c7	30	#include <asm/sizes.h>
4b25408f	31
ce491cf8	32	#include <plat/board-ams-delta.h>
3d12c0c7	33
4b25408f TL	34	#include <mach/hardware.h>
4b25408f TL	35
3d12c0c7 JM	36	/*
	37	* MTD structure for E3 (Delta)
	38	*/
	39	static struct mtd_info *ams_delta_mtd = NULL;
	40
3d12c0c7 JM	41	/*
	42	* Define partitions for flash devices
	43	*/
	44
	45	static struct mtd_partition partition_info[] = {
	46	{ .name = "Kernel",
	47	.offset = 0,
	48	.size = 3 * SZ_1M + SZ_512K },
	49	{ .name = "u-boot",
	50	.offset = 3 * SZ_1M + SZ_512K,
	51	.size = SZ_256K },
	52	{ .name = "u-boot params",
	53	.offset = 3 * SZ_1M + SZ_512K + SZ_256K,
	54	.size = SZ_256K },
	55	{ .name = "Amstrad LDR",
	56	.offset = 4 * SZ_1M,
	57	.size = SZ_256K },
	58	{ .name = "File system",
	59	.offset = 4 * SZ_1M + 1 * SZ_256K,
	60	.size = 27 * SZ_1M },
	61	{ .name = "PBL reserved",
	62	.offset = 32 * SZ_1M - 3 * SZ_256K,
	63	.size = 3 * SZ_256K },
	64	};
	65
3d12c0c7 JM	66	static void ams_delta_write_byte(struct mtd_info *mtd, u_char byte)
	67	{
	68	struct nand_chip *this = mtd->priv;
eaca491f	69	void __iomem *io_base = this->priv;
3d12c0c7	70
eaca491f JK	71	writew(0, io_base + OMAP_MPUIO_IO_CNTL);
eaca491f JK	72	writew(byte, this->IO_ADDR_W);
68f06766	73	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 0);
3d12c0c7	74	ndelay(40);
68f06766	75	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 1);
3d12c0c7 JM	76	}
	77
	78	static u_char ams_delta_read_byte(struct mtd_info *mtd)
	79	{
	80	u_char res;
	81	struct nand_chip *this = mtd->priv;
eaca491f	82	void __iomem *io_base = this->priv;
3d12c0c7	83
68f06766	84	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 0);
3d12c0c7	85	ndelay(40);
eaca491f JK	86	writew(~0, io_base + OMAP_MPUIO_IO_CNTL);
eaca491f JK	87	res = readw(this->IO_ADDR_R);
68f06766	88	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 1);
3d12c0c7 JM	89
	90	return res;
	91	}
	92
	93	static void ams_delta_write_buf(struct mtd_info mtd, const u_char buf,
	94	int len)
	95	{
	96	int i;
	97
	98	for (i=0; i<len; i++)
	99	ams_delta_write_byte(mtd, buf[i]);
	100	}
	101
	102	static void ams_delta_read_buf(struct mtd_info mtd, u_char buf, int len)
	103	{
	104	int i;
	105
	106	for (i=0; i<len; i++)
	107	buf[i] = ams_delta_read_byte(mtd);
	108	}
	109
	110	static int ams_delta_verify_buf(struct mtd_info mtd, const u_char buf,
	111	int len)
	112	{
	113	int i;
	114
	115	for (i=0; i<len; i++)
	116	if (buf[i] != ams_delta_read_byte(mtd))
	117	return -EFAULT;
	118
	119	return 0;
	120	}
	121
7abd3ef9 TG	122	/*
	123	* Command control function
	124	*
	125	* ctrl:
	126	* NAND_NCE: bit 0 -> bit 2
	127	* NAND_CLE: bit 1 -> bit 7
	128	* NAND_ALE: bit 2 -> bit 6
	129	*/
	130	static void ams_delta_hwcontrol(struct mtd_info *mtd, int cmd,
	131	unsigned int ctrl)
	132	{
	133
	134	if (ctrl & NAND_CTRL_CHANGE) {
68f06766 JK	135	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NCE,
	136	(ctrl & NAND_NCE) == 0);
	137	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_CLE,
	138	(ctrl & NAND_CLE) != 0);
	139	gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_ALE,
	140	(ctrl & NAND_ALE) != 0);
7abd3ef9 TG	141	}
	142
	143	if (cmd != NAND_CMD_NONE)
	144	ams_delta_write_byte(mtd, cmd);
	145	}
	146
3d12c0c7 JM	147	static int ams_delta_nand_ready(struct mtd_info *mtd)
3d12c0c7 JM	148	{
93a22f8b	149	return gpio_get_value(AMS_DELTA_GPIO_PIN_NAND_RB);
3d12c0c7 JM	150	}
3d12c0c7 JM	151
da564a05	152	static const struct gpio _mandatory_gpio[] = {
68f06766 JK	153	{
	154	.gpio = AMS_DELTA_GPIO_PIN_NAND_NCE,
	155	.flags = GPIOF_OUT_INIT_HIGH,
	156	.label = "nand_nce",
	157	},
	158	{
	159	.gpio = AMS_DELTA_GPIO_PIN_NAND_NRE,
	160	.flags = GPIOF_OUT_INIT_HIGH,
	161	.label = "nand_nre",
	162	},
	163	{
	164	.gpio = AMS_DELTA_GPIO_PIN_NAND_NWP,
	165	.flags = GPIOF_OUT_INIT_HIGH,
	166	.label = "nand_nwp",
	167	},
	168	{
	169	.gpio = AMS_DELTA_GPIO_PIN_NAND_NWE,
	170	.flags = GPIOF_OUT_INIT_HIGH,
	171	.label = "nand_nwe",
	172	},
	173	{
	174	.gpio = AMS_DELTA_GPIO_PIN_NAND_ALE,
	175	.flags = GPIOF_OUT_INIT_LOW,
	176	.label = "nand_ale",
	177	},
	178	{
	179	.gpio = AMS_DELTA_GPIO_PIN_NAND_CLE,
	180	.flags = GPIOF_OUT_INIT_LOW,
	181	.label = "nand_cle",
	182	},
	183	};
	184
3d12c0c7 JM	185	/*
	186	* Main initialization routine
	187	*/
7e95d1f1	188	static int __devinit ams_delta_init(struct platform_device *pdev)
3d12c0c7 JM	189	{
3d12c0c7 JM	190	struct nand_chip *this;
eaca491f JK	191	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
eaca491f JK	192	void __iomem *io_base;
3d12c0c7 JM	193	int err = 0;
3d12c0c7 JM	194
eaca491f JK	195	if (!res)
	196	return -ENXIO;
	197
3d12c0c7 JM	198	/* Allocate memory for MTD device structure and private data */
	199	ams_delta_mtd = kmalloc(sizeof(struct mtd_info) +
	200	sizeof(struct nand_chip), GFP_KERNEL);
	201	if (!ams_delta_mtd) {
	202	printk (KERN_WARNING "Unable to allocate E3 NAND MTD device structure.\n");
	203	err = -ENOMEM;
	204	goto out;
	205	}
	206
	207	ams_delta_mtd->owner = THIS_MODULE;
	208
	209	/* Get pointer to private data */
	210	this = (struct nand_chip *) (&ams_delta_mtd[1]);
	211
	212	/* Initialize structures */
	213	memset(ams_delta_mtd, 0, sizeof(struct mtd_info));
	214	memset(this, 0, sizeof(struct nand_chip));
	215
	216	/* Link the private data with the MTD structure */
	217	ams_delta_mtd->priv = this;
	218
b027274d JK	219	/*
	220	* Don't try to request the memory region from here,
	221	* it should have been already requested from the
	222	* gpio-omap driver and requesting it again would fail.
	223	*/
eaca491f JK	224
	225	io_base = ioremap(res->start, resource_size(res));
	226	if (io_base == NULL) {
	227	dev_err(&pdev->dev, "ioremap failed\n");
	228	err = -EIO;
b027274d	229	goto out_free;
eaca491f JK	230	}
	231
	232	this->priv = io_base;
	233
3d12c0c7	234	/* Set address of NAND IO lines */
eaca491f JK	235	this->IO_ADDR_R = io_base + OMAP_MPUIO_INPUT_LATCH;
eaca491f JK	236	this->IO_ADDR_W = io_base + OMAP_MPUIO_OUTPUT;
3d12c0c7	237	this->read_byte = ams_delta_read_byte;
3d12c0c7 JM	238	this->write_buf = ams_delta_write_buf;
	239	this->read_buf = ams_delta_read_buf;
	240	this->verify_buf = ams_delta_verify_buf;
7abd3ef9	241	this->cmd_ctrl = ams_delta_hwcontrol;
93a22f8b	242	if (gpio_request(AMS_DELTA_GPIO_PIN_NAND_RB, "nand_rdy") == 0) {
3d12c0c7 JM	243	this->dev_ready = ams_delta_nand_ready;
	244	} else {
	245	this->dev_ready = NULL;
	246	printk(KERN_NOTICE "Couldn't request gpio for Delta NAND ready.\n");
	247	}
	248	/* 25 us command delay time */
	249	this->chip_delay = 30;
6dfc6d25	250	this->ecc.mode = NAND_ECC_SOFT;
3d12c0c7	251
eaca491f JK	252	platform_set_drvdata(pdev, io_base);
eaca491f JK	253
3d12c0c7	254	/* Set chip enabled, but */
68f06766 JK	255	err = gpio_request_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
	256	if (err)
	257	goto out_gpio;
3d12c0c7	258
25985edc	259	/* Scan to find existence of the device */
3d12c0c7 JM	260	if (nand_scan(ams_delta_mtd, 1)) {
	261	err = -ENXIO;
	262	goto out_mtd;
	263	}
	264
	265	/* Register the partitions */
ee0e87b1 JI	266	mtd_device_register(ams_delta_mtd, partition_info,
ee0e87b1 JI	267	ARRAY_SIZE(partition_info));
3d12c0c7 JM	268
	269	goto out;
	270
	271	out_mtd:
68f06766 JK	272	gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
68f06766 JK	273	out_gpio:
eaca491f	274	platform_set_drvdata(pdev, NULL);
68f06766	275	gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB);
eaca491f	276	iounmap(io_base);
eaca491f	277	out_free:
3d12c0c7 JM	278	kfree(ams_delta_mtd);
	279	out:
	280	return err;
	281	}
	282
3d12c0c7 JM	283	/*
	284	* Clean up routine
	285	*/
7e95d1f1	286	static int __devexit ams_delta_cleanup(struct platform_device *pdev)
3d12c0c7	287	{
eaca491f	288	void __iomem *io_base = platform_get_drvdata(pdev);
eaca491f	289
3d12c0c7 JM	290	/* Release resources, unregister device */
	291	nand_release(ams_delta_mtd);
	292
68f06766 JK	293	gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
68f06766 JK	294	gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB);
eaca491f	295	iounmap(io_base);
eaca491f	296
3d12c0c7 JM	297	/* Free the MTD device structure */
3d12c0c7 JM	298	kfree(ams_delta_mtd);
7e95d1f1 JK	299
	300	return 0;
	301	}
	302
	303	static struct platform_driver ams_delta_nand_driver = {
	304	.probe = ams_delta_init,
	305	.remove = __devexit_p(ams_delta_cleanup),
	306	.driver = {
	307	.name = "ams-delta-nand",
	308	.owner = THIS_MODULE,
	309	},
	310	};
	311
f99640de	312	module_platform_driver(ams_delta_nand_driver);
3d12c0c7 JM	313
	314	MODULE_LICENSE("GPL");
	315	MODULE_AUTHOR("Jonathan McDowell <noodles@earth.li>");
	316	MODULE_DESCRIPTION("Glue layer for NAND flash on Amstrad E3 (Delta)");