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42cb1403 1/*
1c7b874d 2 * Copyright © 2003 Rick Bronson
42cb1403
AV		 3 *
4 * Derived from drivers/mtd/nand/autcpu12.c
1c7b874d 5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
42cb1403
AV		 6 *
7 * Derived from drivers/mtd/spia.c
1c7b874d 8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
42cb1403 9 *
77f5492c
RG		 10 *
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
1c7b874d 12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
77f5492c
RG		 13 *
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
1c7b874d 16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
77f5492c 17 *
1c7b874d
JW		 18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
77f5492c 20 *
7dc37de7
JW		 21 * Add Nand Flash Controller support for SAMA5 SoC
22 * © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
23 *
42cb1403
AV		 24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
27 *
28 */
29
b7f080cf 30#include <linux/dma-mapping.h>
42cb1403
AV		 31#include <linux/slab.h>
32#include <linux/module.h>
f4fa697c 33#include <linux/moduleparam.h>
42cb1403 34#include <linux/platform_device.h>
d6a01661
JCPV		 35#include <linux/of.h>
36#include <linux/of_device.h>
37#include <linux/of_gpio.h>
38#include <linux/of_mtd.h>
42cb1403
AV		 39#include <linux/mtd/mtd.h>
40#include <linux/mtd/nand.h>
41#include <linux/mtd/partitions.h>
42
7dc37de7 43#include <linux/delay.h>
5c39c4c5 44#include <linux/dmaengine.h>
90574d0a 45#include <linux/gpio.h>
7dc37de7 46#include <linux/interrupt.h>
90574d0a 47#include <linux/io.h>
bf4289cb 48#include <linux/platform_data/atmel.h>
42cb1403 49
cbc6c5e7
HX		 50static int use_dma = 1;
51module_param(use_dma, int, 0);
52
f4fa697c
SP		 53static int on_flash_bbt = 0;
54module_param(on_flash_bbt, int, 0);
55
77f5492c
RG		 56/* Register access macros */
57#define ecc_readl(add, reg) \
3c3796cc 58 __raw_readl(add + ATMEL_ECC_##reg)
77f5492c 59#define ecc_writel(add, reg, value) \
3c3796cc 60 __raw_writel((value), add + ATMEL_ECC_##reg)
77f5492c 61
d4f4c0aa 62#include "atmel_nand_ecc.h" /* Hardware ECC registers */
7dc37de7 63#include "atmel_nand_nfc.h" /* Nand Flash Controller definition */
77f5492c
RG		 64
65/* oob layout for large page size
66 * bad block info is on bytes 0 and 1
67 * the bytes have to be consecutives to avoid
68 * several NAND_CMD_RNDOUT during read
69 */
3c3796cc 70static struct nand_ecclayout atmel_oobinfo_large = {
77f5492c
RG		 71 .eccbytes = 4,
72 .eccpos = {60, 61, 62, 63},
73 .oobfree = {
74 {2, 58}
75 },
76};
77
78/* oob layout for small page size
79 * bad block info is on bytes 4 and 5
80 * the bytes have to be consecutives to avoid
81 * several NAND_CMD_RNDOUT during read
82 */
3c3796cc 83static struct nand_ecclayout atmel_oobinfo_small = {
77f5492c
RG		 84 .eccbytes = 4,
85 .eccpos = {0, 1, 2, 3},
86 .oobfree = {
87 {6, 10}
88 },
89};
90
7dc37de7
JW		 91struct atmel_nfc {
92 void __iomem *base_cmd_regs;
93 void __iomem *hsmc_regs;
94 void __iomem *sram_bank0;
95 dma_addr_t sram_bank0_phys;
1ae9c092 96 bool use_nfc_sram;
6054d4d5 97 bool write_by_sram;
7dc37de7
JW		 98
99 bool is_initialized;
e4e06934
JW		 100 struct completion comp_ready;
101 struct completion comp_cmd_done;
102 struct completion comp_xfer_done;
1ae9c092
JW		 103
104 /* Point to the sram bank which include readed data via NFC */
105 void __iomem *data_in_sram;
6054d4d5 106 bool will_write_sram;
7dc37de7
JW		 107};
108static struct atmel_nfc nand_nfc;
109
3c3796cc 110struct atmel_nand_host {
42cb1403
AV		 111 struct nand_chip nand_chip;
112 struct mtd_info mtd;
113 void __iomem *io_base;
cbc6c5e7 114 dma_addr_t io_phys;
d6a01661 115 struct atmel_nand_data board;
77f5492c
RG		 116 struct device *dev;
117 void __iomem *ecc;
cbc6c5e7
HX		 118
119 struct completion comp;
120 struct dma_chan *dma_chan;
a41b51a1 121
7dc37de7
JW		 122 struct atmel_nfc *nfc;
123
a41b51a1
JW		 124 bool has_pmecc;
125 u8 pmecc_corr_cap;
126 u16 pmecc_sector_size;
127 u32 pmecc_lookup_table_offset;
e66b4318
JW		 128 u32 pmecc_lookup_table_offset_512;
129 u32 pmecc_lookup_table_offset_1024;
1c7b874d
JW		 130
131 int pmecc_bytes_per_sector;
132 int pmecc_sector_number;
133 int pmecc_degree; /* Degree of remainders */
134 int pmecc_cw_len; /* Length of codeword */
135
136 void __iomem *pmerrloc_base;
137 void __iomem *pmecc_rom_base;
138
139 /* lookup table for alpha_to and index_of */
140 void __iomem *pmecc_alpha_to;
141 void __iomem *pmecc_index_of;
142
143 /* data for pmecc computation */
144 int16_t *pmecc_partial_syn;
145 int16_t *pmecc_si;
146 int16_t *pmecc_smu; /* Sigma table */
147 int16_t *pmecc_lmu; /* polynomal order */
148 int *pmecc_mu;
149 int *pmecc_dmu;
150 int *pmecc_delta;
42cb1403
AV		 151};
152
1c7b874d
JW		 153static struct nand_ecclayout atmel_pmecc_oobinfo;
154
8136508c
AN		 155/*
156 * Enable NAND.
157 */
3c3796cc 158static void atmel_nand_enable(struct atmel_nand_host *host)
8136508c 159{
d6a01661
JCPV		 160 if (gpio_is_valid(host->board.enable_pin))
161 gpio_set_value(host->board.enable_pin, 0);
8136508c
AN		 162}
163
164/*
165 * Disable NAND.
166 */
3c3796cc 167static void atmel_nand_disable(struct atmel_nand_host *host)
8136508c 168{
d6a01661
JCPV		 169 if (gpio_is_valid(host->board.enable_pin))
170 gpio_set_value(host->board.enable_pin, 1);
8136508c
AN		 171}
172
42cb1403
AV		 173/*
174 * Hardware specific access to control-lines
175 */
3c3796cc 176static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
42cb1403
AV		 177{
178 struct nand_chip *nand_chip = mtd->priv;
3c3796cc 179 struct atmel_nand_host *host = nand_chip->priv;
42cb1403 180
8136508c 181 if (ctrl & NAND_CTRL_CHANGE) {
2314488e 182 if (ctrl & NAND_NCE)
3c3796cc 183 atmel_nand_enable(host);
2314488e 184 else
3c3796cc 185 atmel_nand_disable(host);
2314488e 186 }
42cb1403
AV		 187 if (cmd == NAND_CMD_NONE)
188 return;
189
190 if (ctrl & NAND_CLE)
d6a01661 191 writeb(cmd, host->io_base + (1 << host->board.cle));
42cb1403 192 else
d6a01661 193 writeb(cmd, host->io_base + (1 << host->board.ale));
42cb1403
AV		 194}
195
196/*
197 * Read the Device Ready pin.
198 */
3c3796cc 199static int atmel_nand_device_ready(struct mtd_info *mtd)
42cb1403
AV		 200{
201 struct nand_chip *nand_chip = mtd->priv;
3c3796cc 202 struct atmel_nand_host *host = nand_chip->priv;
42cb1403 203
d6a01661
JCPV		 204 return gpio_get_value(host->board.rdy_pin) ^
205 !!host->board.rdy_pin_active_low;
42cb1403
AV		 206}
207
7dc37de7
JW		 208/* Set up for hardware ready pin and enable pin. */
209static int atmel_nand_set_enable_ready_pins(struct mtd_info *mtd)
210{
211 struct nand_chip *chip = mtd->priv;
212 struct atmel_nand_host *host = chip->priv;
213 int res = 0;
214
215 if (gpio_is_valid(host->board.rdy_pin)) {
216 res = devm_gpio_request(host->dev,
217 host->board.rdy_pin, "nand_rdy");
218 if (res < 0) {
219 dev_err(host->dev,
220 "can't request rdy gpio %d\n",
221 host->board.rdy_pin);
222 return res;
223 }
224
225 res = gpio_direction_input(host->board.rdy_pin);
226 if (res < 0) {
227 dev_err(host->dev,
228 "can't request input direction rdy gpio %d\n",
229 host->board.rdy_pin);
230 return res;
231 }
232
233 chip->dev_ready = atmel_nand_device_ready;
234 }
235
236 if (gpio_is_valid(host->board.enable_pin)) {
237 res = devm_gpio_request(host->dev,
238 host->board.enable_pin, "nand_enable");
239 if (res < 0) {
240 dev_err(host->dev,
241 "can't request enable gpio %d\n",
242 host->board.enable_pin);
243 return res;
244 }
245
246 res = gpio_direction_output(host->board.enable_pin, 1);
247 if (res < 0) {
248 dev_err(host->dev,
249 "can't request output direction enable gpio %d\n",
250 host->board.enable_pin);
251 return res;
252 }
253 }
254
255 return res;
256}
257
1ae9c092
JW		 258static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
259{
260 int i;
261 u32 *t = trg;
262 const __iomem u32 *s = src;
263
264 for (i = 0; i < (size >> 2); i++)
265 *t++ = readl_relaxed(s++);
266}
267
6054d4d5
JW		 268static void memcpy32_toio(void __iomem *trg, const void *src, int size)
269{
270 int i;
271 u32 __iomem *t = trg;
272 const u32 *s = src;
273
274 for (i = 0; i < (size >> 2); i++)
275 writel_relaxed(*s++, t++);
276}
277
50082319
AB		 278/*
279 * Minimal-overhead PIO for data access.
280 */
281static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
282{
283 struct nand_chip *nand_chip = mtd->priv;
1ae9c092 284 struct atmel_nand_host *host = nand_chip->priv;
50082319 285
1ae9c092
JW		 286 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
287 memcpy32_fromio(buf, host->nfc->data_in_sram, len);
288 host->nfc->data_in_sram += len;
289 } else {
290 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
291 }
50082319
AB		 292}
293
294static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
295{
296 struct nand_chip *nand_chip = mtd->priv;
1ae9c092 297 struct atmel_nand_host *host = nand_chip->priv;
50082319 298
1ae9c092
JW		 299 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
300 memcpy32_fromio(buf, host->nfc->data_in_sram, len);
301 host->nfc->data_in_sram += len;
302 } else {
303 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
304 }
50082319
AB		 305}
306
307static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
308{
309 struct nand_chip *nand_chip = mtd->priv;
310
311 __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
312}
313
314static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
315{
316 struct nand_chip *nand_chip = mtd->priv;
317
318 __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
319}
320
cbc6c5e7
HX		 321static void dma_complete_func(void *completion)
322{
323 complete(completion);
324}
325
1ae9c092
JW		 326static int nfc_set_sram_bank(struct atmel_nand_host *host, unsigned int bank)
327{
328 /* NFC only has two banks. Must be 0 or 1 */
329 if (bank > 1)
330 return -EINVAL;
331
332 if (bank) {
333 /* Only for a 2k-page or lower flash, NFC can handle 2 banks */
334 if (host->mtd.writesize > 2048)
335 return -EINVAL;
336 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK1);
337 } else {
338 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK0);
339 }
340
341 return 0;
342}
343
344static uint nfc_get_sram_off(struct atmel_nand_host *host)
345{
346 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
347 return NFC_SRAM_BANK1_OFFSET;
348 else
349 return 0;
350}
351
352static dma_addr_t nfc_sram_phys(struct atmel_nand_host *host)
353{
354 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
355 return host->nfc->sram_bank0_phys + NFC_SRAM_BANK1_OFFSET;
356 else
357 return host->nfc->sram_bank0_phys;
358}
359
cbc6c5e7
HX		 360static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
361 int is_read)
362{
363 struct dma_device *dma_dev;
364 enum dma_ctrl_flags flags;
365 dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
366 struct dma_async_tx_descriptor *tx = NULL;
367 dma_cookie_t cookie;
368 struct nand_chip *chip = mtd->priv;
369 struct atmel_nand_host *host = chip->priv;
370 void *p = buf;
371 int err = -EIO;
372 enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1ae9c092 373 struct atmel_nfc *nfc = host->nfc;
cbc6c5e7 374
80b4f81a
HX		 375 if (buf >= high_memory)
376 goto err_buf;
cbc6c5e7
HX		 377
378 dma_dev = host->dma_chan->device;
379
0776ae7b 380 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
cbc6c5e7
HX		 381
382 phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
383 if (dma_mapping_error(dma_dev->dev, phys_addr)) {
384 dev_err(host->dev, "Failed to dma_map_single\n");
385 goto err_buf;
386 }
387
388 if (is_read) {
1ae9c092
JW		 389 if (nfc && nfc->data_in_sram)
390 dma_src_addr = nfc_sram_phys(host) + (nfc->data_in_sram
391 - (nfc->sram_bank0 + nfc_get_sram_off(host)));
392 else
393 dma_src_addr = host->io_phys;
394
cbc6c5e7
HX		 395 dma_dst_addr = phys_addr;
396 } else {
397 dma_src_addr = phys_addr;
6054d4d5
JW		 398
399 if (nfc && nfc->write_by_sram)
400 dma_dst_addr = nfc_sram_phys(host);
401 else
402 dma_dst_addr = host->io_phys;
cbc6c5e7
HX		 403 }
404
405 tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
406 dma_src_addr, len, flags);
407 if (!tx) {
408 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
409 goto err_dma;
410 }
411
412 init_completion(&host->comp);
413 tx->callback = dma_complete_func;
414 tx->callback_param = &host->comp;
415
416 cookie = tx->tx_submit(tx);
417 if (dma_submit_error(cookie)) {
418 dev_err(host->dev, "Failed to do DMA tx_submit\n");
419 goto err_dma;
420 }
421
422 dma_async_issue_pending(host->dma_chan);
423 wait_for_completion(&host->comp);
424
1ae9c092
JW		 425 if (is_read && nfc && nfc->data_in_sram)
426 /* After read data from SRAM, need to increase the position */
427 nfc->data_in_sram += len;
428
cbc6c5e7
HX		 429 err = 0;
430
431err_dma:
432 dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
433err_buf:
434 if (err != 0)
74414a94 435 dev_dbg(host->dev, "Fall back to CPU I/O\n");
cbc6c5e7
HX		 436 return err;
437}
438
439static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
440{
441 struct nand_chip *chip = mtd->priv;
50082319 442 struct atmel_nand_host *host = chip->priv;
cbc6c5e7 443
9d51567e
NF		 444 if (use_dma && len > mtd->oobsize)
445 /* only use DMA for bigger than oob size: better performances */
cbc6c5e7
HX		 446 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
447 return;
448
d6a01661 449 if (host->board.bus_width_16)
50082319
AB		 450 atmel_read_buf16(mtd, buf, len);
451 else
452 atmel_read_buf8(mtd, buf, len);
cbc6c5e7
HX		 453}
454
455static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
456{
457 struct nand_chip *chip = mtd->priv;
50082319 458 struct atmel_nand_host *host = chip->priv;
cbc6c5e7 459
9d51567e
NF		 460 if (use_dma && len > mtd->oobsize)
461 /* only use DMA for bigger than oob size: better performances */
cbc6c5e7
HX		 462 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
463 return;
464
d6a01661 465 if (host->board.bus_width_16)
50082319
AB		 466 atmel_write_buf16(mtd, buf, len);
467 else
468 atmel_write_buf8(mtd, buf, len);
cbc6c5e7
HX		 469}
470
1c7b874d
JW		 471/*
472 * Return number of ecc bytes per sector according to sector size and
473 * correction capability
474 *
475 * Following table shows what at91 PMECC supported:
476 * Correction Capability Sector_512_bytes Sector_1024_bytes
477 * ===================== ================ =================
478 * 2-bits 4-bytes 4-bytes
479 * 4-bits 7-bytes 7-bytes
480 * 8-bits 13-bytes 14-bytes
481 * 12-bits 20-bytes 21-bytes
482 * 24-bits 39-bytes 42-bytes
483 */
06f25510 484static int pmecc_get_ecc_bytes(int cap, int sector_size)
1c7b874d
JW		 485{
486 int m = 12 + sector_size / 512;
487 return (m * cap + 7) / 8;
488}
489
06f25510 490static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
d8929942 491 int oobsize, int ecc_len)
1c7b874d
JW		 492{
493 int i;
494
495 layout->eccbytes = ecc_len;
496
497 /* ECC will occupy the last ecc_len bytes continuously */
498 for (i = 0; i < ecc_len; i++)
499 layout->eccpos[i] = oobsize - ecc_len + i;
500
501 layout->oobfree[0].offset = 2;
502 layout->oobfree[0].length =
503 oobsize - ecc_len - layout->oobfree[0].offset;
504}
505
06f25510 506static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
1c7b874d
JW		 507{
508 int table_size;
509
510 table_size = host->pmecc_sector_size == 512 ?
511 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
512
513 return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
514 table_size * sizeof(int16_t);
515}
516
06f25510 517static int pmecc_data_alloc(struct atmel_nand_host *host)
1c7b874d
JW		 518{
519 const int cap = host->pmecc_corr_cap;
0d63748d
JCPV		 520 int size;
521
522 size = (2 * cap + 1) * sizeof(int16_t);
523 host->pmecc_partial_syn = devm_kzalloc(host->dev, size, GFP_KERNEL);
524 host->pmecc_si = devm_kzalloc(host->dev, size, GFP_KERNEL);
525 host->pmecc_lmu = devm_kzalloc(host->dev,
526 (cap + 1) * sizeof(int16_t), GFP_KERNEL);
527 host->pmecc_smu = devm_kzalloc(host->dev,
528 (cap + 2) * size, GFP_KERNEL);
529
530 size = (cap + 1) * sizeof(int);
531 host->pmecc_mu = devm_kzalloc(host->dev, size, GFP_KERNEL);
532 host->pmecc_dmu = devm_kzalloc(host->dev, size, GFP_KERNEL);
533 host->pmecc_delta = devm_kzalloc(host->dev, size, GFP_KERNEL);
534
535 if (!host->pmecc_partial_syn ||
536 !host->pmecc_si ||
537 !host->pmecc_lmu ||
538 !host->pmecc_smu ||
539 !host->pmecc_mu ||
540 !host->pmecc_dmu ||
541 !host->pmecc_delta)
542 return -ENOMEM;
1c7b874d 543
0d63748d 544 return 0;
1c7b874d
JW		 545}
546
547static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
548{
549 struct nand_chip *nand_chip = mtd->priv;
550 struct atmel_nand_host *host = nand_chip->priv;
551 int i;
552 uint32_t value;
553
554 /* Fill odd syndromes */
555 for (i = 0; i < host->pmecc_corr_cap; i++) {
556 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
557 if (i & 1)
558 value >>= 16;
559 value &= 0xffff;
560 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
561 }
562}
563
564static void pmecc_substitute(struct mtd_info *mtd)
565{
566 struct nand_chip *nand_chip = mtd->priv;
567 struct atmel_nand_host *host = nand_chip->priv;
568 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
569 int16_t __iomem *index_of = host->pmecc_index_of;
570 int16_t *partial_syn = host->pmecc_partial_syn;
571 const int cap = host->pmecc_corr_cap;
572 int16_t *si;
573 int i, j;
574
575 /* si[] is a table that holds the current syndrome value,
576 * an element of that table belongs to the field
577 */
578 si = host->pmecc_si;
579
580 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
581
582 /* Computation 2t syndromes based on S(x) */
583 /* Odd syndromes */
584 for (i = 1; i < 2 * cap; i += 2) {
585 for (j = 0; j < host->pmecc_degree; j++) {
586 if (partial_syn[i] & ((unsigned short)0x1 << j))
587 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
588 }
589 }
590 /* Even syndrome = (Odd syndrome) ** 2 */
591 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
592 if (si[j] == 0) {
593 si[i] = 0;
594 } else {
595 int16_t tmp;
596
597 tmp = readw_relaxed(index_of + si[j]);
598 tmp = (tmp * 2) % host->pmecc_cw_len;
599 si[i] = readw_relaxed(alpha_to + tmp);
600 }
601 }
602
603 return;
604}
605
606static void pmecc_get_sigma(struct mtd_info *mtd)
607{
608 struct nand_chip *nand_chip = mtd->priv;
609 struct atmel_nand_host *host = nand_chip->priv;
610
611 int16_t *lmu = host->pmecc_lmu;
612 int16_t *si = host->pmecc_si;
613 int *mu = host->pmecc_mu;
614 int *dmu = host->pmecc_dmu; /* Discrepancy */
615 int *delta = host->pmecc_delta; /* Delta order */
616 int cw_len = host->pmecc_cw_len;
617 const int16_t cap = host->pmecc_corr_cap;
618 const int num = 2 * cap + 1;
619 int16_t __iomem *index_of = host->pmecc_index_of;
620 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
621 int i, j, k;
622 uint32_t dmu_0_count, tmp;
623 int16_t *smu = host->pmecc_smu;
624
625 /* index of largest delta */
626 int ro;
627 int largest;
628 int diff;
629
630 dmu_0_count = 0;
631
632 /* First Row */
633
634 /* Mu */
635 mu[0] = -1;
636
637 memset(smu, 0, sizeof(int16_t) * num);
638 smu[0] = 1;
639
640 /* discrepancy set to 1 */
641 dmu[0] = 1;
642 /* polynom order set to 0 */
643 lmu[0] = 0;
644 delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
645
646 /* Second Row */
647
648 /* Mu */
649 mu[1] = 0;
650 /* Sigma(x) set to 1 */
651 memset(&smu[num], 0, sizeof(int16_t) * num);
652 smu[num] = 1;
653
654 /* discrepancy set to S1 */
655 dmu[1] = si[1];
656
657 /* polynom order set to 0 */
658 lmu[1] = 0;
659
660 delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
661
662 /* Init the Sigma(x) last row */
663 memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
664
665 for (i = 1; i <= cap; i++) {
666 mu[i + 1] = i << 1;
667 /* Begin Computing Sigma (Mu+1) and L(mu) */
668 /* check if discrepancy is set to 0 */
669 if (dmu[i] == 0) {
670 dmu_0_count++;
671
672 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
673 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
674 tmp += 2;
675 else
676 tmp += 1;
677
678 if (dmu_0_count == tmp) {
679 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
680 smu[(cap + 1) * num + j] =
681 smu[i * num + j];
682
683 lmu[cap + 1] = lmu[i];
684 return;
685 }
686
687 /* copy polynom */
688 for (j = 0; j <= lmu[i] >> 1; j++)
689 smu[(i + 1) * num + j] = smu[i * num + j];
690
691 /* copy previous polynom order to the next */
692 lmu[i + 1] = lmu[i];
693 } else {
694 ro = 0;
695 largest = -1;
696 /* find largest delta with dmu != 0 */
697 for (j = 0; j < i; j++) {
698 if ((dmu[j]) && (delta[j] > largest)) {
699 largest = delta[j];
700 ro = j;
701 }
702 }
703
704 /* compute difference */
705 diff = (mu[i] - mu[ro]);
706
707 /* Compute degree of the new smu polynomial */
708 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
709 lmu[i + 1] = lmu[i];
710 else
711 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
712
713 /* Init smu[i+1] with 0 */
714 for (k = 0; k < num; k++)
715 smu[(i + 1) * num + k] = 0;
716
717 /* Compute smu[i+1] */
718 for (k = 0; k <= lmu[ro] >> 1; k++) {
719 int16_t a, b, c;
720
721 if (!(smu[ro * num + k] && dmu[i]))
722 continue;
723 a = readw_relaxed(index_of + dmu[i]);
724 b = readw_relaxed(index_of + dmu[ro]);
725 c = readw_relaxed(index_of + smu[ro * num + k]);
726 tmp = a + (cw_len - b) + c;
727 a = readw_relaxed(alpha_to + tmp % cw_len);
728 smu[(i + 1) * num + (k + diff)] = a;
729 }
730
731 for (k = 0; k <= lmu[i] >> 1; k++)
732 smu[(i + 1) * num + k] ^= smu[i * num + k];
733 }
734
735 /* End Computing Sigma (Mu+1) and L(mu) */
736 /* In either case compute delta */
737 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
738
739 /* Do not compute discrepancy for the last iteration */
740 if (i >= cap)
741 continue;
742
743 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
744 tmp = 2 * (i - 1);
745 if (k == 0) {
746 dmu[i + 1] = si[tmp + 3];
747 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
748 int16_t a, b, c;
749 a = readw_relaxed(index_of +
750 smu[(i + 1) * num + k]);
751 b = si[2 * (i - 1) + 3 - k];
752 c = readw_relaxed(index_of + b);
753 tmp = a + c;
754 tmp %= cw_len;
755 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
756 dmu[i + 1];
757 }
758 }
759 }
760
761 return;
762}
763
764static int pmecc_err_location(struct mtd_info *mtd)
765{
766 struct nand_chip *nand_chip = mtd->priv;
767 struct atmel_nand_host *host = nand_chip->priv;
768 unsigned long end_time;
769 const int cap = host->pmecc_corr_cap;
770 const int num = 2 * cap + 1;
771 int sector_size = host->pmecc_sector_size;
772 int err_nbr = 0; /* number of error */
773 int roots_nbr; /* number of roots */
774 int i;
775 uint32_t val;
776 int16_t *smu = host->pmecc_smu;
777
778 pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
779
780 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
781 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
782 smu[(cap + 1) * num + i]);
783 err_nbr++;
784 }
785
786 val = (err_nbr - 1) << 16;
787 if (sector_size == 1024)
788 val |= 1;
789
790 pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
791 pmerrloc_writel(host->pmerrloc_base, ELEN,
792 sector_size * 8 + host->pmecc_degree * cap);
793
794 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
795 while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
796 & PMERRLOC_CALC_DONE)) {
797 if (unlikely(time_after(jiffies, end_time))) {
798 dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
799 return -1;
800 }
801 cpu_relax();
802 }
803
804 roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
805 & PMERRLOC_ERR_NUM_MASK) >> 8;
806 /* Number of roots == degree of smu hence <= cap */
807 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
808 return err_nbr - 1;
809
810 /* Number of roots does not match the degree of smu
811 * unable to correct error */
812 return -1;
813}
814
815static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
816 int sector_num, int extra_bytes, int err_nbr)
817{
818 struct nand_chip *nand_chip = mtd->priv;
819 struct atmel_nand_host *host = nand_chip->priv;
820 int i = 0;
821 int byte_pos, bit_pos, sector_size, pos;
822 uint32_t tmp;
823 uint8_t err_byte;
824
825 sector_size = host->pmecc_sector_size;
826
827 while (err_nbr) {
828 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
829 byte_pos = tmp / 8;
830 bit_pos = tmp % 8;
831
832 if (byte_pos >= (sector_size + extra_bytes))
833 BUG(); /* should never happen */
834
835 if (byte_pos < sector_size) {
836 err_byte = *(buf + byte_pos);
837 *(buf + byte_pos) ^= (1 << bit_pos);
838
839 pos = sector_num * host->pmecc_sector_size + byte_pos;
840 dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
841 pos, bit_pos, err_byte, *(buf + byte_pos));
842 } else {
843 /* Bit flip in OOB area */
844 tmp = sector_num * host->pmecc_bytes_per_sector
845 + (byte_pos - sector_size);
846 err_byte = ecc[tmp];
847 ecc[tmp] ^= (1 << bit_pos);
848
849 pos = tmp + nand_chip->ecc.layout->eccpos[0];
850 dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
851 pos, bit_pos, err_byte, ecc[tmp]);
852 }
853
854 i++;
855 err_nbr--;
856 }
857
858 return;
859}
860
861static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
862 u8 *ecc)
863{
864 struct nand_chip *nand_chip = mtd->priv;
865 struct atmel_nand_host *host = nand_chip->priv;
b3857666 866 int i, err_nbr;
1c7b874d 867 uint8_t *buf_pos;
c0c70d9e 868 int total_err = 0;
1c7b874d 869
b3857666 870 for (i = 0; i < nand_chip->ecc.total; i++)
1c7b874d
JW		 871 if (ecc[i] != 0xff)
872 goto normal_check;
873 /* Erased page, return OK */
874 return 0;
875
876normal_check:
877 for (i = 0; i < host->pmecc_sector_number; i++) {
878 err_nbr = 0;
879 if (pmecc_stat & 0x1) {
880 buf_pos = buf + i * host->pmecc_sector_size;
881
882 pmecc_gen_syndrome(mtd, i);
883 pmecc_substitute(mtd);
884 pmecc_get_sigma(mtd);
885
886 err_nbr = pmecc_err_location(mtd);
887 if (err_nbr == -1) {
888 dev_err(host->dev, "PMECC: Too many errors\n");
889 mtd->ecc_stats.failed++;
890 return -EIO;
891 } else {
892 pmecc_correct_data(mtd, buf_pos, ecc, i,
893 host->pmecc_bytes_per_sector, err_nbr);
894 mtd->ecc_stats.corrected += err_nbr;
c0c70d9e 895 total_err += err_nbr;
1c7b874d
JW		 896 }
897 }
898 pmecc_stat >>= 1;
899 }
900
c0c70d9e 901 return total_err;
1c7b874d
JW		 902}
903
5ee3d9da
JW		 904static void pmecc_enable(struct atmel_nand_host *host, int ecc_op)
905{
906 u32 val;
907
5ee3d9da
JW		 908 if (ecc_op != NAND_ECC_READ && ecc_op != NAND_ECC_WRITE) {
909 dev_err(host->dev, "atmel_nand: wrong pmecc operation type!");
910 return;
911 }
912
1fad0e8b
JW		 913 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
914 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
915 val = pmecc_readl_relaxed(host->ecc, CFG);
916
5ee3d9da
JW		 917 if (ecc_op == NAND_ECC_READ)
918 pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP)
919 | PMECC_CFG_AUTO_ENABLE);
920 else
921 pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP)
922 & ~PMECC_CFG_AUTO_ENABLE);
923
924 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
925 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
926}
927
1c7b874d
JW		 928static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
929 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
930{
931 struct atmel_nand_host *host = chip->priv;
b3857666 932 int eccsize = chip->ecc.size * chip->ecc.steps;
1c7b874d
JW		 933 uint8_t *oob = chip->oob_poi;
934 uint32_t *eccpos = chip->ecc.layout->eccpos;
935 uint32_t stat;
936 unsigned long end_time;
c0c70d9e 937 int bitflips = 0;
1c7b874d 938
1ae9c092
JW		 939 if (!host->nfc || !host->nfc->use_nfc_sram)
940 pmecc_enable(host, NAND_ECC_READ);
1c7b874d
JW		 941
942 chip->read_buf(mtd, buf, eccsize);
943 chip->read_buf(mtd, oob, mtd->oobsize);
944
945 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
946 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
947 if (unlikely(time_after(jiffies, end_time))) {
948 dev_err(host->dev, "PMECC: Timeout to get error status.\n");
949 return -EIO;
950 }
951 cpu_relax();
952 }
953
954 stat = pmecc_readl_relaxed(host->ecc, ISR);
c0c70d9e
JW		 955 if (stat != 0) {
956 bitflips = pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]);
957 if (bitflips < 0)
958 /* uncorrectable errors */
959 return 0;
960 }
1c7b874d 961
c0c70d9e 962 return bitflips;
1c7b874d
JW		 963}
964
965static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
966 struct nand_chip *chip, const uint8_t *buf, int oob_required)
967{
968 struct atmel_nand_host *host = chip->priv;
969 uint32_t *eccpos = chip->ecc.layout->eccpos;
970 int i, j;
971 unsigned long end_time;
972
6054d4d5
JW		 973 if (!host->nfc || !host->nfc->write_by_sram) {
974 pmecc_enable(host, NAND_ECC_WRITE);
975 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
976 }
1c7b874d
JW		 977
978 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
979 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
980 if (unlikely(time_after(jiffies, end_time))) {
981 dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
982 return -EIO;
983 }
984 cpu_relax();
985 }
986
987 for (i = 0; i < host->pmecc_sector_number; i++) {
988 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
989 int pos;
990
991 pos = i * host->pmecc_bytes_per_sector + j;
992 chip->oob_poi[eccpos[pos]] =
993 pmecc_readb_ecc_relaxed(host->ecc, i, j);
994 }
995 }
996 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
997
998 return 0;
999}
1000
1001static void atmel_pmecc_core_init(struct mtd_info *mtd)
1002{
1003 struct nand_chip *nand_chip = mtd->priv;
1004 struct atmel_nand_host *host = nand_chip->priv;
1005 uint32_t val = 0;
1006 struct nand_ecclayout *ecc_layout;
1007
1008 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
1009 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1010
1011 switch (host->pmecc_corr_cap) {
1012 case 2:
1013 val = PMECC_CFG_BCH_ERR2;
1014 break;
1015 case 4:
1016 val = PMECC_CFG_BCH_ERR4;
1017 break;
1018 case 8:
1019 val = PMECC_CFG_BCH_ERR8;
1020 break;
1021 case 12:
1022 val = PMECC_CFG_BCH_ERR12;
1023 break;
1024 case 24:
1025 val = PMECC_CFG_BCH_ERR24;
1026 break;
1027 }
1028
1029 if (host->pmecc_sector_size == 512)
1030 val |= PMECC_CFG_SECTOR512;
1031 else if (host->pmecc_sector_size == 1024)
1032 val |= PMECC_CFG_SECTOR1024;
1033
1034 switch (host->pmecc_sector_number) {
1035 case 1:
1036 val |= PMECC_CFG_PAGE_1SECTOR;
1037 break;
1038 case 2:
1039 val |= PMECC_CFG_PAGE_2SECTORS;
1040 break;
1041 case 4:
1042 val |= PMECC_CFG_PAGE_4SECTORS;
1043 break;
1044 case 8:
1045 val |= PMECC_CFG_PAGE_8SECTORS;
1046 break;
1047 }
1048
1049 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
1050 | PMECC_CFG_AUTO_DISABLE);
1051 pmecc_writel(host->ecc, CFG, val);
1052
1053 ecc_layout = nand_chip->ecc.layout;
1054 pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
1055 pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
1056 pmecc_writel(host->ecc, EADDR,
1057 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
1058 /* See datasheet about PMECC Clock Control Register */
1059 pmecc_writel(host->ecc, CLK, 2);
1060 pmecc_writel(host->ecc, IDR, 0xff);
1061 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
1062}
1063
84cfbbb8 1064/*
2a3d933a 1065 * Get minimum ecc requirements from NAND.
84cfbbb8 1066 * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
2a3d933a 1067 * will set them according to minimum ecc requirement. Otherwise, use the
84cfbbb8
JW		 1068 * value in DTS file.
1069 * return 0 if success. otherwise return error code.
1070 */
1071static int pmecc_choose_ecc(struct atmel_nand_host *host,
1072 int *cap, int *sector_size)
1073{
2a3d933a
JW		 1074 /* Get minimum ECC requirements */
1075 if (host->nand_chip.ecc_strength_ds) {
1076 *cap = host->nand_chip.ecc_strength_ds;
1077 *sector_size = host->nand_chip.ecc_step_ds;
1078 dev_info(host->dev, "minimum ECC: %d bits in %d bytes\n",
84cfbbb8 1079 *cap, *sector_size);
84cfbbb8 1080 } else {
84cfbbb8
JW		 1081 *cap = 2;
1082 *sector_size = 512;
2a3d933a 1083 dev_info(host->dev, "can't detect min. ECC, assume 2 bits in 512 bytes\n");
84cfbbb8
JW		 1084 }
1085
2a3d933a 1086 /* If device tree doesn't specify, use NAND's minimum ECC parameters */
84cfbbb8
JW		 1087 if (host->pmecc_corr_cap == 0) {
1088 /* use the most fitable ecc bits (the near bigger one ) */
1089 if (*cap <= 2)
1090 host->pmecc_corr_cap = 2;
1091 else if (*cap <= 4)
1092 host->pmecc_corr_cap = 4;
edc9cba4 1093 else if (*cap <= 8)
84cfbbb8 1094 host->pmecc_corr_cap = 8;
edc9cba4 1095 else if (*cap <= 12)
84cfbbb8 1096 host->pmecc_corr_cap = 12;
edc9cba4 1097 else if (*cap <= 24)
84cfbbb8
JW		 1098 host->pmecc_corr_cap = 24;
1099 else
1100 return -EINVAL;
1101 }
1102 if (host->pmecc_sector_size == 0) {
1103 /* use the most fitable sector size (the near smaller one ) */
1104 if (*sector_size >= 1024)
1105 host->pmecc_sector_size = 1024;
1106 else if (*sector_size >= 512)
1107 host->pmecc_sector_size = 512;
1108 else
1109 return -EINVAL;
1110 }
1111 return 0;
1112}
1113
2c2b9285 1114static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
1c7b874d
JW		 1115 struct atmel_nand_host *host)
1116{
1117 struct mtd_info *mtd = &host->mtd;
1118 struct nand_chip *nand_chip = &host->nand_chip;
1119 struct resource *regs, *regs_pmerr, *regs_rom;
1120 int cap, sector_size, err_no;
1121
84cfbbb8
JW		 1122 err_no = pmecc_choose_ecc(host, &cap, &sector_size);
1123 if (err_no) {
1124 dev_err(host->dev, "The NAND flash's ECC requirement are not support!");
1125 return err_no;
1126 }
1127
f666d649 1128 if (cap > host->pmecc_corr_cap ||
84cfbbb8
JW		 1129 sector_size != host->pmecc_sector_size)
1130 dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
e66b4318 1131
1c7b874d
JW		 1132 cap = host->pmecc_corr_cap;
1133 sector_size = host->pmecc_sector_size;
e66b4318
JW		 1134 host->pmecc_lookup_table_offset = (sector_size == 512) ?
1135 host->pmecc_lookup_table_offset_512 :
1136 host->pmecc_lookup_table_offset_1024;
1137
1c7b874d
JW		 1138 dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
1139 cap, sector_size);
1140
1141 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1142 if (!regs) {
1143 dev_warn(host->dev,
1144 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1145 nand_chip->ecc.mode = NAND_ECC_SOFT;
1146 return 0;
1147 }
1148
0d63748d
JCPV		 1149 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1150 if (IS_ERR(host->ecc)) {
0d63748d
JCPV		 1151 err_no = PTR_ERR(host->ecc);
1152 goto err;
1c7b874d
JW		 1153 }
1154
1155 regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
0d63748d
JCPV		 1156 host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr);
1157 if (IS_ERR(host->pmerrloc_base)) {
0d63748d
JCPV		 1158 err_no = PTR_ERR(host->pmerrloc_base);
1159 goto err;
1c7b874d
JW		 1160 }
1161
0d63748d
JCPV		 1162 regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1163 host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev, regs_rom);
1164 if (IS_ERR(host->pmecc_rom_base)) {
0d63748d
JCPV		 1165 err_no = PTR_ERR(host->pmecc_rom_base);
1166 goto err;
1c7b874d
JW		 1167 }
1168
b3857666 1169 nand_chip->ecc.size = sector_size;
1c7b874d
JW		 1170
1171 /* set ECC page size and oob layout */
1172 switch (mtd->writesize) {
a3557105
WJ		 1173 case 512:
1174 case 1024:
1c7b874d 1175 case 2048:
a3557105
WJ		 1176 case 4096:
1177 case 8192:
1178 if (sector_size > mtd->writesize) {
1179 dev_err(host->dev, "pmecc sector size is bigger than the page size!\n");
1180 err_no = -EINVAL;
1181 goto err;
1182 }
1183
2fa831f9
JW		 1184 host->pmecc_degree = (sector_size == 512) ?
1185 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
1c7b874d
JW		 1186 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
1187 host->pmecc_sector_number = mtd->writesize / sector_size;
1188 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
1189 cap, sector_size);
1190 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
1191 host->pmecc_index_of = host->pmecc_rom_base +
1192 host->pmecc_lookup_table_offset;
1193
b3857666 1194 nand_chip->ecc.steps = host->pmecc_sector_number;
1c7b874d 1195 nand_chip->ecc.strength = cap;
b3857666
BS		 1196 nand_chip->ecc.bytes = host->pmecc_bytes_per_sector;
1197 nand_chip->ecc.total = host->pmecc_bytes_per_sector *
1c7b874d 1198 host->pmecc_sector_number;
b3857666 1199 if (nand_chip->ecc.total > mtd->oobsize - 2) {
1c7b874d
JW		 1200 dev_err(host->dev, "No room for ECC bytes\n");
1201 err_no = -EINVAL;
0d63748d 1202 goto err;
1c7b874d
JW		 1203 }
1204 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
1205 mtd->oobsize,
b3857666
BS		 1206 nand_chip->ecc.total);
1207
1c7b874d
JW		 1208 nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
1209 break;
a3557105 1210 default:
1c7b874d
JW		 1211 dev_warn(host->dev,
1212 "Unsupported page size for PMECC, use Software ECC\n");
1c7b874d
JW		 1213 /* page size not handled by HW ECC */
1214 /* switching back to soft ECC */
1215 nand_chip->ecc.mode = NAND_ECC_SOFT;
1216 return 0;
1217 }
1218
1219 /* Allocate data for PMECC computation */
1220 err_no = pmecc_data_alloc(host);
1221 if (err_no) {
1222 dev_err(host->dev,
1223 "Cannot allocate memory for PMECC computation!\n");
0d63748d 1224 goto err;
1c7b874d
JW		 1225 }
1226
90445ff6 1227 nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
1c7b874d
JW		 1228 nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
1229 nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1230
1231 atmel_pmecc_core_init(mtd);
1232
1233 return 0;
1234
0d63748d 1235err:
1c7b874d
JW		 1236 return err_no;
1237}
1238
77f5492c
RG		 1239/*
1240 * Calculate HW ECC
1241 *
1242 * function called after a write
1243 *
1244 * mtd: MTD block structure
1245 * dat: raw data (unused)
1246 * ecc_code: buffer for ECC
1247 */
3c3796cc 1248static int atmel_nand_calculate(struct mtd_info *mtd,
77f5492c
RG		 1249 const u_char *dat, unsigned char *ecc_code)
1250{
1251 struct nand_chip *nand_chip = mtd->priv;
3c3796cc 1252 struct atmel_nand_host *host = nand_chip->priv;
77f5492c
RG		 1253 unsigned int ecc_value;
1254
1255 /* get the first 2 ECC bytes */
d43fa149 1256 ecc_value = ecc_readl(host->ecc, PR);
77f5492c 1257
3fc23898
RG		 1258 ecc_code[0] = ecc_value & 0xFF;
1259 ecc_code[1] = (ecc_value >> 8) & 0xFF;
77f5492c
RG		 1260
1261 /* get the last 2 ECC bytes */
3c3796cc 1262 ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
77f5492c 1263
3fc23898
RG		 1264 ecc_code[2] = ecc_value & 0xFF;
1265 ecc_code[3] = (ecc_value >> 8) & 0xFF;
77f5492c
RG		 1266
1267 return 0;
1268}
1269
1270/*
1271 * HW ECC read page function
1272 *
1273 * mtd: mtd info structure
1274 * chip: nand chip info structure
1275 * buf: buffer to store read data
1fbb938d 1276 * oob_required: caller expects OOB data read to chip->oob_poi
77f5492c 1277 */
1fbb938d
BN		 1278static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1279 uint8_t *buf, int oob_required, int page)
77f5492c
RG		 1280{
1281 int eccsize = chip->ecc.size;
1282 int eccbytes = chip->ecc.bytes;
1283 uint32_t *eccpos = chip->ecc.layout->eccpos;
1284 uint8_t *p = buf;
1285 uint8_t *oob = chip->oob_poi;
1286 uint8_t *ecc_pos;
1287 int stat;
3f91e94f 1288 unsigned int max_bitflips = 0;
77f5492c 1289
d6248fdd
HS		 1290 /*
1291 * Errata: ALE is incorrectly wired up to the ECC controller
1292 * on the AP7000, so it will include the address cycles in the
1293 * ECC calculation.
1294 *
1295 * Workaround: Reset the parity registers before reading the
1296 * actual data.
1297 */
71b94e2e
JW		 1298 struct atmel_nand_host *host = chip->priv;
1299 if (host->board.need_reset_workaround)
d6248fdd 1300 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
d6248fdd 1301
77f5492c
RG		 1302 /* read the page */
1303 chip->read_buf(mtd, p, eccsize);
1304
1305 /* move to ECC position if needed */
1306 if (eccpos[0] != 0) {
1307 /* This only works on large pages
1308 * because the ECC controller waits for
1309 * NAND_CMD_RNDOUTSTART after the
1310 * NAND_CMD_RNDOUT.
1311 * anyway, for small pages, the eccpos[0] == 0
1312 */
1313 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1314 mtd->writesize + eccpos[0], -1);
1315 }
1316
1317 /* the ECC controller needs to read the ECC just after the data */
1318 ecc_pos = oob + eccpos[0];
1319 chip->read_buf(mtd, ecc_pos, eccbytes);
1320
1321 /* check if there's an error */
1322 stat = chip->ecc.correct(mtd, p, oob, NULL);
1323
3f91e94f 1324 if (stat < 0) {
77f5492c 1325 mtd->ecc_stats.failed++;
3f91e94f 1326 } else {
77f5492c 1327 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1328 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1329 }
77f5492c
RG		 1330
1331 /* get back to oob start (end of page) */
1332 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1333
1334 /* read the oob */
1335 chip->read_buf(mtd, oob, mtd->oobsize);
1336
3f91e94f 1337 return max_bitflips;
77f5492c
RG		 1338}
1339
1340/*
1341 * HW ECC Correction
1342 *
1343 * function called after a read
1344 *
1345 * mtd: MTD block structure
1346 * dat: raw data read from the chip
1347 * read_ecc: ECC from the chip (unused)
1348 * isnull: unused
1349 *
1350 * Detect and correct a 1 bit error for a page
1351 */
3c3796cc 1352static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
77f5492c
RG		 1353 u_char *read_ecc, u_char *isnull)
1354{
1355 struct nand_chip *nand_chip = mtd->priv;
3c3796cc 1356 struct atmel_nand_host *host = nand_chip->priv;
77f5492c
RG		 1357 unsigned int ecc_status;
1358 unsigned int ecc_word, ecc_bit;
1359
1360 /* get the status from the Status Register */
1361 ecc_status = ecc_readl(host->ecc, SR);
1362
1363 /* if there's no error */
3c3796cc 1364 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
77f5492c
RG		 1365 return 0;
1366
1367 /* get error bit offset (4 bits) */
3c3796cc 1368 ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
77f5492c 1369 /* get word address (12 bits) */
3c3796cc 1370 ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
77f5492c
RG		 1371 ecc_word >>= 4;
1372
1373 /* if there are multiple errors */
3c3796cc 1374 if (ecc_status & ATMEL_ECC_MULERR) {
77f5492c
RG		 1375 /* check if it is a freshly erased block
1376 * (filled with 0xff) */
3c3796cc
HS		 1377 if ((ecc_bit == ATMEL_ECC_BITADDR)
1378 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
77f5492c
RG		 1379 /* the block has just been erased, return OK */
1380 return 0;
1381 }
1382 /* it doesn't seems to be a freshly
1383 * erased block.
1384 * We can't correct so many errors */
3c3796cc 1385 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
77f5492c
RG		 1386 " Unable to correct.\n");
1387 return -EIO;
1388 }
1389
1390 /* if there's a single bit error : we can correct it */
3c3796cc 1391 if (ecc_status & ATMEL_ECC_ECCERR) {
77f5492c
RG		 1392 /* there's nothing much to do here.
1393 * the bit error is on the ECC itself.
1394 */
3c3796cc 1395 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
77f5492c
RG		 1396 " Nothing to correct\n");
1397 return 0;
1398 }
1399
3c3796cc 1400 dev_dbg(host->dev, "atmel_nand : one bit error on data."
77f5492c
RG		 1401 " (word offset in the page :"
1402 " 0x%x bit offset : 0x%x)\n",
1403 ecc_word, ecc_bit);
1404 /* correct the error */
1405 if (nand_chip->options & NAND_BUSWIDTH_16) {
1406 /* 16 bits words */
1407 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1408 } else {
1409 /* 8 bits words */
1410 dat[ecc_word] ^= (1 << ecc_bit);
1411 }
3c3796cc 1412 dev_dbg(host->dev, "atmel_nand : error corrected\n");
77f5492c
RG		 1413 return 1;
1414}
1415
1416/*
d6248fdd 1417 * Enable HW ECC : unused on most chips
77f5492c 1418 */
d6248fdd
HS		 1419static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1420{
71b94e2e
JW		 1421 struct nand_chip *nand_chip = mtd->priv;
1422 struct atmel_nand_host *host = nand_chip->priv;
1423
1424 if (host->board.need_reset_workaround)
d6248fdd 1425 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
d6248fdd 1426}
77f5492c 1427
06f25510 1428static int atmel_of_init_port(struct atmel_nand_host *host,
d8929942 1429 struct device_node *np)
d6a01661 1430{
c0cf787f 1431 u32 val;
a41b51a1 1432 u32 offset[2];
d6a01661
JCPV		 1433 int ecc_mode;
1434 struct atmel_nand_data *board = &host->board;
e9d8da80 1435 enum of_gpio_flags flags = 0;
d6a01661
JCPV		 1436
1437 if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
1438 if (val >= 32) {
1439 dev_err(host->dev, "invalid addr-offset %u\n", val);
1440 return -EINVAL;
1441 }
1442 board->ale = val;
1443 }
1444
1445 if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
1446 if (val >= 32) {
1447 dev_err(host->dev, "invalid cmd-offset %u\n", val);
1448 return -EINVAL;
1449 }
1450 board->cle = val;
1451 }
1452
1453 ecc_mode = of_get_nand_ecc_mode(np);
1454
1455 board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
1456
1457 board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
1458
1b719265
JW		 1459 board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma");
1460
d6a01661
JCPV		 1461 if (of_get_nand_bus_width(np) == 16)
1462 board->bus_width_16 = 1;
1463
1464 board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
1465 board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
1466
1467 board->enable_pin = of_get_gpio(np, 1);
1468 board->det_pin = of_get_gpio(np, 2);
1469
a41b51a1
JW		 1470 host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1471
7dc37de7
JW		 1472 /* load the nfc driver if there is */
1473 of_platform_populate(np, NULL, NULL, host->dev);
1474
a41b51a1
JW		 1475 if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
1476 return 0; /* Not using PMECC */
1477
1478 /* use PMECC, get correction capability, sector size and lookup
1479 * table offset.
e66b4318
JW		 1480 * If correction bits and sector size are not specified, then find
1481 * them from NAND ONFI parameters.
a41b51a1 1482 */
e66b4318
JW		 1483 if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
1484 if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
1485 (val != 24)) {
1486 dev_err(host->dev,
1487 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1488 val);
1489 return -EINVAL;
1490 }
1491 host->pmecc_corr_cap = (u8)val;
a41b51a1 1492 }
a41b51a1 1493
e66b4318
JW		 1494 if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
1495 if ((val != 512) && (val != 1024)) {
1496 dev_err(host->dev,
1497 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1498 val);
1499 return -EINVAL;
1500 }
1501 host->pmecc_sector_size = (u16)val;
a41b51a1 1502 }
a41b51a1
JW		 1503
1504 if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1505 offset, 2) != 0) {
1506 dev_err(host->dev, "Cannot get PMECC lookup table offset\n");
1507 return -EINVAL;
1508 }
c0cf787f 1509 if (!offset[0] && !offset[1]) {
a41b51a1
JW		 1510 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1511 return -EINVAL;
1512 }
e66b4318
JW		 1513 host->pmecc_lookup_table_offset_512 = offset[0];
1514 host->pmecc_lookup_table_offset_1024 = offset[1];
a41b51a1 1515
d6a01661
JCPV		 1516 return 0;
1517}
d6a01661 1518
2c2b9285 1519static int atmel_hw_nand_init_params(struct platform_device *pdev,
3dfe41a4
JW		 1520 struct atmel_nand_host *host)
1521{
1522 struct mtd_info *mtd = &host->mtd;
1523 struct nand_chip *nand_chip = &host->nand_chip;
1524 struct resource *regs;
1525
1526 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1527 if (!regs) {
1528 dev_err(host->dev,
1529 "Can't get I/O resource regs, use software ECC\n");
1530 nand_chip->ecc.mode = NAND_ECC_SOFT;
1531 return 0;
1532 }
1533
0d63748d 1534 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
8fb7b930 1535 if (IS_ERR(host->ecc))
0d63748d 1536 return PTR_ERR(host->ecc);
3dfe41a4
JW		 1537
1538 /* ECC is calculated for the whole page (1 step) */
1539 nand_chip->ecc.size = mtd->writesize;
1540
1541 /* set ECC page size and oob layout */
1542 switch (mtd->writesize) {
1543 case 512:
1544 nand_chip->ecc.layout = &atmel_oobinfo_small;
1545 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1546 break;
1547 case 1024:
1548 nand_chip->ecc.layout = &atmel_oobinfo_large;
1549 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1550 break;
1551 case 2048:
1552 nand_chip->ecc.layout = &atmel_oobinfo_large;
1553 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1554 break;
1555 case 4096:
1556 nand_chip->ecc.layout = &atmel_oobinfo_large;
1557 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1558 break;
1559 default:
1560 /* page size not handled by HW ECC */
1561 /* switching back to soft ECC */
1562 nand_chip->ecc.mode = NAND_ECC_SOFT;
1563 return 0;
1564 }
1565
1566 /* set up for HW ECC */
1567 nand_chip->ecc.calculate = atmel_nand_calculate;
1568 nand_chip->ecc.correct = atmel_nand_correct;
1569 nand_chip->ecc.hwctl = atmel_nand_hwctl;
1570 nand_chip->ecc.read_page = atmel_nand_read_page;
1571 nand_chip->ecc.bytes = 4;
1572 nand_chip->ecc.strength = 1;
1573
1574 return 0;
1575}
1576
50e04e2f
WJ		 1577static inline u32 nfc_read_status(struct atmel_nand_host *host)
1578{
1579 u32 err_flags = NFC_SR_DTOE | NFC_SR_UNDEF | NFC_SR_AWB | NFC_SR_ASE;
1580 u32 nfc_status = nfc_readl(host->nfc->hsmc_regs, SR);
1581
1582 if (unlikely(nfc_status & err_flags)) {
1583 if (nfc_status & NFC_SR_DTOE)
1584 dev_err(host->dev, "NFC: Waiting Nand R/B Timeout Error\n");
1585 else if (nfc_status & NFC_SR_UNDEF)
1586 dev_err(host->dev, "NFC: Access Undefined Area Error\n");
1587 else if (nfc_status & NFC_SR_AWB)
1588 dev_err(host->dev, "NFC: Access memory While NFC is busy\n");
1589 else if (nfc_status & NFC_SR_ASE)
1590 dev_err(host->dev, "NFC: Access memory Size Error\n");
1591 }
1592
1593 return nfc_status;
1594}
1595
7dc37de7
JW		 1596/* SMC interrupt service routine */
1597static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
1598{
1599 struct atmel_nand_host *host = dev_id;
1600 u32 status, mask, pending;
e4e06934 1601 irqreturn_t ret = IRQ_NONE;
7dc37de7 1602
50e04e2f 1603 status = nfc_read_status(host);
7dc37de7
JW		 1604 mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1605 pending = status & mask;
1606
1607 if (pending & NFC_SR_XFR_DONE) {
e4e06934 1608 complete(&host->nfc->comp_xfer_done);
7dc37de7 1609 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
e4e06934
JW		 1610 ret = IRQ_HANDLED;
1611 }
1612 if (pending & NFC_SR_RB_EDGE) {
1613 complete(&host->nfc->comp_ready);
7dc37de7 1614 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
e4e06934
JW		 1615 ret = IRQ_HANDLED;
1616 }
1617 if (pending & NFC_SR_CMD_DONE) {
1618 complete(&host->nfc->comp_cmd_done);
7dc37de7 1619 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_CMD_DONE);
e4e06934 1620 ret = IRQ_HANDLED;
7dc37de7
JW		 1621 }
1622
1623 return ret;
1624}
1625
1626/* NFC(Nand Flash Controller) related functions */
e4e06934 1627static void nfc_prepare_interrupt(struct atmel_nand_host *host, u32 flag)
7dc37de7 1628{
e4e06934
JW		 1629 if (flag & NFC_SR_XFR_DONE)
1630 init_completion(&host->nfc->comp_xfer_done);
1631
1632 if (flag & NFC_SR_RB_EDGE)
1633 init_completion(&host->nfc->comp_ready);
1634
1635 if (flag & NFC_SR_CMD_DONE)
1636 init_completion(&host->nfc->comp_cmd_done);
7dc37de7
JW		 1637
1638 /* Enable interrupt that need to wait for */
1639 nfc_writel(host->nfc->hsmc_regs, IER, flag);
e4e06934 1640}
7dc37de7 1641
e4e06934
JW		 1642static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
1643{
1644 int i, index = 0;
1645 struct completion *comp[3]; /* Support 3 interrupt completion */
1646
1647 if (flag & NFC_SR_XFR_DONE)
1648 comp[index++] = &host->nfc->comp_xfer_done;
1649
1650 if (flag & NFC_SR_RB_EDGE)
1651 comp[index++] = &host->nfc->comp_ready;
7dc37de7 1652
e4e06934
JW		 1653 if (flag & NFC_SR_CMD_DONE)
1654 comp[index++] = &host->nfc->comp_cmd_done;
1655
1656 if (index == 0) {
1657 dev_err(host->dev, "Unkown interrupt flag: 0x%08x\n", flag);
1658 return -EINVAL;
1659 }
1660
1661 for (i = 0; i < index; i++) {
1662 if (wait_for_completion_timeout(comp[i],
1663 msecs_to_jiffies(NFC_TIME_OUT_MS)))
1664 continue; /* wait for next completion */
1665 else
1666 goto err_timeout;
1667 }
1668
1669 return 0;
1670
1671err_timeout:
7dc37de7 1672 dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag);
e4e06934
JW		 1673 /* Disable the interrupt as it is not handled by interrupt handler */
1674 nfc_writel(host->nfc->hsmc_regs, IDR, flag);
7dc37de7
JW		 1675 return -ETIMEDOUT;
1676}
1677
1678static int nfc_send_command(struct atmel_nand_host *host,
1679 unsigned int cmd, unsigned int addr, unsigned char cycle0)
1680{
1681 unsigned long timeout;
e4e06934
JW		 1682 u32 flag = NFC_SR_CMD_DONE;
1683 flag |= cmd & NFCADDR_CMD_DATAEN ? NFC_SR_XFR_DONE : 0;
1684
7dc37de7
JW		 1685 dev_dbg(host->dev,
1686 "nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
1687 cmd, addr, cycle0);
1688
1689 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1690 while (nfc_cmd_readl(NFCADDR_CMD_NFCBUSY, host->nfc->base_cmd_regs)
1691 & NFCADDR_CMD_NFCBUSY) {
1692 if (time_after(jiffies, timeout)) {
1693 dev_err(host->dev,
1694 "Time out to wait CMD_NFCBUSY ready!\n");
1695 return -ETIMEDOUT;
1696 }
1697 }
e4e06934
JW		 1698
1699 nfc_prepare_interrupt(host, flag);
7dc37de7
JW		 1700 nfc_writel(host->nfc->hsmc_regs, CYCLE0, cycle0);
1701 nfc_cmd_addr1234_writel(cmd, addr, host->nfc->base_cmd_regs);
e4e06934 1702 return nfc_wait_interrupt(host, flag);
7dc37de7
JW		 1703}
1704
1705static int nfc_device_ready(struct mtd_info *mtd)
1706{
72a78e3c 1707 u32 status, mask;
7dc37de7
JW		 1708 struct nand_chip *nand_chip = mtd->priv;
1709 struct atmel_nand_host *host = nand_chip->priv;
72a78e3c
WJ		 1710
1711 status = nfc_read_status(host);
1712 mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1713
1714 /* The mask should be 0. If not we may lost interrupts */
1715 if (unlikely(mask & status))
1716 dev_err(host->dev, "Lost the interrupt flags: 0x%08x\n",
1717 mask & status);
1718
1719 return status & NFC_SR_RB_EDGE;
7dc37de7
JW		 1720}
1721
1722static void nfc_select_chip(struct mtd_info *mtd, int chip)
1723{
1724 struct nand_chip *nand_chip = mtd->priv;
1725 struct atmel_nand_host *host = nand_chip->priv;
1726
1727 if (chip == -1)
1728 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_DISABLE);
1729 else
1730 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_ENABLE);
1731}
1732
3dad2344
BN		 1733static int nfc_make_addr(struct mtd_info *mtd, int command, int column,
1734 int page_addr, unsigned int *addr1234, unsigned int *cycle0)
7dc37de7
JW		 1735{
1736 struct nand_chip *chip = mtd->priv;
1737
1738 int acycle = 0;
1739 unsigned char addr_bytes[8];
1740 int index = 0, bit_shift;
1741
1742 BUG_ON(addr1234 == NULL || cycle0 == NULL);
1743
1744 *cycle0 = 0;
1745 *addr1234 = 0;
1746
1747 if (column != -1) {
3dad2344
BN		 1748 if (chip->options & NAND_BUSWIDTH_16 &&
1749 !nand_opcode_8bits(command))
7dc37de7
JW		 1750 column >>= 1;
1751 addr_bytes[acycle++] = column & 0xff;
1752 if (mtd->writesize > 512)
1753 addr_bytes[acycle++] = (column >> 8) & 0xff;
1754 }
1755
1756 if (page_addr != -1) {
1757 addr_bytes[acycle++] = page_addr & 0xff;
1758 addr_bytes[acycle++] = (page_addr >> 8) & 0xff;
1759 if (chip->chipsize > (128 << 20))
1760 addr_bytes[acycle++] = (page_addr >> 16) & 0xff;
1761 }
1762
1763 if (acycle > 4)
1764 *cycle0 = addr_bytes[index++];
1765
1766 for (bit_shift = 0; index < acycle; bit_shift += 8)
1767 *addr1234 += addr_bytes[index++] << bit_shift;
1768
1769 /* return acycle in cmd register */
1770 return acycle << NFCADDR_CMD_ACYCLE_BIT_POS;
1771}
1772
1773static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
1774 int column, int page_addr)
1775{
1776 struct nand_chip *chip = mtd->priv;
1777 struct atmel_nand_host *host = chip->priv;
1778 unsigned long timeout;
1779 unsigned int nfc_addr_cmd = 0;
1780
1781 unsigned int cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1782
1783 /* Set default settings: no cmd2, no addr cycle. read from nand */
1784 unsigned int cmd2 = 0;
1785 unsigned int vcmd2 = 0;
1786 int acycle = NFCADDR_CMD_ACYCLE_NONE;
1787 int csid = NFCADDR_CMD_CSID_3;
1788 int dataen = NFCADDR_CMD_DATADIS;
1789 int nfcwr = NFCADDR_CMD_NFCRD;
1790 unsigned int addr1234 = 0;
1791 unsigned int cycle0 = 0;
1792 bool do_addr = true;
1ae9c092 1793 host->nfc->data_in_sram = NULL;
7dc37de7
JW		 1794
1795 dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
1796 __func__, command, column, page_addr);
1797
1798 switch (command) {
1799 case NAND_CMD_RESET:
1800 nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr;
1801 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1802 udelay(chip->chip_delay);
1803
1804 nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
1805 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1806 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) {
1807 if (time_after(jiffies, timeout)) {
1808 dev_err(host->dev,
1809 "Time out to wait status ready!\n");
1810 break;
1811 }
1812 }
1813 return;
1814 case NAND_CMD_STATUS:
1815 do_addr = false;
1816 break;
1817 case NAND_CMD_PARAM:
1818 case NAND_CMD_READID:
1819 do_addr = false;
1820 acycle = NFCADDR_CMD_ACYCLE_1;
1821 if (column != -1)
1822 addr1234 = column;
1823 break;
1824 case NAND_CMD_RNDOUT:
1825 cmd2 = NAND_CMD_RNDOUTSTART << NFCADDR_CMD_CMD2_BIT_POS;
1826 vcmd2 = NFCADDR_CMD_VCMD2;
1827 break;
1828 case NAND_CMD_READ0:
1829 case NAND_CMD_READOOB:
1830 if (command == NAND_CMD_READOOB) {
1831 column += mtd->writesize;
1832 command = NAND_CMD_READ0; /* only READ0 is valid */
1833 cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1834 }
1ae9c092
JW		 1835 if (host->nfc->use_nfc_sram) {
1836 /* Enable Data transfer to sram */
1837 dataen = NFCADDR_CMD_DATAEN;
1838
1839 /* Need enable PMECC now, since NFC will transfer
1840 * data in bus after sending nfc read command.
1841 */
1842 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1843 pmecc_enable(host, NAND_ECC_READ);
1844 }
7dc37de7
JW		 1845
1846 cmd2 = NAND_CMD_READSTART << NFCADDR_CMD_CMD2_BIT_POS;
1847 vcmd2 = NFCADDR_CMD_VCMD2;
1848 break;
1849 /* For prgramming command, the cmd need set to write enable */
1850 case NAND_CMD_PAGEPROG:
1851 case NAND_CMD_SEQIN:
1852 case NAND_CMD_RNDIN:
1853 nfcwr = NFCADDR_CMD_NFCWR;
6054d4d5
JW		 1854 if (host->nfc->will_write_sram && command == NAND_CMD_SEQIN)
1855 dataen = NFCADDR_CMD_DATAEN;
7dc37de7
JW		 1856 break;
1857 default:
1858 break;
1859 }
1860
1861 if (do_addr)
3dad2344
BN		 1862 acycle = nfc_make_addr(mtd, command, column, page_addr,
1863 &addr1234, &cycle0);
7dc37de7
JW		 1864
1865 nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
1866 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1867
1868 /*
1869 * Program and erase have their own busy handlers status, sequential
1870 * in, and deplete1 need no delay.
1871 */
1872 switch (command) {
1873 case NAND_CMD_CACHEDPROG:
1874 case NAND_CMD_PAGEPROG:
1875 case NAND_CMD_ERASE1:
1876 case NAND_CMD_ERASE2:
1877 case NAND_CMD_RNDIN:
1878 case NAND_CMD_STATUS:
1879 case NAND_CMD_RNDOUT:
1880 case NAND_CMD_SEQIN:
1881 case NAND_CMD_READID:
1882 return;
1883
1884 case NAND_CMD_READ0:
1ae9c092
JW		 1885 if (dataen == NFCADDR_CMD_DATAEN) {
1886 host->nfc->data_in_sram = host->nfc->sram_bank0 +
1887 nfc_get_sram_off(host);
1888 return;
1889 }
7dc37de7
JW		 1890 /* fall through */
1891 default:
e4e06934 1892 nfc_prepare_interrupt(host, NFC_SR_RB_EDGE);
7dc37de7
JW		 1893 nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
1894 }
1895}
1896
6054d4d5
JW		 1897static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1898 uint32_t offset, int data_len, const uint8_t *buf,
1899 int oob_required, int page, int cached, int raw)
1900{
1901 int cfg, len;
1902 int status = 0;
1903 struct atmel_nand_host *host = chip->priv;
1904 void __iomem *sram = host->nfc->sram_bank0 + nfc_get_sram_off(host);
1905
1906 /* Subpage write is not supported */
1907 if (offset || (data_len < mtd->writesize))
1908 return -EINVAL;
1909
1910 cfg = nfc_readl(host->nfc->hsmc_regs, CFG);
1911 len = mtd->writesize;
1912
1913 if (unlikely(raw)) {
1914 len += mtd->oobsize;
1915 nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE);
1916 } else
1917 nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE);
1918
1919 /* Copy page data to sram that will write to nand via NFC */
1920 if (use_dma) {
1921 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0)
1922 /* Fall back to use cpu copy */
1923 memcpy32_toio(sram, buf, len);
1924 } else {
1925 memcpy32_toio(sram, buf, len);
1926 }
1927
1928 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1929 /*
1930 * When use NFC sram, need set up PMECC before send
1931 * NAND_CMD_SEQIN command. Since when the nand command
1932 * is sent, nfc will do transfer from sram and nand.
1933 */
1934 pmecc_enable(host, NAND_ECC_WRITE);
1935
1936 host->nfc->will_write_sram = true;
1937 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1938 host->nfc->will_write_sram = false;
1939
1940 if (likely(!raw))
1941 /* Need to write ecc into oob */
1942 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
1943
1944 if (status < 0)
1945 return status;
1946
1947 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1948 status = chip->waitfunc(mtd, chip);
1949
1950 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1951 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
1952
1953 if (status & NAND_STATUS_FAIL)
1954 return -EIO;
1955
1956 return 0;
1957}
1958
1ae9c092
JW		 1959static int nfc_sram_init(struct mtd_info *mtd)
1960{
1961 struct nand_chip *chip = mtd->priv;
1962 struct atmel_nand_host *host = chip->priv;
1963 int res = 0;
1964
1965 /* Initialize the NFC CFG register */
1966 unsigned int cfg_nfc = 0;
1967
1968 /* set page size and oob layout */
1969 switch (mtd->writesize) {
1970 case 512:
1971 cfg_nfc = NFC_CFG_PAGESIZE_512;
1972 break;
1973 case 1024:
1974 cfg_nfc = NFC_CFG_PAGESIZE_1024;
1975 break;
1976 case 2048:
1977 cfg_nfc = NFC_CFG_PAGESIZE_2048;
1978 break;
1979 case 4096:
1980 cfg_nfc = NFC_CFG_PAGESIZE_4096;
1981 break;
1982 case 8192:
1983 cfg_nfc = NFC_CFG_PAGESIZE_8192;
1984 break;
1985 default:
1986 dev_err(host->dev, "Unsupported page size for NFC.\n");
1987 res = -ENXIO;
1988 return res;
1989 }
1990
1991 /* oob bytes size = (NFCSPARESIZE + 1) * 4
1992 * Max support spare size is 512 bytes. */
1993 cfg_nfc |= (((mtd->oobsize / 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS
1994 & NFC_CFG_NFC_SPARESIZE);
1995 /* default set a max timeout */
1996 cfg_nfc |= NFC_CFG_RSPARE |
1997 NFC_CFG_NFC_DTOCYC | NFC_CFG_NFC_DTOMUL;
1998
1999 nfc_writel(host->nfc->hsmc_regs, CFG, cfg_nfc);
2000
6054d4d5 2001 host->nfc->will_write_sram = false;
1ae9c092
JW		 2002 nfc_set_sram_bank(host, 0);
2003
6054d4d5
JW		 2004 /* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
2005 if (host->nfc->write_by_sram) {
2006 if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) ||
2007 chip->ecc.mode == NAND_ECC_NONE)
2008 chip->write_page = nfc_sram_write_page;
2009 else
2010 host->nfc->write_by_sram = false;
2011 }
1ae9c092 2012
6054d4d5
JW		 2013 dev_info(host->dev, "Using NFC Sram read %s\n",
2014 host->nfc->write_by_sram ? "and write" : "");
1ae9c092
JW		 2015 return 0;
2016}
2017
7dc37de7 2018static struct platform_driver atmel_nand_nfc_driver;
42cb1403
AV		 2019/*
2020 * Probe for the NAND device.
2021 */
2c2b9285 2022static int atmel_nand_probe(struct platform_device *pdev)
42cb1403 2023{
3c3796cc 2024 struct atmel_nand_host *host;
42cb1403
AV		 2025 struct mtd_info *mtd;
2026 struct nand_chip *nand_chip;
77f5492c 2027 struct resource *mem;
d6a01661 2028 struct mtd_part_parser_data ppdata = {};
7dc37de7 2029 int res, irq;
42cb1403
AV		 2030
2031 /* Allocate memory for the device structure (and zero it) */
0d63748d 2032 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
9e3677a8 2033 if (!host)
42cb1403 2034 return -ENOMEM;
42cb1403 2035
7dc37de7
JW		 2036 res = platform_driver_register(&atmel_nand_nfc_driver);
2037 if (res)
2038 dev_err(&pdev->dev, "atmel_nand: can't register NFC driver\n");
2039
0d63748d
JCPV		 2040 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2041 host->io_base = devm_ioremap_resource(&pdev->dev, mem);
2042 if (IS_ERR(host->io_base)) {
0d63748d 2043 res = PTR_ERR(host->io_base);
cc0c72e1 2044 goto err_nand_ioremap;
42cb1403 2045 }
0d63748d 2046 host->io_phys = (dma_addr_t)mem->start;
42cb1403
AV		 2047
2048 mtd = &host->mtd;
2049 nand_chip = &host->nand_chip;
77f5492c 2050 host->dev = &pdev->dev;
e9d8da80
JW		 2051 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
2052 /* Only when CONFIG_OF is enabled of_node can be parsed */
d6a01661
JCPV		 2053 res = atmel_of_init_port(host, pdev->dev.of_node);
2054 if (res)
0d63748d 2055 goto err_nand_ioremap;
d6a01661 2056 } else {
453810b7 2057 memcpy(&host->board, dev_get_platdata(&pdev->dev),
d6a01661
JCPV		 2058 sizeof(struct atmel_nand_data));
2059 }
42cb1403
AV		 2060
2061 nand_chip->priv = host; /* link the private data structures */
2062 mtd->priv = nand_chip;
2063 mtd->owner = THIS_MODULE;
2064
2065 /* Set address of NAND IO lines */
2066 nand_chip->IO_ADDR_R = host->io_base;
2067 nand_chip->IO_ADDR_W = host->io_base;
28446acb 2068
7dc37de7
JW		 2069 if (nand_nfc.is_initialized) {
2070 /* NFC driver is probed and initialized */
2071 host->nfc = &nand_nfc;
28446acb 2072
7dc37de7
JW		 2073 nand_chip->select_chip = nfc_select_chip;
2074 nand_chip->dev_ready = nfc_device_ready;
2075 nand_chip->cmdfunc = nfc_nand_command;
28446acb 2076
7dc37de7
JW		 2077 /* Initialize the interrupt for NFC */
2078 irq = platform_get_irq(pdev, 0);
2079 if (irq < 0) {
2080 dev_err(host->dev, "Cannot get HSMC irq!\n");
ff52c67a 2081 res = irq;
0d63748d 2082 goto err_nand_ioremap;
28446acb
JCPV		 2083 }
2084
7dc37de7
JW		 2085 res = devm_request_irq(&pdev->dev, irq, hsmc_interrupt,
2086 0, "hsmc", host);
2087 if (res) {
2088 dev_err(&pdev->dev, "Unable to request HSMC irq %d\n",
2089 irq);
0d63748d 2090 goto err_nand_ioremap;
28446acb 2091 }
7dc37de7
JW		 2092 } else {
2093 res = atmel_nand_set_enable_ready_pins(mtd);
2094 if (res)
2095 goto err_nand_ioremap;
2096
2097 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
28446acb 2098 }
a4265f8d 2099
d6a01661 2100 nand_chip->ecc.mode = host->board.ecc_mode;
796fe364 2101 nand_chip->chip_delay = 40; /* 40us command delay time */
42cb1403 2102
d6a01661 2103 if (host->board.bus_width_16) /* 16-bit bus width */
dd11b8cd 2104 nand_chip->options |= NAND_BUSWIDTH_16;
cbc6c5e7
HX		 2105
2106 nand_chip->read_buf = atmel_read_buf;
2107 nand_chip->write_buf = atmel_write_buf;
dd11b8cd 2108
42cb1403 2109 platform_set_drvdata(pdev, host);
3c3796cc 2110 atmel_nand_enable(host);
42cb1403 2111
d6a01661 2112 if (gpio_is_valid(host->board.det_pin)) {
0d63748d
JCPV		 2113 res = devm_gpio_request(&pdev->dev,
2114 host->board.det_pin, "nand_det");
28446acb
JCPV		 2115 if (res < 0) {
2116 dev_err(&pdev->dev,
2117 "can't request det gpio %d\n",
2118 host->board.det_pin);
2119 goto err_no_card;
2120 }
2121
2122 res = gpio_direction_input(host->board.det_pin);
2123 if (res < 0) {
2124 dev_err(&pdev->dev,
2125 "can't request input direction det gpio %d\n",
2126 host->board.det_pin);
2127 goto err_no_card;
2128 }
2129
d6a01661 2130 if (gpio_get_value(host->board.det_pin)) {
1295f970 2131 dev_info(&pdev->dev, "No SmartMedia card inserted.\n");
895fb494 2132 res = -ENXIO;
cc0c72e1 2133 goto err_no_card;
42cb1403
AV		 2134 }
2135 }
2136
d6a01661 2137 if (host->board.on_flash_bbt || on_flash_bbt) {
1295f970 2138 dev_info(&pdev->dev, "Use On Flash BBT\n");
bb9ebd4e 2139 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
f4fa697c
SP		 2140 }
2141
1b719265 2142 if (!host->board.has_dma)
cb457a4d
HX		 2143 use_dma = 0;
2144
2145 if (use_dma) {
cbc6c5e7
HX		 2146 dma_cap_mask_t mask;
2147
2148 dma_cap_zero(mask);
2149 dma_cap_set(DMA_MEMCPY, mask);
201ab536 2150 host->dma_chan = dma_request_channel(mask, NULL, NULL);
cbc6c5e7
HX		 2151 if (!host->dma_chan) {
2152 dev_err(host->dev, "Failed to request DMA channel\n");
2153 use_dma = 0;
2154 }
2155 }
2156 if (use_dma)
042bc9c0
NF		 2157 dev_info(host->dev, "Using %s for DMA transfers.\n",
2158 dma_chan_name(host->dma_chan));
cbc6c5e7
HX		 2159 else
2160 dev_info(host->dev, "No DMA support for NAND access.\n");
2161
77f5492c 2162 /* first scan to find the device and get the page size */
5e81e88a 2163 if (nand_scan_ident(mtd, 1, NULL)) {
77f5492c 2164 res = -ENXIO;
cc0c72e1 2165 goto err_scan_ident;
77f5492c
RG		 2166 }
2167
3fc23898 2168 if (nand_chip->ecc.mode == NAND_ECC_HW) {
1c7b874d
JW		 2169 if (host->has_pmecc)
2170 res = atmel_pmecc_nand_init_params(pdev, host);
2171 else
2172 res = atmel_hw_nand_init_params(pdev, host);
2173
3dfe41a4
JW		 2174 if (res != 0)
2175 goto err_hw_ecc;
77f5492c
RG		 2176 }
2177
1ae9c092
JW		 2178 /* initialize the nfc configuration register */
2179 if (host->nfc && host->nfc->use_nfc_sram) {
2180 res = nfc_sram_init(mtd);
2181 if (res) {
2182 host->nfc->use_nfc_sram = false;
2183 dev_err(host->dev, "Disable use nfc sram for data transfer.\n");
2184 }
2185 }
2186
77f5492c
RG		 2187 /* second phase scan */
2188 if (nand_scan_tail(mtd)) {
42cb1403 2189 res = -ENXIO;
cc0c72e1 2190 goto err_scan_tail;
42cb1403
AV		 2191 }
2192
3c3796cc 2193 mtd->name = "atmel_nand";
d6a01661
JCPV		 2194 ppdata.of_node = pdev->dev.of_node;
2195 res = mtd_device_parse_register(mtd, NULL, &ppdata,
2196 host->board.parts, host->board.num_parts);
42cb1403
AV		 2197 if (!res)
2198 return res;
2199
cc0c72e1 2200err_scan_tail:
0d63748d 2201 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW)
1c7b874d 2202 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
3dfe41a4 2203err_hw_ecc:
cc0c72e1
HS		 2204err_scan_ident:
2205err_no_card:
3c3796cc 2206 atmel_nand_disable(host);
cbc6c5e7
HX		 2207 if (host->dma_chan)
2208 dma_release_channel(host->dma_chan);
cc0c72e1 2209err_nand_ioremap:
42cb1403
AV		 2210 return res;
2211}
2212
2213/*
2214 * Remove a NAND device.
2215 */
2c2b9285 2216static int atmel_nand_remove(struct platform_device *pdev)
42cb1403 2217{
3c3796cc 2218 struct atmel_nand_host *host = platform_get_drvdata(pdev);
42cb1403
AV		 2219 struct mtd_info *mtd = &host->mtd;
2220
2221 nand_release(mtd);
2222
3c3796cc 2223 atmel_nand_disable(host);
42cb1403 2224
1c7b874d
JW		 2225 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
2226 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2227 pmerrloc_writel(host->pmerrloc_base, ELDIS,
2228 PMERRLOC_DISABLE);
1c7b874d
JW		 2229 }
2230
cbc6c5e7
HX		 2231 if (host->dma_chan)
2232 dma_release_channel(host->dma_chan);
2233
7dc37de7
JW		 2234 platform_driver_unregister(&atmel_nand_nfc_driver);
2235
42cb1403
AV		 2236 return 0;
2237}
2238
d6a01661
JCPV		 2239static const struct of_device_id atmel_nand_dt_ids[] = {
2240 { .compatible = "atmel,at91rm9200-nand" },
2241 { /* sentinel */ }
2242};
2243
2244MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
d6a01661 2245
7dc37de7
JW		 2246static int atmel_nand_nfc_probe(struct platform_device *pdev)
2247{
2248 struct atmel_nfc *nfc = &nand_nfc;
2249 struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
2250
2251 nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2252 nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs);
2253 if (IS_ERR(nfc->base_cmd_regs))
2254 return PTR_ERR(nfc->base_cmd_regs);
2255
2256 nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2257 nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs);
2258 if (IS_ERR(nfc->hsmc_regs))
2259 return PTR_ERR(nfc->hsmc_regs);
2260
2261 nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 2);
2262 if (nfc_sram) {
2263 nfc->sram_bank0 = devm_ioremap_resource(&pdev->dev, nfc_sram);
1ae9c092 2264 if (IS_ERR(nfc->sram_bank0)) {
7dc37de7
JW		 2265 dev_warn(&pdev->dev, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n",
2266 PTR_ERR(nfc->sram_bank0));
1ae9c092
JW		 2267 } else {
2268 nfc->use_nfc_sram = true;
7dc37de7 2269 nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start;
6054d4d5
JW		 2270
2271 if (pdev->dev.of_node)
2272 nfc->write_by_sram = of_property_read_bool(
2273 pdev->dev.of_node,
2274 "atmel,write-by-sram");
1ae9c092 2275 }
7dc37de7
JW		 2276 }
2277
50e04e2f
WJ		 2278 nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
2279 nfc_readl(nfc->hsmc_regs, SR); /* clear the NFC_SR */
2280
7dc37de7
JW		 2281 nfc->is_initialized = true;
2282 dev_info(&pdev->dev, "NFC is probed.\n");
2283 return 0;
2284}
2285
81f29b47 2286static const struct of_device_id atmel_nand_nfc_match[] = {
7dc37de7
JW		 2287 { .compatible = "atmel,sama5d3-nfc" },
2288 { /* sentinel */ }
2289};
81f29b47 2290MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
7dc37de7
JW		 2291
2292static struct platform_driver atmel_nand_nfc_driver = {
2293 .driver = {
2294 .name = "atmel_nand_nfc",
2295 .owner = THIS_MODULE,
2296 .of_match_table = of_match_ptr(atmel_nand_nfc_match),
2297 },
2298 .probe = atmel_nand_nfc_probe,
2299};
2300
3c3796cc 2301static struct platform_driver atmel_nand_driver = {
2c2b9285
JH		 2302 .probe = atmel_nand_probe,
2303 .remove = atmel_nand_remove,
42cb1403 2304 .driver = {
3c3796cc 2305 .name = "atmel_nand",
42cb1403 2306 .owner = THIS_MODULE,
d6a01661 2307 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
42cb1403
AV		 2308 },
2309};
2310
2c2b9285 2311module_platform_driver(atmel_nand_driver);
42cb1403
AV		 2312
2313MODULE_LICENSE("GPL");
2314MODULE_AUTHOR("Rick Bronson");
d4f4c0aa 2315MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
3c3796cc 2316MODULE_ALIAS("platform:atmel_nand");
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