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Commit | Line | Data |
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42cb1403 | 1 | /* |
42cb1403 AV |
2 | * Copyright (C) 2003 Rick Bronson |
3 | * | |
4 | * Derived from drivers/mtd/nand/autcpu12.c | |
5 | * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de) | |
6 | * | |
7 | * Derived from drivers/mtd/spia.c | |
8 | * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com) | |
9 | * | |
77f5492c RG |
10 | * |
11 | * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263 | |
12 | * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007 | |
13 | * | |
14 | * Derived from Das U-Boot source code | |
15 | * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c) | |
16 | * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas | |
17 | * | |
18 | * | |
42cb1403 AV |
19 | * This program is free software; you can redistribute it and/or modify |
20 | * it under the terms of the GNU General Public License version 2 as | |
21 | * published by the Free Software Foundation. | |
22 | * | |
23 | */ | |
24 | ||
b7f080cf | 25 | #include <linux/dma-mapping.h> |
42cb1403 AV |
26 | #include <linux/slab.h> |
27 | #include <linux/module.h> | |
f4fa697c | 28 | #include <linux/moduleparam.h> |
42cb1403 AV |
29 | #include <linux/platform_device.h> |
30 | #include <linux/mtd/mtd.h> | |
31 | #include <linux/mtd/nand.h> | |
32 | #include <linux/mtd/partitions.h> | |
33 | ||
5c39c4c5 | 34 | #include <linux/dmaengine.h> |
90574d0a DW |
35 | #include <linux/gpio.h> |
36 | #include <linux/io.h> | |
bf4289cb | 37 | #include <linux/platform_data/atmel.h> |
42cb1403 | 38 | |
a09e64fb | 39 | #include <mach/cpu.h> |
42cb1403 | 40 | |
cbc6c5e7 HX |
41 | static int use_dma = 1; |
42 | module_param(use_dma, int, 0); | |
43 | ||
f4fa697c SP |
44 | static int on_flash_bbt = 0; |
45 | module_param(on_flash_bbt, int, 0); | |
46 | ||
77f5492c RG |
47 | /* Register access macros */ |
48 | #define ecc_readl(add, reg) \ | |
3c3796cc | 49 | __raw_readl(add + ATMEL_ECC_##reg) |
77f5492c | 50 | #define ecc_writel(add, reg, value) \ |
3c3796cc | 51 | __raw_writel((value), add + ATMEL_ECC_##reg) |
77f5492c | 52 | |
d4f4c0aa | 53 | #include "atmel_nand_ecc.h" /* Hardware ECC registers */ |
77f5492c RG |
54 | |
55 | /* oob layout for large page size | |
56 | * bad block info is on bytes 0 and 1 | |
57 | * the bytes have to be consecutives to avoid | |
58 | * several NAND_CMD_RNDOUT during read | |
59 | */ | |
3c3796cc | 60 | static struct nand_ecclayout atmel_oobinfo_large = { |
77f5492c RG |
61 | .eccbytes = 4, |
62 | .eccpos = {60, 61, 62, 63}, | |
63 | .oobfree = { | |
64 | {2, 58} | |
65 | }, | |
66 | }; | |
67 | ||
68 | /* oob layout for small page size | |
69 | * bad block info is on bytes 4 and 5 | |
70 | * the bytes have to be consecutives to avoid | |
71 | * several NAND_CMD_RNDOUT during read | |
72 | */ | |
3c3796cc | 73 | static struct nand_ecclayout atmel_oobinfo_small = { |
77f5492c RG |
74 | .eccbytes = 4, |
75 | .eccpos = {0, 1, 2, 3}, | |
76 | .oobfree = { | |
77 | {6, 10} | |
78 | }, | |
79 | }; | |
80 | ||
3c3796cc | 81 | struct atmel_nand_host { |
42cb1403 AV |
82 | struct nand_chip nand_chip; |
83 | struct mtd_info mtd; | |
84 | void __iomem *io_base; | |
cbc6c5e7 | 85 | dma_addr_t io_phys; |
3c3796cc | 86 | struct atmel_nand_data *board; |
77f5492c RG |
87 | struct device *dev; |
88 | void __iomem *ecc; | |
cbc6c5e7 HX |
89 | |
90 | struct completion comp; | |
91 | struct dma_chan *dma_chan; | |
42cb1403 AV |
92 | }; |
93 | ||
cbc6c5e7 HX |
94 | static int cpu_has_dma(void) |
95 | { | |
96 | return cpu_is_at91sam9rl() || cpu_is_at91sam9g45(); | |
97 | } | |
98 | ||
8136508c AN |
99 | /* |
100 | * Enable NAND. | |
101 | */ | |
3c3796cc | 102 | static void atmel_nand_enable(struct atmel_nand_host *host) |
8136508c | 103 | { |
1d6dc068 | 104 | if (gpio_is_valid(host->board->enable_pin)) |
62fd71fe | 105 | gpio_set_value(host->board->enable_pin, 0); |
8136508c AN |
106 | } |
107 | ||
108 | /* | |
109 | * Disable NAND. | |
110 | */ | |
3c3796cc | 111 | static void atmel_nand_disable(struct atmel_nand_host *host) |
8136508c | 112 | { |
1d6dc068 | 113 | if (gpio_is_valid(host->board->enable_pin)) |
62fd71fe | 114 | gpio_set_value(host->board->enable_pin, 1); |
8136508c AN |
115 | } |
116 | ||
42cb1403 AV |
117 | /* |
118 | * Hardware specific access to control-lines | |
119 | */ | |
3c3796cc | 120 | static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
42cb1403 AV |
121 | { |
122 | struct nand_chip *nand_chip = mtd->priv; | |
3c3796cc | 123 | struct atmel_nand_host *host = nand_chip->priv; |
42cb1403 | 124 | |
8136508c | 125 | if (ctrl & NAND_CTRL_CHANGE) { |
2314488e | 126 | if (ctrl & NAND_NCE) |
3c3796cc | 127 | atmel_nand_enable(host); |
2314488e | 128 | else |
3c3796cc | 129 | atmel_nand_disable(host); |
2314488e | 130 | } |
42cb1403 AV |
131 | if (cmd == NAND_CMD_NONE) |
132 | return; | |
133 | ||
134 | if (ctrl & NAND_CLE) | |
135 | writeb(cmd, host->io_base + (1 << host->board->cle)); | |
136 | else | |
137 | writeb(cmd, host->io_base + (1 << host->board->ale)); | |
138 | } | |
139 | ||
140 | /* | |
141 | * Read the Device Ready pin. | |
142 | */ | |
3c3796cc | 143 | static int atmel_nand_device_ready(struct mtd_info *mtd) |
42cb1403 AV |
144 | { |
145 | struct nand_chip *nand_chip = mtd->priv; | |
3c3796cc | 146 | struct atmel_nand_host *host = nand_chip->priv; |
42cb1403 | 147 | |
744f6592 GC |
148 | return gpio_get_value(host->board->rdy_pin) ^ |
149 | !!host->board->rdy_pin_active_low; | |
42cb1403 AV |
150 | } |
151 | ||
50082319 AB |
152 | /* |
153 | * Minimal-overhead PIO for data access. | |
154 | */ | |
155 | static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len) | |
156 | { | |
157 | struct nand_chip *nand_chip = mtd->priv; | |
158 | ||
159 | __raw_readsb(nand_chip->IO_ADDR_R, buf, len); | |
160 | } | |
161 | ||
162 | static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len) | |
163 | { | |
164 | struct nand_chip *nand_chip = mtd->priv; | |
165 | ||
166 | __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2); | |
167 | } | |
168 | ||
169 | static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len) | |
170 | { | |
171 | struct nand_chip *nand_chip = mtd->priv; | |
172 | ||
173 | __raw_writesb(nand_chip->IO_ADDR_W, buf, len); | |
174 | } | |
175 | ||
176 | static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len) | |
177 | { | |
178 | struct nand_chip *nand_chip = mtd->priv; | |
179 | ||
180 | __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2); | |
181 | } | |
182 | ||
cbc6c5e7 HX |
183 | static void dma_complete_func(void *completion) |
184 | { | |
185 | complete(completion); | |
186 | } | |
187 | ||
188 | static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len, | |
189 | int is_read) | |
190 | { | |
191 | struct dma_device *dma_dev; | |
192 | enum dma_ctrl_flags flags; | |
193 | dma_addr_t dma_src_addr, dma_dst_addr, phys_addr; | |
194 | struct dma_async_tx_descriptor *tx = NULL; | |
195 | dma_cookie_t cookie; | |
196 | struct nand_chip *chip = mtd->priv; | |
197 | struct atmel_nand_host *host = chip->priv; | |
198 | void *p = buf; | |
199 | int err = -EIO; | |
200 | enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | |
201 | ||
80b4f81a HX |
202 | if (buf >= high_memory) |
203 | goto err_buf; | |
cbc6c5e7 HX |
204 | |
205 | dma_dev = host->dma_chan->device; | |
206 | ||
207 | flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_SRC_UNMAP | | |
208 | DMA_COMPL_SKIP_DEST_UNMAP; | |
209 | ||
210 | phys_addr = dma_map_single(dma_dev->dev, p, len, dir); | |
211 | if (dma_mapping_error(dma_dev->dev, phys_addr)) { | |
212 | dev_err(host->dev, "Failed to dma_map_single\n"); | |
213 | goto err_buf; | |
214 | } | |
215 | ||
216 | if (is_read) { | |
217 | dma_src_addr = host->io_phys; | |
218 | dma_dst_addr = phys_addr; | |
219 | } else { | |
220 | dma_src_addr = phys_addr; | |
221 | dma_dst_addr = host->io_phys; | |
222 | } | |
223 | ||
224 | tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr, | |
225 | dma_src_addr, len, flags); | |
226 | if (!tx) { | |
227 | dev_err(host->dev, "Failed to prepare DMA memcpy\n"); | |
228 | goto err_dma; | |
229 | } | |
230 | ||
231 | init_completion(&host->comp); | |
232 | tx->callback = dma_complete_func; | |
233 | tx->callback_param = &host->comp; | |
234 | ||
235 | cookie = tx->tx_submit(tx); | |
236 | if (dma_submit_error(cookie)) { | |
237 | dev_err(host->dev, "Failed to do DMA tx_submit\n"); | |
238 | goto err_dma; | |
239 | } | |
240 | ||
241 | dma_async_issue_pending(host->dma_chan); | |
242 | wait_for_completion(&host->comp); | |
243 | ||
244 | err = 0; | |
245 | ||
246 | err_dma: | |
247 | dma_unmap_single(dma_dev->dev, phys_addr, len, dir); | |
248 | err_buf: | |
249 | if (err != 0) | |
250 | dev_warn(host->dev, "Fall back to CPU I/O\n"); | |
251 | return err; | |
252 | } | |
253 | ||
254 | static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len) | |
255 | { | |
256 | struct nand_chip *chip = mtd->priv; | |
50082319 | 257 | struct atmel_nand_host *host = chip->priv; |
cbc6c5e7 | 258 | |
9d51567e NF |
259 | if (use_dma && len > mtd->oobsize) |
260 | /* only use DMA for bigger than oob size: better performances */ | |
cbc6c5e7 HX |
261 | if (atmel_nand_dma_op(mtd, buf, len, 1) == 0) |
262 | return; | |
263 | ||
50082319 AB |
264 | if (host->board->bus_width_16) |
265 | atmel_read_buf16(mtd, buf, len); | |
266 | else | |
267 | atmel_read_buf8(mtd, buf, len); | |
cbc6c5e7 HX |
268 | } |
269 | ||
270 | static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len) | |
271 | { | |
272 | struct nand_chip *chip = mtd->priv; | |
50082319 | 273 | struct atmel_nand_host *host = chip->priv; |
cbc6c5e7 | 274 | |
9d51567e NF |
275 | if (use_dma && len > mtd->oobsize) |
276 | /* only use DMA for bigger than oob size: better performances */ | |
cbc6c5e7 HX |
277 | if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0) |
278 | return; | |
279 | ||
50082319 AB |
280 | if (host->board->bus_width_16) |
281 | atmel_write_buf16(mtd, buf, len); | |
282 | else | |
283 | atmel_write_buf8(mtd, buf, len); | |
cbc6c5e7 HX |
284 | } |
285 | ||
77f5492c RG |
286 | /* |
287 | * Calculate HW ECC | |
288 | * | |
289 | * function called after a write | |
290 | * | |
291 | * mtd: MTD block structure | |
292 | * dat: raw data (unused) | |
293 | * ecc_code: buffer for ECC | |
294 | */ | |
3c3796cc | 295 | static int atmel_nand_calculate(struct mtd_info *mtd, |
77f5492c RG |
296 | const u_char *dat, unsigned char *ecc_code) |
297 | { | |
298 | struct nand_chip *nand_chip = mtd->priv; | |
3c3796cc | 299 | struct atmel_nand_host *host = nand_chip->priv; |
77f5492c RG |
300 | unsigned int ecc_value; |
301 | ||
302 | /* get the first 2 ECC bytes */ | |
d43fa149 | 303 | ecc_value = ecc_readl(host->ecc, PR); |
77f5492c | 304 | |
3fc23898 RG |
305 | ecc_code[0] = ecc_value & 0xFF; |
306 | ecc_code[1] = (ecc_value >> 8) & 0xFF; | |
77f5492c RG |
307 | |
308 | /* get the last 2 ECC bytes */ | |
3c3796cc | 309 | ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY; |
77f5492c | 310 | |
3fc23898 RG |
311 | ecc_code[2] = ecc_value & 0xFF; |
312 | ecc_code[3] = (ecc_value >> 8) & 0xFF; | |
77f5492c RG |
313 | |
314 | return 0; | |
315 | } | |
316 | ||
317 | /* | |
318 | * HW ECC read page function | |
319 | * | |
320 | * mtd: mtd info structure | |
321 | * chip: nand chip info structure | |
322 | * buf: buffer to store read data | |
323 | */ | |
3c3796cc | 324 | static int atmel_nand_read_page(struct mtd_info *mtd, |
46a8cf2d | 325 | struct nand_chip *chip, uint8_t *buf, int page) |
77f5492c RG |
326 | { |
327 | int eccsize = chip->ecc.size; | |
328 | int eccbytes = chip->ecc.bytes; | |
329 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
330 | uint8_t *p = buf; | |
331 | uint8_t *oob = chip->oob_poi; | |
332 | uint8_t *ecc_pos; | |
333 | int stat; | |
334 | ||
d6248fdd HS |
335 | /* |
336 | * Errata: ALE is incorrectly wired up to the ECC controller | |
337 | * on the AP7000, so it will include the address cycles in the | |
338 | * ECC calculation. | |
339 | * | |
340 | * Workaround: Reset the parity registers before reading the | |
341 | * actual data. | |
342 | */ | |
343 | if (cpu_is_at32ap7000()) { | |
344 | struct atmel_nand_host *host = chip->priv; | |
345 | ecc_writel(host->ecc, CR, ATMEL_ECC_RST); | |
346 | } | |
347 | ||
77f5492c RG |
348 | /* read the page */ |
349 | chip->read_buf(mtd, p, eccsize); | |
350 | ||
351 | /* move to ECC position if needed */ | |
352 | if (eccpos[0] != 0) { | |
353 | /* This only works on large pages | |
354 | * because the ECC controller waits for | |
355 | * NAND_CMD_RNDOUTSTART after the | |
356 | * NAND_CMD_RNDOUT. | |
357 | * anyway, for small pages, the eccpos[0] == 0 | |
358 | */ | |
359 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, | |
360 | mtd->writesize + eccpos[0], -1); | |
361 | } | |
362 | ||
363 | /* the ECC controller needs to read the ECC just after the data */ | |
364 | ecc_pos = oob + eccpos[0]; | |
365 | chip->read_buf(mtd, ecc_pos, eccbytes); | |
366 | ||
367 | /* check if there's an error */ | |
368 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
369 | ||
370 | if (stat < 0) | |
371 | mtd->ecc_stats.failed++; | |
372 | else | |
373 | mtd->ecc_stats.corrected += stat; | |
374 | ||
375 | /* get back to oob start (end of page) */ | |
376 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
377 | ||
378 | /* read the oob */ | |
379 | chip->read_buf(mtd, oob, mtd->oobsize); | |
380 | ||
381 | return 0; | |
382 | } | |
383 | ||
384 | /* | |
385 | * HW ECC Correction | |
386 | * | |
387 | * function called after a read | |
388 | * | |
389 | * mtd: MTD block structure | |
390 | * dat: raw data read from the chip | |
391 | * read_ecc: ECC from the chip (unused) | |
392 | * isnull: unused | |
393 | * | |
394 | * Detect and correct a 1 bit error for a page | |
395 | */ | |
3c3796cc | 396 | static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat, |
77f5492c RG |
397 | u_char *read_ecc, u_char *isnull) |
398 | { | |
399 | struct nand_chip *nand_chip = mtd->priv; | |
3c3796cc | 400 | struct atmel_nand_host *host = nand_chip->priv; |
77f5492c RG |
401 | unsigned int ecc_status; |
402 | unsigned int ecc_word, ecc_bit; | |
403 | ||
404 | /* get the status from the Status Register */ | |
405 | ecc_status = ecc_readl(host->ecc, SR); | |
406 | ||
407 | /* if there's no error */ | |
3c3796cc | 408 | if (likely(!(ecc_status & ATMEL_ECC_RECERR))) |
77f5492c RG |
409 | return 0; |
410 | ||
411 | /* get error bit offset (4 bits) */ | |
3c3796cc | 412 | ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR; |
77f5492c | 413 | /* get word address (12 bits) */ |
3c3796cc | 414 | ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR; |
77f5492c RG |
415 | ecc_word >>= 4; |
416 | ||
417 | /* if there are multiple errors */ | |
3c3796cc | 418 | if (ecc_status & ATMEL_ECC_MULERR) { |
77f5492c RG |
419 | /* check if it is a freshly erased block |
420 | * (filled with 0xff) */ | |
3c3796cc HS |
421 | if ((ecc_bit == ATMEL_ECC_BITADDR) |
422 | && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) { | |
77f5492c RG |
423 | /* the block has just been erased, return OK */ |
424 | return 0; | |
425 | } | |
426 | /* it doesn't seems to be a freshly | |
427 | * erased block. | |
428 | * We can't correct so many errors */ | |
3c3796cc | 429 | dev_dbg(host->dev, "atmel_nand : multiple errors detected." |
77f5492c RG |
430 | " Unable to correct.\n"); |
431 | return -EIO; | |
432 | } | |
433 | ||
434 | /* if there's a single bit error : we can correct it */ | |
3c3796cc | 435 | if (ecc_status & ATMEL_ECC_ECCERR) { |
77f5492c RG |
436 | /* there's nothing much to do here. |
437 | * the bit error is on the ECC itself. | |
438 | */ | |
3c3796cc | 439 | dev_dbg(host->dev, "atmel_nand : one bit error on ECC code." |
77f5492c RG |
440 | " Nothing to correct\n"); |
441 | return 0; | |
442 | } | |
443 | ||
3c3796cc | 444 | dev_dbg(host->dev, "atmel_nand : one bit error on data." |
77f5492c RG |
445 | " (word offset in the page :" |
446 | " 0x%x bit offset : 0x%x)\n", | |
447 | ecc_word, ecc_bit); | |
448 | /* correct the error */ | |
449 | if (nand_chip->options & NAND_BUSWIDTH_16) { | |
450 | /* 16 bits words */ | |
451 | ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit); | |
452 | } else { | |
453 | /* 8 bits words */ | |
454 | dat[ecc_word] ^= (1 << ecc_bit); | |
455 | } | |
3c3796cc | 456 | dev_dbg(host->dev, "atmel_nand : error corrected\n"); |
77f5492c RG |
457 | return 1; |
458 | } | |
459 | ||
460 | /* | |
d6248fdd | 461 | * Enable HW ECC : unused on most chips |
77f5492c | 462 | */ |
d6248fdd HS |
463 | static void atmel_nand_hwctl(struct mtd_info *mtd, int mode) |
464 | { | |
465 | if (cpu_is_at32ap7000()) { | |
466 | struct nand_chip *nand_chip = mtd->priv; | |
467 | struct atmel_nand_host *host = nand_chip->priv; | |
468 | ecc_writel(host->ecc, CR, ATMEL_ECC_RST); | |
469 | } | |
470 | } | |
77f5492c | 471 | |
42cb1403 AV |
472 | /* |
473 | * Probe for the NAND device. | |
474 | */ | |
3c3796cc | 475 | static int __init atmel_nand_probe(struct platform_device *pdev) |
42cb1403 | 476 | { |
3c3796cc | 477 | struct atmel_nand_host *host; |
42cb1403 AV |
478 | struct mtd_info *mtd; |
479 | struct nand_chip *nand_chip; | |
77f5492c RG |
480 | struct resource *regs; |
481 | struct resource *mem; | |
42cb1403 | 482 | int res; |
42cb1403 | 483 | |
cc0c72e1 HS |
484 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
485 | if (!mem) { | |
486 | printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n"); | |
487 | return -ENXIO; | |
488 | } | |
489 | ||
42cb1403 | 490 | /* Allocate memory for the device structure (and zero it) */ |
3c3796cc | 491 | host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL); |
42cb1403 | 492 | if (!host) { |
3c3796cc | 493 | printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n"); |
42cb1403 AV |
494 | return -ENOMEM; |
495 | } | |
496 | ||
cbc6c5e7 HX |
497 | host->io_phys = (dma_addr_t)mem->start; |
498 | ||
28f65c11 | 499 | host->io_base = ioremap(mem->start, resource_size(mem)); |
42cb1403 | 500 | if (host->io_base == NULL) { |
3c3796cc | 501 | printk(KERN_ERR "atmel_nand: ioremap failed\n"); |
cc0c72e1 HS |
502 | res = -EIO; |
503 | goto err_nand_ioremap; | |
42cb1403 AV |
504 | } |
505 | ||
506 | mtd = &host->mtd; | |
507 | nand_chip = &host->nand_chip; | |
508 | host->board = pdev->dev.platform_data; | |
77f5492c | 509 | host->dev = &pdev->dev; |
42cb1403 AV |
510 | |
511 | nand_chip->priv = host; /* link the private data structures */ | |
512 | mtd->priv = nand_chip; | |
513 | mtd->owner = THIS_MODULE; | |
514 | ||
515 | /* Set address of NAND IO lines */ | |
516 | nand_chip->IO_ADDR_R = host->io_base; | |
517 | nand_chip->IO_ADDR_W = host->io_base; | |
3c3796cc | 518 | nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl; |
a4265f8d | 519 | |
1d6dc068 | 520 | if (gpio_is_valid(host->board->rdy_pin)) |
3c3796cc | 521 | nand_chip->dev_ready = atmel_nand_device_ready; |
a4265f8d | 522 | |
bf4289cb JCPV |
523 | nand_chip->ecc.mode = host->board->ecc_mode; |
524 | ||
77f5492c | 525 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
bf4289cb | 526 | if (!regs && nand_chip->ecc.mode == NAND_ECC_HW) { |
3c3796cc | 527 | printk(KERN_ERR "atmel_nand: can't get I/O resource " |
77f5492c | 528 | "regs\nFalling back on software ECC\n"); |
bf4289cb | 529 | nand_chip->ecc.mode = NAND_ECC_SOFT; |
77f5492c RG |
530 | } |
531 | ||
bf4289cb | 532 | if (nand_chip->ecc.mode == NAND_ECC_HW) { |
28f65c11 | 533 | host->ecc = ioremap(regs->start, resource_size(regs)); |
77f5492c | 534 | if (host->ecc == NULL) { |
3c3796cc | 535 | printk(KERN_ERR "atmel_nand: ioremap failed\n"); |
77f5492c RG |
536 | res = -EIO; |
537 | goto err_ecc_ioremap; | |
538 | } | |
3c3796cc HS |
539 | nand_chip->ecc.calculate = atmel_nand_calculate; |
540 | nand_chip->ecc.correct = atmel_nand_correct; | |
541 | nand_chip->ecc.hwctl = atmel_nand_hwctl; | |
542 | nand_chip->ecc.read_page = atmel_nand_read_page; | |
77f5492c | 543 | nand_chip->ecc.bytes = 4; |
77f5492c RG |
544 | } |
545 | ||
42cb1403 AV |
546 | nand_chip->chip_delay = 20; /* 20us command delay time */ |
547 | ||
cbc6c5e7 | 548 | if (host->board->bus_width_16) /* 16-bit bus width */ |
dd11b8cd | 549 | nand_chip->options |= NAND_BUSWIDTH_16; |
cbc6c5e7 HX |
550 | |
551 | nand_chip->read_buf = atmel_read_buf; | |
552 | nand_chip->write_buf = atmel_write_buf; | |
dd11b8cd | 553 | |
42cb1403 | 554 | platform_set_drvdata(pdev, host); |
3c3796cc | 555 | atmel_nand_enable(host); |
42cb1403 | 556 | |
1d6dc068 | 557 | if (gpio_is_valid(host->board->det_pin)) { |
62fd71fe | 558 | if (gpio_get_value(host->board->det_pin)) { |
f4fa697c | 559 | printk(KERN_INFO "No SmartMedia card inserted.\n"); |
895fb494 | 560 | res = -ENXIO; |
cc0c72e1 | 561 | goto err_no_card; |
42cb1403 AV |
562 | } |
563 | } | |
564 | ||
3dcb7ea1 | 565 | if (host->board->on_flash_bbt || on_flash_bbt) { |
f4fa697c | 566 | printk(KERN_INFO "atmel_nand: Use On Flash BBT\n"); |
bb9ebd4e | 567 | nand_chip->bbt_options |= NAND_BBT_USE_FLASH; |
f4fa697c SP |
568 | } |
569 | ||
cb457a4d HX |
570 | if (!cpu_has_dma()) |
571 | use_dma = 0; | |
572 | ||
573 | if (use_dma) { | |
cbc6c5e7 HX |
574 | dma_cap_mask_t mask; |
575 | ||
576 | dma_cap_zero(mask); | |
577 | dma_cap_set(DMA_MEMCPY, mask); | |
201ab536 | 578 | host->dma_chan = dma_request_channel(mask, NULL, NULL); |
cbc6c5e7 HX |
579 | if (!host->dma_chan) { |
580 | dev_err(host->dev, "Failed to request DMA channel\n"); | |
581 | use_dma = 0; | |
582 | } | |
583 | } | |
584 | if (use_dma) | |
042bc9c0 NF |
585 | dev_info(host->dev, "Using %s for DMA transfers.\n", |
586 | dma_chan_name(host->dma_chan)); | |
cbc6c5e7 HX |
587 | else |
588 | dev_info(host->dev, "No DMA support for NAND access.\n"); | |
589 | ||
77f5492c | 590 | /* first scan to find the device and get the page size */ |
5e81e88a | 591 | if (nand_scan_ident(mtd, 1, NULL)) { |
77f5492c | 592 | res = -ENXIO; |
cc0c72e1 | 593 | goto err_scan_ident; |
77f5492c RG |
594 | } |
595 | ||
3fc23898 | 596 | if (nand_chip->ecc.mode == NAND_ECC_HW) { |
77f5492c RG |
597 | /* ECC is calculated for the whole page (1 step) */ |
598 | nand_chip->ecc.size = mtd->writesize; | |
599 | ||
600 | /* set ECC page size and oob layout */ | |
601 | switch (mtd->writesize) { | |
602 | case 512: | |
3c3796cc | 603 | nand_chip->ecc.layout = &atmel_oobinfo_small; |
3c3796cc | 604 | ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528); |
77f5492c RG |
605 | break; |
606 | case 1024: | |
3c3796cc HS |
607 | nand_chip->ecc.layout = &atmel_oobinfo_large; |
608 | ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056); | |
77f5492c RG |
609 | break; |
610 | case 2048: | |
3c3796cc HS |
611 | nand_chip->ecc.layout = &atmel_oobinfo_large; |
612 | ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112); | |
77f5492c RG |
613 | break; |
614 | case 4096: | |
3c3796cc HS |
615 | nand_chip->ecc.layout = &atmel_oobinfo_large; |
616 | ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224); | |
77f5492c RG |
617 | break; |
618 | default: | |
619 | /* page size not handled by HW ECC */ | |
620 | /* switching back to soft ECC */ | |
621 | nand_chip->ecc.mode = NAND_ECC_SOFT; | |
622 | nand_chip->ecc.calculate = NULL; | |
623 | nand_chip->ecc.correct = NULL; | |
624 | nand_chip->ecc.hwctl = NULL; | |
625 | nand_chip->ecc.read_page = NULL; | |
626 | nand_chip->ecc.postpad = 0; | |
627 | nand_chip->ecc.prepad = 0; | |
628 | nand_chip->ecc.bytes = 0; | |
629 | break; | |
630 | } | |
631 | } | |
632 | ||
633 | /* second phase scan */ | |
634 | if (nand_scan_tail(mtd)) { | |
42cb1403 | 635 | res = -ENXIO; |
cc0c72e1 | 636 | goto err_scan_tail; |
42cb1403 AV |
637 | } |
638 | ||
3c3796cc | 639 | mtd->name = "atmel_nand"; |
ef5d79f1 DES |
640 | res = mtd_device_parse_register(mtd, NULL, 0, |
641 | host->board->parts, host->board->num_parts); | |
42cb1403 AV |
642 | if (!res) |
643 | return res; | |
644 | ||
cc0c72e1 HS |
645 | err_scan_tail: |
646 | err_scan_ident: | |
647 | err_no_card: | |
3c3796cc | 648 | atmel_nand_disable(host); |
42cb1403 | 649 | platform_set_drvdata(pdev, NULL); |
cbc6c5e7 HX |
650 | if (host->dma_chan) |
651 | dma_release_channel(host->dma_chan); | |
cc0c72e1 HS |
652 | if (host->ecc) |
653 | iounmap(host->ecc); | |
654 | err_ecc_ioremap: | |
42cb1403 | 655 | iounmap(host->io_base); |
cc0c72e1 | 656 | err_nand_ioremap: |
42cb1403 AV |
657 | kfree(host); |
658 | return res; | |
659 | } | |
660 | ||
661 | /* | |
662 | * Remove a NAND device. | |
663 | */ | |
23a346ca | 664 | static int __exit atmel_nand_remove(struct platform_device *pdev) |
42cb1403 | 665 | { |
3c3796cc | 666 | struct atmel_nand_host *host = platform_get_drvdata(pdev); |
42cb1403 AV |
667 | struct mtd_info *mtd = &host->mtd; |
668 | ||
669 | nand_release(mtd); | |
670 | ||
3c3796cc | 671 | atmel_nand_disable(host); |
42cb1403 | 672 | |
cc0c72e1 HS |
673 | if (host->ecc) |
674 | iounmap(host->ecc); | |
cbc6c5e7 HX |
675 | |
676 | if (host->dma_chan) | |
677 | dma_release_channel(host->dma_chan); | |
678 | ||
42cb1403 AV |
679 | iounmap(host->io_base); |
680 | kfree(host); | |
681 | ||
682 | return 0; | |
683 | } | |
684 | ||
3c3796cc | 685 | static struct platform_driver atmel_nand_driver = { |
23a346ca | 686 | .remove = __exit_p(atmel_nand_remove), |
42cb1403 | 687 | .driver = { |
3c3796cc | 688 | .name = "atmel_nand", |
42cb1403 AV |
689 | .owner = THIS_MODULE, |
690 | }, | |
691 | }; | |
692 | ||
3c3796cc | 693 | static int __init atmel_nand_init(void) |
42cb1403 | 694 | { |
23a346ca | 695 | return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe); |
42cb1403 AV |
696 | } |
697 | ||
698 | ||
3c3796cc | 699 | static void __exit atmel_nand_exit(void) |
42cb1403 | 700 | { |
3c3796cc | 701 | platform_driver_unregister(&atmel_nand_driver); |
42cb1403 AV |
702 | } |
703 | ||
704 | ||
3c3796cc HS |
705 | module_init(atmel_nand_init); |
706 | module_exit(atmel_nand_exit); | |
42cb1403 AV |
707 | |
708 | MODULE_LICENSE("GPL"); | |
709 | MODULE_AUTHOR("Rick Bronson"); | |
d4f4c0aa | 710 | MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32"); |
3c3796cc | 711 | MODULE_ALIAS("platform:atmel_nand"); |