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arm: at91: dt: at91sam9 add nand pinctrl support
[mirror_ubuntu-zesty-kernel.git] / drivers / mtd / nand / atmel_nand.c
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42cb1403 1/*
1c7b874d 2 * Copyright © 2003 Rick Bronson
42cb1403
AV		 3 *
4 * Derived from drivers/mtd/nand/autcpu12.c
1c7b874d 5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
42cb1403
AV		 6 *
7 * Derived from drivers/mtd/spia.c
1c7b874d 8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
42cb1403 9 *
77f5492c
RG		 10 *
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
1c7b874d 12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
77f5492c
RG		 13 *
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
1c7b874d 16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
77f5492c 17 *
1c7b874d
JW		 18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
77f5492c 20 *
42cb1403
AV		 21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License version 2 as
23 * published by the Free Software Foundation.
24 *
25 */
26
b7f080cf 27#include <linux/dma-mapping.h>
42cb1403
AV		 28#include <linux/slab.h>
29#include <linux/module.h>
f4fa697c 30#include <linux/moduleparam.h>
42cb1403 31#include <linux/platform_device.h>
d6a01661
JCPV		 32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_gpio.h>
35#include <linux/of_mtd.h>
42cb1403
AV		 36#include <linux/mtd/mtd.h>
37#include <linux/mtd/nand.h>
38#include <linux/mtd/partitions.h>
39
5c39c4c5 40#include <linux/dmaengine.h>
90574d0a
DW		 41#include <linux/gpio.h>
42#include <linux/io.h>
bf4289cb 43#include <linux/platform_data/atmel.h>
42cb1403 44
a09e64fb 45#include <mach/cpu.h>
42cb1403 46
cbc6c5e7
HX		 47static int use_dma = 1;
48module_param(use_dma, int, 0);
49
f4fa697c
SP		 50static int on_flash_bbt = 0;
51module_param(on_flash_bbt, int, 0);
52
77f5492c
RG		 53/* Register access macros */
54#define ecc_readl(add, reg) \
3c3796cc 55 __raw_readl(add + ATMEL_ECC_##reg)
77f5492c 56#define ecc_writel(add, reg, value) \
3c3796cc 57 __raw_writel((value), add + ATMEL_ECC_##reg)
77f5492c 58
d4f4c0aa 59#include "atmel_nand_ecc.h" /* Hardware ECC registers */
77f5492c
RG		 60
61/* oob layout for large page size
62 * bad block info is on bytes 0 and 1
63 * the bytes have to be consecutives to avoid
64 * several NAND_CMD_RNDOUT during read
65 */
3c3796cc 66static struct nand_ecclayout atmel_oobinfo_large = {
77f5492c
RG		 67 .eccbytes = 4,
68 .eccpos = {60, 61, 62, 63},
69 .oobfree = {
70 {2, 58}
71 },
72};
73
74/* oob layout for small page size
75 * bad block info is on bytes 4 and 5
76 * the bytes have to be consecutives to avoid
77 * several NAND_CMD_RNDOUT during read
78 */
3c3796cc 79static struct nand_ecclayout atmel_oobinfo_small = {
77f5492c
RG		 80 .eccbytes = 4,
81 .eccpos = {0, 1, 2, 3},
82 .oobfree = {
83 {6, 10}
84 },
85};
86
3c3796cc 87struct atmel_nand_host {
42cb1403
AV		 88 struct nand_chip nand_chip;
89 struct mtd_info mtd;
90 void __iomem *io_base;
cbc6c5e7 91 dma_addr_t io_phys;
d6a01661 92 struct atmel_nand_data board;
77f5492c
RG		 93 struct device *dev;
94 void __iomem *ecc;
cbc6c5e7
HX		 95
96 struct completion comp;
97 struct dma_chan *dma_chan;
a41b51a1
JW		 98
99 bool has_pmecc;
100 u8 pmecc_corr_cap;
101 u16 pmecc_sector_size;
102 u32 pmecc_lookup_table_offset;
1c7b874d
JW		 103
104 int pmecc_bytes_per_sector;
105 int pmecc_sector_number;
106 int pmecc_degree; /* Degree of remainders */
107 int pmecc_cw_len; /* Length of codeword */
108
109 void __iomem *pmerrloc_base;
110 void __iomem *pmecc_rom_base;
111
112 /* lookup table for alpha_to and index_of */
113 void __iomem *pmecc_alpha_to;
114 void __iomem *pmecc_index_of;
115
116 /* data for pmecc computation */
117 int16_t *pmecc_partial_syn;
118 int16_t *pmecc_si;
119 int16_t *pmecc_smu; /* Sigma table */
120 int16_t *pmecc_lmu; /* polynomal order */
121 int *pmecc_mu;
122 int *pmecc_dmu;
123 int *pmecc_delta;
42cb1403
AV		 124};
125
1c7b874d
JW		 126static struct nand_ecclayout atmel_pmecc_oobinfo;
127
cbc6c5e7
HX		 128static int cpu_has_dma(void)
129{
130 return cpu_is_at91sam9rl() || cpu_is_at91sam9g45();
131}
132
8136508c
AN		 133/*
134 * Enable NAND.
135 */
3c3796cc 136static void atmel_nand_enable(struct atmel_nand_host *host)
8136508c 137{
d6a01661
JCPV		 138 if (gpio_is_valid(host->board.enable_pin))
139 gpio_set_value(host->board.enable_pin, 0);
8136508c
AN		 140}
141
142/*
143 * Disable NAND.
144 */
3c3796cc 145static void atmel_nand_disable(struct atmel_nand_host *host)
8136508c 146{
d6a01661
JCPV		 147 if (gpio_is_valid(host->board.enable_pin))
148 gpio_set_value(host->board.enable_pin, 1);
8136508c
AN		 149}
150
42cb1403
AV		 151/*
152 * Hardware specific access to control-lines
153 */
3c3796cc 154static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
42cb1403
AV		 155{
156 struct nand_chip *nand_chip = mtd->priv;
3c3796cc 157 struct atmel_nand_host *host = nand_chip->priv;
42cb1403 158
8136508c 159 if (ctrl & NAND_CTRL_CHANGE) {
2314488e 160 if (ctrl & NAND_NCE)
3c3796cc 161 atmel_nand_enable(host);
2314488e 162 else
3c3796cc 163 atmel_nand_disable(host);
2314488e 164 }
42cb1403
AV		 165 if (cmd == NAND_CMD_NONE)
166 return;
167
168 if (ctrl & NAND_CLE)
d6a01661 169 writeb(cmd, host->io_base + (1 << host->board.cle));
42cb1403 170 else
d6a01661 171 writeb(cmd, host->io_base + (1 << host->board.ale));
42cb1403
AV		 172}
173
174/*
175 * Read the Device Ready pin.
176 */
3c3796cc 177static int atmel_nand_device_ready(struct mtd_info *mtd)
42cb1403
AV		 178{
179 struct nand_chip *nand_chip = mtd->priv;
3c3796cc 180 struct atmel_nand_host *host = nand_chip->priv;
42cb1403 181
d6a01661
JCPV		 182 return gpio_get_value(host->board.rdy_pin) ^
183 !!host->board.rdy_pin_active_low;
42cb1403
AV		 184}
185
50082319
AB		 186/*
187 * Minimal-overhead PIO for data access.
188 */
189static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
190{
191 struct nand_chip *nand_chip = mtd->priv;
192
193 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
194}
195
196static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
197{
198 struct nand_chip *nand_chip = mtd->priv;
199
200 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
201}
202
203static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
204{
205 struct nand_chip *nand_chip = mtd->priv;
206
207 __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
208}
209
210static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
211{
212 struct nand_chip *nand_chip = mtd->priv;
213
214 __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
215}
216
cbc6c5e7
HX		 217static void dma_complete_func(void *completion)
218{
219 complete(completion);
220}
221
222static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
223 int is_read)
224{
225 struct dma_device *dma_dev;
226 enum dma_ctrl_flags flags;
227 dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
228 struct dma_async_tx_descriptor *tx = NULL;
229 dma_cookie_t cookie;
230 struct nand_chip *chip = mtd->priv;
231 struct atmel_nand_host *host = chip->priv;
232 void *p = buf;
233 int err = -EIO;
234 enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
235
80b4f81a
HX		 236 if (buf >= high_memory)
237 goto err_buf;
cbc6c5e7
HX		 238
239 dma_dev = host->dma_chan->device;
240
241 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_SRC_UNMAP |
242 DMA_COMPL_SKIP_DEST_UNMAP;
243
244 phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
245 if (dma_mapping_error(dma_dev->dev, phys_addr)) {
246 dev_err(host->dev, "Failed to dma_map_single\n");
247 goto err_buf;
248 }
249
250 if (is_read) {
251 dma_src_addr = host->io_phys;
252 dma_dst_addr = phys_addr;
253 } else {
254 dma_src_addr = phys_addr;
255 dma_dst_addr = host->io_phys;
256 }
257
258 tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
259 dma_src_addr, len, flags);
260 if (!tx) {
261 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
262 goto err_dma;
263 }
264
265 init_completion(&host->comp);
266 tx->callback = dma_complete_func;
267 tx->callback_param = &host->comp;
268
269 cookie = tx->tx_submit(tx);
270 if (dma_submit_error(cookie)) {
271 dev_err(host->dev, "Failed to do DMA tx_submit\n");
272 goto err_dma;
273 }
274
275 dma_async_issue_pending(host->dma_chan);
276 wait_for_completion(&host->comp);
277
278 err = 0;
279
280err_dma:
281 dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
282err_buf:
283 if (err != 0)
284 dev_warn(host->dev, "Fall back to CPU I/O\n");
285 return err;
286}
287
288static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
289{
290 struct nand_chip *chip = mtd->priv;
50082319 291 struct atmel_nand_host *host = chip->priv;
cbc6c5e7 292
9d51567e
NF		 293 if (use_dma && len > mtd->oobsize)
294 /* only use DMA for bigger than oob size: better performances */
cbc6c5e7
HX		 295 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
296 return;
297
d6a01661 298 if (host->board.bus_width_16)
50082319
AB		 299 atmel_read_buf16(mtd, buf, len);
300 else
301 atmel_read_buf8(mtd, buf, len);
cbc6c5e7
HX		 302}
303
304static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
305{
306 struct nand_chip *chip = mtd->priv;
50082319 307 struct atmel_nand_host *host = chip->priv;
cbc6c5e7 308
9d51567e
NF		 309 if (use_dma && len > mtd->oobsize)
310 /* only use DMA for bigger than oob size: better performances */
cbc6c5e7
HX		 311 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
312 return;
313
d6a01661 314 if (host->board.bus_width_16)
50082319
AB		 315 atmel_write_buf16(mtd, buf, len);
316 else
317 atmel_write_buf8(mtd, buf, len);
cbc6c5e7
HX		 318}
319
1c7b874d
JW		 320/*
321 * Return number of ecc bytes per sector according to sector size and
322 * correction capability
323 *
324 * Following table shows what at91 PMECC supported:
325 * Correction Capability Sector_512_bytes Sector_1024_bytes
326 * ===================== ================ =================
327 * 2-bits 4-bytes 4-bytes
328 * 4-bits 7-bytes 7-bytes
329 * 8-bits 13-bytes 14-bytes
330 * 12-bits 20-bytes 21-bytes
331 * 24-bits 39-bytes 42-bytes
332 */
333static int __devinit pmecc_get_ecc_bytes(int cap, int sector_size)
334{
335 int m = 12 + sector_size / 512;
336 return (m * cap + 7) / 8;
337}
338
339static void __devinit pmecc_config_ecc_layout(struct nand_ecclayout *layout,
340 int oobsize, int ecc_len)
341{
342 int i;
343
344 layout->eccbytes = ecc_len;
345
346 /* ECC will occupy the last ecc_len bytes continuously */
347 for (i = 0; i < ecc_len; i++)
348 layout->eccpos[i] = oobsize - ecc_len + i;
349
350 layout->oobfree[0].offset = 2;
351 layout->oobfree[0].length =
352 oobsize - ecc_len - layout->oobfree[0].offset;
353}
354
355static void __devinit __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
356{
357 int table_size;
358
359 table_size = host->pmecc_sector_size == 512 ?
360 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
361
362 return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
363 table_size * sizeof(int16_t);
364}
365
366static void pmecc_data_free(struct atmel_nand_host *host)
367{
368 kfree(host->pmecc_partial_syn);
369 kfree(host->pmecc_si);
370 kfree(host->pmecc_lmu);
371 kfree(host->pmecc_smu);
372 kfree(host->pmecc_mu);
373 kfree(host->pmecc_dmu);
374 kfree(host->pmecc_delta);
375}
376
377static int __devinit pmecc_data_alloc(struct atmel_nand_host *host)
378{
379 const int cap = host->pmecc_corr_cap;
380
381 host->pmecc_partial_syn = kzalloc((2 * cap + 1) * sizeof(int16_t),
382 GFP_KERNEL);
383 host->pmecc_si = kzalloc((2 * cap + 1) * sizeof(int16_t), GFP_KERNEL);
384 host->pmecc_lmu = kzalloc((cap + 1) * sizeof(int16_t), GFP_KERNEL);
385 host->pmecc_smu = kzalloc((cap + 2) * (2 * cap + 1) * sizeof(int16_t),
386 GFP_KERNEL);
387 host->pmecc_mu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
388 host->pmecc_dmu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
389 host->pmecc_delta = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
390
391 if (host->pmecc_partial_syn &&
392 host->pmecc_si &&
393 host->pmecc_lmu &&
394 host->pmecc_smu &&
395 host->pmecc_mu &&
396 host->pmecc_dmu &&
397 host->pmecc_delta)
398 return 0;
399
400 /* error happened */
401 pmecc_data_free(host);
402 return -ENOMEM;
403}
404
405static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
406{
407 struct nand_chip *nand_chip = mtd->priv;
408 struct atmel_nand_host *host = nand_chip->priv;
409 int i;
410 uint32_t value;
411
412 /* Fill odd syndromes */
413 for (i = 0; i < host->pmecc_corr_cap; i++) {
414 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
415 if (i & 1)
416 value >>= 16;
417 value &= 0xffff;
418 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
419 }
420}
421
422static void pmecc_substitute(struct mtd_info *mtd)
423{
424 struct nand_chip *nand_chip = mtd->priv;
425 struct atmel_nand_host *host = nand_chip->priv;
426 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
427 int16_t __iomem *index_of = host->pmecc_index_of;
428 int16_t *partial_syn = host->pmecc_partial_syn;
429 const int cap = host->pmecc_corr_cap;
430 int16_t *si;
431 int i, j;
432
433 /* si[] is a table that holds the current syndrome value,
434 * an element of that table belongs to the field
435 */
436 si = host->pmecc_si;
437
438 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
439
440 /* Computation 2t syndromes based on S(x) */
441 /* Odd syndromes */
442 for (i = 1; i < 2 * cap; i += 2) {
443 for (j = 0; j < host->pmecc_degree; j++) {
444 if (partial_syn[i] & ((unsigned short)0x1 << j))
445 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
446 }
447 }
448 /* Even syndrome = (Odd syndrome) ** 2 */
449 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
450 if (si[j] == 0) {
451 si[i] = 0;
452 } else {
453 int16_t tmp;
454
455 tmp = readw_relaxed(index_of + si[j]);
456 tmp = (tmp * 2) % host->pmecc_cw_len;
457 si[i] = readw_relaxed(alpha_to + tmp);
458 }
459 }
460
461 return;
462}
463
464static void pmecc_get_sigma(struct mtd_info *mtd)
465{
466 struct nand_chip *nand_chip = mtd->priv;
467 struct atmel_nand_host *host = nand_chip->priv;
468
469 int16_t *lmu = host->pmecc_lmu;
470 int16_t *si = host->pmecc_si;
471 int *mu = host->pmecc_mu;
472 int *dmu = host->pmecc_dmu; /* Discrepancy */
473 int *delta = host->pmecc_delta; /* Delta order */
474 int cw_len = host->pmecc_cw_len;
475 const int16_t cap = host->pmecc_corr_cap;
476 const int num = 2 * cap + 1;
477 int16_t __iomem *index_of = host->pmecc_index_of;
478 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
479 int i, j, k;
480 uint32_t dmu_0_count, tmp;
481 int16_t *smu = host->pmecc_smu;
482
483 /* index of largest delta */
484 int ro;
485 int largest;
486 int diff;
487
488 dmu_0_count = 0;
489
490 /* First Row */
491
492 /* Mu */
493 mu[0] = -1;
494
495 memset(smu, 0, sizeof(int16_t) * num);
496 smu[0] = 1;
497
498 /* discrepancy set to 1 */
499 dmu[0] = 1;
500 /* polynom order set to 0 */
501 lmu[0] = 0;
502 delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
503
504 /* Second Row */
505
506 /* Mu */
507 mu[1] = 0;
508 /* Sigma(x) set to 1 */
509 memset(&smu[num], 0, sizeof(int16_t) * num);
510 smu[num] = 1;
511
512 /* discrepancy set to S1 */
513 dmu[1] = si[1];
514
515 /* polynom order set to 0 */
516 lmu[1] = 0;
517
518 delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
519
520 /* Init the Sigma(x) last row */
521 memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
522
523 for (i = 1; i <= cap; i++) {
524 mu[i + 1] = i << 1;
525 /* Begin Computing Sigma (Mu+1) and L(mu) */
526 /* check if discrepancy is set to 0 */
527 if (dmu[i] == 0) {
528 dmu_0_count++;
529
530 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
531 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
532 tmp += 2;
533 else
534 tmp += 1;
535
536 if (dmu_0_count == tmp) {
537 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
538 smu[(cap + 1) * num + j] =
539 smu[i * num + j];
540
541 lmu[cap + 1] = lmu[i];
542 return;
543 }
544
545 /* copy polynom */
546 for (j = 0; j <= lmu[i] >> 1; j++)
547 smu[(i + 1) * num + j] = smu[i * num + j];
548
549 /* copy previous polynom order to the next */
550 lmu[i + 1] = lmu[i];
551 } else {
552 ro = 0;
553 largest = -1;
554 /* find largest delta with dmu != 0 */
555 for (j = 0; j < i; j++) {
556 if ((dmu[j]) && (delta[j] > largest)) {
557 largest = delta[j];
558 ro = j;
559 }
560 }
561
562 /* compute difference */
563 diff = (mu[i] - mu[ro]);
564
565 /* Compute degree of the new smu polynomial */
566 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
567 lmu[i + 1] = lmu[i];
568 else
569 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
570
571 /* Init smu[i+1] with 0 */
572 for (k = 0; k < num; k++)
573 smu[(i + 1) * num + k] = 0;
574
575 /* Compute smu[i+1] */
576 for (k = 0; k <= lmu[ro] >> 1; k++) {
577 int16_t a, b, c;
578
579 if (!(smu[ro * num + k] && dmu[i]))
580 continue;
581 a = readw_relaxed(index_of + dmu[i]);
582 b = readw_relaxed(index_of + dmu[ro]);
583 c = readw_relaxed(index_of + smu[ro * num + k]);
584 tmp = a + (cw_len - b) + c;
585 a = readw_relaxed(alpha_to + tmp % cw_len);
586 smu[(i + 1) * num + (k + diff)] = a;
587 }
588
589 for (k = 0; k <= lmu[i] >> 1; k++)
590 smu[(i + 1) * num + k] ^= smu[i * num + k];
591 }
592
593 /* End Computing Sigma (Mu+1) and L(mu) */
594 /* In either case compute delta */
595 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
596
597 /* Do not compute discrepancy for the last iteration */
598 if (i >= cap)
599 continue;
600
601 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
602 tmp = 2 * (i - 1);
603 if (k == 0) {
604 dmu[i + 1] = si[tmp + 3];
605 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
606 int16_t a, b, c;
607 a = readw_relaxed(index_of +
608 smu[(i + 1) * num + k]);
609 b = si[2 * (i - 1) + 3 - k];
610 c = readw_relaxed(index_of + b);
611 tmp = a + c;
612 tmp %= cw_len;
613 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
614 dmu[i + 1];
615 }
616 }
617 }
618
619 return;
620}
621
622static int pmecc_err_location(struct mtd_info *mtd)
623{
624 struct nand_chip *nand_chip = mtd->priv;
625 struct atmel_nand_host *host = nand_chip->priv;
626 unsigned long end_time;
627 const int cap = host->pmecc_corr_cap;
628 const int num = 2 * cap + 1;
629 int sector_size = host->pmecc_sector_size;
630 int err_nbr = 0; /* number of error */
631 int roots_nbr; /* number of roots */
632 int i;
633 uint32_t val;
634 int16_t *smu = host->pmecc_smu;
635
636 pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
637
638 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
639 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
640 smu[(cap + 1) * num + i]);
641 err_nbr++;
642 }
643
644 val = (err_nbr - 1) << 16;
645 if (sector_size == 1024)
646 val |= 1;
647
648 pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
649 pmerrloc_writel(host->pmerrloc_base, ELEN,
650 sector_size * 8 + host->pmecc_degree * cap);
651
652 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
653 while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
654 & PMERRLOC_CALC_DONE)) {
655 if (unlikely(time_after(jiffies, end_time))) {
656 dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
657 return -1;
658 }
659 cpu_relax();
660 }
661
662 roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
663 & PMERRLOC_ERR_NUM_MASK) >> 8;
664 /* Number of roots == degree of smu hence <= cap */
665 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
666 return err_nbr - 1;
667
668 /* Number of roots does not match the degree of smu
669 * unable to correct error */
670 return -1;
671}
672
673static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
674 int sector_num, int extra_bytes, int err_nbr)
675{
676 struct nand_chip *nand_chip = mtd->priv;
677 struct atmel_nand_host *host = nand_chip->priv;
678 int i = 0;
679 int byte_pos, bit_pos, sector_size, pos;
680 uint32_t tmp;
681 uint8_t err_byte;
682
683 sector_size = host->pmecc_sector_size;
684
685 while (err_nbr) {
686 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
687 byte_pos = tmp / 8;
688 bit_pos = tmp % 8;
689
690 if (byte_pos >= (sector_size + extra_bytes))
691 BUG(); /* should never happen */
692
693 if (byte_pos < sector_size) {
694 err_byte = *(buf + byte_pos);
695 *(buf + byte_pos) ^= (1 << bit_pos);
696
697 pos = sector_num * host->pmecc_sector_size + byte_pos;
698 dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
699 pos, bit_pos, err_byte, *(buf + byte_pos));
700 } else {
701 /* Bit flip in OOB area */
702 tmp = sector_num * host->pmecc_bytes_per_sector
703 + (byte_pos - sector_size);
704 err_byte = ecc[tmp];
705 ecc[tmp] ^= (1 << bit_pos);
706
707 pos = tmp + nand_chip->ecc.layout->eccpos[0];
708 dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
709 pos, bit_pos, err_byte, ecc[tmp]);
710 }
711
712 i++;
713 err_nbr--;
714 }
715
716 return;
717}
718
719static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
720 u8 *ecc)
721{
722 struct nand_chip *nand_chip = mtd->priv;
723 struct atmel_nand_host *host = nand_chip->priv;
724 int i, err_nbr, eccbytes;
725 uint8_t *buf_pos;
726
727 eccbytes = nand_chip->ecc.bytes;
728 for (i = 0; i < eccbytes; i++)
729 if (ecc[i] != 0xff)
730 goto normal_check;
731 /* Erased page, return OK */
732 return 0;
733
734normal_check:
735 for (i = 0; i < host->pmecc_sector_number; i++) {
736 err_nbr = 0;
737 if (pmecc_stat & 0x1) {
738 buf_pos = buf + i * host->pmecc_sector_size;
739
740 pmecc_gen_syndrome(mtd, i);
741 pmecc_substitute(mtd);
742 pmecc_get_sigma(mtd);
743
744 err_nbr = pmecc_err_location(mtd);
745 if (err_nbr == -1) {
746 dev_err(host->dev, "PMECC: Too many errors\n");
747 mtd->ecc_stats.failed++;
748 return -EIO;
749 } else {
750 pmecc_correct_data(mtd, buf_pos, ecc, i,
751 host->pmecc_bytes_per_sector, err_nbr);
752 mtd->ecc_stats.corrected += err_nbr;
753 }
754 }
755 pmecc_stat >>= 1;
756 }
757
758 return 0;
759}
760
761static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
762 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
763{
764 struct atmel_nand_host *host = chip->priv;
765 int eccsize = chip->ecc.size;
766 uint8_t *oob = chip->oob_poi;
767 uint32_t *eccpos = chip->ecc.layout->eccpos;
768 uint32_t stat;
769 unsigned long end_time;
770
771 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
772 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
773 pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG)
774 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
775
776 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
777 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
778
779 chip->read_buf(mtd, buf, eccsize);
780 chip->read_buf(mtd, oob, mtd->oobsize);
781
782 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
783 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
784 if (unlikely(time_after(jiffies, end_time))) {
785 dev_err(host->dev, "PMECC: Timeout to get error status.\n");
786 return -EIO;
787 }
788 cpu_relax();
789 }
790
791 stat = pmecc_readl_relaxed(host->ecc, ISR);
792 if (stat != 0)
793 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
794 return -EIO;
795
796 return 0;
797}
798
799static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
800 struct nand_chip *chip, const uint8_t *buf, int oob_required)
801{
802 struct atmel_nand_host *host = chip->priv;
803 uint32_t *eccpos = chip->ecc.layout->eccpos;
804 int i, j;
805 unsigned long end_time;
806
807 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
808 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
809
810 pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG) |
811 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
812
813 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
814 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
815
816 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
817
818 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
819 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
820 if (unlikely(time_after(jiffies, end_time))) {
821 dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
822 return -EIO;
823 }
824 cpu_relax();
825 }
826
827 for (i = 0; i < host->pmecc_sector_number; i++) {
828 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
829 int pos;
830
831 pos = i * host->pmecc_bytes_per_sector + j;
832 chip->oob_poi[eccpos[pos]] =
833 pmecc_readb_ecc_relaxed(host->ecc, i, j);
834 }
835 }
836 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
837
838 return 0;
839}
840
841static void atmel_pmecc_core_init(struct mtd_info *mtd)
842{
843 struct nand_chip *nand_chip = mtd->priv;
844 struct atmel_nand_host *host = nand_chip->priv;
845 uint32_t val = 0;
846 struct nand_ecclayout *ecc_layout;
847
848 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
849 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
850
851 switch (host->pmecc_corr_cap) {
852 case 2:
853 val = PMECC_CFG_BCH_ERR2;
854 break;
855 case 4:
856 val = PMECC_CFG_BCH_ERR4;
857 break;
858 case 8:
859 val = PMECC_CFG_BCH_ERR8;
860 break;
861 case 12:
862 val = PMECC_CFG_BCH_ERR12;
863 break;
864 case 24:
865 val = PMECC_CFG_BCH_ERR24;
866 break;
867 }
868
869 if (host->pmecc_sector_size == 512)
870 val |= PMECC_CFG_SECTOR512;
871 else if (host->pmecc_sector_size == 1024)
872 val |= PMECC_CFG_SECTOR1024;
873
874 switch (host->pmecc_sector_number) {
875 case 1:
876 val |= PMECC_CFG_PAGE_1SECTOR;
877 break;
878 case 2:
879 val |= PMECC_CFG_PAGE_2SECTORS;
880 break;
881 case 4:
882 val |= PMECC_CFG_PAGE_4SECTORS;
883 break;
884 case 8:
885 val |= PMECC_CFG_PAGE_8SECTORS;
886 break;
887 }
888
889 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
890 | PMECC_CFG_AUTO_DISABLE);
891 pmecc_writel(host->ecc, CFG, val);
892
893 ecc_layout = nand_chip->ecc.layout;
894 pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
895 pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
896 pmecc_writel(host->ecc, EADDR,
897 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
898 /* See datasheet about PMECC Clock Control Register */
899 pmecc_writel(host->ecc, CLK, 2);
900 pmecc_writel(host->ecc, IDR, 0xff);
901 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
902}
903
904static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev,
905 struct atmel_nand_host *host)
906{
907 struct mtd_info *mtd = &host->mtd;
908 struct nand_chip *nand_chip = &host->nand_chip;
909 struct resource *regs, *regs_pmerr, *regs_rom;
910 int cap, sector_size, err_no;
911
912 cap = host->pmecc_corr_cap;
913 sector_size = host->pmecc_sector_size;
914 dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
915 cap, sector_size);
916
917 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
918 if (!regs) {
919 dev_warn(host->dev,
920 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
921 nand_chip->ecc.mode = NAND_ECC_SOFT;
922 return 0;
923 }
924
925 host->ecc = ioremap(regs->start, resource_size(regs));
926 if (host->ecc == NULL) {
927 dev_err(host->dev, "ioremap failed\n");
928 err_no = -EIO;
929 goto err_pmecc_ioremap;
930 }
931
932 regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
933 regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
934 if (regs_pmerr && regs_rom) {
935 host->pmerrloc_base = ioremap(regs_pmerr->start,
936 resource_size(regs_pmerr));
937 host->pmecc_rom_base = ioremap(regs_rom->start,
938 resource_size(regs_rom));
939 }
940
941 if (!host->pmerrloc_base || !host->pmecc_rom_base) {
942 dev_err(host->dev,
943 "Can not get I/O resource for PMECC ERRLOC controller or ROM!\n");
944 err_no = -EIO;
945 goto err_pmloc_ioremap;
946 }
947
948 /* ECC is calculated for the whole page (1 step) */
949 nand_chip->ecc.size = mtd->writesize;
950
951 /* set ECC page size and oob layout */
952 switch (mtd->writesize) {
953 case 2048:
954 host->pmecc_degree = PMECC_GF_DIMENSION_13;
955 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
956 host->pmecc_sector_number = mtd->writesize / sector_size;
957 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
958 cap, sector_size);
959 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
960 host->pmecc_index_of = host->pmecc_rom_base +
961 host->pmecc_lookup_table_offset;
962
963 nand_chip->ecc.steps = 1;
964 nand_chip->ecc.strength = cap;
965 nand_chip->ecc.bytes = host->pmecc_bytes_per_sector *
966 host->pmecc_sector_number;
967 if (nand_chip->ecc.bytes > mtd->oobsize - 2) {
968 dev_err(host->dev, "No room for ECC bytes\n");
969 err_no = -EINVAL;
970 goto err_no_ecc_room;
971 }
972 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
973 mtd->oobsize,
974 nand_chip->ecc.bytes);
975 nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
976 break;
977 case 512:
978 case 1024:
979 case 4096:
980 /* TODO */
981 dev_warn(host->dev,
982 "Unsupported page size for PMECC, use Software ECC\n");
983 default:
984 /* page size not handled by HW ECC */
985 /* switching back to soft ECC */
986 nand_chip->ecc.mode = NAND_ECC_SOFT;
987 return 0;
988 }
989
990 /* Allocate data for PMECC computation */
991 err_no = pmecc_data_alloc(host);
992 if (err_no) {
993 dev_err(host->dev,
994 "Cannot allocate memory for PMECC computation!\n");
995 goto err_pmecc_data_alloc;
996 }
997
998 nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
999 nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1000
1001 atmel_pmecc_core_init(mtd);
1002
1003 return 0;
1004
1005err_pmecc_data_alloc:
1006err_no_ecc_room:
1007err_pmloc_ioremap:
1008 iounmap(host->ecc);
1009 if (host->pmerrloc_base)
1010 iounmap(host->pmerrloc_base);
1011 if (host->pmecc_rom_base)
1012 iounmap(host->pmecc_rom_base);
1013err_pmecc_ioremap:
1014 return err_no;
1015}
1016
77f5492c
RG		 1017/*
1018 * Calculate HW ECC
1019 *
1020 * function called after a write
1021 *
1022 * mtd: MTD block structure
1023 * dat: raw data (unused)
1024 * ecc_code: buffer for ECC
1025 */
3c3796cc 1026static int atmel_nand_calculate(struct mtd_info *mtd,
77f5492c
RG		 1027 const u_char *dat, unsigned char *ecc_code)
1028{
1029 struct nand_chip *nand_chip = mtd->priv;
3c3796cc 1030 struct atmel_nand_host *host = nand_chip->priv;
77f5492c
RG		 1031 unsigned int ecc_value;
1032
1033 /* get the first 2 ECC bytes */
d43fa149 1034 ecc_value = ecc_readl(host->ecc, PR);
77f5492c 1035
3fc23898
RG		 1036 ecc_code[0] = ecc_value & 0xFF;
1037 ecc_code[1] = (ecc_value >> 8) & 0xFF;
77f5492c
RG		 1038
1039 /* get the last 2 ECC bytes */
3c3796cc 1040 ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
77f5492c 1041
3fc23898
RG		 1042 ecc_code[2] = ecc_value & 0xFF;
1043 ecc_code[3] = (ecc_value >> 8) & 0xFF;
77f5492c
RG		 1044
1045 return 0;
1046}
1047
1048/*
1049 * HW ECC read page function
1050 *
1051 * mtd: mtd info structure
1052 * chip: nand chip info structure
1053 * buf: buffer to store read data
1fbb938d 1054 * oob_required: caller expects OOB data read to chip->oob_poi
77f5492c 1055 */
1fbb938d
BN		 1056static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1057 uint8_t *buf, int oob_required, int page)
77f5492c
RG		 1058{
1059 int eccsize = chip->ecc.size;
1060 int eccbytes = chip->ecc.bytes;
1061 uint32_t *eccpos = chip->ecc.layout->eccpos;
1062 uint8_t *p = buf;
1063 uint8_t *oob = chip->oob_poi;
1064 uint8_t *ecc_pos;
1065 int stat;
3f91e94f 1066 unsigned int max_bitflips = 0;
77f5492c 1067
d6248fdd
HS		 1068 /*
1069 * Errata: ALE is incorrectly wired up to the ECC controller
1070 * on the AP7000, so it will include the address cycles in the
1071 * ECC calculation.
1072 *
1073 * Workaround: Reset the parity registers before reading the
1074 * actual data.
1075 */
1076 if (cpu_is_at32ap7000()) {
1077 struct atmel_nand_host *host = chip->priv;
1078 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1079 }
1080
77f5492c
RG		 1081 /* read the page */
1082 chip->read_buf(mtd, p, eccsize);
1083
1084 /* move to ECC position if needed */
1085 if (eccpos[0] != 0) {
1086 /* This only works on large pages
1087 * because the ECC controller waits for
1088 * NAND_CMD_RNDOUTSTART after the
1089 * NAND_CMD_RNDOUT.
1090 * anyway, for small pages, the eccpos[0] == 0
1091 */
1092 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1093 mtd->writesize + eccpos[0], -1);
1094 }
1095
1096 /* the ECC controller needs to read the ECC just after the data */
1097 ecc_pos = oob + eccpos[0];
1098 chip->read_buf(mtd, ecc_pos, eccbytes);
1099
1100 /* check if there's an error */
1101 stat = chip->ecc.correct(mtd, p, oob, NULL);
1102
3f91e94f 1103 if (stat < 0) {
77f5492c 1104 mtd->ecc_stats.failed++;
3f91e94f 1105 } else {
77f5492c 1106 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1107 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1108 }
77f5492c
RG		 1109
1110 /* get back to oob start (end of page) */
1111 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1112
1113 /* read the oob */
1114 chip->read_buf(mtd, oob, mtd->oobsize);
1115
3f91e94f 1116 return max_bitflips;
77f5492c
RG		 1117}
1118
1119/*
1120 * HW ECC Correction
1121 *
1122 * function called after a read
1123 *
1124 * mtd: MTD block structure
1125 * dat: raw data read from the chip
1126 * read_ecc: ECC from the chip (unused)
1127 * isnull: unused
1128 *
1129 * Detect and correct a 1 bit error for a page
1130 */
3c3796cc 1131static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
77f5492c
RG		 1132 u_char *read_ecc, u_char *isnull)
1133{
1134 struct nand_chip *nand_chip = mtd->priv;
3c3796cc 1135 struct atmel_nand_host *host = nand_chip->priv;
77f5492c
RG		 1136 unsigned int ecc_status;
1137 unsigned int ecc_word, ecc_bit;
1138
1139 /* get the status from the Status Register */
1140 ecc_status = ecc_readl(host->ecc, SR);
1141
1142 /* if there's no error */
3c3796cc 1143 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
77f5492c
RG		 1144 return 0;
1145
1146 /* get error bit offset (4 bits) */
3c3796cc 1147 ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
77f5492c 1148 /* get word address (12 bits) */
3c3796cc 1149 ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
77f5492c
RG		 1150 ecc_word >>= 4;
1151
1152 /* if there are multiple errors */
3c3796cc 1153 if (ecc_status & ATMEL_ECC_MULERR) {
77f5492c
RG		 1154 /* check if it is a freshly erased block
1155 * (filled with 0xff) */
3c3796cc
HS		 1156 if ((ecc_bit == ATMEL_ECC_BITADDR)
1157 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
77f5492c
RG		 1158 /* the block has just been erased, return OK */
1159 return 0;
1160 }
1161 /* it doesn't seems to be a freshly
1162 * erased block.
1163 * We can't correct so many errors */
3c3796cc 1164 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
77f5492c
RG		 1165 " Unable to correct.\n");
1166 return -EIO;
1167 }
1168
1169 /* if there's a single bit error : we can correct it */
3c3796cc 1170 if (ecc_status & ATMEL_ECC_ECCERR) {
77f5492c
RG		 1171 /* there's nothing much to do here.
1172 * the bit error is on the ECC itself.
1173 */
3c3796cc 1174 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
77f5492c
RG		 1175 " Nothing to correct\n");
1176 return 0;
1177 }
1178
3c3796cc 1179 dev_dbg(host->dev, "atmel_nand : one bit error on data."
77f5492c
RG		 1180 " (word offset in the page :"
1181 " 0x%x bit offset : 0x%x)\n",
1182 ecc_word, ecc_bit);
1183 /* correct the error */
1184 if (nand_chip->options & NAND_BUSWIDTH_16) {
1185 /* 16 bits words */
1186 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1187 } else {
1188 /* 8 bits words */
1189 dat[ecc_word] ^= (1 << ecc_bit);
1190 }
3c3796cc 1191 dev_dbg(host->dev, "atmel_nand : error corrected\n");
77f5492c
RG		 1192 return 1;
1193}
1194
1195/*
d6248fdd 1196 * Enable HW ECC : unused on most chips
77f5492c 1197 */
d6248fdd
HS		 1198static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1199{
1200 if (cpu_is_at32ap7000()) {
1201 struct nand_chip *nand_chip = mtd->priv;
1202 struct atmel_nand_host *host = nand_chip->priv;
1203 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1204 }
1205}
77f5492c 1206
d6a01661
JCPV		 1207#if defined(CONFIG_OF)
1208static int __devinit atmel_of_init_port(struct atmel_nand_host *host,
1209 struct device_node *np)
1210{
a41b51a1
JW		 1211 u32 val, table_offset;
1212 u32 offset[2];
d6a01661
JCPV		 1213 int ecc_mode;
1214 struct atmel_nand_data *board = &host->board;
1215 enum of_gpio_flags flags;
1216
1217 if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
1218 if (val >= 32) {
1219 dev_err(host->dev, "invalid addr-offset %u\n", val);
1220 return -EINVAL;
1221 }
1222 board->ale = val;
1223 }
1224
1225 if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
1226 if (val >= 32) {
1227 dev_err(host->dev, "invalid cmd-offset %u\n", val);
1228 return -EINVAL;
1229 }
1230 board->cle = val;
1231 }
1232
1233 ecc_mode = of_get_nand_ecc_mode(np);
1234
1235 board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
1236
1237 board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
1238
1239 if (of_get_nand_bus_width(np) == 16)
1240 board->bus_width_16 = 1;
1241
1242 board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
1243 board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
1244
1245 board->enable_pin = of_get_gpio(np, 1);
1246 board->det_pin = of_get_gpio(np, 2);
1247
a41b51a1
JW		 1248 host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1249
1250 if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
1251 return 0; /* Not using PMECC */
1252
1253 /* use PMECC, get correction capability, sector size and lookup
1254 * table offset.
1255 */
1256 if (of_property_read_u32(np, "atmel,pmecc-cap", &val) != 0) {
1257 dev_err(host->dev, "Cannot decide PMECC Capability\n");
1258 return -EINVAL;
1259 } else if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
1260 (val != 24)) {
1261 dev_err(host->dev,
1262 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1263 val);
1264 return -EINVAL;
1265 }
1266 host->pmecc_corr_cap = (u8)val;
1267
1268 if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) != 0) {
1269 dev_err(host->dev, "Cannot decide PMECC Sector Size\n");
1270 return -EINVAL;
1271 } else if ((val != 512) && (val != 1024)) {
1272 dev_err(host->dev,
1273 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1274 val);
1275 return -EINVAL;
1276 }
1277 host->pmecc_sector_size = (u16)val;
1278
1279 if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1280 offset, 2) != 0) {
1281 dev_err(host->dev, "Cannot get PMECC lookup table offset\n");
1282 return -EINVAL;
1283 }
1284 table_offset = host->pmecc_sector_size == 512 ? offset[0] : offset[1];
1285
1286 if (!table_offset) {
1287 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1288 return -EINVAL;
1289 }
1290 host->pmecc_lookup_table_offset = table_offset;
1291
d6a01661
JCPV		 1292 return 0;
1293}
1294#else
1295static int __devinit atmel_of_init_port(struct atmel_nand_host *host,
1296 struct device_node *np)
1297{
1298 return -EINVAL;
1299}
1300#endif
1301
3dfe41a4
JW		 1302static int __init atmel_hw_nand_init_params(struct platform_device *pdev,
1303 struct atmel_nand_host *host)
1304{
1305 struct mtd_info *mtd = &host->mtd;
1306 struct nand_chip *nand_chip = &host->nand_chip;
1307 struct resource *regs;
1308
1309 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1310 if (!regs) {
1311 dev_err(host->dev,
1312 "Can't get I/O resource regs, use software ECC\n");
1313 nand_chip->ecc.mode = NAND_ECC_SOFT;
1314 return 0;
1315 }
1316
1317 host->ecc = ioremap(regs->start, resource_size(regs));
1318 if (host->ecc == NULL) {
1319 dev_err(host->dev, "ioremap failed\n");
1320 return -EIO;
1321 }
1322
1323 /* ECC is calculated for the whole page (1 step) */
1324 nand_chip->ecc.size = mtd->writesize;
1325
1326 /* set ECC page size and oob layout */
1327 switch (mtd->writesize) {
1328 case 512:
1329 nand_chip->ecc.layout = &atmel_oobinfo_small;
1330 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1331 break;
1332 case 1024:
1333 nand_chip->ecc.layout = &atmel_oobinfo_large;
1334 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1335 break;
1336 case 2048:
1337 nand_chip->ecc.layout = &atmel_oobinfo_large;
1338 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1339 break;
1340 case 4096:
1341 nand_chip->ecc.layout = &atmel_oobinfo_large;
1342 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1343 break;
1344 default:
1345 /* page size not handled by HW ECC */
1346 /* switching back to soft ECC */
1347 nand_chip->ecc.mode = NAND_ECC_SOFT;
1348 return 0;
1349 }
1350
1351 /* set up for HW ECC */
1352 nand_chip->ecc.calculate = atmel_nand_calculate;
1353 nand_chip->ecc.correct = atmel_nand_correct;
1354 nand_chip->ecc.hwctl = atmel_nand_hwctl;
1355 nand_chip->ecc.read_page = atmel_nand_read_page;
1356 nand_chip->ecc.bytes = 4;
1357 nand_chip->ecc.strength = 1;
1358
1359 return 0;
1360}
1361
42cb1403
AV		 1362/*
1363 * Probe for the NAND device.
1364 */
3c3796cc 1365static int __init atmel_nand_probe(struct platform_device *pdev)
42cb1403 1366{
3c3796cc 1367 struct atmel_nand_host *host;
42cb1403
AV		 1368 struct mtd_info *mtd;
1369 struct nand_chip *nand_chip;
77f5492c 1370 struct resource *mem;
d6a01661 1371 struct mtd_part_parser_data ppdata = {};
42cb1403 1372 int res;
42cb1403 1373
cc0c72e1
HS		 1374 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1375 if (!mem) {
1376 printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
1377 return -ENXIO;
1378 }
1379
42cb1403 1380 /* Allocate memory for the device structure (and zero it) */
3c3796cc 1381 host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
42cb1403 1382 if (!host) {
3c3796cc 1383 printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
42cb1403
AV		 1384 return -ENOMEM;
1385 }
1386
cbc6c5e7
HX		 1387 host->io_phys = (dma_addr_t)mem->start;
1388
28f65c11 1389 host->io_base = ioremap(mem->start, resource_size(mem));
42cb1403 1390 if (host->io_base == NULL) {
3c3796cc 1391 printk(KERN_ERR "atmel_nand: ioremap failed\n");
cc0c72e1
HS		 1392 res = -EIO;
1393 goto err_nand_ioremap;
42cb1403
AV		 1394 }
1395
1396 mtd = &host->mtd;
1397 nand_chip = &host->nand_chip;
77f5492c 1398 host->dev = &pdev->dev;
d6a01661
JCPV		 1399 if (pdev->dev.of_node) {
1400 res = atmel_of_init_port(host, pdev->dev.of_node);
1401 if (res)
28446acb 1402 goto err_ecc_ioremap;
d6a01661
JCPV		 1403 } else {
1404 memcpy(&host->board, pdev->dev.platform_data,
1405 sizeof(struct atmel_nand_data));
1406 }
42cb1403
AV		 1407
1408 nand_chip->priv = host; /* link the private data structures */
1409 mtd->priv = nand_chip;
1410 mtd->owner = THIS_MODULE;
1411
1412 /* Set address of NAND IO lines */
1413 nand_chip->IO_ADDR_R = host->io_base;
1414 nand_chip->IO_ADDR_W = host->io_base;
3c3796cc 1415 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
a4265f8d 1416
28446acb
JCPV		 1417 if (gpio_is_valid(host->board.rdy_pin)) {
1418 res = gpio_request(host->board.rdy_pin, "nand_rdy");
1419 if (res < 0) {
1420 dev_err(&pdev->dev,
1421 "can't request rdy gpio %d\n",
1422 host->board.rdy_pin);
1423 goto err_ecc_ioremap;
1424 }
1425
1426 res = gpio_direction_input(host->board.rdy_pin);
1427 if (res < 0) {
1428 dev_err(&pdev->dev,
1429 "can't request input direction rdy gpio %d\n",
1430 host->board.rdy_pin);
1431 goto err_ecc_ioremap;
1432 }
1433
3c3796cc 1434 nand_chip->dev_ready = atmel_nand_device_ready;
28446acb
JCPV		 1435 }
1436
1437 if (gpio_is_valid(host->board.enable_pin)) {
1438 res = gpio_request(host->board.enable_pin, "nand_enable");
1439 if (res < 0) {
1440 dev_err(&pdev->dev,
1441 "can't request enable gpio %d\n",
1442 host->board.enable_pin);
1443 goto err_ecc_ioremap;
1444 }
1445
1446 res = gpio_direction_output(host->board.enable_pin, 1);
1447 if (res < 0) {
1448 dev_err(&pdev->dev,
1449 "can't request output direction enable gpio %d\n",
1450 host->board.enable_pin);
1451 goto err_ecc_ioremap;
1452 }
1453 }
a4265f8d 1454
d6a01661 1455 nand_chip->ecc.mode = host->board.ecc_mode;
42cb1403
AV		 1456 nand_chip->chip_delay = 20; /* 20us command delay time */
1457
d6a01661 1458 if (host->board.bus_width_16) /* 16-bit bus width */
dd11b8cd 1459 nand_chip->options |= NAND_BUSWIDTH_16;
cbc6c5e7
HX		 1460
1461 nand_chip->read_buf = atmel_read_buf;
1462 nand_chip->write_buf = atmel_write_buf;
dd11b8cd 1463
42cb1403 1464 platform_set_drvdata(pdev, host);
3c3796cc 1465 atmel_nand_enable(host);
42cb1403 1466
d6a01661 1467 if (gpio_is_valid(host->board.det_pin)) {
28446acb
JCPV		 1468 res = gpio_request(host->board.det_pin, "nand_det");
1469 if (res < 0) {
1470 dev_err(&pdev->dev,
1471 "can't request det gpio %d\n",
1472 host->board.det_pin);
1473 goto err_no_card;
1474 }
1475
1476 res = gpio_direction_input(host->board.det_pin);
1477 if (res < 0) {
1478 dev_err(&pdev->dev,
1479 "can't request input direction det gpio %d\n",
1480 host->board.det_pin);
1481 goto err_no_card;
1482 }
1483
d6a01661 1484 if (gpio_get_value(host->board.det_pin)) {
f4fa697c 1485 printk(KERN_INFO "No SmartMedia card inserted.\n");
895fb494 1486 res = -ENXIO;
cc0c72e1 1487 goto err_no_card;
42cb1403
AV		 1488 }
1489 }
1490
d6a01661 1491 if (host->board.on_flash_bbt || on_flash_bbt) {
f4fa697c 1492 printk(KERN_INFO "atmel_nand: Use On Flash BBT\n");
bb9ebd4e 1493 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
f4fa697c
SP		 1494 }
1495
cb457a4d
HX		 1496 if (!cpu_has_dma())
1497 use_dma = 0;
1498
1499 if (use_dma) {
cbc6c5e7
HX		 1500 dma_cap_mask_t mask;
1501
1502 dma_cap_zero(mask);
1503 dma_cap_set(DMA_MEMCPY, mask);
201ab536 1504 host->dma_chan = dma_request_channel(mask, NULL, NULL);
cbc6c5e7
HX		 1505 if (!host->dma_chan) {
1506 dev_err(host->dev, "Failed to request DMA channel\n");
1507 use_dma = 0;
1508 }
1509 }
1510 if (use_dma)
042bc9c0
NF		 1511 dev_info(host->dev, "Using %s for DMA transfers.\n",
1512 dma_chan_name(host->dma_chan));
cbc6c5e7
HX		 1513 else
1514 dev_info(host->dev, "No DMA support for NAND access.\n");
1515
77f5492c 1516 /* first scan to find the device and get the page size */
5e81e88a 1517 if (nand_scan_ident(mtd, 1, NULL)) {
77f5492c 1518 res = -ENXIO;
cc0c72e1 1519 goto err_scan_ident;
77f5492c
RG		 1520 }
1521
3fc23898 1522 if (nand_chip->ecc.mode == NAND_ECC_HW) {
1c7b874d
JW		 1523 if (host->has_pmecc)
1524 res = atmel_pmecc_nand_init_params(pdev, host);
1525 else
1526 res = atmel_hw_nand_init_params(pdev, host);
1527
3dfe41a4
JW		 1528 if (res != 0)
1529 goto err_hw_ecc;
77f5492c
RG		 1530 }
1531
1532 /* second phase scan */
1533 if (nand_scan_tail(mtd)) {
42cb1403 1534 res = -ENXIO;
cc0c72e1 1535 goto err_scan_tail;
42cb1403
AV		 1536 }
1537
3c3796cc 1538 mtd->name = "atmel_nand";
d6a01661
JCPV		 1539 ppdata.of_node = pdev->dev.of_node;
1540 res = mtd_device_parse_register(mtd, NULL, &ppdata,
1541 host->board.parts, host->board.num_parts);
42cb1403
AV		 1542 if (!res)
1543 return res;
1544
cc0c72e1 1545err_scan_tail:
1c7b874d
JW		 1546 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
1547 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1548 pmecc_data_free(host);
1549 }
3dfe41a4
JW		 1550 if (host->ecc)
1551 iounmap(host->ecc);
1c7b874d
JW		 1552 if (host->pmerrloc_base)
1553 iounmap(host->pmerrloc_base);
1554 if (host->pmecc_rom_base)
1555 iounmap(host->pmecc_rom_base);
3dfe41a4 1556err_hw_ecc:
cc0c72e1
HS		 1557err_scan_ident:
1558err_no_card:
3c3796cc 1559 atmel_nand_disable(host);
42cb1403 1560 platform_set_drvdata(pdev, NULL);
cbc6c5e7
HX		 1561 if (host->dma_chan)
1562 dma_release_channel(host->dma_chan);
28446acb 1563err_ecc_ioremap:
42cb1403 1564 iounmap(host->io_base);
cc0c72e1 1565err_nand_ioremap:
42cb1403
AV		 1566 kfree(host);
1567 return res;
1568}
1569
1570/*
1571 * Remove a NAND device.
1572 */
23a346ca 1573static int __exit atmel_nand_remove(struct platform_device *pdev)
42cb1403 1574{
3c3796cc 1575 struct atmel_nand_host *host = platform_get_drvdata(pdev);
42cb1403
AV		 1576 struct mtd_info *mtd = &host->mtd;
1577
1578 nand_release(mtd);
1579
3c3796cc 1580 atmel_nand_disable(host);
42cb1403 1581
1c7b874d
JW		 1582 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
1583 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1584 pmerrloc_writel(host->pmerrloc_base, ELDIS,
1585 PMERRLOC_DISABLE);
1586 pmecc_data_free(host);
1587 }
1588
28446acb
JCPV		 1589 if (gpio_is_valid(host->board.det_pin))
1590 gpio_free(host->board.det_pin);
1591
1592 if (gpio_is_valid(host->board.enable_pin))
1593 gpio_free(host->board.enable_pin);
1594
1595 if (gpio_is_valid(host->board.rdy_pin))
1596 gpio_free(host->board.rdy_pin);
1597
cc0c72e1
HS		 1598 if (host->ecc)
1599 iounmap(host->ecc);
1c7b874d
JW		 1600 if (host->pmecc_rom_base)
1601 iounmap(host->pmecc_rom_base);
1602 if (host->pmerrloc_base)
1603 iounmap(host->pmerrloc_base);
cbc6c5e7
HX		 1604
1605 if (host->dma_chan)
1606 dma_release_channel(host->dma_chan);
1607
42cb1403
AV		 1608 iounmap(host->io_base);
1609 kfree(host);
1610
1611 return 0;
1612}
1613
d6a01661
JCPV		 1614#if defined(CONFIG_OF)
1615static const struct of_device_id atmel_nand_dt_ids[] = {
1616 { .compatible = "atmel,at91rm9200-nand" },
1617 { /* sentinel */ }
1618};
1619
1620MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
1621#endif
1622
3c3796cc 1623static struct platform_driver atmel_nand_driver = {
23a346ca 1624 .remove = __exit_p(atmel_nand_remove),
42cb1403 1625 .driver = {
3c3796cc 1626 .name = "atmel_nand",
42cb1403 1627 .owner = THIS_MODULE,
d6a01661 1628 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
42cb1403
AV		 1629 },
1630};
1631
3c3796cc 1632static int __init atmel_nand_init(void)
42cb1403 1633{
23a346ca 1634 return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe);
42cb1403
AV		 1635}
1636
1637
3c3796cc 1638static void __exit atmel_nand_exit(void)
42cb1403 1639{
3c3796cc 1640 platform_driver_unregister(&atmel_nand_driver);
42cb1403
AV		 1641}
1642
1643
3c3796cc
HS		 1644module_init(atmel_nand_init);
1645module_exit(atmel_nand_exit);
42cb1403
AV		 1646
1647MODULE_LICENSE("GPL");
1648MODULE_AUTHOR("Rick Bronson");
d4f4c0aa 1649MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
3c3796cc 1650MODULE_ALIAS("platform:atmel_nand");
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