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mtd: nand: core: use mtd_ooblayout_xxx() helpers where appropriate
[mirror_ubuntu-zesty-kernel.git] / drivers / mtd / nand / atmel_nand.c
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42cb1403 1/*
1c7b874d 2 * Copyright © 2003 Rick Bronson
42cb1403
AV		 3 *
4 * Derived from drivers/mtd/nand/autcpu12.c
1c7b874d 5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
42cb1403
AV		 6 *
7 * Derived from drivers/mtd/spia.c
1c7b874d 8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
42cb1403 9 *
77f5492c
RG		 10 *
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
1c7b874d 12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
77f5492c
RG		 13 *
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
1c7b874d 16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
77f5492c 17 *
1c7b874d
JW		 18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
77f5492c 20 *
7dc37de7
JW		 21 * Add Nand Flash Controller support for SAMA5 SoC
22 * © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
23 *
42cb1403
AV		 24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
27 *
28 */
29
2d405ec5 30#include <linux/clk.h>
b7f080cf 31#include <linux/dma-mapping.h>
42cb1403
AV		 32#include <linux/slab.h>
33#include <linux/module.h>
f4fa697c 34#include <linux/moduleparam.h>
42cb1403 35#include <linux/platform_device.h>
d6a01661
JCPV		 36#include <linux/of.h>
37#include <linux/of_device.h>
38#include <linux/of_gpio.h>
42cb1403
AV		 39#include <linux/mtd/mtd.h>
40#include <linux/mtd/nand.h>
41#include <linux/mtd/partitions.h>
42
7dc37de7 43#include <linux/delay.h>
5c39c4c5 44#include <linux/dmaengine.h>
90574d0a 45#include <linux/gpio.h>
7dc37de7 46#include <linux/interrupt.h>
90574d0a 47#include <linux/io.h>
bf4289cb 48#include <linux/platform_data/atmel.h>
42cb1403 49
cbc6c5e7
HX		 50static int use_dma = 1;
51module_param(use_dma, int, 0);
52
f4fa697c
SP		 53static int on_flash_bbt = 0;
54module_param(on_flash_bbt, int, 0);
55
77f5492c
RG		 56/* Register access macros */
57#define ecc_readl(add, reg) \
3c3796cc 58 __raw_readl(add + ATMEL_ECC_##reg)
77f5492c 59#define ecc_writel(add, reg, value) \
3c3796cc 60 __raw_writel((value), add + ATMEL_ECC_##reg)
77f5492c 61
d4f4c0aa 62#include "atmel_nand_ecc.h" /* Hardware ECC registers */
7dc37de7 63#include "atmel_nand_nfc.h" /* Nand Flash Controller definition */
77f5492c 64
51585778
WJ		 65struct atmel_nand_caps {
66 bool pmecc_correct_erase_page;
55750756 67 uint8_t pmecc_max_correction;
51585778
WJ		 68};
69
5ddc7bd4
RI		 70struct atmel_nand_nfc_caps {
71 uint32_t rb_mask;
72};
73
77f5492c
RG		 74/* oob layout for large page size
75 * bad block info is on bytes 0 and 1
76 * the bytes have to be consecutives to avoid
77 * several NAND_CMD_RNDOUT during read
78 */
3c3796cc 79static struct nand_ecclayout atmel_oobinfo_large = {
77f5492c
RG		 80 .eccbytes = 4,
81 .eccpos = {60, 61, 62, 63},
82 .oobfree = {
83 {2, 58}
84 },
85};
86
87/* oob layout for small page size
88 * bad block info is on bytes 4 and 5
89 * the bytes have to be consecutives to avoid
90 * several NAND_CMD_RNDOUT during read
91 */
3c3796cc 92static struct nand_ecclayout atmel_oobinfo_small = {
77f5492c
RG		 93 .eccbytes = 4,
94 .eccpos = {0, 1, 2, 3},
95 .oobfree = {
96 {6, 10}
97 },
98};
99
7dc37de7
JW		 100struct atmel_nfc {
101 void __iomem *base_cmd_regs;
102 void __iomem *hsmc_regs;
068b44b7 103 void *sram_bank0;
7dc37de7 104 dma_addr_t sram_bank0_phys;
1ae9c092 105 bool use_nfc_sram;
6054d4d5 106 bool write_by_sram;
7dc37de7 107
2d405ec5
BB		 108 struct clk *clk;
109
7dc37de7 110 bool is_initialized;
e4e06934
JW		 111 struct completion comp_ready;
112 struct completion comp_cmd_done;
113 struct completion comp_xfer_done;
1ae9c092
JW		 114
115 /* Point to the sram bank which include readed data via NFC */
068b44b7 116 void *data_in_sram;
6054d4d5 117 bool will_write_sram;
5ddc7bd4 118 const struct atmel_nand_nfc_caps *caps;
7dc37de7
JW		 119};
120static struct atmel_nfc nand_nfc;
121
3c3796cc 122struct atmel_nand_host {
42cb1403 123 struct nand_chip nand_chip;
42cb1403 124 void __iomem *io_base;
cbc6c5e7 125 dma_addr_t io_phys;
d6a01661 126 struct atmel_nand_data board;
77f5492c
RG		 127 struct device *dev;
128 void __iomem *ecc;
cbc6c5e7
HX		 129
130 struct completion comp;
131 struct dma_chan *dma_chan;
a41b51a1 132
7dc37de7
JW		 133 struct atmel_nfc *nfc;
134
72eaec21 135 const struct atmel_nand_caps *caps;
a41b51a1
JW		 136 bool has_pmecc;
137 u8 pmecc_corr_cap;
138 u16 pmecc_sector_size;
abb1cd00 139 bool has_no_lookup_table;
a41b51a1 140 u32 pmecc_lookup_table_offset;
e66b4318
JW		 141 u32 pmecc_lookup_table_offset_512;
142 u32 pmecc_lookup_table_offset_1024;
1c7b874d 143
1c7b874d
JW		 144 int pmecc_degree; /* Degree of remainders */
145 int pmecc_cw_len; /* Length of codeword */
146
147 void __iomem *pmerrloc_base;
55750756 148 void __iomem *pmerrloc_el_base;
1c7b874d
JW		 149 void __iomem *pmecc_rom_base;
150
151 /* lookup table for alpha_to and index_of */
152 void __iomem *pmecc_alpha_to;
153 void __iomem *pmecc_index_of;
154
155 /* data for pmecc computation */
156 int16_t *pmecc_partial_syn;
157 int16_t *pmecc_si;
158 int16_t *pmecc_smu; /* Sigma table */
159 int16_t *pmecc_lmu; /* polynomal order */
160 int *pmecc_mu;
161 int *pmecc_dmu;
162 int *pmecc_delta;
42cb1403
AV		 163};
164
1c7b874d
JW		 165static struct nand_ecclayout atmel_pmecc_oobinfo;
166
8136508c
AN		 167/*
168 * Enable NAND.
169 */
3c3796cc 170static void atmel_nand_enable(struct atmel_nand_host *host)
8136508c 171{
d6a01661
JCPV		 172 if (gpio_is_valid(host->board.enable_pin))
173 gpio_set_value(host->board.enable_pin, 0);
8136508c
AN		 174}
175
176/*
177 * Disable NAND.
178 */
3c3796cc 179static void atmel_nand_disable(struct atmel_nand_host *host)
8136508c 180{
d6a01661
JCPV		 181 if (gpio_is_valid(host->board.enable_pin))
182 gpio_set_value(host->board.enable_pin, 1);
8136508c
AN		 183}
184
42cb1403
AV		 185/*
186 * Hardware specific access to control-lines
187 */
3c3796cc 188static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
42cb1403 189{
4bd4ebcc 190 struct nand_chip *nand_chip = mtd_to_nand(mtd);
d699ed25 191 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
42cb1403 192
8136508c 193 if (ctrl & NAND_CTRL_CHANGE) {
2314488e 194 if (ctrl & NAND_NCE)
3c3796cc 195 atmel_nand_enable(host);
2314488e 196 else
3c3796cc 197 atmel_nand_disable(host);
2314488e 198 }
42cb1403
AV		 199 if (cmd == NAND_CMD_NONE)
200 return;
201
202 if (ctrl & NAND_CLE)
d6a01661 203 writeb(cmd, host->io_base + (1 << host->board.cle));
42cb1403 204 else
d6a01661 205 writeb(cmd, host->io_base + (1 << host->board.ale));
42cb1403
AV		 206}
207
208/*
209 * Read the Device Ready pin.
210 */
3c3796cc 211static int atmel_nand_device_ready(struct mtd_info *mtd)
42cb1403 212{
4bd4ebcc 213 struct nand_chip *nand_chip = mtd_to_nand(mtd);
d699ed25 214 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
42cb1403 215
d6a01661
JCPV		 216 return gpio_get_value(host->board.rdy_pin) ^
217 !!host->board.rdy_pin_active_low;
42cb1403
AV		 218}
219
7dc37de7
JW		 220/* Set up for hardware ready pin and enable pin. */
221static int atmel_nand_set_enable_ready_pins(struct mtd_info *mtd)
222{
4bd4ebcc 223 struct nand_chip *chip = mtd_to_nand(mtd);
d699ed25 224 struct atmel_nand_host *host = nand_get_controller_data(chip);
7dc37de7
JW		 225 int res = 0;
226
227 if (gpio_is_valid(host->board.rdy_pin)) {
228 res = devm_gpio_request(host->dev,
229 host->board.rdy_pin, "nand_rdy");
230 if (res < 0) {
231 dev_err(host->dev,
232 "can't request rdy gpio %d\n",
233 host->board.rdy_pin);
234 return res;
235 }
236
237 res = gpio_direction_input(host->board.rdy_pin);
238 if (res < 0) {
239 dev_err(host->dev,
240 "can't request input direction rdy gpio %d\n",
241 host->board.rdy_pin);
242 return res;
243 }
244
245 chip->dev_ready = atmel_nand_device_ready;
246 }
247
248 if (gpio_is_valid(host->board.enable_pin)) {
249 res = devm_gpio_request(host->dev,
250 host->board.enable_pin, "nand_enable");
251 if (res < 0) {
252 dev_err(host->dev,
253 "can't request enable gpio %d\n",
254 host->board.enable_pin);
255 return res;
256 }
257
258 res = gpio_direction_output(host->board.enable_pin, 1);
259 if (res < 0) {
260 dev_err(host->dev,
261 "can't request output direction enable gpio %d\n",
262 host->board.enable_pin);
263 return res;
264 }
265 }
266
267 return res;
268}
269
50082319
AB		 270/*
271 * Minimal-overhead PIO for data access.
272 */
273static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
274{
4bd4ebcc 275 struct nand_chip *nand_chip = mtd_to_nand(mtd);
d699ed25 276 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
50082319 277
1ae9c092 278 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
068b44b7 279 memcpy(buf, host->nfc->data_in_sram, len);
1ae9c092
JW		 280 host->nfc->data_in_sram += len;
281 } else {
282 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
283 }
50082319
AB		 284}
285
286static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
287{
4bd4ebcc 288 struct nand_chip *nand_chip = mtd_to_nand(mtd);
d699ed25 289 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
50082319 290
1ae9c092 291 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
068b44b7 292 memcpy(buf, host->nfc->data_in_sram, len);
1ae9c092
JW		 293 host->nfc->data_in_sram += len;
294 } else {
295 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
296 }
50082319
AB		 297}
298
299static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
300{
4bd4ebcc 301 struct nand_chip *nand_chip = mtd_to_nand(mtd);
50082319
AB		 302
303 __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
304}
305
306static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
307{
4bd4ebcc 308 struct nand_chip *nand_chip = mtd_to_nand(mtd);
50082319
AB		 309
310 __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
311}
312
cbc6c5e7
HX		 313static void dma_complete_func(void *completion)
314{
315 complete(completion);
316}
317
1ae9c092
JW		 318static int nfc_set_sram_bank(struct atmel_nand_host *host, unsigned int bank)
319{
320 /* NFC only has two banks. Must be 0 or 1 */
321 if (bank > 1)
322 return -EINVAL;
323
324 if (bank) {
ac01efeb
BB		 325 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
326
1ae9c092 327 /* Only for a 2k-page or lower flash, NFC can handle 2 banks */
ac01efeb 328 if (mtd->writesize > 2048)
1ae9c092
JW		 329 return -EINVAL;
330 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK1);
331 } else {
332 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK0);
333 }
334
335 return 0;
336}
337
338static uint nfc_get_sram_off(struct atmel_nand_host *host)
339{
340 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
341 return NFC_SRAM_BANK1_OFFSET;
342 else
343 return 0;
344}
345
346static dma_addr_t nfc_sram_phys(struct atmel_nand_host *host)
347{
348 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
349 return host->nfc->sram_bank0_phys + NFC_SRAM_BANK1_OFFSET;
350 else
351 return host->nfc->sram_bank0_phys;
352}
353
cbc6c5e7
HX		 354static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
355 int is_read)
356{
357 struct dma_device *dma_dev;
358 enum dma_ctrl_flags flags;
359 dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
360 struct dma_async_tx_descriptor *tx = NULL;
361 dma_cookie_t cookie;
4bd4ebcc 362 struct nand_chip *chip = mtd_to_nand(mtd);
d699ed25 363 struct atmel_nand_host *host = nand_get_controller_data(chip);
cbc6c5e7
HX		 364 void *p = buf;
365 int err = -EIO;
366 enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1ae9c092 367 struct atmel_nfc *nfc = host->nfc;
cbc6c5e7 368
80b4f81a
HX		 369 if (buf >= high_memory)
370 goto err_buf;
cbc6c5e7
HX		 371
372 dma_dev = host->dma_chan->device;
373
0776ae7b 374 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
cbc6c5e7
HX		 375
376 phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
377 if (dma_mapping_error(dma_dev->dev, phys_addr)) {
378 dev_err(host->dev, "Failed to dma_map_single\n");
379 goto err_buf;
380 }
381
382 if (is_read) {
1ae9c092
JW		 383 if (nfc && nfc->data_in_sram)
384 dma_src_addr = nfc_sram_phys(host) + (nfc->data_in_sram
385 - (nfc->sram_bank0 + nfc_get_sram_off(host)));
386 else
387 dma_src_addr = host->io_phys;
388
cbc6c5e7
HX		 389 dma_dst_addr = phys_addr;
390 } else {
391 dma_src_addr = phys_addr;
6054d4d5
JW		 392
393 if (nfc && nfc->write_by_sram)
394 dma_dst_addr = nfc_sram_phys(host);
395 else
396 dma_dst_addr = host->io_phys;
cbc6c5e7
HX		 397 }
398
399 tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
400 dma_src_addr, len, flags);
401 if (!tx) {
402 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
403 goto err_dma;
404 }
405
406 init_completion(&host->comp);
407 tx->callback = dma_complete_func;
408 tx->callback_param = &host->comp;
409
410 cookie = tx->tx_submit(tx);
411 if (dma_submit_error(cookie)) {
412 dev_err(host->dev, "Failed to do DMA tx_submit\n");
413 goto err_dma;
414 }
415
416 dma_async_issue_pending(host->dma_chan);
417 wait_for_completion(&host->comp);
418
1ae9c092
JW		 419 if (is_read && nfc && nfc->data_in_sram)
420 /* After read data from SRAM, need to increase the position */
421 nfc->data_in_sram += len;
422
cbc6c5e7
HX		 423 err = 0;
424
425err_dma:
426 dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
427err_buf:
428 if (err != 0)
74414a94 429 dev_dbg(host->dev, "Fall back to CPU I/O\n");
cbc6c5e7
HX		 430 return err;
431}
432
433static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
434{
4bd4ebcc 435 struct nand_chip *chip = mtd_to_nand(mtd);
cbc6c5e7 436
9d51567e
NF		 437 if (use_dma && len > mtd->oobsize)
438 /* only use DMA for bigger than oob size: better performances */
cbc6c5e7
HX		 439 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
440 return;
441
4f3cab9b 442 if (chip->options & NAND_BUSWIDTH_16)
50082319
AB		 443 atmel_read_buf16(mtd, buf, len);
444 else
445 atmel_read_buf8(mtd, buf, len);
cbc6c5e7
HX		 446}
447
448static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
449{
4bd4ebcc 450 struct nand_chip *chip = mtd_to_nand(mtd);
cbc6c5e7 451
9d51567e
NF		 452 if (use_dma && len > mtd->oobsize)
453 /* only use DMA for bigger than oob size: better performances */
cbc6c5e7
HX		 454 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
455 return;
456
4f3cab9b 457 if (chip->options & NAND_BUSWIDTH_16)
50082319
AB		 458 atmel_write_buf16(mtd, buf, len);
459 else
460 atmel_write_buf8(mtd, buf, len);
cbc6c5e7
HX		 461}
462
1c7b874d
JW		 463/*
464 * Return number of ecc bytes per sector according to sector size and
465 * correction capability
466 *
467 * Following table shows what at91 PMECC supported:
468 * Correction Capability Sector_512_bytes Sector_1024_bytes
469 * ===================== ================ =================
470 * 2-bits 4-bytes 4-bytes
471 * 4-bits 7-bytes 7-bytes
472 * 8-bits 13-bytes 14-bytes
473 * 12-bits 20-bytes 21-bytes
474 * 24-bits 39-bytes 42-bytes
94248462 475 * 32-bits 52-bytes 56-bytes
1c7b874d 476 */
06f25510 477static int pmecc_get_ecc_bytes(int cap, int sector_size)
1c7b874d
JW		 478{
479 int m = 12 + sector_size / 512;
480 return (m * cap + 7) / 8;
481}
482
06f25510 483static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
d8929942 484 int oobsize, int ecc_len)
1c7b874d
JW		 485{
486 int i;
487
488 layout->eccbytes = ecc_len;
489
490 /* ECC will occupy the last ecc_len bytes continuously */
491 for (i = 0; i < ecc_len; i++)
492 layout->eccpos[i] = oobsize - ecc_len + i;
493
477478ae 494 layout->oobfree[0].offset = PMECC_OOB_RESERVED_BYTES;
1c7b874d
JW		 495 layout->oobfree[0].length =
496 oobsize - ecc_len - layout->oobfree[0].offset;
497}
498
06f25510 499static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
1c7b874d
JW		 500{
501 int table_size;
502
503 table_size = host->pmecc_sector_size == 512 ?
504 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
505
506 return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
507 table_size * sizeof(int16_t);
508}
509
06f25510 510static int pmecc_data_alloc(struct atmel_nand_host *host)
1c7b874d
JW		 511{
512 const int cap = host->pmecc_corr_cap;
0d63748d
JCPV		 513 int size;
514
515 size = (2 * cap + 1) * sizeof(int16_t);
516 host->pmecc_partial_syn = devm_kzalloc(host->dev, size, GFP_KERNEL);
517 host->pmecc_si = devm_kzalloc(host->dev, size, GFP_KERNEL);
518 host->pmecc_lmu = devm_kzalloc(host->dev,
519 (cap + 1) * sizeof(int16_t), GFP_KERNEL);
520 host->pmecc_smu = devm_kzalloc(host->dev,
521 (cap + 2) * size, GFP_KERNEL);
522
523 size = (cap + 1) * sizeof(int);
524 host->pmecc_mu = devm_kzalloc(host->dev, size, GFP_KERNEL);
525 host->pmecc_dmu = devm_kzalloc(host->dev, size, GFP_KERNEL);
526 host->pmecc_delta = devm_kzalloc(host->dev, size, GFP_KERNEL);
527
528 if (!host->pmecc_partial_syn ||
529 !host->pmecc_si ||
530 !host->pmecc_lmu ||
531 !host->pmecc_smu ||
532 !host->pmecc_mu ||
533 !host->pmecc_dmu ||
534 !host->pmecc_delta)
535 return -ENOMEM;
1c7b874d 536
0d63748d 537 return 0;
1c7b874d
JW		 538}
539
540static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
541{
4bd4ebcc 542 struct nand_chip *nand_chip = mtd_to_nand(mtd);
d699ed25 543 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1c7b874d
JW		 544 int i;
545 uint32_t value;
546
547 /* Fill odd syndromes */
548 for (i = 0; i < host->pmecc_corr_cap; i++) {
549 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
550 if (i & 1)
551 value >>= 16;
552 value &= 0xffff;
553 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
554 }
555}
556
557static void pmecc_substitute(struct mtd_info *mtd)
558{
4bd4ebcc 559 struct nand_chip *nand_chip = mtd_to_nand(mtd);
d699ed25 560 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1c7b874d
JW		 561 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
562 int16_t __iomem *index_of = host->pmecc_index_of;
563 int16_t *partial_syn = host->pmecc_partial_syn;
564 const int cap = host->pmecc_corr_cap;
565 int16_t *si;
566 int i, j;
567
568 /* si[] is a table that holds the current syndrome value,
569 * an element of that table belongs to the field
570 */
571 si = host->pmecc_si;
572
573 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
574
575 /* Computation 2t syndromes based on S(x) */
576 /* Odd syndromes */
577 for (i = 1; i < 2 * cap; i += 2) {
578 for (j = 0; j < host->pmecc_degree; j++) {
579 if (partial_syn[i] & ((unsigned short)0x1 << j))
580 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
581 }
582 }
583 /* Even syndrome = (Odd syndrome) ** 2 */
584 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
585 if (si[j] == 0) {
586 si[i] = 0;
587 } else {
588 int16_t tmp;
589
590 tmp = readw_relaxed(index_of + si[j]);
591 tmp = (tmp * 2) % host->pmecc_cw_len;
592 si[i] = readw_relaxed(alpha_to + tmp);
593 }
594 }
595
596 return;
597}
598
599static void pmecc_get_sigma(struct mtd_info *mtd)
600{
4bd4ebcc 601 struct nand_chip *nand_chip = mtd_to_nand(mtd);
d699ed25 602 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1c7b874d
JW		 603
604 int16_t *lmu = host->pmecc_lmu;
605 int16_t *si = host->pmecc_si;
606 int *mu = host->pmecc_mu;
607 int *dmu = host->pmecc_dmu; /* Discrepancy */
608 int *delta = host->pmecc_delta; /* Delta order */
609 int cw_len = host->pmecc_cw_len;
610 const int16_t cap = host->pmecc_corr_cap;
611 const int num = 2 * cap + 1;
612 int16_t __iomem *index_of = host->pmecc_index_of;
613 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
614 int i, j, k;
615 uint32_t dmu_0_count, tmp;
616 int16_t *smu = host->pmecc_smu;
617
618 /* index of largest delta */
619 int ro;
620 int largest;
621 int diff;
622
623 dmu_0_count = 0;
624
625 /* First Row */
626
627 /* Mu */
628 mu[0] = -1;
629
630 memset(smu, 0, sizeof(int16_t) * num);
631 smu[0] = 1;
632
633 /* discrepancy set to 1 */
634 dmu[0] = 1;
635 /* polynom order set to 0 */
636 lmu[0] = 0;
637 delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
638
639 /* Second Row */
640
641 /* Mu */
642 mu[1] = 0;
643 /* Sigma(x) set to 1 */
644 memset(&smu[num], 0, sizeof(int16_t) * num);
645 smu[num] = 1;
646
647 /* discrepancy set to S1 */
648 dmu[1] = si[1];
649
650 /* polynom order set to 0 */
651 lmu[1] = 0;
652
653 delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
654
655 /* Init the Sigma(x) last row */
656 memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
657
658 for (i = 1; i <= cap; i++) {
659 mu[i + 1] = i << 1;
660 /* Begin Computing Sigma (Mu+1) and L(mu) */
661 /* check if discrepancy is set to 0 */
662 if (dmu[i] == 0) {
663 dmu_0_count++;
664
665 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
666 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
667 tmp += 2;
668 else
669 tmp += 1;
670
671 if (dmu_0_count == tmp) {
672 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
673 smu[(cap + 1) * num + j] =
674 smu[i * num + j];
675
676 lmu[cap + 1] = lmu[i];
677 return;
678 }
679
680 /* copy polynom */
681 for (j = 0; j <= lmu[i] >> 1; j++)
682 smu[(i + 1) * num + j] = smu[i * num + j];
683
684 /* copy previous polynom order to the next */
685 lmu[i + 1] = lmu[i];
686 } else {
687 ro = 0;
688 largest = -1;
689 /* find largest delta with dmu != 0 */
690 for (j = 0; j < i; j++) {
691 if ((dmu[j]) && (delta[j] > largest)) {
692 largest = delta[j];
693 ro = j;
694 }
695 }
696
697 /* compute difference */
698 diff = (mu[i] - mu[ro]);
699
700 /* Compute degree of the new smu polynomial */
701 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
702 lmu[i + 1] = lmu[i];
703 else
704 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
705
706 /* Init smu[i+1] with 0 */
707 for (k = 0; k < num; k++)
708 smu[(i + 1) * num + k] = 0;
709
710 /* Compute smu[i+1] */
711 for (k = 0; k <= lmu[ro] >> 1; k++) {
712 int16_t a, b, c;
713
714 if (!(smu[ro * num + k] && dmu[i]))
715 continue;
716 a = readw_relaxed(index_of + dmu[i]);
717 b = readw_relaxed(index_of + dmu[ro]);
718 c = readw_relaxed(index_of + smu[ro * num + k]);
719 tmp = a + (cw_len - b) + c;
720 a = readw_relaxed(alpha_to + tmp % cw_len);
721 smu[(i + 1) * num + (k + diff)] = a;
722 }
723
724 for (k = 0; k <= lmu[i] >> 1; k++)
725 smu[(i + 1) * num + k] ^= smu[i * num + k];
726 }
727
728 /* End Computing Sigma (Mu+1) and L(mu) */
729 /* In either case compute delta */
730 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
731
732 /* Do not compute discrepancy for the last iteration */
733 if (i >= cap)
734 continue;
735
736 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
737 tmp = 2 * (i - 1);
738 if (k == 0) {
739 dmu[i + 1] = si[tmp + 3];
740 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
741 int16_t a, b, c;
742 a = readw_relaxed(index_of +
743 smu[(i + 1) * num + k]);
744 b = si[2 * (i - 1) + 3 - k];
745 c = readw_relaxed(index_of + b);
746 tmp = a + c;
747 tmp %= cw_len;
748 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
749 dmu[i + 1];
750 }
751 }
752 }
753
754 return;
755}
756
757static int pmecc_err_location(struct mtd_info *mtd)
758{
4bd4ebcc 759 struct nand_chip *nand_chip = mtd_to_nand(mtd);
d699ed25 760 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1c7b874d
JW		 761 unsigned long end_time;
762 const int cap = host->pmecc_corr_cap;
763 const int num = 2 * cap + 1;
764 int sector_size = host->pmecc_sector_size;
765 int err_nbr = 0; /* number of error */
766 int roots_nbr; /* number of roots */
767 int i;
768 uint32_t val;
769 int16_t *smu = host->pmecc_smu;
770
771 pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
772
773 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
774 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
775 smu[(cap + 1) * num + i]);
776 err_nbr++;
777 }
778
779 val = (err_nbr - 1) << 16;
780 if (sector_size == 1024)
781 val |= 1;
782
783 pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
784 pmerrloc_writel(host->pmerrloc_base, ELEN,
785 sector_size * 8 + host->pmecc_degree * cap);
786
787 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
788 while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
789 & PMERRLOC_CALC_DONE)) {
790 if (unlikely(time_after(jiffies, end_time))) {
791 dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
792 return -1;
793 }
794 cpu_relax();
795 }
796
797 roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
798 & PMERRLOC_ERR_NUM_MASK) >> 8;
799 /* Number of roots == degree of smu hence <= cap */
800 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
801 return err_nbr - 1;
802
803 /* Number of roots does not match the degree of smu
804 * unable to correct error */
805 return -1;
806}
807
808static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
809 int sector_num, int extra_bytes, int err_nbr)
810{
4bd4ebcc 811 struct nand_chip *nand_chip = mtd_to_nand(mtd);
d699ed25 812 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1c7b874d
JW		 813 int i = 0;
814 int byte_pos, bit_pos, sector_size, pos;
815 uint32_t tmp;
816 uint8_t err_byte;
817
818 sector_size = host->pmecc_sector_size;
819
820 while (err_nbr) {
55750756 821 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_el_base, i) - 1;
1c7b874d
JW		 822 byte_pos = tmp / 8;
823 bit_pos = tmp % 8;
824
825 if (byte_pos >= (sector_size + extra_bytes))
826 BUG(); /* should never happen */
827
828 if (byte_pos < sector_size) {
829 err_byte = *(buf + byte_pos);
830 *(buf + byte_pos) ^= (1 << bit_pos);
831
832 pos = sector_num * host->pmecc_sector_size + byte_pos;
12197bf2 833 dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
1c7b874d
JW		 834 pos, bit_pos, err_byte, *(buf + byte_pos));
835 } else {
836 /* Bit flip in OOB area */
022a478c 837 tmp = sector_num * nand_chip->ecc.bytes
1c7b874d
JW		 838 + (byte_pos - sector_size);
839 err_byte = ecc[tmp];
840 ecc[tmp] ^= (1 << bit_pos);
841
842 pos = tmp + nand_chip->ecc.layout->eccpos[0];
12197bf2 843 dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
1c7b874d
JW		 844 pos, bit_pos, err_byte, ecc[tmp]);
845 }
846
847 i++;
848 err_nbr--;
849 }
850
851 return;
852}
853
854static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
855 u8 *ecc)
856{
4bd4ebcc 857 struct nand_chip *nand_chip = mtd_to_nand(mtd);
d699ed25 858 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
b3857666 859 int i, err_nbr;
1c7b874d 860 uint8_t *buf_pos;
267d46e6 861 int max_bitflips = 0;
1c7b874d 862
c9447fff 863 for (i = 0; i < nand_chip->ecc.steps; i++) {
1c7b874d
JW		 864 err_nbr = 0;
865 if (pmecc_stat & 0x1) {
866 buf_pos = buf + i * host->pmecc_sector_size;
867
868 pmecc_gen_syndrome(mtd, i);
869 pmecc_substitute(mtd);
870 pmecc_get_sigma(mtd);
871
872 err_nbr = pmecc_err_location(mtd);
ff6ee101
BB		 873 if (err_nbr >= 0) {
874 pmecc_correct_data(mtd, buf_pos, ecc, i,
875 nand_chip->ecc.bytes,
876 err_nbr);
877 } else if (!host->caps->pmecc_correct_erase_page) {
878 u8 *ecc_pos = ecc + (i * nand_chip->ecc.bytes);
879
880 /* Try to detect erased pages */
881 err_nbr = nand_check_erased_ecc_chunk(buf_pos,
882 host->pmecc_sector_size,
883 ecc_pos,
884 nand_chip->ecc.bytes,
885 NULL, 0,
886 nand_chip->ecc.strength);
887 }
888
889 if (err_nbr < 0) {
1c7b874d
JW		 890 dev_err(host->dev, "PMECC: Too many errors\n");
891 mtd->ecc_stats.failed++;
892 return -EIO;
1c7b874d 893 }
ff6ee101
BB		 894
895 mtd->ecc_stats.corrected += err_nbr;
896 max_bitflips = max_t(int, max_bitflips, err_nbr);
1c7b874d
JW		 897 }
898 pmecc_stat >>= 1;
899 }
900
267d46e6 901 return max_bitflips;
1c7b874d
JW		 902}
903
5ee3d9da
JW		 904static void pmecc_enable(struct atmel_nand_host *host, int ecc_op)
905{
906 u32 val;
907
5ee3d9da
JW		 908 if (ecc_op != NAND_ECC_READ && ecc_op != NAND_ECC_WRITE) {
909 dev_err(host->dev, "atmel_nand: wrong pmecc operation type!");
910 return;
911 }
912
1fad0e8b
JW		 913 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
914 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
915 val = pmecc_readl_relaxed(host->ecc, CFG);
916
5ee3d9da
JW		 917 if (ecc_op == NAND_ECC_READ)
918 pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP)
919 | PMECC_CFG_AUTO_ENABLE);
920 else
921 pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP)
922 & ~PMECC_CFG_AUTO_ENABLE);
923
924 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
925 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
926}
927
1c7b874d
JW		 928static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
929 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
930{
d699ed25 931 struct atmel_nand_host *host = nand_get_controller_data(chip);
b3857666 932 int eccsize = chip->ecc.size * chip->ecc.steps;
1c7b874d
JW		 933 uint8_t *oob = chip->oob_poi;
934 uint32_t *eccpos = chip->ecc.layout->eccpos;
935 uint32_t stat;
936 unsigned long end_time;
c0c70d9e 937 int bitflips = 0;
1c7b874d 938
1ae9c092
JW		 939 if (!host->nfc || !host->nfc->use_nfc_sram)
940 pmecc_enable(host, NAND_ECC_READ);
1c7b874d
JW		 941
942 chip->read_buf(mtd, buf, eccsize);
943 chip->read_buf(mtd, oob, mtd->oobsize);
944
945 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
946 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
947 if (unlikely(time_after(jiffies, end_time))) {
948 dev_err(host->dev, "PMECC: Timeout to get error status.\n");
949 return -EIO;
950 }
951 cpu_relax();
952 }
953
954 stat = pmecc_readl_relaxed(host->ecc, ISR);
c0c70d9e
JW		 955 if (stat != 0) {
956 bitflips = pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]);
957 if (bitflips < 0)
958 /* uncorrectable errors */
959 return 0;
960 }
1c7b874d 961
c0c70d9e 962 return bitflips;
1c7b874d
JW		 963}
964
965static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
45aaeff9
BB		 966 struct nand_chip *chip, const uint8_t *buf, int oob_required,
967 int page)
1c7b874d 968{
d699ed25 969 struct atmel_nand_host *host = nand_get_controller_data(chip);
1c7b874d
JW		 970 uint32_t *eccpos = chip->ecc.layout->eccpos;
971 int i, j;
972 unsigned long end_time;
973
6054d4d5
JW		 974 if (!host->nfc || !host->nfc->write_by_sram) {
975 pmecc_enable(host, NAND_ECC_WRITE);
976 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
977 }
1c7b874d
JW		 978
979 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
980 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
981 if (unlikely(time_after(jiffies, end_time))) {
982 dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
983 return -EIO;
984 }
985 cpu_relax();
986 }
987
c9447fff 988 for (i = 0; i < chip->ecc.steps; i++) {
022a478c 989 for (j = 0; j < chip->ecc.bytes; j++) {
1c7b874d
JW		 990 int pos;
991
022a478c 992 pos = i * chip->ecc.bytes + j;
1c7b874d
JW		 993 chip->oob_poi[eccpos[pos]] =
994 pmecc_readb_ecc_relaxed(host->ecc, i, j);
995 }
996 }
997 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
998
999 return 0;
1000}
1001
1002static void atmel_pmecc_core_init(struct mtd_info *mtd)
1003{
4bd4ebcc 1004 struct nand_chip *nand_chip = mtd_to_nand(mtd);
d699ed25 1005 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1c7b874d
JW		 1006 uint32_t val = 0;
1007 struct nand_ecclayout *ecc_layout;
1008
1009 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
1010 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1011
1012 switch (host->pmecc_corr_cap) {
1013 case 2:
1014 val = PMECC_CFG_BCH_ERR2;
1015 break;
1016 case 4:
1017 val = PMECC_CFG_BCH_ERR4;
1018 break;
1019 case 8:
1020 val = PMECC_CFG_BCH_ERR8;
1021 break;
1022 case 12:
1023 val = PMECC_CFG_BCH_ERR12;
1024 break;
1025 case 24:
1026 val = PMECC_CFG_BCH_ERR24;
1027 break;
94248462
RI		 1028 case 32:
1029 val = PMECC_CFG_BCH_ERR32;
1030 break;
1c7b874d
JW		 1031 }
1032
1033 if (host->pmecc_sector_size == 512)
1034 val |= PMECC_CFG_SECTOR512;
1035 else if (host->pmecc_sector_size == 1024)
1036 val |= PMECC_CFG_SECTOR1024;
1037
c9447fff 1038 switch (nand_chip->ecc.steps) {
1c7b874d
JW		 1039 case 1:
1040 val |= PMECC_CFG_PAGE_1SECTOR;
1041 break;
1042 case 2:
1043 val |= PMECC_CFG_PAGE_2SECTORS;
1044 break;
1045 case 4:
1046 val |= PMECC_CFG_PAGE_4SECTORS;
1047 break;
1048 case 8:
1049 val |= PMECC_CFG_PAGE_8SECTORS;
1050 break;
1051 }
1052
1053 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
1054 | PMECC_CFG_AUTO_DISABLE);
1055 pmecc_writel(host->ecc, CFG, val);
1056
1057 ecc_layout = nand_chip->ecc.layout;
1058 pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
1059 pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
1060 pmecc_writel(host->ecc, EADDR,
1061 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
1062 /* See datasheet about PMECC Clock Control Register */
1063 pmecc_writel(host->ecc, CLK, 2);
1064 pmecc_writel(host->ecc, IDR, 0xff);
1065 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
1066}
1067
84cfbbb8 1068/*
2a3d933a 1069 * Get minimum ecc requirements from NAND.
84cfbbb8 1070 * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
2a3d933a 1071 * will set them according to minimum ecc requirement. Otherwise, use the
84cfbbb8
JW		 1072 * value in DTS file.
1073 * return 0 if success. otherwise return error code.
1074 */
1075static int pmecc_choose_ecc(struct atmel_nand_host *host,
1076 int *cap, int *sector_size)
1077{
2a3d933a
JW		 1078 /* Get minimum ECC requirements */
1079 if (host->nand_chip.ecc_strength_ds) {
1080 *cap = host->nand_chip.ecc_strength_ds;
1081 *sector_size = host->nand_chip.ecc_step_ds;
1082 dev_info(host->dev, "minimum ECC: %d bits in %d bytes\n",
84cfbbb8 1083 *cap, *sector_size);
84cfbbb8 1084 } else {
84cfbbb8
JW		 1085 *cap = 2;
1086 *sector_size = 512;
2a3d933a 1087 dev_info(host->dev, "can't detect min. ECC, assume 2 bits in 512 bytes\n");
84cfbbb8
JW		 1088 }
1089
2a3d933a 1090 /* If device tree doesn't specify, use NAND's minimum ECC parameters */
84cfbbb8 1091 if (host->pmecc_corr_cap == 0) {
94248462
RI		 1092 if (*cap > host->caps->pmecc_max_correction)
1093 return -EINVAL;
1094
84cfbbb8
JW		 1095 /* use the most fitable ecc bits (the near bigger one ) */
1096 if (*cap <= 2)
1097 host->pmecc_corr_cap = 2;
1098 else if (*cap <= 4)
1099 host->pmecc_corr_cap = 4;
edc9cba4 1100 else if (*cap <= 8)
84cfbbb8 1101 host->pmecc_corr_cap = 8;
edc9cba4 1102 else if (*cap <= 12)
84cfbbb8 1103 host->pmecc_corr_cap = 12;
edc9cba4 1104 else if (*cap <= 24)
84cfbbb8 1105 host->pmecc_corr_cap = 24;
94248462
RI		 1106 else if (*cap <= 32)
1107 host->pmecc_corr_cap = 32;
84cfbbb8
JW		 1108 else
1109 return -EINVAL;
1110 }
1111 if (host->pmecc_sector_size == 0) {
1112 /* use the most fitable sector size (the near smaller one ) */
1113 if (*sector_size >= 1024)
1114 host->pmecc_sector_size = 1024;
1115 else if (*sector_size >= 512)
1116 host->pmecc_sector_size = 512;
1117 else
1118 return -EINVAL;
1119 }
1120 return 0;
1121}
1122
abb1cd00
JW		 1123static inline int deg(unsigned int poly)
1124{
1125 /* polynomial degree is the most-significant bit index */
1126 return fls(poly) - 1;
1127}
1128
1129static int build_gf_tables(int mm, unsigned int poly,
1130 int16_t *index_of, int16_t *alpha_to)
1131{
1132 unsigned int i, x = 1;
1133 const unsigned int k = 1 << deg(poly);
1134 unsigned int nn = (1 << mm) - 1;
1135
1136 /* primitive polynomial must be of degree m */
1137 if (k != (1u << mm))
1138 return -EINVAL;
1139
1140 for (i = 0; i < nn; i++) {
1141 alpha_to[i] = x;
1142 index_of[x] = i;
1143 if (i && (x == 1))
1144 /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
1145 return -EINVAL;
1146 x <<= 1;
1147 if (x & k)
1148 x ^= poly;
1149 }
1150 alpha_to[nn] = 1;
1151 index_of[0] = 0;
1152
1153 return 0;
1154}
1155
1156static uint16_t *create_lookup_table(struct device *dev, int sector_size)
1157{
1158 int degree = (sector_size == 512) ?
1159 PMECC_GF_DIMENSION_13 :
1160 PMECC_GF_DIMENSION_14;
1161 unsigned int poly = (sector_size == 512) ?
1162 PMECC_GF_13_PRIMITIVE_POLY :
1163 PMECC_GF_14_PRIMITIVE_POLY;
1164 int table_size = (sector_size == 512) ?
1165 PMECC_LOOKUP_TABLE_SIZE_512 :
1166 PMECC_LOOKUP_TABLE_SIZE_1024;
1167
1168 int16_t *addr = devm_kzalloc(dev, 2 * table_size * sizeof(uint16_t),
1169 GFP_KERNEL);
1170 if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
1171 return NULL;
1172
1173 return addr;
1174}
1175
2c2b9285 1176static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
1c7b874d
JW		 1177 struct atmel_nand_host *host)
1178{
1c7b874d 1179 struct nand_chip *nand_chip = &host->nand_chip;
ac01efeb 1180 struct mtd_info *mtd = nand_to_mtd(nand_chip);
1c7b874d 1181 struct resource *regs, *regs_pmerr, *regs_rom;
abb1cd00 1182 uint16_t *galois_table;
1c7b874d
JW		 1183 int cap, sector_size, err_no;
1184
84cfbbb8
JW		 1185 err_no = pmecc_choose_ecc(host, &cap, &sector_size);
1186 if (err_no) {
1187 dev_err(host->dev, "The NAND flash's ECC requirement are not support!");
1188 return err_no;
1189 }
1190
f666d649 1191 if (cap > host->pmecc_corr_cap ||
84cfbbb8
JW		 1192 sector_size != host->pmecc_sector_size)
1193 dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
e66b4318 1194
1c7b874d
JW		 1195 cap = host->pmecc_corr_cap;
1196 sector_size = host->pmecc_sector_size;
e66b4318
JW		 1197 host->pmecc_lookup_table_offset = (sector_size == 512) ?
1198 host->pmecc_lookup_table_offset_512 :
1199 host->pmecc_lookup_table_offset_1024;
1200
1c7b874d
JW		 1201 dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
1202 cap, sector_size);
1203
1204 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1205 if (!regs) {
1206 dev_warn(host->dev,
1207 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1208 nand_chip->ecc.mode = NAND_ECC_SOFT;
1209 return 0;
1210 }
1211
0d63748d
JCPV		 1212 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1213 if (IS_ERR(host->ecc)) {
0d63748d
JCPV		 1214 err_no = PTR_ERR(host->ecc);
1215 goto err;
1c7b874d
JW		 1216 }
1217
1218 regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
0d63748d
JCPV		 1219 host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr);
1220 if (IS_ERR(host->pmerrloc_base)) {
0d63748d
JCPV		 1221 err_no = PTR_ERR(host->pmerrloc_base);
1222 goto err;
1c7b874d 1223 }
55750756
RI		 1224 host->pmerrloc_el_base = host->pmerrloc_base + ATMEL_PMERRLOC_SIGMAx +
1225 (host->caps->pmecc_max_correction + 1) * 4;
1c7b874d 1226
41c7540d
WJ		 1227 if (!host->has_no_lookup_table) {
1228 regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1229 host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev,
1230 regs_rom);
1231 if (IS_ERR(host->pmecc_rom_base)) {
abb1cd00 1232 dev_err(host->dev, "Can not get I/O resource for ROM, will build a lookup table in runtime!\n");
41c7540d
WJ		 1233 host->has_no_lookup_table = true;
1234 }
abb1cd00
JW		 1235 }
1236
1237 if (host->has_no_lookup_table) {
1238 /* Build the look-up table in runtime */
1239 galois_table = create_lookup_table(host->dev, sector_size);
1240 if (!galois_table) {
1241 dev_err(host->dev, "Failed to build a lookup table in runtime!\n");
1242 err_no = -EINVAL;
1243 goto err;
1244 }
1245
1246 host->pmecc_rom_base = (void __iomem *)galois_table;
1247 host->pmecc_lookup_table_offset = 0;
1c7b874d
JW		 1248 }
1249
b3857666 1250 nand_chip->ecc.size = sector_size;
1c7b874d
JW		 1251
1252 /* set ECC page size and oob layout */
1253 switch (mtd->writesize) {
a3557105
WJ		 1254 case 512:
1255 case 1024:
1c7b874d 1256 case 2048:
a3557105
WJ		 1257 case 4096:
1258 case 8192:
1259 if (sector_size > mtd->writesize) {
1260 dev_err(host->dev, "pmecc sector size is bigger than the page size!\n");
1261 err_no = -EINVAL;
1262 goto err;
1263 }
1264
2fa831f9
JW		 1265 host->pmecc_degree = (sector_size == 512) ?
1266 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
1c7b874d 1267 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
1c7b874d
JW		 1268 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
1269 host->pmecc_index_of = host->pmecc_rom_base +
1270 host->pmecc_lookup_table_offset;
1271
1c7b874d 1272 nand_chip->ecc.strength = cap;
022a478c 1273 nand_chip->ecc.bytes = pmecc_get_ecc_bytes(cap, sector_size);
c9447fff
WJ		 1274 nand_chip->ecc.steps = mtd->writesize / sector_size;
1275 nand_chip->ecc.total = nand_chip->ecc.bytes *
1276 nand_chip->ecc.steps;
477478ae
JW		 1277 if (nand_chip->ecc.total >
1278 mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
1c7b874d
JW		 1279 dev_err(host->dev, "No room for ECC bytes\n");
1280 err_no = -EINVAL;
0d63748d 1281 goto err;
1c7b874d
JW		 1282 }
1283 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
1284 mtd->oobsize,
b3857666
BS		 1285 nand_chip->ecc.total);
1286
1c7b874d
JW		 1287 nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
1288 break;
a3557105 1289 default:
1c7b874d
JW		 1290 dev_warn(host->dev,
1291 "Unsupported page size for PMECC, use Software ECC\n");
1c7b874d
JW		 1292 /* page size not handled by HW ECC */
1293 /* switching back to soft ECC */
1294 nand_chip->ecc.mode = NAND_ECC_SOFT;
1295 return 0;
1296 }
1297
1298 /* Allocate data for PMECC computation */
1299 err_no = pmecc_data_alloc(host);
1300 if (err_no) {
1301 dev_err(host->dev,
1302 "Cannot allocate memory for PMECC computation!\n");
0d63748d 1303 goto err;
1c7b874d
JW		 1304 }
1305
90445ff6 1306 nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
1c7b874d
JW		 1307 nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
1308 nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1309
1310 atmel_pmecc_core_init(mtd);
1311
1312 return 0;
1313
0d63748d 1314err:
1c7b874d
JW		 1315 return err_no;
1316}
1317
77f5492c
RG		 1318/*
1319 * Calculate HW ECC
1320 *
1321 * function called after a write
1322 *
1323 * mtd: MTD block structure
1324 * dat: raw data (unused)
1325 * ecc_code: buffer for ECC
1326 */
3c3796cc 1327static int atmel_nand_calculate(struct mtd_info *mtd,
77f5492c
RG		 1328 const u_char *dat, unsigned char *ecc_code)
1329{
4bd4ebcc 1330 struct nand_chip *nand_chip = mtd_to_nand(mtd);
d699ed25 1331 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
77f5492c
RG		 1332 unsigned int ecc_value;
1333
1334 /* get the first 2 ECC bytes */
d43fa149 1335 ecc_value = ecc_readl(host->ecc, PR);
77f5492c 1336
3fc23898
RG		 1337 ecc_code[0] = ecc_value & 0xFF;
1338 ecc_code[1] = (ecc_value >> 8) & 0xFF;
77f5492c
RG		 1339
1340 /* get the last 2 ECC bytes */
3c3796cc 1341 ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
77f5492c 1342
3fc23898
RG		 1343 ecc_code[2] = ecc_value & 0xFF;
1344 ecc_code[3] = (ecc_value >> 8) & 0xFF;
77f5492c
RG		 1345
1346 return 0;
1347}
1348
1349/*
1350 * HW ECC read page function
1351 *
1352 * mtd: mtd info structure
1353 * chip: nand chip info structure
1354 * buf: buffer to store read data
1fbb938d 1355 * oob_required: caller expects OOB data read to chip->oob_poi
77f5492c 1356 */
1fbb938d
BN		 1357static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1358 uint8_t *buf, int oob_required, int page)
77f5492c
RG		 1359{
1360 int eccsize = chip->ecc.size;
1361 int eccbytes = chip->ecc.bytes;
1362 uint32_t *eccpos = chip->ecc.layout->eccpos;
1363 uint8_t *p = buf;
1364 uint8_t *oob = chip->oob_poi;
1365 uint8_t *ecc_pos;
1366 int stat;
3f91e94f 1367 unsigned int max_bitflips = 0;
77f5492c 1368
d6248fdd
HS		 1369 /*
1370 * Errata: ALE is incorrectly wired up to the ECC controller
1371 * on the AP7000, so it will include the address cycles in the
1372 * ECC calculation.
1373 *
1374 * Workaround: Reset the parity registers before reading the
1375 * actual data.
1376 */
d699ed25 1377 struct atmel_nand_host *host = nand_get_controller_data(chip);
71b94e2e 1378 if (host->board.need_reset_workaround)
d6248fdd 1379 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
d6248fdd 1380
77f5492c
RG		 1381 /* read the page */
1382 chip->read_buf(mtd, p, eccsize);
1383
1384 /* move to ECC position if needed */
1385 if (eccpos[0] != 0) {
1386 /* This only works on large pages
1387 * because the ECC controller waits for
1388 * NAND_CMD_RNDOUTSTART after the
1389 * NAND_CMD_RNDOUT.
1390 * anyway, for small pages, the eccpos[0] == 0
1391 */
1392 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1393 mtd->writesize + eccpos[0], -1);
1394 }
1395
1396 /* the ECC controller needs to read the ECC just after the data */
1397 ecc_pos = oob + eccpos[0];
1398 chip->read_buf(mtd, ecc_pos, eccbytes);
1399
1400 /* check if there's an error */
1401 stat = chip->ecc.correct(mtd, p, oob, NULL);
1402
3f91e94f 1403 if (stat < 0) {
77f5492c 1404 mtd->ecc_stats.failed++;
3f91e94f 1405 } else {
77f5492c 1406 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1407 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1408 }
77f5492c
RG		 1409
1410 /* get back to oob start (end of page) */
1411 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1412
1413 /* read the oob */
1414 chip->read_buf(mtd, oob, mtd->oobsize);
1415
3f91e94f 1416 return max_bitflips;
77f5492c
RG		 1417}
1418
1419/*
1420 * HW ECC Correction
1421 *
1422 * function called after a read
1423 *
1424 * mtd: MTD block structure
1425 * dat: raw data read from the chip
1426 * read_ecc: ECC from the chip (unused)
1427 * isnull: unused
1428 *
1429 * Detect and correct a 1 bit error for a page
1430 */
3c3796cc 1431static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
77f5492c
RG		 1432 u_char *read_ecc, u_char *isnull)
1433{
4bd4ebcc 1434 struct nand_chip *nand_chip = mtd_to_nand(mtd);
d699ed25 1435 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
77f5492c
RG		 1436 unsigned int ecc_status;
1437 unsigned int ecc_word, ecc_bit;
1438
1439 /* get the status from the Status Register */
1440 ecc_status = ecc_readl(host->ecc, SR);
1441
1442 /* if there's no error */
3c3796cc 1443 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
77f5492c
RG		 1444 return 0;
1445
1446 /* get error bit offset (4 bits) */
3c3796cc 1447 ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
77f5492c 1448 /* get word address (12 bits) */
3c3796cc 1449 ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
77f5492c
RG		 1450 ecc_word >>= 4;
1451
1452 /* if there are multiple errors */
3c3796cc 1453 if (ecc_status & ATMEL_ECC_MULERR) {
77f5492c
RG		 1454 /* check if it is a freshly erased block
1455 * (filled with 0xff) */
3c3796cc
HS		 1456 if ((ecc_bit == ATMEL_ECC_BITADDR)
1457 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
77f5492c
RG		 1458 /* the block has just been erased, return OK */
1459 return 0;
1460 }
1461 /* it doesn't seems to be a freshly
1462 * erased block.
1463 * We can't correct so many errors */
3c3796cc 1464 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
77f5492c 1465 " Unable to correct.\n");
6e941192 1466 return -EBADMSG;
77f5492c
RG		 1467 }
1468
1469 /* if there's a single bit error : we can correct it */
3c3796cc 1470 if (ecc_status & ATMEL_ECC_ECCERR) {
77f5492c
RG		 1471 /* there's nothing much to do here.
1472 * the bit error is on the ECC itself.
1473 */
3c3796cc 1474 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
77f5492c
RG		 1475 " Nothing to correct\n");
1476 return 0;
1477 }
1478
3c3796cc 1479 dev_dbg(host->dev, "atmel_nand : one bit error on data."
77f5492c
RG		 1480 " (word offset in the page :"
1481 " 0x%x bit offset : 0x%x)\n",
1482 ecc_word, ecc_bit);
1483 /* correct the error */
1484 if (nand_chip->options & NAND_BUSWIDTH_16) {
1485 /* 16 bits words */
1486 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1487 } else {
1488 /* 8 bits words */
1489 dat[ecc_word] ^= (1 << ecc_bit);
1490 }
3c3796cc 1491 dev_dbg(host->dev, "atmel_nand : error corrected\n");
77f5492c
RG		 1492 return 1;
1493}
1494
1495/*
d6248fdd 1496 * Enable HW ECC : unused on most chips
77f5492c 1497 */
d6248fdd
HS		 1498static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1499{
4bd4ebcc 1500 struct nand_chip *nand_chip = mtd_to_nand(mtd);
d699ed25 1501 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
71b94e2e
JW		 1502
1503 if (host->board.need_reset_workaround)
d6248fdd 1504 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
d6248fdd 1505}
77f5492c 1506
4f3cab9b
BB		 1507static int atmel_of_init_ecc(struct atmel_nand_host *host,
1508 struct device_node *np)
d6a01661 1509{
a41b51a1 1510 u32 offset[2];
4f3cab9b 1511 u32 val;
d6a01661 1512
a41b51a1
JW		 1513 host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1514
4f3cab9b
BB		 1515 /* Not using PMECC */
1516 if (!(host->nand_chip.ecc.mode == NAND_ECC_HW) || !host->has_pmecc)
1517 return 0;
a41b51a1
JW		 1518
1519 /* use PMECC, get correction capability, sector size and lookup
1520 * table offset.
e66b4318
JW		 1521 * If correction bits and sector size are not specified, then find
1522 * them from NAND ONFI parameters.
a41b51a1 1523 */
e66b4318 1524 if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
94248462
RI		 1525 if (val > host->caps->pmecc_max_correction) {
1526 dev_err(host->dev,
1527 "Required ECC strength too high: %u max %u\n",
1528 val, host->caps->pmecc_max_correction);
1529 return -EINVAL;
1530 }
1531 if ((val != 2) && (val != 4) && (val != 8) &&
1532 (val != 12) && (val != 24) && (val != 32)) {
e66b4318 1533 dev_err(host->dev,
e88b7f7d 1534 "Required ECC strength not supported: %u\n",
e66b4318
JW		 1535 val);
1536 return -EINVAL;
1537 }
1538 host->pmecc_corr_cap = (u8)val;
a41b51a1 1539 }
a41b51a1 1540
e66b4318
JW		 1541 if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
1542 if ((val != 512) && (val != 1024)) {
1543 dev_err(host->dev,
e88b7f7d 1544 "Required ECC sector size not supported: %u\n",
e66b4318
JW		 1545 val);
1546 return -EINVAL;
1547 }
1548 host->pmecc_sector_size = (u16)val;
a41b51a1 1549 }
a41b51a1
JW		 1550
1551 if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1552 offset, 2) != 0) {
abb1cd00
JW		 1553 dev_err(host->dev, "Cannot get PMECC lookup table offset, will build a lookup table in runtime.\n");
1554 host->has_no_lookup_table = true;
1555 /* Will build a lookup table and initialize the offset later */
1556 return 0;
a41b51a1 1557 }
4f3cab9b 1558
c0cf787f 1559 if (!offset[0] && !offset[1]) {
a41b51a1
JW		 1560 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1561 return -EINVAL;
1562 }
4f3cab9b 1563
e66b4318
JW		 1564 host->pmecc_lookup_table_offset_512 = offset[0];
1565 host->pmecc_lookup_table_offset_1024 = offset[1];
a41b51a1 1566
d6a01661
JCPV		 1567 return 0;
1568}
d6a01661 1569
4f3cab9b
BB		 1570static int atmel_of_init_port(struct atmel_nand_host *host,
1571 struct device_node *np)
1572{
1573 u32 val;
1574 struct atmel_nand_data *board = &host->board;
1575 enum of_gpio_flags flags = 0;
1576
1577 host->caps = (struct atmel_nand_caps *)
1578 of_device_get_match_data(host->dev);
1579
1580 if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
1581 if (val >= 32) {
1582 dev_err(host->dev, "invalid addr-offset %u\n", val);
1583 return -EINVAL;
1584 }
1585 board->ale = val;
1586 }
1587
1588 if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
1589 if (val >= 32) {
1590 dev_err(host->dev, "invalid cmd-offset %u\n", val);
1591 return -EINVAL;
1592 }
1593 board->cle = val;
1594 }
1595
1596 board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma");
1597
1598 board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
1599 board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
1600
1601 board->enable_pin = of_get_gpio(np, 1);
1602 board->det_pin = of_get_gpio(np, 2);
1603
1604 /* load the nfc driver if there is */
1605 of_platform_populate(np, NULL, NULL, host->dev);
1606
1607 /*
1608 * Initialize ECC mode to NAND_ECC_SOFT so that we have a correct value
1609 * even if the nand-ecc-mode property is not defined.
1610 */
1611 host->nand_chip.ecc.mode = NAND_ECC_SOFT;
1612
1613 return 0;
1614}
1615
2c2b9285 1616static int atmel_hw_nand_init_params(struct platform_device *pdev,
3dfe41a4
JW		 1617 struct atmel_nand_host *host)
1618{
3dfe41a4 1619 struct nand_chip *nand_chip = &host->nand_chip;
ac01efeb 1620 struct mtd_info *mtd = nand_to_mtd(nand_chip);
3dfe41a4
JW		 1621 struct resource *regs;
1622
1623 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1624 if (!regs) {
1625 dev_err(host->dev,
1626 "Can't get I/O resource regs, use software ECC\n");
1627 nand_chip->ecc.mode = NAND_ECC_SOFT;
1628 return 0;
1629 }
1630
0d63748d 1631 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
8fb7b930 1632 if (IS_ERR(host->ecc))
0d63748d 1633 return PTR_ERR(host->ecc);
3dfe41a4
JW		 1634
1635 /* ECC is calculated for the whole page (1 step) */
1636 nand_chip->ecc.size = mtd->writesize;
1637
1638 /* set ECC page size and oob layout */
1639 switch (mtd->writesize) {
1640 case 512:
1641 nand_chip->ecc.layout = &atmel_oobinfo_small;
1642 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1643 break;
1644 case 1024:
1645 nand_chip->ecc.layout = &atmel_oobinfo_large;
1646 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1647 break;
1648 case 2048:
1649 nand_chip->ecc.layout = &atmel_oobinfo_large;
1650 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1651 break;
1652 case 4096:
1653 nand_chip->ecc.layout = &atmel_oobinfo_large;
1654 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1655 break;
1656 default:
1657 /* page size not handled by HW ECC */
1658 /* switching back to soft ECC */
1659 nand_chip->ecc.mode = NAND_ECC_SOFT;
1660 return 0;
1661 }
1662
1663 /* set up for HW ECC */
1664 nand_chip->ecc.calculate = atmel_nand_calculate;
1665 nand_chip->ecc.correct = atmel_nand_correct;
1666 nand_chip->ecc.hwctl = atmel_nand_hwctl;
1667 nand_chip->ecc.read_page = atmel_nand_read_page;
1668 nand_chip->ecc.bytes = 4;
1669 nand_chip->ecc.strength = 1;
1670
1671 return 0;
1672}
1673
50e04e2f
WJ		 1674static inline u32 nfc_read_status(struct atmel_nand_host *host)
1675{
1676 u32 err_flags = NFC_SR_DTOE | NFC_SR_UNDEF | NFC_SR_AWB | NFC_SR_ASE;
1677 u32 nfc_status = nfc_readl(host->nfc->hsmc_regs, SR);
1678
1679 if (unlikely(nfc_status & err_flags)) {
1680 if (nfc_status & NFC_SR_DTOE)
1681 dev_err(host->dev, "NFC: Waiting Nand R/B Timeout Error\n");
1682 else if (nfc_status & NFC_SR_UNDEF)
1683 dev_err(host->dev, "NFC: Access Undefined Area Error\n");
1684 else if (nfc_status & NFC_SR_AWB)
1685 dev_err(host->dev, "NFC: Access memory While NFC is busy\n");
1686 else if (nfc_status & NFC_SR_ASE)
1687 dev_err(host->dev, "NFC: Access memory Size Error\n");
1688 }
1689
1690 return nfc_status;
1691}
1692
7dc37de7
JW		 1693/* SMC interrupt service routine */
1694static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
1695{
1696 struct atmel_nand_host *host = dev_id;
1697 u32 status, mask, pending;
e4e06934 1698 irqreturn_t ret = IRQ_NONE;
7dc37de7 1699
50e04e2f 1700 status = nfc_read_status(host);
7dc37de7
JW		 1701 mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1702 pending = status & mask;
1703
1704 if (pending & NFC_SR_XFR_DONE) {
e4e06934 1705 complete(&host->nfc->comp_xfer_done);
7dc37de7 1706 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
e4e06934
JW		 1707 ret = IRQ_HANDLED;
1708 }
5ddc7bd4 1709 if (pending & host->nfc->caps->rb_mask) {
e4e06934 1710 complete(&host->nfc->comp_ready);
5ddc7bd4 1711 nfc_writel(host->nfc->hsmc_regs, IDR, host->nfc->caps->rb_mask);
e4e06934
JW		 1712 ret = IRQ_HANDLED;
1713 }
1714 if (pending & NFC_SR_CMD_DONE) {
1715 complete(&host->nfc->comp_cmd_done);
7dc37de7 1716 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_CMD_DONE);
e4e06934 1717 ret = IRQ_HANDLED;
7dc37de7
JW		 1718 }
1719
1720 return ret;
1721}
1722
1723/* NFC(Nand Flash Controller) related functions */
e4e06934 1724static void nfc_prepare_interrupt(struct atmel_nand_host *host, u32 flag)
7dc37de7 1725{
e4e06934
JW		 1726 if (flag & NFC_SR_XFR_DONE)
1727 init_completion(&host->nfc->comp_xfer_done);
1728
5ddc7bd4 1729 if (flag & host->nfc->caps->rb_mask)
e4e06934
JW		 1730 init_completion(&host->nfc->comp_ready);
1731
1732 if (flag & NFC_SR_CMD_DONE)
1733 init_completion(&host->nfc->comp_cmd_done);
7dc37de7
JW		 1734
1735 /* Enable interrupt that need to wait for */
1736 nfc_writel(host->nfc->hsmc_regs, IER, flag);
e4e06934 1737}
7dc37de7 1738
e4e06934
JW		 1739static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
1740{
1741 int i, index = 0;
1742 struct completion *comp[3]; /* Support 3 interrupt completion */
1743
1744 if (flag & NFC_SR_XFR_DONE)
1745 comp[index++] = &host->nfc->comp_xfer_done;
1746
5ddc7bd4 1747 if (flag & host->nfc->caps->rb_mask)
e4e06934 1748 comp[index++] = &host->nfc->comp_ready;
7dc37de7 1749
e4e06934
JW		 1750 if (flag & NFC_SR_CMD_DONE)
1751 comp[index++] = &host->nfc->comp_cmd_done;
1752
1753 if (index == 0) {
393d23c4 1754 dev_err(host->dev, "Unknown interrupt flag: 0x%08x\n", flag);
e4e06934
JW		 1755 return -EINVAL;
1756 }
1757
1758 for (i = 0; i < index; i++) {
1759 if (wait_for_completion_timeout(comp[i],
1760 msecs_to_jiffies(NFC_TIME_OUT_MS)))
1761 continue; /* wait for next completion */
1762 else
1763 goto err_timeout;
1764 }
1765
1766 return 0;
1767
1768err_timeout:
7dc37de7 1769 dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag);
e4e06934
JW		 1770 /* Disable the interrupt as it is not handled by interrupt handler */
1771 nfc_writel(host->nfc->hsmc_regs, IDR, flag);
7dc37de7
JW		 1772 return -ETIMEDOUT;
1773}
1774
1775static int nfc_send_command(struct atmel_nand_host *host,
1776 unsigned int cmd, unsigned int addr, unsigned char cycle0)
1777{
1778 unsigned long timeout;
e4e06934
JW		 1779 u32 flag = NFC_SR_CMD_DONE;
1780 flag |= cmd & NFCADDR_CMD_DATAEN ? NFC_SR_XFR_DONE : 0;
1781
7dc37de7
JW		 1782 dev_dbg(host->dev,
1783 "nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
1784 cmd, addr, cycle0);
1785
1786 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
111573cc 1787 while (nfc_readl(host->nfc->hsmc_regs, SR) & NFC_SR_BUSY) {
7dc37de7
JW		 1788 if (time_after(jiffies, timeout)) {
1789 dev_err(host->dev,
111573cc 1790 "Time out to wait for NFC ready!\n");
7dc37de7
JW		 1791 return -ETIMEDOUT;
1792 }
1793 }
e4e06934
JW		 1794
1795 nfc_prepare_interrupt(host, flag);
7dc37de7
JW		 1796 nfc_writel(host->nfc->hsmc_regs, CYCLE0, cycle0);
1797 nfc_cmd_addr1234_writel(cmd, addr, host->nfc->base_cmd_regs);
e4e06934 1798 return nfc_wait_interrupt(host, flag);
7dc37de7
JW		 1799}
1800
1801static int nfc_device_ready(struct mtd_info *mtd)
1802{
72a78e3c 1803 u32 status, mask;
4bd4ebcc 1804 struct nand_chip *nand_chip = mtd_to_nand(mtd);
d699ed25 1805 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
72a78e3c
WJ		 1806
1807 status = nfc_read_status(host);
1808 mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1809
1810 /* The mask should be 0. If not we may lost interrupts */
1811 if (unlikely(mask & status))
1812 dev_err(host->dev, "Lost the interrupt flags: 0x%08x\n",
1813 mask & status);
1814
5ddc7bd4 1815 return status & host->nfc->caps->rb_mask;
7dc37de7
JW		 1816}
1817
1818static void nfc_select_chip(struct mtd_info *mtd, int chip)
1819{
4bd4ebcc 1820 struct nand_chip *nand_chip = mtd_to_nand(mtd);
d699ed25 1821 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
7dc37de7
JW		 1822
1823 if (chip == -1)
1824 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_DISABLE);
1825 else
1826 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_ENABLE);
1827}
1828
3dad2344
BN		 1829static int nfc_make_addr(struct mtd_info *mtd, int command, int column,
1830 int page_addr, unsigned int *addr1234, unsigned int *cycle0)
7dc37de7 1831{
4bd4ebcc 1832 struct nand_chip *chip = mtd_to_nand(mtd);
7dc37de7
JW		 1833
1834 int acycle = 0;
1835 unsigned char addr_bytes[8];
1836 int index = 0, bit_shift;
1837
1838 BUG_ON(addr1234 == NULL || cycle0 == NULL);
1839
1840 *cycle0 = 0;
1841 *addr1234 = 0;
1842
1843 if (column != -1) {
3dad2344
BN		 1844 if (chip->options & NAND_BUSWIDTH_16 &&
1845 !nand_opcode_8bits(command))
7dc37de7
JW		 1846 column >>= 1;
1847 addr_bytes[acycle++] = column & 0xff;
1848 if (mtd->writesize > 512)
1849 addr_bytes[acycle++] = (column >> 8) & 0xff;
1850 }
1851
1852 if (page_addr != -1) {
1853 addr_bytes[acycle++] = page_addr & 0xff;
1854 addr_bytes[acycle++] = (page_addr >> 8) & 0xff;
1855 if (chip->chipsize > (128 << 20))
1856 addr_bytes[acycle++] = (page_addr >> 16) & 0xff;
1857 }
1858
1859 if (acycle > 4)
1860 *cycle0 = addr_bytes[index++];
1861
1862 for (bit_shift = 0; index < acycle; bit_shift += 8)
1863 *addr1234 += addr_bytes[index++] << bit_shift;
1864
1865 /* return acycle in cmd register */
1866 return acycle << NFCADDR_CMD_ACYCLE_BIT_POS;
1867}
1868
1869static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
1870 int column, int page_addr)
1871{
4bd4ebcc 1872 struct nand_chip *chip = mtd_to_nand(mtd);
d699ed25 1873 struct atmel_nand_host *host = nand_get_controller_data(chip);
7dc37de7
JW		 1874 unsigned long timeout;
1875 unsigned int nfc_addr_cmd = 0;
1876
1877 unsigned int cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1878
1879 /* Set default settings: no cmd2, no addr cycle. read from nand */
1880 unsigned int cmd2 = 0;
1881 unsigned int vcmd2 = 0;
1882 int acycle = NFCADDR_CMD_ACYCLE_NONE;
1883 int csid = NFCADDR_CMD_CSID_3;
1884 int dataen = NFCADDR_CMD_DATADIS;
1885 int nfcwr = NFCADDR_CMD_NFCRD;
1886 unsigned int addr1234 = 0;
1887 unsigned int cycle0 = 0;
1888 bool do_addr = true;
1ae9c092 1889 host->nfc->data_in_sram = NULL;
7dc37de7
JW		 1890
1891 dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
1892 __func__, command, column, page_addr);
1893
1894 switch (command) {
1895 case NAND_CMD_RESET:
1896 nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr;
1897 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1898 udelay(chip->chip_delay);
1899
1900 nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
1901 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1902 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) {
1903 if (time_after(jiffies, timeout)) {
1904 dev_err(host->dev,
1905 "Time out to wait status ready!\n");
1906 break;
1907 }
1908 }
1909 return;
1910 case NAND_CMD_STATUS:
1911 do_addr = false;
1912 break;
1913 case NAND_CMD_PARAM:
1914 case NAND_CMD_READID:
1915 do_addr = false;
1916 acycle = NFCADDR_CMD_ACYCLE_1;
1917 if (column != -1)
1918 addr1234 = column;
1919 break;
1920 case NAND_CMD_RNDOUT:
1921 cmd2 = NAND_CMD_RNDOUTSTART << NFCADDR_CMD_CMD2_BIT_POS;
1922 vcmd2 = NFCADDR_CMD_VCMD2;
1923 break;
1924 case NAND_CMD_READ0:
1925 case NAND_CMD_READOOB:
1926 if (command == NAND_CMD_READOOB) {
1927 column += mtd->writesize;
1928 command = NAND_CMD_READ0; /* only READ0 is valid */
1929 cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1930 }
1ae9c092
JW		 1931 if (host->nfc->use_nfc_sram) {
1932 /* Enable Data transfer to sram */
1933 dataen = NFCADDR_CMD_DATAEN;
1934
1935 /* Need enable PMECC now, since NFC will transfer
1936 * data in bus after sending nfc read command.
1937 */
1938 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1939 pmecc_enable(host, NAND_ECC_READ);
1940 }
7dc37de7
JW		 1941
1942 cmd2 = NAND_CMD_READSTART << NFCADDR_CMD_CMD2_BIT_POS;
1943 vcmd2 = NFCADDR_CMD_VCMD2;
1944 break;
1945 /* For prgramming command, the cmd need set to write enable */
1946 case NAND_CMD_PAGEPROG:
1947 case NAND_CMD_SEQIN:
1948 case NAND_CMD_RNDIN:
1949 nfcwr = NFCADDR_CMD_NFCWR;
6054d4d5
JW		 1950 if (host->nfc->will_write_sram && command == NAND_CMD_SEQIN)
1951 dataen = NFCADDR_CMD_DATAEN;
7dc37de7
JW		 1952 break;
1953 default:
1954 break;
1955 }
1956
1957 if (do_addr)
3dad2344
BN		 1958 acycle = nfc_make_addr(mtd, command, column, page_addr,
1959 &addr1234, &cycle0);
7dc37de7
JW		 1960
1961 nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
1962 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1963
1964 /*
1965 * Program and erase have their own busy handlers status, sequential
1966 * in, and deplete1 need no delay.
1967 */
1968 switch (command) {
1969 case NAND_CMD_CACHEDPROG:
1970 case NAND_CMD_PAGEPROG:
1971 case NAND_CMD_ERASE1:
1972 case NAND_CMD_ERASE2:
1973 case NAND_CMD_RNDIN:
1974 case NAND_CMD_STATUS:
1975 case NAND_CMD_RNDOUT:
1976 case NAND_CMD_SEQIN:
1977 case NAND_CMD_READID:
1978 return;
1979
1980 case NAND_CMD_READ0:
1ae9c092
JW		 1981 if (dataen == NFCADDR_CMD_DATAEN) {
1982 host->nfc->data_in_sram = host->nfc->sram_bank0 +
1983 nfc_get_sram_off(host);
1984 return;
1985 }
7dc37de7
JW		 1986 /* fall through */
1987 default:
5ddc7bd4
RI		 1988 nfc_prepare_interrupt(host, host->nfc->caps->rb_mask);
1989 nfc_wait_interrupt(host, host->nfc->caps->rb_mask);
7dc37de7
JW		 1990 }
1991}
1992
6054d4d5
JW		 1993static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1994 uint32_t offset, int data_len, const uint8_t *buf,
1995 int oob_required, int page, int cached, int raw)
1996{
1997 int cfg, len;
1998 int status = 0;
d699ed25 1999 struct atmel_nand_host *host = nand_get_controller_data(chip);
068b44b7 2000 void *sram = host->nfc->sram_bank0 + nfc_get_sram_off(host);
6054d4d5
JW		 2001
2002 /* Subpage write is not supported */
2003 if (offset || (data_len < mtd->writesize))
2004 return -EINVAL;
2005
6054d4d5 2006 len = mtd->writesize;
6054d4d5
JW		 2007 /* Copy page data to sram that will write to nand via NFC */
2008 if (use_dma) {
2009 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0)
2010 /* Fall back to use cpu copy */
068b44b7 2011 memcpy(sram, buf, len);
6054d4d5 2012 } else {
068b44b7 2013 memcpy(sram, buf, len);
6054d4d5
JW		 2014 }
2015
ff0a2154
WJ		 2016 cfg = nfc_readl(host->nfc->hsmc_regs, CFG);
2017 if (unlikely(raw) && oob_required) {
068b44b7 2018 memcpy(sram + len, chip->oob_poi, mtd->oobsize);
ff0a2154
WJ		 2019 len += mtd->oobsize;
2020 nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE);
2021 } else {
2022 nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE);
2023 }
2024
6054d4d5
JW		 2025 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
2026 /*
2027 * When use NFC sram, need set up PMECC before send
2028 * NAND_CMD_SEQIN command. Since when the nand command
2029 * is sent, nfc will do transfer from sram and nand.
2030 */
2031 pmecc_enable(host, NAND_ECC_WRITE);
2032
2033 host->nfc->will_write_sram = true;
2034 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2035 host->nfc->will_write_sram = false;
2036
2037 if (likely(!raw))
2038 /* Need to write ecc into oob */
45aaeff9
BB		 2039 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
2040 page);
6054d4d5
JW		 2041
2042 if (status < 0)
2043 return status;
2044
2045 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2046 status = chip->waitfunc(mtd, chip);
2047
2048 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2049 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
2050
2051 if (status & NAND_STATUS_FAIL)
2052 return -EIO;
2053
2054 return 0;
2055}
2056
1ae9c092
JW		 2057static int nfc_sram_init(struct mtd_info *mtd)
2058{
4bd4ebcc 2059 struct nand_chip *chip = mtd_to_nand(mtd);
d699ed25 2060 struct atmel_nand_host *host = nand_get_controller_data(chip);
1ae9c092
JW		 2061 int res = 0;
2062
2063 /* Initialize the NFC CFG register */
2064 unsigned int cfg_nfc = 0;
2065
2066 /* set page size and oob layout */
2067 switch (mtd->writesize) {
2068 case 512:
2069 cfg_nfc = NFC_CFG_PAGESIZE_512;
2070 break;
2071 case 1024:
2072 cfg_nfc = NFC_CFG_PAGESIZE_1024;
2073 break;
2074 case 2048:
2075 cfg_nfc = NFC_CFG_PAGESIZE_2048;
2076 break;
2077 case 4096:
2078 cfg_nfc = NFC_CFG_PAGESIZE_4096;
2079 break;
2080 case 8192:
2081 cfg_nfc = NFC_CFG_PAGESIZE_8192;
2082 break;
2083 default:
2084 dev_err(host->dev, "Unsupported page size for NFC.\n");
2085 res = -ENXIO;
2086 return res;
2087 }
2088
2089 /* oob bytes size = (NFCSPARESIZE + 1) * 4
2090 * Max support spare size is 512 bytes. */
2091 cfg_nfc |= (((mtd->oobsize / 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS
2092 & NFC_CFG_NFC_SPARESIZE);
2093 /* default set a max timeout */
2094 cfg_nfc |= NFC_CFG_RSPARE |
2095 NFC_CFG_NFC_DTOCYC | NFC_CFG_NFC_DTOMUL;
2096
2097 nfc_writel(host->nfc->hsmc_regs, CFG, cfg_nfc);
2098
6054d4d5 2099 host->nfc->will_write_sram = false;
1ae9c092
JW		 2100 nfc_set_sram_bank(host, 0);
2101
6054d4d5
JW		 2102 /* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
2103 if (host->nfc->write_by_sram) {
2104 if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) ||
2105 chip->ecc.mode == NAND_ECC_NONE)
2106 chip->write_page = nfc_sram_write_page;
2107 else
2108 host->nfc->write_by_sram = false;
2109 }
1ae9c092 2110
6054d4d5
JW		 2111 dev_info(host->dev, "Using NFC Sram read %s\n",
2112 host->nfc->write_by_sram ? "and write" : "");
1ae9c092
JW		 2113 return 0;
2114}
2115
7dc37de7 2116static struct platform_driver atmel_nand_nfc_driver;
42cb1403
AV		 2117/*
2118 * Probe for the NAND device.
2119 */
2c2b9285 2120static int atmel_nand_probe(struct platform_device *pdev)
42cb1403 2121{
3c3796cc 2122 struct atmel_nand_host *host;
42cb1403
AV		 2123 struct mtd_info *mtd;
2124 struct nand_chip *nand_chip;
77f5492c 2125 struct resource *mem;
7dc37de7 2126 int res, irq;
42cb1403
AV		 2127
2128 /* Allocate memory for the device structure (and zero it) */
0d63748d 2129 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
9e3677a8 2130 if (!host)
42cb1403 2131 return -ENOMEM;
42cb1403 2132
7dc37de7
JW		 2133 res = platform_driver_register(&atmel_nand_nfc_driver);
2134 if (res)
2135 dev_err(&pdev->dev, "atmel_nand: can't register NFC driver\n");
2136
0d63748d
JCPV		 2137 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2138 host->io_base = devm_ioremap_resource(&pdev->dev, mem);
2139 if (IS_ERR(host->io_base)) {
0d63748d 2140 res = PTR_ERR(host->io_base);
cc0c72e1 2141 goto err_nand_ioremap;
42cb1403 2142 }
0d63748d 2143 host->io_phys = (dma_addr_t)mem->start;
42cb1403 2144
42cb1403 2145 nand_chip = &host->nand_chip;
ac01efeb 2146 mtd = nand_to_mtd(nand_chip);
77f5492c 2147 host->dev = &pdev->dev;
e9d8da80 2148 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
a61ae81a 2149 nand_set_flash_node(nand_chip, pdev->dev.of_node);
e9d8da80 2150 /* Only when CONFIG_OF is enabled of_node can be parsed */
d6a01661
JCPV		 2151 res = atmel_of_init_port(host, pdev->dev.of_node);
2152 if (res)
0d63748d 2153 goto err_nand_ioremap;
d6a01661 2154 } else {
453810b7 2155 memcpy(&host->board, dev_get_platdata(&pdev->dev),
d6a01661 2156 sizeof(struct atmel_nand_data));
4f3cab9b
BB		 2157 nand_chip->ecc.mode = host->board.ecc_mode;
2158
2159 /* 16-bit bus width */
2160 if (host->board.bus_width_16)
2161 nand_chip->options |= NAND_BUSWIDTH_16;
d6a01661 2162 }
42cb1403 2163
d699ed25
BB		 2164 /* link the private data structures */
2165 nand_set_controller_data(nand_chip, host);
03c287d2 2166 mtd->dev.parent = &pdev->dev;
42cb1403
AV		 2167
2168 /* Set address of NAND IO lines */
2169 nand_chip->IO_ADDR_R = host->io_base;
2170 nand_chip->IO_ADDR_W = host->io_base;
28446acb 2171
7dc37de7
JW		 2172 if (nand_nfc.is_initialized) {
2173 /* NFC driver is probed and initialized */
2174 host->nfc = &nand_nfc;
28446acb 2175
7dc37de7
JW		 2176 nand_chip->select_chip = nfc_select_chip;
2177 nand_chip->dev_ready = nfc_device_ready;
2178 nand_chip->cmdfunc = nfc_nand_command;
28446acb 2179
7dc37de7
JW		 2180 /* Initialize the interrupt for NFC */
2181 irq = platform_get_irq(pdev, 0);
2182 if (irq < 0) {
2183 dev_err(host->dev, "Cannot get HSMC irq!\n");
ff52c67a 2184 res = irq;
0d63748d 2185 goto err_nand_ioremap;
28446acb
JCPV		 2186 }
2187
7dc37de7
JW		 2188 res = devm_request_irq(&pdev->dev, irq, hsmc_interrupt,
2189 0, "hsmc", host);
2190 if (res) {
2191 dev_err(&pdev->dev, "Unable to request HSMC irq %d\n",
2192 irq);
0d63748d 2193 goto err_nand_ioremap;
28446acb 2194 }
7dc37de7
JW		 2195 } else {
2196 res = atmel_nand_set_enable_ready_pins(mtd);
2197 if (res)
2198 goto err_nand_ioremap;
2199
2200 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
28446acb 2201 }
a4265f8d 2202
796fe364 2203 nand_chip->chip_delay = 40; /* 40us command delay time */
42cb1403 2204
cbc6c5e7
HX		 2205
2206 nand_chip->read_buf = atmel_read_buf;
2207 nand_chip->write_buf = atmel_write_buf;
dd11b8cd 2208
42cb1403 2209 platform_set_drvdata(pdev, host);
3c3796cc 2210 atmel_nand_enable(host);
42cb1403 2211
d6a01661 2212 if (gpio_is_valid(host->board.det_pin)) {
0d63748d
JCPV		 2213 res = devm_gpio_request(&pdev->dev,
2214 host->board.det_pin, "nand_det");
28446acb
JCPV		 2215 if (res < 0) {
2216 dev_err(&pdev->dev,
2217 "can't request det gpio %d\n",
2218 host->board.det_pin);
2219 goto err_no_card;
2220 }
2221
2222 res = gpio_direction_input(host->board.det_pin);
2223 if (res < 0) {
2224 dev_err(&pdev->dev,
2225 "can't request input direction det gpio %d\n",
2226 host->board.det_pin);
2227 goto err_no_card;
2228 }
2229
d6a01661 2230 if (gpio_get_value(host->board.det_pin)) {
1295f970 2231 dev_info(&pdev->dev, "No SmartMedia card inserted.\n");
895fb494 2232 res = -ENXIO;
cc0c72e1 2233 goto err_no_card;
42cb1403
AV		 2234 }
2235 }
2236
1b719265 2237 if (!host->board.has_dma)
cb457a4d
HX		 2238 use_dma = 0;
2239
2240 if (use_dma) {
cbc6c5e7
HX		 2241 dma_cap_mask_t mask;
2242
2243 dma_cap_zero(mask);
2244 dma_cap_set(DMA_MEMCPY, mask);
201ab536 2245 host->dma_chan = dma_request_channel(mask, NULL, NULL);
cbc6c5e7
HX		 2246 if (!host->dma_chan) {
2247 dev_err(host->dev, "Failed to request DMA channel\n");
2248 use_dma = 0;
2249 }
2250 }
2251 if (use_dma)
042bc9c0
NF		 2252 dev_info(host->dev, "Using %s for DMA transfers.\n",
2253 dma_chan_name(host->dma_chan));
cbc6c5e7
HX		 2254 else
2255 dev_info(host->dev, "No DMA support for NAND access.\n");
2256
77f5492c 2257 /* first scan to find the device and get the page size */
5e81e88a 2258 if (nand_scan_ident(mtd, 1, NULL)) {
77f5492c 2259 res = -ENXIO;
cc0c72e1 2260 goto err_scan_ident;
77f5492c
RG		 2261 }
2262
4f3cab9b
BB		 2263 if (host->board.on_flash_bbt || on_flash_bbt)
2264 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
2265
2266 if (nand_chip->bbt_options & NAND_BBT_USE_FLASH)
2267 dev_info(&pdev->dev, "Use On Flash BBT\n");
2268
2269 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
2270 res = atmel_of_init_ecc(host, pdev->dev.of_node);
2271 if (res)
2272 goto err_hw_ecc;
2273 }
2274
3fc23898 2275 if (nand_chip->ecc.mode == NAND_ECC_HW) {
1c7b874d
JW		 2276 if (host->has_pmecc)
2277 res = atmel_pmecc_nand_init_params(pdev, host);
2278 else
2279 res = atmel_hw_nand_init_params(pdev, host);
2280
3dfe41a4
JW		 2281 if (res != 0)
2282 goto err_hw_ecc;
77f5492c
RG		 2283 }
2284
1ae9c092
JW		 2285 /* initialize the nfc configuration register */
2286 if (host->nfc && host->nfc->use_nfc_sram) {
2287 res = nfc_sram_init(mtd);
2288 if (res) {
2289 host->nfc->use_nfc_sram = false;
2290 dev_err(host->dev, "Disable use nfc sram for data transfer.\n");
2291 }
2292 }
2293
77f5492c
RG		 2294 /* second phase scan */
2295 if (nand_scan_tail(mtd)) {
42cb1403 2296 res = -ENXIO;
cc0c72e1 2297 goto err_scan_tail;
42cb1403
AV		 2298 }
2299
3c3796cc 2300 mtd->name = "atmel_nand";
a61ae81a
BN		 2301 res = mtd_device_register(mtd, host->board.parts,
2302 host->board.num_parts);
42cb1403
AV		 2303 if (!res)
2304 return res;
2305
cc0c72e1 2306err_scan_tail:
0d63748d 2307 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW)
1c7b874d 2308 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
3dfe41a4 2309err_hw_ecc:
cc0c72e1
HS		 2310err_scan_ident:
2311err_no_card:
3c3796cc 2312 atmel_nand_disable(host);
cbc6c5e7
HX		 2313 if (host->dma_chan)
2314 dma_release_channel(host->dma_chan);
cc0c72e1 2315err_nand_ioremap:
42cb1403
AV		 2316 return res;
2317}
2318
2319/*
2320 * Remove a NAND device.
2321 */
2c2b9285 2322static int atmel_nand_remove(struct platform_device *pdev)
42cb1403 2323{
3c3796cc 2324 struct atmel_nand_host *host = platform_get_drvdata(pdev);
ac01efeb 2325 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
42cb1403
AV		 2326
2327 nand_release(mtd);
2328
3c3796cc 2329 atmel_nand_disable(host);
42cb1403 2330
1c7b874d
JW		 2331 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
2332 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2333 pmerrloc_writel(host->pmerrloc_base, ELDIS,
2334 PMERRLOC_DISABLE);
1c7b874d
JW		 2335 }
2336
cbc6c5e7
HX		 2337 if (host->dma_chan)
2338 dma_release_channel(host->dma_chan);
2339
7dc37de7
JW		 2340 platform_driver_unregister(&atmel_nand_nfc_driver);
2341
42cb1403
AV		 2342 return 0;
2343}
2344
55750756
RI		 2345/*
2346 * AT91RM9200 does not have PMECC or PMECC Errloc peripherals for
2347 * BCH ECC. Combined with the "atmel,has-pmecc", it is used to describe
2348 * devices from the SAM9 family that have those.
2349 */
72eaec21 2350static const struct atmel_nand_caps at91rm9200_caps = {
51585778 2351 .pmecc_correct_erase_page = false,
55750756 2352 .pmecc_max_correction = 24,
51585778
WJ		 2353};
2354
72eaec21 2355static const struct atmel_nand_caps sama5d4_caps = {
51585778 2356 .pmecc_correct_erase_page = true,
55750756
RI		 2357 .pmecc_max_correction = 24,
2358};
2359
2360/*
2361 * The PMECC Errloc controller starting in SAMA5D2 is not compatible,
2362 * as the increased correction strength requires more registers.
2363 */
2364static const struct atmel_nand_caps sama5d2_caps = {
2365 .pmecc_correct_erase_page = true,
2366 .pmecc_max_correction = 32,
51585778
WJ		 2367};
2368
d6a01661 2369static const struct of_device_id atmel_nand_dt_ids[] = {
51585778
WJ		 2370 { .compatible = "atmel,at91rm9200-nand", .data = &at91rm9200_caps },
2371 { .compatible = "atmel,sama5d4-nand", .data = &sama5d4_caps },
55750756 2372 { .compatible = "atmel,sama5d2-nand", .data = &sama5d2_caps },
d6a01661
JCPV		 2373 { /* sentinel */ }
2374};
2375
2376MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
d6a01661 2377
7dc37de7
JW		 2378static int atmel_nand_nfc_probe(struct platform_device *pdev)
2379{
2380 struct atmel_nfc *nfc = &nand_nfc;
2381 struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
2d405ec5 2382 int ret;
7dc37de7
JW		 2383
2384 nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2385 nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs);
2386 if (IS_ERR(nfc->base_cmd_regs))
2387 return PTR_ERR(nfc->base_cmd_regs);
2388
2389 nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2390 nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs);
2391 if (IS_ERR(nfc->hsmc_regs))
2392 return PTR_ERR(nfc->hsmc_regs);
2393
2394 nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 2);
2395 if (nfc_sram) {
068b44b7
WJ		 2396 nfc->sram_bank0 = (void * __force)
2397 devm_ioremap_resource(&pdev->dev, nfc_sram);
1ae9c092 2398 if (IS_ERR(nfc->sram_bank0)) {
7dc37de7
JW		 2399 dev_warn(&pdev->dev, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n",
2400 PTR_ERR(nfc->sram_bank0));
1ae9c092
JW		 2401 } else {
2402 nfc->use_nfc_sram = true;
7dc37de7 2403 nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start;
6054d4d5
JW		 2404
2405 if (pdev->dev.of_node)
2406 nfc->write_by_sram = of_property_read_bool(
2407 pdev->dev.of_node,
2408 "atmel,write-by-sram");
1ae9c092 2409 }
7dc37de7
JW		 2410 }
2411
5ddc7bd4
RI		 2412 nfc->caps = (const struct atmel_nand_nfc_caps *)
2413 of_device_get_match_data(&pdev->dev);
2414 if (!nfc->caps)
2415 return -ENODEV;
2416
50e04e2f
WJ		 2417 nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
2418 nfc_readl(nfc->hsmc_regs, SR); /* clear the NFC_SR */
2419
2d405ec5
BB		 2420 nfc->clk = devm_clk_get(&pdev->dev, NULL);
2421 if (!IS_ERR(nfc->clk)) {
2422 ret = clk_prepare_enable(nfc->clk);
2423 if (ret)
2424 return ret;
2425 } else {
2426 dev_warn(&pdev->dev, "NFC clock missing, update your Device Tree");
2427 }
2428
7dc37de7
JW		 2429 nfc->is_initialized = true;
2430 dev_info(&pdev->dev, "NFC is probed.\n");
2d405ec5
BB		 2431
2432 return 0;
2433}
2434
2435static int atmel_nand_nfc_remove(struct platform_device *pdev)
2436{
2437 struct atmel_nfc *nfc = &nand_nfc;
2438
2439 if (!IS_ERR(nfc->clk))
2440 clk_disable_unprepare(nfc->clk);
2441
7dc37de7
JW		 2442 return 0;
2443}
2444
5ddc7bd4
RI		 2445static const struct atmel_nand_nfc_caps sama5d3_nfc_caps = {
2446 .rb_mask = NFC_SR_RB_EDGE0,
2447};
2448
2449static const struct atmel_nand_nfc_caps sama5d4_nfc_caps = {
2450 .rb_mask = NFC_SR_RB_EDGE3,
2451};
2452
81f29b47 2453static const struct of_device_id atmel_nand_nfc_match[] = {
5ddc7bd4
RI		 2454 { .compatible = "atmel,sama5d3-nfc", .data = &sama5d3_nfc_caps },
2455 { .compatible = "atmel,sama5d4-nfc", .data = &sama5d4_nfc_caps },
7dc37de7
JW		 2456 { /* sentinel */ }
2457};
81f29b47 2458MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
7dc37de7
JW		 2459
2460static struct platform_driver atmel_nand_nfc_driver = {
2461 .driver = {
2462 .name = "atmel_nand_nfc",
7dc37de7
JW		 2463 .of_match_table = of_match_ptr(atmel_nand_nfc_match),
2464 },
2465 .probe = atmel_nand_nfc_probe,
2d405ec5 2466 .remove = atmel_nand_nfc_remove,
7dc37de7
JW		 2467};
2468
3c3796cc 2469static struct platform_driver atmel_nand_driver = {
2c2b9285
JH		 2470 .probe = atmel_nand_probe,
2471 .remove = atmel_nand_remove,
42cb1403 2472 .driver = {
3c3796cc 2473 .name = "atmel_nand",
d6a01661 2474 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
42cb1403
AV		 2475 },
2476};
2477
2c2b9285 2478module_platform_driver(atmel_nand_driver);
42cb1403
AV		 2479
2480MODULE_LICENSE("GPL");
2481MODULE_AUTHOR("Rick Bronson");
d4f4c0aa 2482MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
3c3796cc 2483MODULE_ALIAS("platform:atmel_nand");
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