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[mirror_ubuntu-zesty-kernel.git] / drivers / mtd / nand / atmel_nand.c
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42cb1403 1/*
1c7b874d 2 * Copyright © 2003 Rick Bronson
42cb1403
AV		 3 *
4 * Derived from drivers/mtd/nand/autcpu12.c
1c7b874d 5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
42cb1403
AV		 6 *
7 * Derived from drivers/mtd/spia.c
1c7b874d 8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
42cb1403 9 *
77f5492c
RG		 10 *
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
1c7b874d 12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
77f5492c
RG		 13 *
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
1c7b874d 16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
77f5492c 17 *
1c7b874d
JW		 18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
77f5492c 20 *
7dc37de7
JW		 21 * Add Nand Flash Controller support for SAMA5 SoC
22 * © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
23 *
42cb1403
AV		 24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
27 *
28 */
29
b7f080cf 30#include <linux/dma-mapping.h>
42cb1403
AV		 31#include <linux/slab.h>
32#include <linux/module.h>
f4fa697c 33#include <linux/moduleparam.h>
42cb1403 34#include <linux/platform_device.h>
d6a01661
JCPV		 35#include <linux/of.h>
36#include <linux/of_device.h>
37#include <linux/of_gpio.h>
38#include <linux/of_mtd.h>
42cb1403
AV		 39#include <linux/mtd/mtd.h>
40#include <linux/mtd/nand.h>
41#include <linux/mtd/partitions.h>
42
7dc37de7 43#include <linux/delay.h>
5c39c4c5 44#include <linux/dmaengine.h>
90574d0a 45#include <linux/gpio.h>
7dc37de7 46#include <linux/interrupt.h>
90574d0a 47#include <linux/io.h>
bf4289cb 48#include <linux/platform_data/atmel.h>
42cb1403 49
cbc6c5e7
HX		 50static int use_dma = 1;
51module_param(use_dma, int, 0);
52
f4fa697c
SP		 53static int on_flash_bbt = 0;
54module_param(on_flash_bbt, int, 0);
55
77f5492c
RG		 56/* Register access macros */
57#define ecc_readl(add, reg) \
3c3796cc 58 __raw_readl(add + ATMEL_ECC_##reg)
77f5492c 59#define ecc_writel(add, reg, value) \
3c3796cc 60 __raw_writel((value), add + ATMEL_ECC_##reg)
77f5492c 61
d4f4c0aa 62#include "atmel_nand_ecc.h" /* Hardware ECC registers */
7dc37de7 63#include "atmel_nand_nfc.h" /* Nand Flash Controller definition */
77f5492c
RG		 64
65/* oob layout for large page size
66 * bad block info is on bytes 0 and 1
67 * the bytes have to be consecutives to avoid
68 * several NAND_CMD_RNDOUT during read
69 */
3c3796cc 70static struct nand_ecclayout atmel_oobinfo_large = {
77f5492c
RG		 71 .eccbytes = 4,
72 .eccpos = {60, 61, 62, 63},
73 .oobfree = {
74 {2, 58}
75 },
76};
77
78/* oob layout for small page size
79 * bad block info is on bytes 4 and 5
80 * the bytes have to be consecutives to avoid
81 * several NAND_CMD_RNDOUT during read
82 */
3c3796cc 83static struct nand_ecclayout atmel_oobinfo_small = {
77f5492c
RG		 84 .eccbytes = 4,
85 .eccpos = {0, 1, 2, 3},
86 .oobfree = {
87 {6, 10}
88 },
89};
90
7dc37de7
JW		 91struct atmel_nfc {
92 void __iomem *base_cmd_regs;
93 void __iomem *hsmc_regs;
94 void __iomem *sram_bank0;
95 dma_addr_t sram_bank0_phys;
1ae9c092 96 bool use_nfc_sram;
6054d4d5 97 bool write_by_sram;
7dc37de7
JW		 98
99 bool is_initialized;
100 struct completion comp_nfc;
1ae9c092
JW		 101
102 /* Point to the sram bank which include readed data via NFC */
103 void __iomem *data_in_sram;
6054d4d5 104 bool will_write_sram;
7dc37de7
JW		 105};
106static struct atmel_nfc nand_nfc;
107
3c3796cc 108struct atmel_nand_host {
42cb1403
AV		 109 struct nand_chip nand_chip;
110 struct mtd_info mtd;
111 void __iomem *io_base;
cbc6c5e7 112 dma_addr_t io_phys;
d6a01661 113 struct atmel_nand_data board;
77f5492c
RG		 114 struct device *dev;
115 void __iomem *ecc;
cbc6c5e7
HX		 116
117 struct completion comp;
118 struct dma_chan *dma_chan;
a41b51a1 119
7dc37de7
JW		 120 struct atmel_nfc *nfc;
121
a41b51a1
JW		 122 bool has_pmecc;
123 u8 pmecc_corr_cap;
124 u16 pmecc_sector_size;
125 u32 pmecc_lookup_table_offset;
e66b4318
JW		 126 u32 pmecc_lookup_table_offset_512;
127 u32 pmecc_lookup_table_offset_1024;
1c7b874d
JW		 128
129 int pmecc_bytes_per_sector;
130 int pmecc_sector_number;
131 int pmecc_degree; /* Degree of remainders */
132 int pmecc_cw_len; /* Length of codeword */
133
134 void __iomem *pmerrloc_base;
135 void __iomem *pmecc_rom_base;
136
137 /* lookup table for alpha_to and index_of */
138 void __iomem *pmecc_alpha_to;
139 void __iomem *pmecc_index_of;
140
141 /* data for pmecc computation */
142 int16_t *pmecc_partial_syn;
143 int16_t *pmecc_si;
144 int16_t *pmecc_smu; /* Sigma table */
145 int16_t *pmecc_lmu; /* polynomal order */
146 int *pmecc_mu;
147 int *pmecc_dmu;
148 int *pmecc_delta;
42cb1403
AV		 149};
150
1c7b874d
JW		 151static struct nand_ecclayout atmel_pmecc_oobinfo;
152
8136508c
AN		 153/*
154 * Enable NAND.
155 */
3c3796cc 156static void atmel_nand_enable(struct atmel_nand_host *host)
8136508c 157{
d6a01661
JCPV		 158 if (gpio_is_valid(host->board.enable_pin))
159 gpio_set_value(host->board.enable_pin, 0);
8136508c
AN		 160}
161
162/*
163 * Disable NAND.
164 */
3c3796cc 165static void atmel_nand_disable(struct atmel_nand_host *host)
8136508c 166{
d6a01661
JCPV		 167 if (gpio_is_valid(host->board.enable_pin))
168 gpio_set_value(host->board.enable_pin, 1);
8136508c
AN		 169}
170
42cb1403
AV		 171/*
172 * Hardware specific access to control-lines
173 */
3c3796cc 174static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
42cb1403
AV		 175{
176 struct nand_chip *nand_chip = mtd->priv;
3c3796cc 177 struct atmel_nand_host *host = nand_chip->priv;
42cb1403 178
8136508c 179 if (ctrl & NAND_CTRL_CHANGE) {
2314488e 180 if (ctrl & NAND_NCE)
3c3796cc 181 atmel_nand_enable(host);
2314488e 182 else
3c3796cc 183 atmel_nand_disable(host);
2314488e 184 }
42cb1403
AV		 185 if (cmd == NAND_CMD_NONE)
186 return;
187
188 if (ctrl & NAND_CLE)
d6a01661 189 writeb(cmd, host->io_base + (1 << host->board.cle));
42cb1403 190 else
d6a01661 191 writeb(cmd, host->io_base + (1 << host->board.ale));
42cb1403
AV		 192}
193
194/*
195 * Read the Device Ready pin.
196 */
3c3796cc 197static int atmel_nand_device_ready(struct mtd_info *mtd)
42cb1403
AV		 198{
199 struct nand_chip *nand_chip = mtd->priv;
3c3796cc 200 struct atmel_nand_host *host = nand_chip->priv;
42cb1403 201
d6a01661
JCPV		 202 return gpio_get_value(host->board.rdy_pin) ^
203 !!host->board.rdy_pin_active_low;
42cb1403
AV		 204}
205
7dc37de7
JW		 206/* Set up for hardware ready pin and enable pin. */
207static int atmel_nand_set_enable_ready_pins(struct mtd_info *mtd)
208{
209 struct nand_chip *chip = mtd->priv;
210 struct atmel_nand_host *host = chip->priv;
211 int res = 0;
212
213 if (gpio_is_valid(host->board.rdy_pin)) {
214 res = devm_gpio_request(host->dev,
215 host->board.rdy_pin, "nand_rdy");
216 if (res < 0) {
217 dev_err(host->dev,
218 "can't request rdy gpio %d\n",
219 host->board.rdy_pin);
220 return res;
221 }
222
223 res = gpio_direction_input(host->board.rdy_pin);
224 if (res < 0) {
225 dev_err(host->dev,
226 "can't request input direction rdy gpio %d\n",
227 host->board.rdy_pin);
228 return res;
229 }
230
231 chip->dev_ready = atmel_nand_device_ready;
232 }
233
234 if (gpio_is_valid(host->board.enable_pin)) {
235 res = devm_gpio_request(host->dev,
236 host->board.enable_pin, "nand_enable");
237 if (res < 0) {
238 dev_err(host->dev,
239 "can't request enable gpio %d\n",
240 host->board.enable_pin);
241 return res;
242 }
243
244 res = gpio_direction_output(host->board.enable_pin, 1);
245 if (res < 0) {
246 dev_err(host->dev,
247 "can't request output direction enable gpio %d\n",
248 host->board.enable_pin);
249 return res;
250 }
251 }
252
253 return res;
254}
255
1ae9c092
JW		 256static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
257{
258 int i;
259 u32 *t = trg;
260 const __iomem u32 *s = src;
261
262 for (i = 0; i < (size >> 2); i++)
263 *t++ = readl_relaxed(s++);
264}
265
6054d4d5
JW		 266static void memcpy32_toio(void __iomem *trg, const void *src, int size)
267{
268 int i;
269 u32 __iomem *t = trg;
270 const u32 *s = src;
271
272 for (i = 0; i < (size >> 2); i++)
273 writel_relaxed(*s++, t++);
274}
275
50082319
AB		 276/*
277 * Minimal-overhead PIO for data access.
278 */
279static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
280{
281 struct nand_chip *nand_chip = mtd->priv;
1ae9c092 282 struct atmel_nand_host *host = nand_chip->priv;
50082319 283
1ae9c092
JW		 284 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
285 memcpy32_fromio(buf, host->nfc->data_in_sram, len);
286 host->nfc->data_in_sram += len;
287 } else {
288 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
289 }
50082319
AB		 290}
291
292static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
293{
294 struct nand_chip *nand_chip = mtd->priv;
1ae9c092 295 struct atmel_nand_host *host = nand_chip->priv;
50082319 296
1ae9c092
JW		 297 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
298 memcpy32_fromio(buf, host->nfc->data_in_sram, len);
299 host->nfc->data_in_sram += len;
300 } else {
301 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
302 }
50082319
AB		 303}
304
305static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
306{
307 struct nand_chip *nand_chip = mtd->priv;
308
309 __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
310}
311
312static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
313{
314 struct nand_chip *nand_chip = mtd->priv;
315
316 __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
317}
318
cbc6c5e7
HX		 319static void dma_complete_func(void *completion)
320{
321 complete(completion);
322}
323
1ae9c092
JW		 324static int nfc_set_sram_bank(struct atmel_nand_host *host, unsigned int bank)
325{
326 /* NFC only has two banks. Must be 0 or 1 */
327 if (bank > 1)
328 return -EINVAL;
329
330 if (bank) {
331 /* Only for a 2k-page or lower flash, NFC can handle 2 banks */
332 if (host->mtd.writesize > 2048)
333 return -EINVAL;
334 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK1);
335 } else {
336 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK0);
337 }
338
339 return 0;
340}
341
342static uint nfc_get_sram_off(struct atmel_nand_host *host)
343{
344 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
345 return NFC_SRAM_BANK1_OFFSET;
346 else
347 return 0;
348}
349
350static dma_addr_t nfc_sram_phys(struct atmel_nand_host *host)
351{
352 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
353 return host->nfc->sram_bank0_phys + NFC_SRAM_BANK1_OFFSET;
354 else
355 return host->nfc->sram_bank0_phys;
356}
357
cbc6c5e7
HX		 358static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
359 int is_read)
360{
361 struct dma_device *dma_dev;
362 enum dma_ctrl_flags flags;
363 dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
364 struct dma_async_tx_descriptor *tx = NULL;
365 dma_cookie_t cookie;
366 struct nand_chip *chip = mtd->priv;
367 struct atmel_nand_host *host = chip->priv;
368 void *p = buf;
369 int err = -EIO;
370 enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1ae9c092 371 struct atmel_nfc *nfc = host->nfc;
cbc6c5e7 372
80b4f81a
HX		 373 if (buf >= high_memory)
374 goto err_buf;
cbc6c5e7
HX		 375
376 dma_dev = host->dma_chan->device;
377
378 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_SRC_UNMAP |
379 DMA_COMPL_SKIP_DEST_UNMAP;
380
381 phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
382 if (dma_mapping_error(dma_dev->dev, phys_addr)) {
383 dev_err(host->dev, "Failed to dma_map_single\n");
384 goto err_buf;
385 }
386
387 if (is_read) {
1ae9c092
JW		 388 if (nfc && nfc->data_in_sram)
389 dma_src_addr = nfc_sram_phys(host) + (nfc->data_in_sram
390 - (nfc->sram_bank0 + nfc_get_sram_off(host)));
391 else
392 dma_src_addr = host->io_phys;
393
cbc6c5e7
HX		 394 dma_dst_addr = phys_addr;
395 } else {
396 dma_src_addr = phys_addr;
6054d4d5
JW		 397
398 if (nfc && nfc->write_by_sram)
399 dma_dst_addr = nfc_sram_phys(host);
400 else
401 dma_dst_addr = host->io_phys;
cbc6c5e7
HX		 402 }
403
404 tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
405 dma_src_addr, len, flags);
406 if (!tx) {
407 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
408 goto err_dma;
409 }
410
411 init_completion(&host->comp);
412 tx->callback = dma_complete_func;
413 tx->callback_param = &host->comp;
414
415 cookie = tx->tx_submit(tx);
416 if (dma_submit_error(cookie)) {
417 dev_err(host->dev, "Failed to do DMA tx_submit\n");
418 goto err_dma;
419 }
420
421 dma_async_issue_pending(host->dma_chan);
422 wait_for_completion(&host->comp);
423
1ae9c092
JW		 424 if (is_read && nfc && nfc->data_in_sram)
425 /* After read data from SRAM, need to increase the position */
426 nfc->data_in_sram += len;
427
cbc6c5e7
HX		 428 err = 0;
429
430err_dma:
431 dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
432err_buf:
433 if (err != 0)
434 dev_warn(host->dev, "Fall back to CPU I/O\n");
435 return err;
436}
437
438static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
439{
440 struct nand_chip *chip = mtd->priv;
50082319 441 struct atmel_nand_host *host = chip->priv;
cbc6c5e7 442
9d51567e
NF		 443 if (use_dma && len > mtd->oobsize)
444 /* only use DMA for bigger than oob size: better performances */
cbc6c5e7
HX		 445 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
446 return;
447
d6a01661 448 if (host->board.bus_width_16)
50082319
AB		 449 atmel_read_buf16(mtd, buf, len);
450 else
451 atmel_read_buf8(mtd, buf, len);
cbc6c5e7
HX		 452}
453
454static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
455{
456 struct nand_chip *chip = mtd->priv;
50082319 457 struct atmel_nand_host *host = chip->priv;
cbc6c5e7 458
9d51567e
NF		 459 if (use_dma && len > mtd->oobsize)
460 /* only use DMA for bigger than oob size: better performances */
cbc6c5e7
HX		 461 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
462 return;
463
d6a01661 464 if (host->board.bus_width_16)
50082319
AB		 465 atmel_write_buf16(mtd, buf, len);
466 else
467 atmel_write_buf8(mtd, buf, len);
cbc6c5e7
HX		 468}
469
1c7b874d
JW		 470/*
471 * Return number of ecc bytes per sector according to sector size and
472 * correction capability
473 *
474 * Following table shows what at91 PMECC supported:
475 * Correction Capability Sector_512_bytes Sector_1024_bytes
476 * ===================== ================ =================
477 * 2-bits 4-bytes 4-bytes
478 * 4-bits 7-bytes 7-bytes
479 * 8-bits 13-bytes 14-bytes
480 * 12-bits 20-bytes 21-bytes
481 * 24-bits 39-bytes 42-bytes
482 */
06f25510 483static int pmecc_get_ecc_bytes(int cap, int sector_size)
1c7b874d
JW		 484{
485 int m = 12 + sector_size / 512;
486 return (m * cap + 7) / 8;
487}
488
06f25510 489static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
d8929942 490 int oobsize, int ecc_len)
1c7b874d
JW		 491{
492 int i;
493
494 layout->eccbytes = ecc_len;
495
496 /* ECC will occupy the last ecc_len bytes continuously */
497 for (i = 0; i < ecc_len; i++)
498 layout->eccpos[i] = oobsize - ecc_len + i;
499
500 layout->oobfree[0].offset = 2;
501 layout->oobfree[0].length =
502 oobsize - ecc_len - layout->oobfree[0].offset;
503}
504
06f25510 505static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
1c7b874d
JW		 506{
507 int table_size;
508
509 table_size = host->pmecc_sector_size == 512 ?
510 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
511
512 return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
513 table_size * sizeof(int16_t);
514}
515
06f25510 516static int pmecc_data_alloc(struct atmel_nand_host *host)
1c7b874d
JW		 517{
518 const int cap = host->pmecc_corr_cap;
0d63748d
JCPV		 519 int size;
520
521 size = (2 * cap + 1) * sizeof(int16_t);
522 host->pmecc_partial_syn = devm_kzalloc(host->dev, size, GFP_KERNEL);
523 host->pmecc_si = devm_kzalloc(host->dev, size, GFP_KERNEL);
524 host->pmecc_lmu = devm_kzalloc(host->dev,
525 (cap + 1) * sizeof(int16_t), GFP_KERNEL);
526 host->pmecc_smu = devm_kzalloc(host->dev,
527 (cap + 2) * size, GFP_KERNEL);
528
529 size = (cap + 1) * sizeof(int);
530 host->pmecc_mu = devm_kzalloc(host->dev, size, GFP_KERNEL);
531 host->pmecc_dmu = devm_kzalloc(host->dev, size, GFP_KERNEL);
532 host->pmecc_delta = devm_kzalloc(host->dev, size, GFP_KERNEL);
533
534 if (!host->pmecc_partial_syn ||
535 !host->pmecc_si ||
536 !host->pmecc_lmu ||
537 !host->pmecc_smu ||
538 !host->pmecc_mu ||
539 !host->pmecc_dmu ||
540 !host->pmecc_delta)
541 return -ENOMEM;
1c7b874d 542
0d63748d 543 return 0;
1c7b874d
JW		 544}
545
546static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
547{
548 struct nand_chip *nand_chip = mtd->priv;
549 struct atmel_nand_host *host = nand_chip->priv;
550 int i;
551 uint32_t value;
552
553 /* Fill odd syndromes */
554 for (i = 0; i < host->pmecc_corr_cap; i++) {
555 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
556 if (i & 1)
557 value >>= 16;
558 value &= 0xffff;
559 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
560 }
561}
562
563static void pmecc_substitute(struct mtd_info *mtd)
564{
565 struct nand_chip *nand_chip = mtd->priv;
566 struct atmel_nand_host *host = nand_chip->priv;
567 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
568 int16_t __iomem *index_of = host->pmecc_index_of;
569 int16_t *partial_syn = host->pmecc_partial_syn;
570 const int cap = host->pmecc_corr_cap;
571 int16_t *si;
572 int i, j;
573
574 /* si[] is a table that holds the current syndrome value,
575 * an element of that table belongs to the field
576 */
577 si = host->pmecc_si;
578
579 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
580
581 /* Computation 2t syndromes based on S(x) */
582 /* Odd syndromes */
583 for (i = 1; i < 2 * cap; i += 2) {
584 for (j = 0; j < host->pmecc_degree; j++) {
585 if (partial_syn[i] & ((unsigned short)0x1 << j))
586 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
587 }
588 }
589 /* Even syndrome = (Odd syndrome) ** 2 */
590 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
591 if (si[j] == 0) {
592 si[i] = 0;
593 } else {
594 int16_t tmp;
595
596 tmp = readw_relaxed(index_of + si[j]);
597 tmp = (tmp * 2) % host->pmecc_cw_len;
598 si[i] = readw_relaxed(alpha_to + tmp);
599 }
600 }
601
602 return;
603}
604
605static void pmecc_get_sigma(struct mtd_info *mtd)
606{
607 struct nand_chip *nand_chip = mtd->priv;
608 struct atmel_nand_host *host = nand_chip->priv;
609
610 int16_t *lmu = host->pmecc_lmu;
611 int16_t *si = host->pmecc_si;
612 int *mu = host->pmecc_mu;
613 int *dmu = host->pmecc_dmu; /* Discrepancy */
614 int *delta = host->pmecc_delta; /* Delta order */
615 int cw_len = host->pmecc_cw_len;
616 const int16_t cap = host->pmecc_corr_cap;
617 const int num = 2 * cap + 1;
618 int16_t __iomem *index_of = host->pmecc_index_of;
619 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
620 int i, j, k;
621 uint32_t dmu_0_count, tmp;
622 int16_t *smu = host->pmecc_smu;
623
624 /* index of largest delta */
625 int ro;
626 int largest;
627 int diff;
628
629 dmu_0_count = 0;
630
631 /* First Row */
632
633 /* Mu */
634 mu[0] = -1;
635
636 memset(smu, 0, sizeof(int16_t) * num);
637 smu[0] = 1;
638
639 /* discrepancy set to 1 */
640 dmu[0] = 1;
641 /* polynom order set to 0 */
642 lmu[0] = 0;
643 delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
644
645 /* Second Row */
646
647 /* Mu */
648 mu[1] = 0;
649 /* Sigma(x) set to 1 */
650 memset(&smu[num], 0, sizeof(int16_t) * num);
651 smu[num] = 1;
652
653 /* discrepancy set to S1 */
654 dmu[1] = si[1];
655
656 /* polynom order set to 0 */
657 lmu[1] = 0;
658
659 delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
660
661 /* Init the Sigma(x) last row */
662 memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
663
664 for (i = 1; i <= cap; i++) {
665 mu[i + 1] = i << 1;
666 /* Begin Computing Sigma (Mu+1) and L(mu) */
667 /* check if discrepancy is set to 0 */
668 if (dmu[i] == 0) {
669 dmu_0_count++;
670
671 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
672 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
673 tmp += 2;
674 else
675 tmp += 1;
676
677 if (dmu_0_count == tmp) {
678 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
679 smu[(cap + 1) * num + j] =
680 smu[i * num + j];
681
682 lmu[cap + 1] = lmu[i];
683 return;
684 }
685
686 /* copy polynom */
687 for (j = 0; j <= lmu[i] >> 1; j++)
688 smu[(i + 1) * num + j] = smu[i * num + j];
689
690 /* copy previous polynom order to the next */
691 lmu[i + 1] = lmu[i];
692 } else {
693 ro = 0;
694 largest = -1;
695 /* find largest delta with dmu != 0 */
696 for (j = 0; j < i; j++) {
697 if ((dmu[j]) && (delta[j] > largest)) {
698 largest = delta[j];
699 ro = j;
700 }
701 }
702
703 /* compute difference */
704 diff = (mu[i] - mu[ro]);
705
706 /* Compute degree of the new smu polynomial */
707 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
708 lmu[i + 1] = lmu[i];
709 else
710 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
711
712 /* Init smu[i+1] with 0 */
713 for (k = 0; k < num; k++)
714 smu[(i + 1) * num + k] = 0;
715
716 /* Compute smu[i+1] */
717 for (k = 0; k <= lmu[ro] >> 1; k++) {
718 int16_t a, b, c;
719
720 if (!(smu[ro * num + k] && dmu[i]))
721 continue;
722 a = readw_relaxed(index_of + dmu[i]);
723 b = readw_relaxed(index_of + dmu[ro]);
724 c = readw_relaxed(index_of + smu[ro * num + k]);
725 tmp = a + (cw_len - b) + c;
726 a = readw_relaxed(alpha_to + tmp % cw_len);
727 smu[(i + 1) * num + (k + diff)] = a;
728 }
729
730 for (k = 0; k <= lmu[i] >> 1; k++)
731 smu[(i + 1) * num + k] ^= smu[i * num + k];
732 }
733
734 /* End Computing Sigma (Mu+1) and L(mu) */
735 /* In either case compute delta */
736 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
737
738 /* Do not compute discrepancy for the last iteration */
739 if (i >= cap)
740 continue;
741
742 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
743 tmp = 2 * (i - 1);
744 if (k == 0) {
745 dmu[i + 1] = si[tmp + 3];
746 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
747 int16_t a, b, c;
748 a = readw_relaxed(index_of +
749 smu[(i + 1) * num + k]);
750 b = si[2 * (i - 1) + 3 - k];
751 c = readw_relaxed(index_of + b);
752 tmp = a + c;
753 tmp %= cw_len;
754 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
755 dmu[i + 1];
756 }
757 }
758 }
759
760 return;
761}
762
763static int pmecc_err_location(struct mtd_info *mtd)
764{
765 struct nand_chip *nand_chip = mtd->priv;
766 struct atmel_nand_host *host = nand_chip->priv;
767 unsigned long end_time;
768 const int cap = host->pmecc_corr_cap;
769 const int num = 2 * cap + 1;
770 int sector_size = host->pmecc_sector_size;
771 int err_nbr = 0; /* number of error */
772 int roots_nbr; /* number of roots */
773 int i;
774 uint32_t val;
775 int16_t *smu = host->pmecc_smu;
776
777 pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
778
779 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
780 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
781 smu[(cap + 1) * num + i]);
782 err_nbr++;
783 }
784
785 val = (err_nbr - 1) << 16;
786 if (sector_size == 1024)
787 val |= 1;
788
789 pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
790 pmerrloc_writel(host->pmerrloc_base, ELEN,
791 sector_size * 8 + host->pmecc_degree * cap);
792
793 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
794 while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
795 & PMERRLOC_CALC_DONE)) {
796 if (unlikely(time_after(jiffies, end_time))) {
797 dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
798 return -1;
799 }
800 cpu_relax();
801 }
802
803 roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
804 & PMERRLOC_ERR_NUM_MASK) >> 8;
805 /* Number of roots == degree of smu hence <= cap */
806 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
807 return err_nbr - 1;
808
809 /* Number of roots does not match the degree of smu
810 * unable to correct error */
811 return -1;
812}
813
814static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
815 int sector_num, int extra_bytes, int err_nbr)
816{
817 struct nand_chip *nand_chip = mtd->priv;
818 struct atmel_nand_host *host = nand_chip->priv;
819 int i = 0;
820 int byte_pos, bit_pos, sector_size, pos;
821 uint32_t tmp;
822 uint8_t err_byte;
823
824 sector_size = host->pmecc_sector_size;
825
826 while (err_nbr) {
827 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
828 byte_pos = tmp / 8;
829 bit_pos = tmp % 8;
830
831 if (byte_pos >= (sector_size + extra_bytes))
832 BUG(); /* should never happen */
833
834 if (byte_pos < sector_size) {
835 err_byte = *(buf + byte_pos);
836 *(buf + byte_pos) ^= (1 << bit_pos);
837
838 pos = sector_num * host->pmecc_sector_size + byte_pos;
839 dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
840 pos, bit_pos, err_byte, *(buf + byte_pos));
841 } else {
842 /* Bit flip in OOB area */
843 tmp = sector_num * host->pmecc_bytes_per_sector
844 + (byte_pos - sector_size);
845 err_byte = ecc[tmp];
846 ecc[tmp] ^= (1 << bit_pos);
847
848 pos = tmp + nand_chip->ecc.layout->eccpos[0];
849 dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
850 pos, bit_pos, err_byte, ecc[tmp]);
851 }
852
853 i++;
854 err_nbr--;
855 }
856
857 return;
858}
859
860static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
861 u8 *ecc)
862{
863 struct nand_chip *nand_chip = mtd->priv;
864 struct atmel_nand_host *host = nand_chip->priv;
865 int i, err_nbr, eccbytes;
866 uint8_t *buf_pos;
c0c70d9e 867 int total_err = 0;
1c7b874d
JW		 868
869 eccbytes = nand_chip->ecc.bytes;
870 for (i = 0; i < eccbytes; i++)
871 if (ecc[i] != 0xff)
872 goto normal_check;
873 /* Erased page, return OK */
874 return 0;
875
876normal_check:
877 for (i = 0; i < host->pmecc_sector_number; i++) {
878 err_nbr = 0;
879 if (pmecc_stat & 0x1) {
880 buf_pos = buf + i * host->pmecc_sector_size;
881
882 pmecc_gen_syndrome(mtd, i);
883 pmecc_substitute(mtd);
884 pmecc_get_sigma(mtd);
885
886 err_nbr = pmecc_err_location(mtd);
887 if (err_nbr == -1) {
888 dev_err(host->dev, "PMECC: Too many errors\n");
889 mtd->ecc_stats.failed++;
890 return -EIO;
891 } else {
892 pmecc_correct_data(mtd, buf_pos, ecc, i,
893 host->pmecc_bytes_per_sector, err_nbr);
894 mtd->ecc_stats.corrected += err_nbr;
c0c70d9e 895 total_err += err_nbr;
1c7b874d
JW		 896 }
897 }
898 pmecc_stat >>= 1;
899 }
900
c0c70d9e 901 return total_err;
1c7b874d
JW		 902}
903
5ee3d9da
JW		 904static void pmecc_enable(struct atmel_nand_host *host, int ecc_op)
905{
906 u32 val;
907
908 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
909 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
910 val = pmecc_readl_relaxed(host->ecc, CFG);
911
912 if (ecc_op != NAND_ECC_READ && ecc_op != NAND_ECC_WRITE) {
913 dev_err(host->dev, "atmel_nand: wrong pmecc operation type!");
914 return;
915 }
916
917 if (ecc_op == NAND_ECC_READ)
918 pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP)
919 | PMECC_CFG_AUTO_ENABLE);
920 else
921 pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP)
922 & ~PMECC_CFG_AUTO_ENABLE);
923
924 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
925 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
926}
927
1c7b874d
JW		 928static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
929 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
930{
931 struct atmel_nand_host *host = chip->priv;
932 int eccsize = chip->ecc.size;
933 uint8_t *oob = chip->oob_poi;
934 uint32_t *eccpos = chip->ecc.layout->eccpos;
935 uint32_t stat;
936 unsigned long end_time;
c0c70d9e 937 int bitflips = 0;
1c7b874d 938
1ae9c092
JW		 939 if (!host->nfc || !host->nfc->use_nfc_sram)
940 pmecc_enable(host, NAND_ECC_READ);
1c7b874d
JW		 941
942 chip->read_buf(mtd, buf, eccsize);
943 chip->read_buf(mtd, oob, mtd->oobsize);
944
945 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
946 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
947 if (unlikely(time_after(jiffies, end_time))) {
948 dev_err(host->dev, "PMECC: Timeout to get error status.\n");
949 return -EIO;
950 }
951 cpu_relax();
952 }
953
954 stat = pmecc_readl_relaxed(host->ecc, ISR);
c0c70d9e
JW		 955 if (stat != 0) {
956 bitflips = pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]);
957 if (bitflips < 0)
958 /* uncorrectable errors */
959 return 0;
960 }
1c7b874d 961
c0c70d9e 962 return bitflips;
1c7b874d
JW		 963}
964
965static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
966 struct nand_chip *chip, const uint8_t *buf, int oob_required)
967{
968 struct atmel_nand_host *host = chip->priv;
969 uint32_t *eccpos = chip->ecc.layout->eccpos;
970 int i, j;
971 unsigned long end_time;
972
6054d4d5
JW		 973 if (!host->nfc || !host->nfc->write_by_sram) {
974 pmecc_enable(host, NAND_ECC_WRITE);
975 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
976 }
1c7b874d
JW		 977
978 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
979 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
980 if (unlikely(time_after(jiffies, end_time))) {
981 dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
982 return -EIO;
983 }
984 cpu_relax();
985 }
986
987 for (i = 0; i < host->pmecc_sector_number; i++) {
988 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
989 int pos;
990
991 pos = i * host->pmecc_bytes_per_sector + j;
992 chip->oob_poi[eccpos[pos]] =
993 pmecc_readb_ecc_relaxed(host->ecc, i, j);
994 }
995 }
996 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
997
998 return 0;
999}
1000
1001static void atmel_pmecc_core_init(struct mtd_info *mtd)
1002{
1003 struct nand_chip *nand_chip = mtd->priv;
1004 struct atmel_nand_host *host = nand_chip->priv;
1005 uint32_t val = 0;
1006 struct nand_ecclayout *ecc_layout;
1007
1008 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
1009 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1010
1011 switch (host->pmecc_corr_cap) {
1012 case 2:
1013 val = PMECC_CFG_BCH_ERR2;
1014 break;
1015 case 4:
1016 val = PMECC_CFG_BCH_ERR4;
1017 break;
1018 case 8:
1019 val = PMECC_CFG_BCH_ERR8;
1020 break;
1021 case 12:
1022 val = PMECC_CFG_BCH_ERR12;
1023 break;
1024 case 24:
1025 val = PMECC_CFG_BCH_ERR24;
1026 break;
1027 }
1028
1029 if (host->pmecc_sector_size == 512)
1030 val |= PMECC_CFG_SECTOR512;
1031 else if (host->pmecc_sector_size == 1024)
1032 val |= PMECC_CFG_SECTOR1024;
1033
1034 switch (host->pmecc_sector_number) {
1035 case 1:
1036 val |= PMECC_CFG_PAGE_1SECTOR;
1037 break;
1038 case 2:
1039 val |= PMECC_CFG_PAGE_2SECTORS;
1040 break;
1041 case 4:
1042 val |= PMECC_CFG_PAGE_4SECTORS;
1043 break;
1044 case 8:
1045 val |= PMECC_CFG_PAGE_8SECTORS;
1046 break;
1047 }
1048
1049 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
1050 | PMECC_CFG_AUTO_DISABLE);
1051 pmecc_writel(host->ecc, CFG, val);
1052
1053 ecc_layout = nand_chip->ecc.layout;
1054 pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
1055 pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
1056 pmecc_writel(host->ecc, EADDR,
1057 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
1058 /* See datasheet about PMECC Clock Control Register */
1059 pmecc_writel(host->ecc, CLK, 2);
1060 pmecc_writel(host->ecc, IDR, 0xff);
1061 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
1062}
1063
84cfbbb8
JW		 1064/*
1065 * Get ECC requirement in ONFI parameters, returns -1 if ONFI
1066 * parameters is not supported.
1067 * return 0 if success to get the ECC requirement.
1068 */
1069static int get_onfi_ecc_param(struct nand_chip *chip,
1070 int *ecc_bits, int *sector_size)
1071{
1072 *ecc_bits = *sector_size = 0;
1073
1074 if (chip->onfi_params.ecc_bits == 0xff)
1075 /* TODO: the sector_size and ecc_bits need to be find in
1076 * extended ecc parameter, currently we don't support it.
1077 */
1078 return -1;
1079
1080 *ecc_bits = chip->onfi_params.ecc_bits;
1081
1082 /* The default sector size (ecc codeword size) is 512 */
1083 *sector_size = 512;
1084
1085 return 0;
1086}
1087
1088/*
1089 * Get ecc requirement from ONFI parameters ecc requirement.
1090 * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
1091 * will set them according to ONFI ecc requirement. Otherwise, use the
1092 * value in DTS file.
1093 * return 0 if success. otherwise return error code.
1094 */
1095static int pmecc_choose_ecc(struct atmel_nand_host *host,
1096 int *cap, int *sector_size)
1097{
1098 /* Get ECC requirement from ONFI parameters */
1099 *cap = *sector_size = 0;
1100 if (host->nand_chip.onfi_version) {
1101 if (!get_onfi_ecc_param(&host->nand_chip, cap, sector_size))
1102 dev_info(host->dev, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
1103 *cap, *sector_size);
1104 else
1105 dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n");
1106 } else {
1107 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes");
1108 }
1109 if (*cap == 0 && *sector_size == 0) {
1110 *cap = 2;
1111 *sector_size = 512;
1112 }
1113
1114 /* If dts file doesn't specify then use the one in ONFI parameters */
1115 if (host->pmecc_corr_cap == 0) {
1116 /* use the most fitable ecc bits (the near bigger one ) */
1117 if (*cap <= 2)
1118 host->pmecc_corr_cap = 2;
1119 else if (*cap <= 4)
1120 host->pmecc_corr_cap = 4;
edc9cba4 1121 else if (*cap <= 8)
84cfbbb8 1122 host->pmecc_corr_cap = 8;
edc9cba4 1123 else if (*cap <= 12)
84cfbbb8 1124 host->pmecc_corr_cap = 12;
edc9cba4 1125 else if (*cap <= 24)
84cfbbb8
JW		 1126 host->pmecc_corr_cap = 24;
1127 else
1128 return -EINVAL;
1129 }
1130 if (host->pmecc_sector_size == 0) {
1131 /* use the most fitable sector size (the near smaller one ) */
1132 if (*sector_size >= 1024)
1133 host->pmecc_sector_size = 1024;
1134 else if (*sector_size >= 512)
1135 host->pmecc_sector_size = 512;
1136 else
1137 return -EINVAL;
1138 }
1139 return 0;
1140}
1141
1c7b874d
JW		 1142static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev,
1143 struct atmel_nand_host *host)
1144{
1145 struct mtd_info *mtd = &host->mtd;
1146 struct nand_chip *nand_chip = &host->nand_chip;
1147 struct resource *regs, *regs_pmerr, *regs_rom;
1148 int cap, sector_size, err_no;
1149
84cfbbb8
JW		 1150 err_no = pmecc_choose_ecc(host, &cap, &sector_size);
1151 if (err_no) {
1152 dev_err(host->dev, "The NAND flash's ECC requirement are not support!");
1153 return err_no;
1154 }
1155
f666d649 1156 if (cap > host->pmecc_corr_cap ||
84cfbbb8
JW		 1157 sector_size != host->pmecc_sector_size)
1158 dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
e66b4318 1159
1c7b874d
JW		 1160 cap = host->pmecc_corr_cap;
1161 sector_size = host->pmecc_sector_size;
e66b4318
JW		 1162 host->pmecc_lookup_table_offset = (sector_size == 512) ?
1163 host->pmecc_lookup_table_offset_512 :
1164 host->pmecc_lookup_table_offset_1024;
1165
1c7b874d
JW		 1166 dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
1167 cap, sector_size);
1168
1169 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1170 if (!regs) {
1171 dev_warn(host->dev,
1172 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1173 nand_chip->ecc.mode = NAND_ECC_SOFT;
1174 return 0;
1175 }
1176
0d63748d
JCPV		 1177 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1178 if (IS_ERR(host->ecc)) {
1c7b874d 1179 dev_err(host->dev, "ioremap failed\n");
0d63748d
JCPV		 1180 err_no = PTR_ERR(host->ecc);
1181 goto err;
1c7b874d
JW		 1182 }
1183
1184 regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
0d63748d
JCPV		 1185 host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr);
1186 if (IS_ERR(host->pmerrloc_base)) {
1187 dev_err(host->dev,
1188 "Can not get I/O resource for PMECC ERRLOC controller!\n");
1189 err_no = PTR_ERR(host->pmerrloc_base);
1190 goto err;
1c7b874d
JW		 1191 }
1192
0d63748d
JCPV		 1193 regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1194 host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev, regs_rom);
1195 if (IS_ERR(host->pmecc_rom_base)) {
1196 dev_err(host->dev, "Can not get I/O resource for ROM!\n");
1197 err_no = PTR_ERR(host->pmecc_rom_base);
1198 goto err;
1c7b874d
JW		 1199 }
1200
1201 /* ECC is calculated for the whole page (1 step) */
1202 nand_chip->ecc.size = mtd->writesize;
1203
1204 /* set ECC page size and oob layout */
1205 switch (mtd->writesize) {
1206 case 2048:
1207 host->pmecc_degree = PMECC_GF_DIMENSION_13;
1208 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
1209 host->pmecc_sector_number = mtd->writesize / sector_size;
1210 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
1211 cap, sector_size);
1212 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
1213 host->pmecc_index_of = host->pmecc_rom_base +
1214 host->pmecc_lookup_table_offset;
1215
1216 nand_chip->ecc.steps = 1;
1217 nand_chip->ecc.strength = cap;
1218 nand_chip->ecc.bytes = host->pmecc_bytes_per_sector *
1219 host->pmecc_sector_number;
1220 if (nand_chip->ecc.bytes > mtd->oobsize - 2) {
1221 dev_err(host->dev, "No room for ECC bytes\n");
1222 err_no = -EINVAL;
0d63748d 1223 goto err;
1c7b874d
JW		 1224 }
1225 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
1226 mtd->oobsize,
1227 nand_chip->ecc.bytes);
1228 nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
1229 break;
1230 case 512:
1231 case 1024:
1232 case 4096:
1233 /* TODO */
1234 dev_warn(host->dev,
1235 "Unsupported page size for PMECC, use Software ECC\n");
1236 default:
1237 /* page size not handled by HW ECC */
1238 /* switching back to soft ECC */
1239 nand_chip->ecc.mode = NAND_ECC_SOFT;
1240 return 0;
1241 }
1242
1243 /* Allocate data for PMECC computation */
1244 err_no = pmecc_data_alloc(host);
1245 if (err_no) {
1246 dev_err(host->dev,
1247 "Cannot allocate memory for PMECC computation!\n");
0d63748d 1248 goto err;
1c7b874d
JW		 1249 }
1250
1251 nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
1252 nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1253
1254 atmel_pmecc_core_init(mtd);
1255
1256 return 0;
1257
0d63748d 1258err:
1c7b874d
JW		 1259 return err_no;
1260}
1261
77f5492c
RG		 1262/*
1263 * Calculate HW ECC
1264 *
1265 * function called after a write
1266 *
1267 * mtd: MTD block structure
1268 * dat: raw data (unused)
1269 * ecc_code: buffer for ECC
1270 */
3c3796cc 1271static int atmel_nand_calculate(struct mtd_info *mtd,
77f5492c
RG		 1272 const u_char *dat, unsigned char *ecc_code)
1273{
1274 struct nand_chip *nand_chip = mtd->priv;
3c3796cc 1275 struct atmel_nand_host *host = nand_chip->priv;
77f5492c
RG		 1276 unsigned int ecc_value;
1277
1278 /* get the first 2 ECC bytes */
d43fa149 1279 ecc_value = ecc_readl(host->ecc, PR);
77f5492c 1280
3fc23898
RG		 1281 ecc_code[0] = ecc_value & 0xFF;
1282 ecc_code[1] = (ecc_value >> 8) & 0xFF;
77f5492c
RG		 1283
1284 /* get the last 2 ECC bytes */
3c3796cc 1285 ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
77f5492c 1286
3fc23898
RG		 1287 ecc_code[2] = ecc_value & 0xFF;
1288 ecc_code[3] = (ecc_value >> 8) & 0xFF;
77f5492c
RG		 1289
1290 return 0;
1291}
1292
1293/*
1294 * HW ECC read page function
1295 *
1296 * mtd: mtd info structure
1297 * chip: nand chip info structure
1298 * buf: buffer to store read data
1fbb938d 1299 * oob_required: caller expects OOB data read to chip->oob_poi
77f5492c 1300 */
1fbb938d
BN		 1301static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1302 uint8_t *buf, int oob_required, int page)
77f5492c
RG		 1303{
1304 int eccsize = chip->ecc.size;
1305 int eccbytes = chip->ecc.bytes;
1306 uint32_t *eccpos = chip->ecc.layout->eccpos;
1307 uint8_t *p = buf;
1308 uint8_t *oob = chip->oob_poi;
1309 uint8_t *ecc_pos;
1310 int stat;
3f91e94f 1311 unsigned int max_bitflips = 0;
77f5492c 1312
d6248fdd
HS		 1313 /*
1314 * Errata: ALE is incorrectly wired up to the ECC controller
1315 * on the AP7000, so it will include the address cycles in the
1316 * ECC calculation.
1317 *
1318 * Workaround: Reset the parity registers before reading the
1319 * actual data.
1320 */
71b94e2e
JW		 1321 struct atmel_nand_host *host = chip->priv;
1322 if (host->board.need_reset_workaround)
d6248fdd 1323 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
d6248fdd 1324
77f5492c
RG		 1325 /* read the page */
1326 chip->read_buf(mtd, p, eccsize);
1327
1328 /* move to ECC position if needed */
1329 if (eccpos[0] != 0) {
1330 /* This only works on large pages
1331 * because the ECC controller waits for
1332 * NAND_CMD_RNDOUTSTART after the
1333 * NAND_CMD_RNDOUT.
1334 * anyway, for small pages, the eccpos[0] == 0
1335 */
1336 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1337 mtd->writesize + eccpos[0], -1);
1338 }
1339
1340 /* the ECC controller needs to read the ECC just after the data */
1341 ecc_pos = oob + eccpos[0];
1342 chip->read_buf(mtd, ecc_pos, eccbytes);
1343
1344 /* check if there's an error */
1345 stat = chip->ecc.correct(mtd, p, oob, NULL);
1346
3f91e94f 1347 if (stat < 0) {
77f5492c 1348 mtd->ecc_stats.failed++;
3f91e94f 1349 } else {
77f5492c 1350 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1351 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1352 }
77f5492c
RG		 1353
1354 /* get back to oob start (end of page) */
1355 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1356
1357 /* read the oob */
1358 chip->read_buf(mtd, oob, mtd->oobsize);
1359
3f91e94f 1360 return max_bitflips;
77f5492c
RG		 1361}
1362
1363/*
1364 * HW ECC Correction
1365 *
1366 * function called after a read
1367 *
1368 * mtd: MTD block structure
1369 * dat: raw data read from the chip
1370 * read_ecc: ECC from the chip (unused)
1371 * isnull: unused
1372 *
1373 * Detect and correct a 1 bit error for a page
1374 */
3c3796cc 1375static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
77f5492c
RG		 1376 u_char *read_ecc, u_char *isnull)
1377{
1378 struct nand_chip *nand_chip = mtd->priv;
3c3796cc 1379 struct atmel_nand_host *host = nand_chip->priv;
77f5492c
RG		 1380 unsigned int ecc_status;
1381 unsigned int ecc_word, ecc_bit;
1382
1383 /* get the status from the Status Register */
1384 ecc_status = ecc_readl(host->ecc, SR);
1385
1386 /* if there's no error */
3c3796cc 1387 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
77f5492c
RG		 1388 return 0;
1389
1390 /* get error bit offset (4 bits) */
3c3796cc 1391 ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
77f5492c 1392 /* get word address (12 bits) */
3c3796cc 1393 ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
77f5492c
RG		 1394 ecc_word >>= 4;
1395
1396 /* if there are multiple errors */
3c3796cc 1397 if (ecc_status & ATMEL_ECC_MULERR) {
77f5492c
RG		 1398 /* check if it is a freshly erased block
1399 * (filled with 0xff) */
3c3796cc
HS		 1400 if ((ecc_bit == ATMEL_ECC_BITADDR)
1401 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
77f5492c
RG		 1402 /* the block has just been erased, return OK */
1403 return 0;
1404 }
1405 /* it doesn't seems to be a freshly
1406 * erased block.
1407 * We can't correct so many errors */
3c3796cc 1408 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
77f5492c
RG		 1409 " Unable to correct.\n");
1410 return -EIO;
1411 }
1412
1413 /* if there's a single bit error : we can correct it */
3c3796cc 1414 if (ecc_status & ATMEL_ECC_ECCERR) {
77f5492c
RG		 1415 /* there's nothing much to do here.
1416 * the bit error is on the ECC itself.
1417 */
3c3796cc 1418 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
77f5492c
RG		 1419 " Nothing to correct\n");
1420 return 0;
1421 }
1422
3c3796cc 1423 dev_dbg(host->dev, "atmel_nand : one bit error on data."
77f5492c
RG		 1424 " (word offset in the page :"
1425 " 0x%x bit offset : 0x%x)\n",
1426 ecc_word, ecc_bit);
1427 /* correct the error */
1428 if (nand_chip->options & NAND_BUSWIDTH_16) {
1429 /* 16 bits words */
1430 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1431 } else {
1432 /* 8 bits words */
1433 dat[ecc_word] ^= (1 << ecc_bit);
1434 }
3c3796cc 1435 dev_dbg(host->dev, "atmel_nand : error corrected\n");
77f5492c
RG		 1436 return 1;
1437}
1438
1439/*
d6248fdd 1440 * Enable HW ECC : unused on most chips
77f5492c 1441 */
d6248fdd
HS		 1442static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1443{
71b94e2e
JW		 1444 struct nand_chip *nand_chip = mtd->priv;
1445 struct atmel_nand_host *host = nand_chip->priv;
1446
1447 if (host->board.need_reset_workaround)
d6248fdd 1448 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
d6248fdd 1449}
77f5492c 1450
d6a01661 1451#if defined(CONFIG_OF)
06f25510 1452static int atmel_of_init_port(struct atmel_nand_host *host,
d8929942 1453 struct device_node *np)
d6a01661 1454{
c0cf787f 1455 u32 val;
a41b51a1 1456 u32 offset[2];
d6a01661
JCPV		 1457 int ecc_mode;
1458 struct atmel_nand_data *board = &host->board;
1459 enum of_gpio_flags flags;
1460
1461 if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
1462 if (val >= 32) {
1463 dev_err(host->dev, "invalid addr-offset %u\n", val);
1464 return -EINVAL;
1465 }
1466 board->ale = val;
1467 }
1468
1469 if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
1470 if (val >= 32) {
1471 dev_err(host->dev, "invalid cmd-offset %u\n", val);
1472 return -EINVAL;
1473 }
1474 board->cle = val;
1475 }
1476
1477 ecc_mode = of_get_nand_ecc_mode(np);
1478
1479 board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
1480
1481 board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
1482
1b719265
JW		 1483 board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma");
1484
d6a01661
JCPV		 1485 if (of_get_nand_bus_width(np) == 16)
1486 board->bus_width_16 = 1;
1487
1488 board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
1489 board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
1490
1491 board->enable_pin = of_get_gpio(np, 1);
1492 board->det_pin = of_get_gpio(np, 2);
1493
a41b51a1
JW		 1494 host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1495
7dc37de7
JW		 1496 /* load the nfc driver if there is */
1497 of_platform_populate(np, NULL, NULL, host->dev);
1498
a41b51a1
JW		 1499 if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
1500 return 0; /* Not using PMECC */
1501
1502 /* use PMECC, get correction capability, sector size and lookup
1503 * table offset.
e66b4318
JW		 1504 * If correction bits and sector size are not specified, then find
1505 * them from NAND ONFI parameters.
a41b51a1 1506 */
e66b4318
JW		 1507 if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
1508 if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
1509 (val != 24)) {
1510 dev_err(host->dev,
1511 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1512 val);
1513 return -EINVAL;
1514 }
1515 host->pmecc_corr_cap = (u8)val;
a41b51a1 1516 }
a41b51a1 1517
e66b4318
JW		 1518 if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
1519 if ((val != 512) && (val != 1024)) {
1520 dev_err(host->dev,
1521 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1522 val);
1523 return -EINVAL;
1524 }
1525 host->pmecc_sector_size = (u16)val;
a41b51a1 1526 }
a41b51a1
JW		 1527
1528 if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1529 offset, 2) != 0) {
1530 dev_err(host->dev, "Cannot get PMECC lookup table offset\n");
1531 return -EINVAL;
1532 }
c0cf787f 1533 if (!offset[0] && !offset[1]) {
a41b51a1
JW		 1534 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1535 return -EINVAL;
1536 }
e66b4318
JW		 1537 host->pmecc_lookup_table_offset_512 = offset[0];
1538 host->pmecc_lookup_table_offset_1024 = offset[1];
a41b51a1 1539
d6a01661
JCPV		 1540 return 0;
1541}
1542#else
06f25510 1543static int atmel_of_init_port(struct atmel_nand_host *host,
d8929942 1544 struct device_node *np)
d6a01661
JCPV		 1545{
1546 return -EINVAL;
1547}
1548#endif
1549
3dfe41a4
JW		 1550static int __init atmel_hw_nand_init_params(struct platform_device *pdev,
1551 struct atmel_nand_host *host)
1552{
1553 struct mtd_info *mtd = &host->mtd;
1554 struct nand_chip *nand_chip = &host->nand_chip;
1555 struct resource *regs;
1556
1557 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1558 if (!regs) {
1559 dev_err(host->dev,
1560 "Can't get I/O resource regs, use software ECC\n");
1561 nand_chip->ecc.mode = NAND_ECC_SOFT;
1562 return 0;
1563 }
1564
0d63748d
JCPV		 1565 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1566 if (IS_ERR(host->ecc)) {
3dfe41a4 1567 dev_err(host->dev, "ioremap failed\n");
0d63748d 1568 return PTR_ERR(host->ecc);
3dfe41a4
JW		 1569 }
1570
1571 /* ECC is calculated for the whole page (1 step) */
1572 nand_chip->ecc.size = mtd->writesize;
1573
1574 /* set ECC page size and oob layout */
1575 switch (mtd->writesize) {
1576 case 512:
1577 nand_chip->ecc.layout = &atmel_oobinfo_small;
1578 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1579 break;
1580 case 1024:
1581 nand_chip->ecc.layout = &atmel_oobinfo_large;
1582 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1583 break;
1584 case 2048:
1585 nand_chip->ecc.layout = &atmel_oobinfo_large;
1586 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1587 break;
1588 case 4096:
1589 nand_chip->ecc.layout = &atmel_oobinfo_large;
1590 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1591 break;
1592 default:
1593 /* page size not handled by HW ECC */
1594 /* switching back to soft ECC */
1595 nand_chip->ecc.mode = NAND_ECC_SOFT;
1596 return 0;
1597 }
1598
1599 /* set up for HW ECC */
1600 nand_chip->ecc.calculate = atmel_nand_calculate;
1601 nand_chip->ecc.correct = atmel_nand_correct;
1602 nand_chip->ecc.hwctl = atmel_nand_hwctl;
1603 nand_chip->ecc.read_page = atmel_nand_read_page;
1604 nand_chip->ecc.bytes = 4;
1605 nand_chip->ecc.strength = 1;
1606
1607 return 0;
1608}
1609
7dc37de7
JW		 1610/* SMC interrupt service routine */
1611static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
1612{
1613 struct atmel_nand_host *host = dev_id;
1614 u32 status, mask, pending;
1615 irqreturn_t ret = IRQ_HANDLED;
1616
1617 status = nfc_readl(host->nfc->hsmc_regs, SR);
1618 mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1619 pending = status & mask;
1620
1621 if (pending & NFC_SR_XFR_DONE) {
1622 complete(&host->nfc->comp_nfc);
1623 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
1624 } else if (pending & NFC_SR_RB_EDGE) {
1625 complete(&host->nfc->comp_nfc);
1626 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
1627 } else if (pending & NFC_SR_CMD_DONE) {
1628 complete(&host->nfc->comp_nfc);
1629 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_CMD_DONE);
1630 } else {
1631 ret = IRQ_NONE;
1632 }
1633
1634 return ret;
1635}
1636
1637/* NFC(Nand Flash Controller) related functions */
1638static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
1639{
1640 unsigned long timeout;
1641 init_completion(&host->nfc->comp_nfc);
1642
1643 /* Enable interrupt that need to wait for */
1644 nfc_writel(host->nfc->hsmc_regs, IER, flag);
1645
1646 timeout = wait_for_completion_timeout(&host->nfc->comp_nfc,
1647 msecs_to_jiffies(NFC_TIME_OUT_MS));
1648 if (timeout)
1649 return 0;
1650
1651 /* Time out to wait for the interrupt */
1652 dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag);
1653 return -ETIMEDOUT;
1654}
1655
1656static int nfc_send_command(struct atmel_nand_host *host,
1657 unsigned int cmd, unsigned int addr, unsigned char cycle0)
1658{
1659 unsigned long timeout;
1660 dev_dbg(host->dev,
1661 "nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
1662 cmd, addr, cycle0);
1663
1664 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1665 while (nfc_cmd_readl(NFCADDR_CMD_NFCBUSY, host->nfc->base_cmd_regs)
1666 & NFCADDR_CMD_NFCBUSY) {
1667 if (time_after(jiffies, timeout)) {
1668 dev_err(host->dev,
1669 "Time out to wait CMD_NFCBUSY ready!\n");
1670 return -ETIMEDOUT;
1671 }
1672 }
1673 nfc_writel(host->nfc->hsmc_regs, CYCLE0, cycle0);
1674 nfc_cmd_addr1234_writel(cmd, addr, host->nfc->base_cmd_regs);
1675 return nfc_wait_interrupt(host, NFC_SR_CMD_DONE);
1676}
1677
1678static int nfc_device_ready(struct mtd_info *mtd)
1679{
1680 struct nand_chip *nand_chip = mtd->priv;
1681 struct atmel_nand_host *host = nand_chip->priv;
1682 if (!nfc_wait_interrupt(host, NFC_SR_RB_EDGE))
1683 return 1;
1684 return 0;
1685}
1686
1687static void nfc_select_chip(struct mtd_info *mtd, int chip)
1688{
1689 struct nand_chip *nand_chip = mtd->priv;
1690 struct atmel_nand_host *host = nand_chip->priv;
1691
1692 if (chip == -1)
1693 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_DISABLE);
1694 else
1695 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_ENABLE);
1696}
1697
1698static int nfc_make_addr(struct mtd_info *mtd, int column, int page_addr,
1699 unsigned int *addr1234, unsigned int *cycle0)
1700{
1701 struct nand_chip *chip = mtd->priv;
1702
1703 int acycle = 0;
1704 unsigned char addr_bytes[8];
1705 int index = 0, bit_shift;
1706
1707 BUG_ON(addr1234 == NULL || cycle0 == NULL);
1708
1709 *cycle0 = 0;
1710 *addr1234 = 0;
1711
1712 if (column != -1) {
1713 if (chip->options & NAND_BUSWIDTH_16)
1714 column >>= 1;
1715 addr_bytes[acycle++] = column & 0xff;
1716 if (mtd->writesize > 512)
1717 addr_bytes[acycle++] = (column >> 8) & 0xff;
1718 }
1719
1720 if (page_addr != -1) {
1721 addr_bytes[acycle++] = page_addr & 0xff;
1722 addr_bytes[acycle++] = (page_addr >> 8) & 0xff;
1723 if (chip->chipsize > (128 << 20))
1724 addr_bytes[acycle++] = (page_addr >> 16) & 0xff;
1725 }
1726
1727 if (acycle > 4)
1728 *cycle0 = addr_bytes[index++];
1729
1730 for (bit_shift = 0; index < acycle; bit_shift += 8)
1731 *addr1234 += addr_bytes[index++] << bit_shift;
1732
1733 /* return acycle in cmd register */
1734 return acycle << NFCADDR_CMD_ACYCLE_BIT_POS;
1735}
1736
1737static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
1738 int column, int page_addr)
1739{
1740 struct nand_chip *chip = mtd->priv;
1741 struct atmel_nand_host *host = chip->priv;
1742 unsigned long timeout;
1743 unsigned int nfc_addr_cmd = 0;
1744
1745 unsigned int cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1746
1747 /* Set default settings: no cmd2, no addr cycle. read from nand */
1748 unsigned int cmd2 = 0;
1749 unsigned int vcmd2 = 0;
1750 int acycle = NFCADDR_CMD_ACYCLE_NONE;
1751 int csid = NFCADDR_CMD_CSID_3;
1752 int dataen = NFCADDR_CMD_DATADIS;
1753 int nfcwr = NFCADDR_CMD_NFCRD;
1754 unsigned int addr1234 = 0;
1755 unsigned int cycle0 = 0;
1756 bool do_addr = true;
1ae9c092 1757 host->nfc->data_in_sram = NULL;
7dc37de7
JW		 1758
1759 dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
1760 __func__, command, column, page_addr);
1761
1762 switch (command) {
1763 case NAND_CMD_RESET:
1764 nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr;
1765 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1766 udelay(chip->chip_delay);
1767
1768 nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
1769 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1770 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) {
1771 if (time_after(jiffies, timeout)) {
1772 dev_err(host->dev,
1773 "Time out to wait status ready!\n");
1774 break;
1775 }
1776 }
1777 return;
1778 case NAND_CMD_STATUS:
1779 do_addr = false;
1780 break;
1781 case NAND_CMD_PARAM:
1782 case NAND_CMD_READID:
1783 do_addr = false;
1784 acycle = NFCADDR_CMD_ACYCLE_1;
1785 if (column != -1)
1786 addr1234 = column;
1787 break;
1788 case NAND_CMD_RNDOUT:
1789 cmd2 = NAND_CMD_RNDOUTSTART << NFCADDR_CMD_CMD2_BIT_POS;
1790 vcmd2 = NFCADDR_CMD_VCMD2;
1791 break;
1792 case NAND_CMD_READ0:
1793 case NAND_CMD_READOOB:
1794 if (command == NAND_CMD_READOOB) {
1795 column += mtd->writesize;
1796 command = NAND_CMD_READ0; /* only READ0 is valid */
1797 cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1798 }
1ae9c092
JW		 1799 if (host->nfc->use_nfc_sram) {
1800 /* Enable Data transfer to sram */
1801 dataen = NFCADDR_CMD_DATAEN;
1802
1803 /* Need enable PMECC now, since NFC will transfer
1804 * data in bus after sending nfc read command.
1805 */
1806 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1807 pmecc_enable(host, NAND_ECC_READ);
1808 }
7dc37de7
JW		 1809
1810 cmd2 = NAND_CMD_READSTART << NFCADDR_CMD_CMD2_BIT_POS;
1811 vcmd2 = NFCADDR_CMD_VCMD2;
1812 break;
1813 /* For prgramming command, the cmd need set to write enable */
1814 case NAND_CMD_PAGEPROG:
1815 case NAND_CMD_SEQIN:
1816 case NAND_CMD_RNDIN:
1817 nfcwr = NFCADDR_CMD_NFCWR;
6054d4d5
JW		 1818 if (host->nfc->will_write_sram && command == NAND_CMD_SEQIN)
1819 dataen = NFCADDR_CMD_DATAEN;
7dc37de7
JW		 1820 break;
1821 default:
1822 break;
1823 }
1824
1825 if (do_addr)
1826 acycle = nfc_make_addr(mtd, column, page_addr, &addr1234,
1827 &cycle0);
1828
1829 nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
1830 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1831
1ae9c092
JW		 1832 if (dataen == NFCADDR_CMD_DATAEN)
1833 if (nfc_wait_interrupt(host, NFC_SR_XFR_DONE))
1834 dev_err(host->dev, "something wrong, No XFR_DONE interrupt comes.\n");
1835
7dc37de7
JW		 1836 /*
1837 * Program and erase have their own busy handlers status, sequential
1838 * in, and deplete1 need no delay.
1839 */
1840 switch (command) {
1841 case NAND_CMD_CACHEDPROG:
1842 case NAND_CMD_PAGEPROG:
1843 case NAND_CMD_ERASE1:
1844 case NAND_CMD_ERASE2:
1845 case NAND_CMD_RNDIN:
1846 case NAND_CMD_STATUS:
1847 case NAND_CMD_RNDOUT:
1848 case NAND_CMD_SEQIN:
1849 case NAND_CMD_READID:
1850 return;
1851
1852 case NAND_CMD_READ0:
1ae9c092
JW		 1853 if (dataen == NFCADDR_CMD_DATAEN) {
1854 host->nfc->data_in_sram = host->nfc->sram_bank0 +
1855 nfc_get_sram_off(host);
1856 return;
1857 }
7dc37de7
JW		 1858 /* fall through */
1859 default:
1860 nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
1861 }
1862}
1863
6054d4d5
JW		 1864static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1865 uint32_t offset, int data_len, const uint8_t *buf,
1866 int oob_required, int page, int cached, int raw)
1867{
1868 int cfg, len;
1869 int status = 0;
1870 struct atmel_nand_host *host = chip->priv;
1871 void __iomem *sram = host->nfc->sram_bank0 + nfc_get_sram_off(host);
1872
1873 /* Subpage write is not supported */
1874 if (offset || (data_len < mtd->writesize))
1875 return -EINVAL;
1876
1877 cfg = nfc_readl(host->nfc->hsmc_regs, CFG);
1878 len = mtd->writesize;
1879
1880 if (unlikely(raw)) {
1881 len += mtd->oobsize;
1882 nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE);
1883 } else
1884 nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE);
1885
1886 /* Copy page data to sram that will write to nand via NFC */
1887 if (use_dma) {
1888 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0)
1889 /* Fall back to use cpu copy */
1890 memcpy32_toio(sram, buf, len);
1891 } else {
1892 memcpy32_toio(sram, buf, len);
1893 }
1894
1895 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1896 /*
1897 * When use NFC sram, need set up PMECC before send
1898 * NAND_CMD_SEQIN command. Since when the nand command
1899 * is sent, nfc will do transfer from sram and nand.
1900 */
1901 pmecc_enable(host, NAND_ECC_WRITE);
1902
1903 host->nfc->will_write_sram = true;
1904 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1905 host->nfc->will_write_sram = false;
1906
1907 if (likely(!raw))
1908 /* Need to write ecc into oob */
1909 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
1910
1911 if (status < 0)
1912 return status;
1913
1914 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1915 status = chip->waitfunc(mtd, chip);
1916
1917 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1918 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
1919
1920 if (status & NAND_STATUS_FAIL)
1921 return -EIO;
1922
1923 return 0;
1924}
1925
1ae9c092
JW		 1926static int nfc_sram_init(struct mtd_info *mtd)
1927{
1928 struct nand_chip *chip = mtd->priv;
1929 struct atmel_nand_host *host = chip->priv;
1930 int res = 0;
1931
1932 /* Initialize the NFC CFG register */
1933 unsigned int cfg_nfc = 0;
1934
1935 /* set page size and oob layout */
1936 switch (mtd->writesize) {
1937 case 512:
1938 cfg_nfc = NFC_CFG_PAGESIZE_512;
1939 break;
1940 case 1024:
1941 cfg_nfc = NFC_CFG_PAGESIZE_1024;
1942 break;
1943 case 2048:
1944 cfg_nfc = NFC_CFG_PAGESIZE_2048;
1945 break;
1946 case 4096:
1947 cfg_nfc = NFC_CFG_PAGESIZE_4096;
1948 break;
1949 case 8192:
1950 cfg_nfc = NFC_CFG_PAGESIZE_8192;
1951 break;
1952 default:
1953 dev_err(host->dev, "Unsupported page size for NFC.\n");
1954 res = -ENXIO;
1955 return res;
1956 }
1957
1958 /* oob bytes size = (NFCSPARESIZE + 1) * 4
1959 * Max support spare size is 512 bytes. */
1960 cfg_nfc |= (((mtd->oobsize / 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS
1961 & NFC_CFG_NFC_SPARESIZE);
1962 /* default set a max timeout */
1963 cfg_nfc |= NFC_CFG_RSPARE |
1964 NFC_CFG_NFC_DTOCYC | NFC_CFG_NFC_DTOMUL;
1965
1966 nfc_writel(host->nfc->hsmc_regs, CFG, cfg_nfc);
1967
6054d4d5 1968 host->nfc->will_write_sram = false;
1ae9c092
JW		 1969 nfc_set_sram_bank(host, 0);
1970
6054d4d5
JW		 1971 /* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
1972 if (host->nfc->write_by_sram) {
1973 if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) ||
1974 chip->ecc.mode == NAND_ECC_NONE)
1975 chip->write_page = nfc_sram_write_page;
1976 else
1977 host->nfc->write_by_sram = false;
1978 }
1ae9c092 1979
6054d4d5
JW		 1980 dev_info(host->dev, "Using NFC Sram read %s\n",
1981 host->nfc->write_by_sram ? "and write" : "");
1ae9c092
JW		 1982 return 0;
1983}
1984
7dc37de7 1985static struct platform_driver atmel_nand_nfc_driver;
42cb1403
AV		 1986/*
1987 * Probe for the NAND device.
1988 */
3c3796cc 1989static int __init atmel_nand_probe(struct platform_device *pdev)
42cb1403 1990{
3c3796cc 1991 struct atmel_nand_host *host;
42cb1403
AV		 1992 struct mtd_info *mtd;
1993 struct nand_chip *nand_chip;
77f5492c 1994 struct resource *mem;
d6a01661 1995 struct mtd_part_parser_data ppdata = {};
7dc37de7 1996 int res, irq;
42cb1403
AV		 1997
1998 /* Allocate memory for the device structure (and zero it) */
0d63748d 1999 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
42cb1403 2000 if (!host) {
3c3796cc 2001 printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
42cb1403
AV		 2002 return -ENOMEM;
2003 }
2004
7dc37de7
JW		 2005 res = platform_driver_register(&atmel_nand_nfc_driver);
2006 if (res)
2007 dev_err(&pdev->dev, "atmel_nand: can't register NFC driver\n");
2008
0d63748d
JCPV		 2009 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2010 host->io_base = devm_ioremap_resource(&pdev->dev, mem);
2011 if (IS_ERR(host->io_base)) {
2012 dev_err(&pdev->dev, "atmel_nand: ioremap resource failed\n");
2013 res = PTR_ERR(host->io_base);
cc0c72e1 2014 goto err_nand_ioremap;
42cb1403 2015 }
0d63748d 2016 host->io_phys = (dma_addr_t)mem->start;
42cb1403
AV		 2017
2018 mtd = &host->mtd;
2019 nand_chip = &host->nand_chip;
77f5492c 2020 host->dev = &pdev->dev;
d6a01661
JCPV		 2021 if (pdev->dev.of_node) {
2022 res = atmel_of_init_port(host, pdev->dev.of_node);
2023 if (res)
0d63748d 2024 goto err_nand_ioremap;
d6a01661
JCPV		 2025 } else {
2026 memcpy(&host->board, pdev->dev.platform_data,
2027 sizeof(struct atmel_nand_data));
2028 }
42cb1403
AV		 2029
2030 nand_chip->priv = host; /* link the private data structures */
2031 mtd->priv = nand_chip;
2032 mtd->owner = THIS_MODULE;
2033
2034 /* Set address of NAND IO lines */
2035 nand_chip->IO_ADDR_R = host->io_base;
2036 nand_chip->IO_ADDR_W = host->io_base;
28446acb 2037
7dc37de7
JW		 2038 if (nand_nfc.is_initialized) {
2039 /* NFC driver is probed and initialized */
2040 host->nfc = &nand_nfc;
28446acb 2041
7dc37de7
JW		 2042 nand_chip->select_chip = nfc_select_chip;
2043 nand_chip->dev_ready = nfc_device_ready;
2044 nand_chip->cmdfunc = nfc_nand_command;
28446acb 2045
7dc37de7
JW		 2046 /* Initialize the interrupt for NFC */
2047 irq = platform_get_irq(pdev, 0);
2048 if (irq < 0) {
2049 dev_err(host->dev, "Cannot get HSMC irq!\n");
0d63748d 2050 goto err_nand_ioremap;
28446acb
JCPV		 2051 }
2052
7dc37de7
JW		 2053 res = devm_request_irq(&pdev->dev, irq, hsmc_interrupt,
2054 0, "hsmc", host);
2055 if (res) {
2056 dev_err(&pdev->dev, "Unable to request HSMC irq %d\n",
2057 irq);
0d63748d 2058 goto err_nand_ioremap;
28446acb 2059 }
7dc37de7
JW		 2060 } else {
2061 res = atmel_nand_set_enable_ready_pins(mtd);
2062 if (res)
2063 goto err_nand_ioremap;
2064
2065 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
28446acb 2066 }
a4265f8d 2067
d6a01661 2068 nand_chip->ecc.mode = host->board.ecc_mode;
42cb1403
AV		 2069 nand_chip->chip_delay = 20; /* 20us command delay time */
2070
d6a01661 2071 if (host->board.bus_width_16) /* 16-bit bus width */
dd11b8cd 2072 nand_chip->options |= NAND_BUSWIDTH_16;
cbc6c5e7
HX		 2073
2074 nand_chip->read_buf = atmel_read_buf;
2075 nand_chip->write_buf = atmel_write_buf;
dd11b8cd 2076
42cb1403 2077 platform_set_drvdata(pdev, host);
3c3796cc 2078 atmel_nand_enable(host);
42cb1403 2079
d6a01661 2080 if (gpio_is_valid(host->board.det_pin)) {
0d63748d
JCPV		 2081 res = devm_gpio_request(&pdev->dev,
2082 host->board.det_pin, "nand_det");
28446acb
JCPV		 2083 if (res < 0) {
2084 dev_err(&pdev->dev,
2085 "can't request det gpio %d\n",
2086 host->board.det_pin);
2087 goto err_no_card;
2088 }
2089
2090 res = gpio_direction_input(host->board.det_pin);
2091 if (res < 0) {
2092 dev_err(&pdev->dev,
2093 "can't request input direction det gpio %d\n",
2094 host->board.det_pin);
2095 goto err_no_card;
2096 }
2097
d6a01661 2098 if (gpio_get_value(host->board.det_pin)) {
f4fa697c 2099 printk(KERN_INFO "No SmartMedia card inserted.\n");
895fb494 2100 res = -ENXIO;
cc0c72e1 2101 goto err_no_card;
42cb1403
AV		 2102 }
2103 }
2104
d6a01661 2105 if (host->board.on_flash_bbt || on_flash_bbt) {
f4fa697c 2106 printk(KERN_INFO "atmel_nand: Use On Flash BBT\n");
bb9ebd4e 2107 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
f4fa697c
SP		 2108 }
2109
1b719265 2110 if (!host->board.has_dma)
cb457a4d
HX		 2111 use_dma = 0;
2112
2113 if (use_dma) {
cbc6c5e7
HX		 2114 dma_cap_mask_t mask;
2115
2116 dma_cap_zero(mask);
2117 dma_cap_set(DMA_MEMCPY, mask);
201ab536 2118 host->dma_chan = dma_request_channel(mask, NULL, NULL);
cbc6c5e7
HX		 2119 if (!host->dma_chan) {
2120 dev_err(host->dev, "Failed to request DMA channel\n");
2121 use_dma = 0;
2122 }
2123 }
2124 if (use_dma)
042bc9c0
NF		 2125 dev_info(host->dev, "Using %s for DMA transfers.\n",
2126 dma_chan_name(host->dma_chan));
cbc6c5e7
HX		 2127 else
2128 dev_info(host->dev, "No DMA support for NAND access.\n");
2129
77f5492c 2130 /* first scan to find the device and get the page size */
5e81e88a 2131 if (nand_scan_ident(mtd, 1, NULL)) {
77f5492c 2132 res = -ENXIO;
cc0c72e1 2133 goto err_scan_ident;
77f5492c
RG		 2134 }
2135
3fc23898 2136 if (nand_chip->ecc.mode == NAND_ECC_HW) {
1c7b874d
JW		 2137 if (host->has_pmecc)
2138 res = atmel_pmecc_nand_init_params(pdev, host);
2139 else
2140 res = atmel_hw_nand_init_params(pdev, host);
2141
3dfe41a4
JW		 2142 if (res != 0)
2143 goto err_hw_ecc;
77f5492c
RG		 2144 }
2145
1ae9c092
JW		 2146 /* initialize the nfc configuration register */
2147 if (host->nfc && host->nfc->use_nfc_sram) {
2148 res = nfc_sram_init(mtd);
2149 if (res) {
2150 host->nfc->use_nfc_sram = false;
2151 dev_err(host->dev, "Disable use nfc sram for data transfer.\n");
2152 }
2153 }
2154
77f5492c
RG		 2155 /* second phase scan */
2156 if (nand_scan_tail(mtd)) {
42cb1403 2157 res = -ENXIO;
cc0c72e1 2158 goto err_scan_tail;
42cb1403
AV		 2159 }
2160
3c3796cc 2161 mtd->name = "atmel_nand";
d6a01661
JCPV		 2162 ppdata.of_node = pdev->dev.of_node;
2163 res = mtd_device_parse_register(mtd, NULL, &ppdata,
2164 host->board.parts, host->board.num_parts);
42cb1403
AV		 2165 if (!res)
2166 return res;
2167
cc0c72e1 2168err_scan_tail:
0d63748d 2169 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW)
1c7b874d 2170 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
3dfe41a4 2171err_hw_ecc:
cc0c72e1
HS		 2172err_scan_ident:
2173err_no_card:
3c3796cc 2174 atmel_nand_disable(host);
cbc6c5e7
HX		 2175 if (host->dma_chan)
2176 dma_release_channel(host->dma_chan);
cc0c72e1 2177err_nand_ioremap:
7dc37de7 2178 platform_driver_unregister(&atmel_nand_nfc_driver);
42cb1403
AV		 2179 return res;
2180}
2181
2182/*
2183 * Remove a NAND device.
2184 */
23a346ca 2185static int __exit atmel_nand_remove(struct platform_device *pdev)
42cb1403 2186{
3c3796cc 2187 struct atmel_nand_host *host = platform_get_drvdata(pdev);
42cb1403
AV		 2188 struct mtd_info *mtd = &host->mtd;
2189
2190 nand_release(mtd);
2191
3c3796cc 2192 atmel_nand_disable(host);
42cb1403 2193
1c7b874d
JW		 2194 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
2195 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2196 pmerrloc_writel(host->pmerrloc_base, ELDIS,
2197 PMERRLOC_DISABLE);
1c7b874d
JW		 2198 }
2199
cbc6c5e7
HX		 2200 if (host->dma_chan)
2201 dma_release_channel(host->dma_chan);
2202
7dc37de7
JW		 2203 platform_driver_unregister(&atmel_nand_nfc_driver);
2204
42cb1403
AV		 2205 return 0;
2206}
2207
d6a01661
JCPV		 2208#if defined(CONFIG_OF)
2209static const struct of_device_id atmel_nand_dt_ids[] = {
2210 { .compatible = "atmel,at91rm9200-nand" },
2211 { /* sentinel */ }
2212};
2213
2214MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
2215#endif
2216
7dc37de7
JW		 2217static int atmel_nand_nfc_probe(struct platform_device *pdev)
2218{
2219 struct atmel_nfc *nfc = &nand_nfc;
2220 struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
2221
2222 nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2223 nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs);
2224 if (IS_ERR(nfc->base_cmd_regs))
2225 return PTR_ERR(nfc->base_cmd_regs);
2226
2227 nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2228 nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs);
2229 if (IS_ERR(nfc->hsmc_regs))
2230 return PTR_ERR(nfc->hsmc_regs);
2231
2232 nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 2);
2233 if (nfc_sram) {
2234 nfc->sram_bank0 = devm_ioremap_resource(&pdev->dev, nfc_sram);
1ae9c092 2235 if (IS_ERR(nfc->sram_bank0)) {
7dc37de7
JW		 2236 dev_warn(&pdev->dev, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n",
2237 PTR_ERR(nfc->sram_bank0));
1ae9c092
JW		 2238 } else {
2239 nfc->use_nfc_sram = true;
7dc37de7 2240 nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start;
6054d4d5
JW		 2241
2242 if (pdev->dev.of_node)
2243 nfc->write_by_sram = of_property_read_bool(
2244 pdev->dev.of_node,
2245 "atmel,write-by-sram");
1ae9c092 2246 }
7dc37de7
JW		 2247 }
2248
2249 nfc->is_initialized = true;
2250 dev_info(&pdev->dev, "NFC is probed.\n");
2251 return 0;
2252}
2253
9fe5f52c 2254#if defined(CONFIG_OF)
7dc37de7
JW		 2255static struct of_device_id atmel_nand_nfc_match[] = {
2256 { .compatible = "atmel,sama5d3-nfc" },
2257 { /* sentinel */ }
2258};
9fe5f52c 2259#endif
7dc37de7
JW		 2260
2261static struct platform_driver atmel_nand_nfc_driver = {
2262 .driver = {
2263 .name = "atmel_nand_nfc",
2264 .owner = THIS_MODULE,
2265 .of_match_table = of_match_ptr(atmel_nand_nfc_match),
2266 },
2267 .probe = atmel_nand_nfc_probe,
2268};
2269
3c3796cc 2270static struct platform_driver atmel_nand_driver = {
23a346ca 2271 .remove = __exit_p(atmel_nand_remove),
42cb1403 2272 .driver = {
3c3796cc 2273 .name = "atmel_nand",
42cb1403 2274 .owner = THIS_MODULE,
d6a01661 2275 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
42cb1403
AV		 2276 },
2277};
2278
c5345edf 2279module_platform_driver_probe(atmel_nand_driver, atmel_nand_probe);
42cb1403
AV		 2280
2281MODULE_LICENSE("GPL");
2282MODULE_AUTHOR("Rick Bronson");
d4f4c0aa 2283MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
3c3796cc 2284MODULE_ALIAS("platform:atmel_nand");
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