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mtd: nand: remove useless mtd->priv = chip assignments
[mirror_ubuntu-artful-kernel.git] / drivers / mtd / nand / brcmnand / brcmnand.c
CommitLineData
27c5b17c
BN		 1/*
2 * Copyright © 2010-2015 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
5c05bc00 14#include <linux/clk.h>
27c5b17c
BN		 15#include <linux/version.h>
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/device.h>
20#include <linux/platform_device.h>
21#include <linux/err.h>
22#include <linux/completion.h>
23#include <linux/interrupt.h>
24#include <linux/spinlock.h>
25#include <linux/dma-mapping.h>
26#include <linux/ioport.h>
27#include <linux/bug.h>
28#include <linux/kernel.h>
29#include <linux/bitops.h>
30#include <linux/mm.h>
31#include <linux/mtd/mtd.h>
32#include <linux/mtd/nand.h>
33#include <linux/mtd/partitions.h>
34#include <linux/of.h>
35#include <linux/of_mtd.h>
36#include <linux/of_platform.h>
37#include <linux/slab.h>
38#include <linux/list.h>
39#include <linux/log2.h>
40
41#include "brcmnand.h"
42
43/*
44 * This flag controls if WP stays on between erase/write commands to mitigate
45 * flash corruption due to power glitches. Values:
46 * 0: NAND_WP is not used or not available
47 * 1: NAND_WP is set by default, cleared for erase/write operations
48 * 2: NAND_WP is always cleared
49 */
50static int wp_on = 1;
51module_param(wp_on, int, 0444);
52
53/***********************************************************************
54 * Definitions
55 ***********************************************************************/
56
57#define DRV_NAME "brcmnand"
58
59#define CMD_NULL 0x00
60#define CMD_PAGE_READ 0x01
61#define CMD_SPARE_AREA_READ 0x02
62#define CMD_STATUS_READ 0x03
63#define CMD_PROGRAM_PAGE 0x04
64#define CMD_PROGRAM_SPARE_AREA 0x05
65#define CMD_COPY_BACK 0x06
66#define CMD_DEVICE_ID_READ 0x07
67#define CMD_BLOCK_ERASE 0x08
68#define CMD_FLASH_RESET 0x09
69#define CMD_BLOCKS_LOCK 0x0a
70#define CMD_BLOCKS_LOCK_DOWN 0x0b
71#define CMD_BLOCKS_UNLOCK 0x0c
72#define CMD_READ_BLOCKS_LOCK_STATUS 0x0d
73#define CMD_PARAMETER_READ 0x0e
74#define CMD_PARAMETER_CHANGE_COL 0x0f
75#define CMD_LOW_LEVEL_OP 0x10
76
77struct brcm_nand_dma_desc {
78 u32 next_desc;
79 u32 next_desc_ext;
80 u32 cmd_irq;
81 u32 dram_addr;
82 u32 dram_addr_ext;
83 u32 tfr_len;
84 u32 total_len;
85 u32 flash_addr;
86 u32 flash_addr_ext;
87 u32 cs;
88 u32 pad2[5];
89 u32 status_valid;
90} __packed;
91
92/* Bitfields for brcm_nand_dma_desc::status_valid */
93#define FLASH_DMA_ECC_ERROR (1 << 8)
94#define FLASH_DMA_CORR_ERROR (1 << 9)
95
96/* 512B flash cache in the NAND controller HW */
97#define FC_SHIFT 9U
98#define FC_BYTES 512U
99#define FC_WORDS (FC_BYTES >> 2)
100
101#define BRCMNAND_MIN_PAGESIZE 512
102#define BRCMNAND_MIN_BLOCKSIZE (8 * 1024)
103#define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024)
104
105/* Controller feature flags */
106enum {
107 BRCMNAND_HAS_1K_SECTORS = BIT(0),
108 BRCMNAND_HAS_PREFETCH = BIT(1),
109 BRCMNAND_HAS_CACHE_MODE = BIT(2),
110 BRCMNAND_HAS_WP = BIT(3),
111};
112
113struct brcmnand_controller {
114 struct device *dev;
115 struct nand_hw_control controller;
116 void __iomem *nand_base;
117 void __iomem *nand_fc; /* flash cache */
118 void __iomem *flash_dma_base;
119 unsigned int irq;
120 unsigned int dma_irq;
121 int nand_version;
122
c26211d3
BN		 123 /* Some SoCs provide custom interrupt status register(s) */
124 struct brcmnand_soc *soc;
125
5c05bc00
SA		 126 /* Some SoCs have a gateable clock for the controller */
127 struct clk *clk;
128
27c5b17c
BN		 129 int cmd_pending;
130 bool dma_pending;
131 struct completion done;
132 struct completion dma_done;
133
134 /* List of NAND hosts (one for each chip-select) */
135 struct list_head host_list;
136
137 struct brcm_nand_dma_desc *dma_desc;
138 dma_addr_t dma_pa;
139
140 /* in-memory cache of the FLASH_CACHE, used only for some commands */
d618baf9 141 u8 flash_cache[FC_BYTES];
27c5b17c
BN		 142
143 /* Controller revision details */
144 const u16 *reg_offsets;
145 unsigned int reg_spacing; /* between CS1, CS2, ... regs */
146 const u8 *cs_offsets; /* within each chip-select */
147 const u8 *cs0_offsets; /* within CS0, if different */
148 unsigned int max_block_size;
149 const unsigned int *block_sizes;
150 unsigned int max_page_size;
151 const unsigned int *page_sizes;
152 unsigned int max_oob;
153 u32 features;
154
155 /* for low-power standby/resume only */
156 u32 nand_cs_nand_select;
157 u32 nand_cs_nand_xor;
158 u32 corr_stat_threshold;
159 u32 flash_dma_mode;
160};
161
162struct brcmnand_cfg {
163 u64 device_size;
164 unsigned int block_size;
165 unsigned int page_size;
166 unsigned int spare_area_size;
167 unsigned int device_width;
168 unsigned int col_adr_bytes;
169 unsigned int blk_adr_bytes;
170 unsigned int ful_adr_bytes;
171 unsigned int sector_size_1k;
172 unsigned int ecc_level;
173 /* use for low-power standby/resume only */
174 u32 acc_control;
175 u32 config;
176 u32 config_ext;
177 u32 timing_1;
178 u32 timing_2;
179};
180
181struct brcmnand_host {
182 struct list_head node;
27c5b17c
BN		 183
184 struct nand_chip chip;
27c5b17c
BN		 185 struct platform_device *pdev;
186 int cs;
187
188 unsigned int last_cmd;
189 unsigned int last_byte;
190 u64 last_addr;
191 struct brcmnand_cfg hwcfg;
192 struct brcmnand_controller *ctrl;
193};
194
195enum brcmnand_reg {
196 BRCMNAND_CMD_START = 0,
197 BRCMNAND_CMD_EXT_ADDRESS,
198 BRCMNAND_CMD_ADDRESS,
199 BRCMNAND_INTFC_STATUS,
200 BRCMNAND_CS_SELECT,
201 BRCMNAND_CS_XOR,
202 BRCMNAND_LL_OP,
203 BRCMNAND_CS0_BASE,
204 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
205 BRCMNAND_CORR_THRESHOLD,
206 BRCMNAND_CORR_THRESHOLD_EXT,
207 BRCMNAND_UNCORR_COUNT,
208 BRCMNAND_CORR_COUNT,
209 BRCMNAND_CORR_EXT_ADDR,
210 BRCMNAND_CORR_ADDR,
211 BRCMNAND_UNCORR_EXT_ADDR,
212 BRCMNAND_UNCORR_ADDR,
213 BRCMNAND_SEMAPHORE,
214 BRCMNAND_ID,
215 BRCMNAND_ID_EXT,
216 BRCMNAND_LL_RDATA,
217 BRCMNAND_OOB_READ_BASE,
218 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
219 BRCMNAND_OOB_WRITE_BASE,
220 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
221 BRCMNAND_FC_BASE,
222};
223
224/* BRCMNAND v4.0 */
225static const u16 brcmnand_regs_v40[] = {
226 [BRCMNAND_CMD_START] = 0x04,
227 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
228 [BRCMNAND_CMD_ADDRESS] = 0x0c,
229 [BRCMNAND_INTFC_STATUS] = 0x6c,
230 [BRCMNAND_CS_SELECT] = 0x14,
231 [BRCMNAND_CS_XOR] = 0x18,
232 [BRCMNAND_LL_OP] = 0x178,
233 [BRCMNAND_CS0_BASE] = 0x40,
234 [BRCMNAND_CS1_BASE] = 0xd0,
235 [BRCMNAND_CORR_THRESHOLD] = 0x84,
236 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
237 [BRCMNAND_UNCORR_COUNT] = 0,
238 [BRCMNAND_CORR_COUNT] = 0,
239 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
240 [BRCMNAND_CORR_ADDR] = 0x74,
241 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
242 [BRCMNAND_UNCORR_ADDR] = 0x7c,
243 [BRCMNAND_SEMAPHORE] = 0x58,
244 [BRCMNAND_ID] = 0x60,
245 [BRCMNAND_ID_EXT] = 0x64,
246 [BRCMNAND_LL_RDATA] = 0x17c,
247 [BRCMNAND_OOB_READ_BASE] = 0x20,
248 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
249 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
250 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
251 [BRCMNAND_FC_BASE] = 0x200,
252};
253
254/* BRCMNAND v5.0 */
255static const u16 brcmnand_regs_v50[] = {
256 [BRCMNAND_CMD_START] = 0x04,
257 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
258 [BRCMNAND_CMD_ADDRESS] = 0x0c,
259 [BRCMNAND_INTFC_STATUS] = 0x6c,
260 [BRCMNAND_CS_SELECT] = 0x14,
261 [BRCMNAND_CS_XOR] = 0x18,
262 [BRCMNAND_LL_OP] = 0x178,
263 [BRCMNAND_CS0_BASE] = 0x40,
264 [BRCMNAND_CS1_BASE] = 0xd0,
265 [BRCMNAND_CORR_THRESHOLD] = 0x84,
266 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
267 [BRCMNAND_UNCORR_COUNT] = 0,
268 [BRCMNAND_CORR_COUNT] = 0,
269 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
270 [BRCMNAND_CORR_ADDR] = 0x74,
271 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
272 [BRCMNAND_UNCORR_ADDR] = 0x7c,
273 [BRCMNAND_SEMAPHORE] = 0x58,
274 [BRCMNAND_ID] = 0x60,
275 [BRCMNAND_ID_EXT] = 0x64,
276 [BRCMNAND_LL_RDATA] = 0x17c,
277 [BRCMNAND_OOB_READ_BASE] = 0x20,
278 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
279 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
280 [BRCMNAND_OOB_WRITE_10_BASE] = 0x140,
281 [BRCMNAND_FC_BASE] = 0x200,
282};
283
284/* BRCMNAND v6.0 - v7.1 */
285static const u16 brcmnand_regs_v60[] = {
286 [BRCMNAND_CMD_START] = 0x04,
287 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
288 [BRCMNAND_CMD_ADDRESS] = 0x0c,
289 [BRCMNAND_INTFC_STATUS] = 0x14,
290 [BRCMNAND_CS_SELECT] = 0x18,
291 [BRCMNAND_CS_XOR] = 0x1c,
292 [BRCMNAND_LL_OP] = 0x20,
293 [BRCMNAND_CS0_BASE] = 0x50,
294 [BRCMNAND_CS1_BASE] = 0,
295 [BRCMNAND_CORR_THRESHOLD] = 0xc0,
296 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4,
297 [BRCMNAND_UNCORR_COUNT] = 0xfc,
298 [BRCMNAND_CORR_COUNT] = 0x100,
299 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
300 [BRCMNAND_CORR_ADDR] = 0x110,
301 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
302 [BRCMNAND_UNCORR_ADDR] = 0x118,
303 [BRCMNAND_SEMAPHORE] = 0x150,
304 [BRCMNAND_ID] = 0x194,
305 [BRCMNAND_ID_EXT] = 0x198,
306 [BRCMNAND_LL_RDATA] = 0x19c,
307 [BRCMNAND_OOB_READ_BASE] = 0x200,
308 [BRCMNAND_OOB_READ_10_BASE] = 0,
309 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
310 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
311 [BRCMNAND_FC_BASE] = 0x400,
312};
313
314enum brcmnand_cs_reg {
315 BRCMNAND_CS_CFG_EXT = 0,
316 BRCMNAND_CS_CFG,
317 BRCMNAND_CS_ACC_CONTROL,
318 BRCMNAND_CS_TIMING1,
319 BRCMNAND_CS_TIMING2,
320};
321
322/* Per chip-select offsets for v7.1 */
323static const u8 brcmnand_cs_offsets_v71[] = {
324 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
325 [BRCMNAND_CS_CFG_EXT] = 0x04,
326 [BRCMNAND_CS_CFG] = 0x08,
327 [BRCMNAND_CS_TIMING1] = 0x0c,
328 [BRCMNAND_CS_TIMING2] = 0x10,
329};
330
331/* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
332static const u8 brcmnand_cs_offsets[] = {
333 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
334 [BRCMNAND_CS_CFG_EXT] = 0x04,
335 [BRCMNAND_CS_CFG] = 0x04,
336 [BRCMNAND_CS_TIMING1] = 0x08,
337 [BRCMNAND_CS_TIMING2] = 0x0c,
338};
339
340/* Per chip-select offset for <= v5.0 on CS0 only */
341static const u8 brcmnand_cs_offsets_cs0[] = {
342 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
343 [BRCMNAND_CS_CFG_EXT] = 0x08,
344 [BRCMNAND_CS_CFG] = 0x08,
345 [BRCMNAND_CS_TIMING1] = 0x10,
346 [BRCMNAND_CS_TIMING2] = 0x14,
347};
348
3f06d2a9
BN		 349/*
350 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
351 * one config register, but once the bitfields overflowed, newer controllers
352 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
353 */
354enum {
355 CFG_BLK_ADR_BYTES_SHIFT = 8,
356 CFG_COL_ADR_BYTES_SHIFT = 12,
357 CFG_FUL_ADR_BYTES_SHIFT = 16,
358 CFG_BUS_WIDTH_SHIFT = 23,
359 CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT),
360 CFG_DEVICE_SIZE_SHIFT = 24,
361
362 /* Only for pre-v7.1 (with no CFG_EXT register) */
363 CFG_PAGE_SIZE_SHIFT = 20,
364 CFG_BLK_SIZE_SHIFT = 28,
365
366 /* Only for v7.1+ (with CFG_EXT register) */
367 CFG_EXT_PAGE_SIZE_SHIFT = 0,
368 CFG_EXT_BLK_SIZE_SHIFT = 4,
369};
370
27c5b17c
BN		 371/* BRCMNAND_INTFC_STATUS */
372enum {
373 INTFC_FLASH_STATUS = GENMASK(7, 0),
374
375 INTFC_ERASED = BIT(27),
376 INTFC_OOB_VALID = BIT(28),
377 INTFC_CACHE_VALID = BIT(29),
378 INTFC_FLASH_READY = BIT(30),
379 INTFC_CTLR_READY = BIT(31),
380};
381
382static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
383{
384 return brcmnand_readl(ctrl->nand_base + offs);
385}
386
387static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
388 u32 val)
389{
390 brcmnand_writel(val, ctrl->nand_base + offs);
391}
392
393static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
394{
395 static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
396 static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
397 static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
398
399 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
400
401 /* Only support v4.0+? */
402 if (ctrl->nand_version < 0x0400) {
403 dev_err(ctrl->dev, "version %#x not supported\n",
404 ctrl->nand_version);
405 return -ENODEV;
406 }
407
408 /* Register offsets */
409 if (ctrl->nand_version >= 0x0600)
410 ctrl->reg_offsets = brcmnand_regs_v60;
411 else if (ctrl->nand_version >= 0x0500)
412 ctrl->reg_offsets = brcmnand_regs_v50;
413 else if (ctrl->nand_version >= 0x0400)
414 ctrl->reg_offsets = brcmnand_regs_v40;
415
416 /* Chip-select stride */
417 if (ctrl->nand_version >= 0x0701)
418 ctrl->reg_spacing = 0x14;
419 else
420 ctrl->reg_spacing = 0x10;
421
422 /* Per chip-select registers */
423 if (ctrl->nand_version >= 0x0701) {
424 ctrl->cs_offsets = brcmnand_cs_offsets_v71;
425 } else {
426 ctrl->cs_offsets = brcmnand_cs_offsets;
427
428 /* v5.0 and earlier has a different CS0 offset layout */
429 if (ctrl->nand_version <= 0x0500)
430 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
431 }
432
433 /* Page / block sizes */
434 if (ctrl->nand_version >= 0x0701) {
435 /* >= v7.1 use nice power-of-2 values! */
436 ctrl->max_page_size = 16 * 1024;
437 ctrl->max_block_size = 2 * 1024 * 1024;
438 } else {
439 ctrl->page_sizes = page_sizes;
440 if (ctrl->nand_version >= 0x0600)
441 ctrl->block_sizes = block_sizes_v6;
442 else
443 ctrl->block_sizes = block_sizes_v4;
444
445 if (ctrl->nand_version < 0x0400) {
446 ctrl->max_page_size = 4096;
447 ctrl->max_block_size = 512 * 1024;
448 }
449 }
450
451 /* Maximum spare area sector size (per 512B) */
452 if (ctrl->nand_version >= 0x0600)
453 ctrl->max_oob = 64;
454 else if (ctrl->nand_version >= 0x0500)
455 ctrl->max_oob = 32;
456 else
457 ctrl->max_oob = 16;
458
459 /* v6.0 and newer (except v6.1) have prefetch support */
460 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
461 ctrl->features |= BRCMNAND_HAS_PREFETCH;
462
463 /*
464 * v6.x has cache mode, but it's implemented differently. Ignore it for
465 * now.
466 */
467 if (ctrl->nand_version >= 0x0700)
468 ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
469
470 if (ctrl->nand_version >= 0x0500)
471 ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
472
473 if (ctrl->nand_version >= 0x0700)
474 ctrl->features |= BRCMNAND_HAS_WP;
475 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
476 ctrl->features |= BRCMNAND_HAS_WP;
477
478 return 0;
479}
480
481static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
482 enum brcmnand_reg reg)
483{
484 u16 offs = ctrl->reg_offsets[reg];
485
486 if (offs)
487 return nand_readreg(ctrl, offs);
488 else
489 return 0;
490}
491
492static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
493 enum brcmnand_reg reg, u32 val)
494{
495 u16 offs = ctrl->reg_offsets[reg];
496
497 if (offs)
498 nand_writereg(ctrl, offs, val);
499}
500
501static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
502 enum brcmnand_reg reg, u32 mask, unsigned
503 int shift, u32 val)
504{
505 u32 tmp = brcmnand_read_reg(ctrl, reg);
506
507 tmp &= ~mask;
508 tmp |= val << shift;
509 brcmnand_write_reg(ctrl, reg, tmp);
510}
511
512static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
513{
514 return __raw_readl(ctrl->nand_fc + word * 4);
515}
516
517static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
518 int word, u32 val)
519{
520 __raw_writel(val, ctrl->nand_fc + word * 4);
521}
522
523static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
524 enum brcmnand_cs_reg reg)
525{
526 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
527 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
528 u8 cs_offs;
529
530 if (cs == 0 && ctrl->cs0_offsets)
531 cs_offs = ctrl->cs0_offsets[reg];
532 else
533 cs_offs = ctrl->cs_offsets[reg];
534
535 if (cs && offs_cs1)
536 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
537
538 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
539}
540
541static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
542{
543 if (ctrl->nand_version < 0x0600)
544 return 1;
545 return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
546}
547
548static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
549{
550 struct brcmnand_controller *ctrl = host->ctrl;
551 unsigned int shift = 0, bits;
552 enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
553 int cs = host->cs;
554
555 if (ctrl->nand_version >= 0x0600)
556 bits = 6;
557 else if (ctrl->nand_version >= 0x0500)
558 bits = 5;
559 else
560 bits = 4;
561
562 if (ctrl->nand_version >= 0x0600) {
563 if (cs >= 5)
564 reg = BRCMNAND_CORR_THRESHOLD_EXT;
565 shift = (cs % 5) * bits;
566 }
567 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
568}
569
570static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
571{
572 if (ctrl->nand_version < 0x0700)
573 return 24;
574 return 0;
575}
576
577/***********************************************************************
578 * NAND ACC CONTROL bitfield
579 *
580 * Some bits have remained constant throughout hardware revision, while
581 * others have shifted around.
582 ***********************************************************************/
583
584/* Constant for all versions (where supported) */
585enum {
586 /* See BRCMNAND_HAS_CACHE_MODE */
587 ACC_CONTROL_CACHE_MODE = BIT(22),
588
589 /* See BRCMNAND_HAS_PREFETCH */
590 ACC_CONTROL_PREFETCH = BIT(23),
591
592 ACC_CONTROL_PAGE_HIT = BIT(24),
593 ACC_CONTROL_WR_PREEMPT = BIT(25),
594 ACC_CONTROL_PARTIAL_PAGE = BIT(26),
595 ACC_CONTROL_RD_ERASED = BIT(27),
596 ACC_CONTROL_FAST_PGM_RDIN = BIT(28),
597 ACC_CONTROL_WR_ECC = BIT(30),
598 ACC_CONTROL_RD_ECC = BIT(31),
599};
600
601static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
602{
603 if (ctrl->nand_version >= 0x0600)
604 return GENMASK(6, 0);
605 else
606 return GENMASK(5, 0);
607}
608
609#define NAND_ACC_CONTROL_ECC_SHIFT 16
610
611static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
612{
613 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
614
615 return mask << NAND_ACC_CONTROL_ECC_SHIFT;
616}
617
618static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
619{
620 struct brcmnand_controller *ctrl = host->ctrl;
621 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
622 u32 acc_control = nand_readreg(ctrl, offs);
623 u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
624
625 if (en) {
626 acc_control |= ecc_flags; /* enable RD/WR ECC */
627 acc_control |= host->hwcfg.ecc_level
628 << NAND_ACC_CONTROL_ECC_SHIFT;
629 } else {
630 acc_control &= ~ecc_flags; /* disable RD/WR ECC */
631 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
632 }
633
634 nand_writereg(ctrl, offs, acc_control);
635}
636
637static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
638{
639 if (ctrl->nand_version >= 0x0600)
640 return 7;
641 else if (ctrl->nand_version >= 0x0500)
642 return 6;
643 else
644 return -1;
645}
646
647static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
648{
649 struct brcmnand_controller *ctrl = host->ctrl;
650 int shift = brcmnand_sector_1k_shift(ctrl);
651 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
652 BRCMNAND_CS_ACC_CONTROL);
653
654 if (shift < 0)
655 return 0;
656
657 return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
658}
659
660static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
661{
662 struct brcmnand_controller *ctrl = host->ctrl;
663 int shift = brcmnand_sector_1k_shift(ctrl);
664 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
665 BRCMNAND_CS_ACC_CONTROL);
666 u32 tmp;
667
668 if (shift < 0)
669 return;
670
671 tmp = nand_readreg(ctrl, acc_control_offs);
672 tmp &= ~(1 << shift);
673 tmp |= (!!val) << shift;
674 nand_writereg(ctrl, acc_control_offs, tmp);
675}
676
677/***********************************************************************
678 * CS_NAND_SELECT
679 ***********************************************************************/
680
681enum {
682 CS_SELECT_NAND_WP = BIT(29),
683 CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30),
684};
685
686static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
687{
688 u32 val = en ? CS_SELECT_NAND_WP : 0;
689
690 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
691}
692
693/***********************************************************************
694 * Flash DMA
695 ***********************************************************************/
696
697enum flash_dma_reg {
698 FLASH_DMA_REVISION = 0x00,
699 FLASH_DMA_FIRST_DESC = 0x04,
700 FLASH_DMA_FIRST_DESC_EXT = 0x08,
701 FLASH_DMA_CTRL = 0x0c,
702 FLASH_DMA_MODE = 0x10,
703 FLASH_DMA_STATUS = 0x14,
704 FLASH_DMA_INTERRUPT_DESC = 0x18,
705 FLASH_DMA_INTERRUPT_DESC_EXT = 0x1c,
706 FLASH_DMA_ERROR_STATUS = 0x20,
707 FLASH_DMA_CURRENT_DESC = 0x24,
708 FLASH_DMA_CURRENT_DESC_EXT = 0x28,
709};
710
711static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
712{
713 return ctrl->flash_dma_base;
714}
715
716static inline bool flash_dma_buf_ok(const void *buf)
717{
718 return buf && !is_vmalloc_addr(buf) &&
719 likely(IS_ALIGNED((uintptr_t)buf, 4));
720}
721
722static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
723 u32 val)
724{
725 brcmnand_writel(val, ctrl->flash_dma_base + offs);
726}
727
728static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
729{
730 return brcmnand_readl(ctrl->flash_dma_base + offs);
731}
732
733/* Low-level operation types: command, address, write, or read */
734enum brcmnand_llop_type {
735 LL_OP_CMD,
736 LL_OP_ADDR,
737 LL_OP_WR,
738 LL_OP_RD,
739};
740
741/***********************************************************************
742 * Internal support functions
743 ***********************************************************************/
744
745static inline bool is_hamming_ecc(struct brcmnand_cfg *cfg)
746{
747 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
748 cfg->ecc_level == 15;
749}
750
751/*
752 * Returns a nand_ecclayout strucutre for the given layout/configuration.
753 * Returns NULL on failure.
754 */
755static struct nand_ecclayout *brcmnand_create_layout(int ecc_level,
756 struct brcmnand_host *host)
757{
758 struct brcmnand_cfg *cfg = &host->hwcfg;
759 int i, j;
760 struct nand_ecclayout *layout;
761 int req;
762 int sectors;
763 int sas;
764 int idx1, idx2;
765
766 layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL);
767 if (!layout)
768 return NULL;
769
770 sectors = cfg->page_size / (512 << cfg->sector_size_1k);
771 sas = cfg->spare_area_size << cfg->sector_size_1k;
772
773 /* Hamming */
774 if (is_hamming_ecc(cfg)) {
775 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
776 /* First sector of each page may have BBI */
777 if (i == 0) {
778 layout->oobfree[idx2].offset = i * sas + 1;
779 /* Small-page NAND use byte 6 for BBI */
780 if (cfg->page_size == 512)
781 layout->oobfree[idx2].offset--;
782 layout->oobfree[idx2].length = 5;
783 } else {
784 layout->oobfree[idx2].offset = i * sas;
785 layout->oobfree[idx2].length = 6;
786 }
787 idx2++;
788 layout->eccpos[idx1++] = i * sas + 6;
789 layout->eccpos[idx1++] = i * sas + 7;
790 layout->eccpos[idx1++] = i * sas + 8;
791 layout->oobfree[idx2].offset = i * sas + 9;
792 layout->oobfree[idx2].length = 7;
793 idx2++;
794 /* Leave zero-terminated entry for OOBFREE */
795 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
796 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
797 break;
798 }
799 goto out;
800 }
801
802 /*
803 * CONTROLLER_VERSION:
804 * < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
805 * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
806 * But we will just be conservative.
807 */
808 req = DIV_ROUND_UP(ecc_level * 14, 8);
809 if (req >= sas) {
810 dev_err(&host->pdev->dev,
811 "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
812 req, sas);
813 return NULL;
814 }
815
816 layout->eccbytes = req * sectors;
817 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
818 for (j = sas - req; j < sas && idx1 <
819 MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++)
820 layout->eccpos[idx1] = i * sas + j;
821
822 /* First sector of each page may have BBI */
823 if (i == 0) {
824 if (cfg->page_size == 512 && (sas - req >= 6)) {
825 /* Small-page NAND use byte 6 for BBI */
826 layout->oobfree[idx2].offset = 0;
827 layout->oobfree[idx2].length = 5;
828 idx2++;
829 if (sas - req > 6) {
830 layout->oobfree[idx2].offset = 6;
831 layout->oobfree[idx2].length =
832 sas - req - 6;
833 idx2++;
834 }
835 } else if (sas > req + 1) {
836 layout->oobfree[idx2].offset = i * sas + 1;
837 layout->oobfree[idx2].length = sas - req - 1;
838 idx2++;
839 }
840 } else if (sas > req) {
841 layout->oobfree[idx2].offset = i * sas;
842 layout->oobfree[idx2].length = sas - req;
843 idx2++;
844 }
845 /* Leave zero-terminated entry for OOBFREE */
846 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
847 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
848 break;
849 }
850out:
851 /* Sum available OOB */
852 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE; i++)
853 layout->oobavail += layout->oobfree[i].length;
854 return layout;
855}
856
857static struct nand_ecclayout *brcmstb_choose_ecc_layout(
858 struct brcmnand_host *host)
859{
860 struct nand_ecclayout *layout;
861 struct brcmnand_cfg *p = &host->hwcfg;
862 unsigned int ecc_level = p->ecc_level;
863
864 if (p->sector_size_1k)
865 ecc_level <<= 1;
866
867 layout = brcmnand_create_layout(ecc_level, host);
868 if (!layout) {
869 dev_err(&host->pdev->dev,
870 "no proper ecc_layout for this NAND cfg\n");
871 return NULL;
872 }
873
874 return layout;
875}
876
877static void brcmnand_wp(struct mtd_info *mtd, int wp)
878{
4bd4ebcc 879 struct nand_chip *chip = mtd_to_nand(mtd);
27c5b17c
BN		 880 struct brcmnand_host *host = chip->priv;
881 struct brcmnand_controller *ctrl = host->ctrl;
882
883 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
884 static int old_wp = -1;
885
886 if (old_wp != wp) {
887 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
888 old_wp = wp;
889 }
890 brcmnand_set_wp(ctrl, wp);
891 }
892}
893
894/* Helper functions for reading and writing OOB registers */
895static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
896{
897 u16 offset0, offset10, reg_offs;
898
899 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
900 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
901
902 if (offs >= ctrl->max_oob)
903 return 0x77;
904
905 if (offs >= 16 && offset10)
906 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
907 else
908 reg_offs = offset0 + (offs & ~0x03);
909
910 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
911}
912
913static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
914 u32 data)
915{
916 u16 offset0, offset10, reg_offs;
917
918 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
919 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
920
921 if (offs >= ctrl->max_oob)
922 return;
923
924 if (offs >= 16 && offset10)
925 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
926 else
927 reg_offs = offset0 + (offs & ~0x03);
928
929 nand_writereg(ctrl, reg_offs, data);
930}
931
932/*
933 * read_oob_from_regs - read data from OOB registers
934 * @ctrl: NAND controller
935 * @i: sub-page sector index
936 * @oob: buffer to read to
937 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
938 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
939 */
940static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
941 int sas, int sector_1k)
942{
943 int tbytes = sas << sector_1k;
944 int j;
945
946 /* Adjust OOB values for 1K sector size */
947 if (sector_1k && (i & 0x01))
948 tbytes = max(0, tbytes - (int)ctrl->max_oob);
949 tbytes = min_t(int, tbytes, ctrl->max_oob);
950
951 for (j = 0; j < tbytes; j++)
952 oob[j] = oob_reg_read(ctrl, j);
953 return tbytes;
954}
955
956/*
957 * write_oob_to_regs - write data to OOB registers
958 * @i: sub-page sector index
959 * @oob: buffer to write from
960 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
961 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
962 */
963static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
964 const u8 *oob, int sas, int sector_1k)
965{
966 int tbytes = sas << sector_1k;
967 int j;
968
969 /* Adjust OOB values for 1K sector size */
970 if (sector_1k && (i & 0x01))
971 tbytes = max(0, tbytes - (int)ctrl->max_oob);
972 tbytes = min_t(int, tbytes, ctrl->max_oob);
973
974 for (j = 0; j < tbytes; j += 4)
975 oob_reg_write(ctrl, j,
976 (oob[j + 0] << 24) |
977 (oob[j + 1] << 16) |
978 (oob[j + 2] << 8) |
979 (oob[j + 3] << 0));
980 return tbytes;
981}
982
983static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
984{
985 struct brcmnand_controller *ctrl = data;
986
987 /* Discard all NAND_CTLRDY interrupts during DMA */
988 if (ctrl->dma_pending)
989 return IRQ_HANDLED;
990
991 complete(&ctrl->done);
992 return IRQ_HANDLED;
993}
994
c26211d3
BN		 995/* Handle SoC-specific interrupt hardware */
996static irqreturn_t brcmnand_irq(int irq, void *data)
997{
998 struct brcmnand_controller *ctrl = data;
999
1000 if (ctrl->soc->ctlrdy_ack(ctrl->soc))
1001 return brcmnand_ctlrdy_irq(irq, data);
1002
1003 return IRQ_NONE;
1004}
1005
27c5b17c
BN		 1006static irqreturn_t brcmnand_dma_irq(int irq, void *data)
1007{
1008 struct brcmnand_controller *ctrl = data;
1009
1010 complete(&ctrl->dma_done);
1011
1012 return IRQ_HANDLED;
1013}
1014
1015static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
1016{
1017 struct brcmnand_controller *ctrl = host->ctrl;
1018 u32 intfc;
1019
1020 dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd,
1021 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS));
1022 BUG_ON(ctrl->cmd_pending != 0);
1023 ctrl->cmd_pending = cmd;
1024
1025 intfc = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
1026 BUG_ON(!(intfc & INTFC_CTLR_READY));
1027
1028 mb(); /* flush previous writes */
1029 brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
1030 cmd << brcmnand_cmd_shift(ctrl));
1031}
1032
1033/***********************************************************************
1034 * NAND MTD API: read/program/erase
1035 ***********************************************************************/
1036
1037static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
1038 unsigned int ctrl)
1039{
1040 /* intentionally left blank */
1041}
1042
1043static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1044{
4bd4ebcc 1045 struct nand_chip *chip = mtd_to_nand(mtd);
27c5b17c
BN		 1046 struct brcmnand_host *host = chip->priv;
1047 struct brcmnand_controller *ctrl = host->ctrl;
1048 unsigned long timeo = msecs_to_jiffies(100);
1049
1050 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1051 if (ctrl->cmd_pending &&
1052 wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
1053 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1054 >> brcmnand_cmd_shift(ctrl);
1055
1056 dev_err_ratelimited(ctrl->dev,
1057 "timeout waiting for command %#02x\n", cmd);
1058 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
1059 brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
1060 }
1061 ctrl->cmd_pending = 0;
1062 return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1063 INTFC_FLASH_STATUS;
1064}
1065
1066enum {
1067 LLOP_RE = BIT(16),
1068 LLOP_WE = BIT(17),
1069 LLOP_ALE = BIT(18),
1070 LLOP_CLE = BIT(19),
1071 LLOP_RETURN_IDLE = BIT(31),
1072
1073 LLOP_DATA_MASK = GENMASK(15, 0),
1074};
1075
1076static int brcmnand_low_level_op(struct brcmnand_host *host,
1077 enum brcmnand_llop_type type, u32 data,
1078 bool last_op)
1079{
f1c4c999 1080 struct mtd_info *mtd = nand_to_mtd(&host->chip);
27c5b17c
BN		 1081 struct nand_chip *chip = &host->chip;
1082 struct brcmnand_controller *ctrl = host->ctrl;
1083 u32 tmp;
1084
1085 tmp = data & LLOP_DATA_MASK;
1086 switch (type) {
1087 case LL_OP_CMD:
1088 tmp |= LLOP_WE | LLOP_CLE;
1089 break;
1090 case LL_OP_ADDR:
1091 /* WE | ALE */
1092 tmp |= LLOP_WE | LLOP_ALE;
1093 break;
1094 case LL_OP_WR:
1095 /* WE */
1096 tmp |= LLOP_WE;
1097 break;
1098 case LL_OP_RD:
1099 /* RE */
1100 tmp |= LLOP_RE;
1101 break;
1102 }
1103 if (last_op)
1104 /* RETURN_IDLE */
1105 tmp |= LLOP_RETURN_IDLE;
1106
1107 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
1108
1109 brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
1110 (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1111
1112 brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1113 return brcmnand_waitfunc(mtd, chip);
1114}
1115
1116static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
1117 int column, int page_addr)
1118{
4bd4ebcc 1119 struct nand_chip *chip = mtd_to_nand(mtd);
27c5b17c
BN		 1120 struct brcmnand_host *host = chip->priv;
1121 struct brcmnand_controller *ctrl = host->ctrl;
1122 u64 addr = (u64)page_addr << chip->page_shift;
1123 int native_cmd = 0;
1124
1125 if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
1126 command == NAND_CMD_RNDOUT)
1127 addr = (u64)column;
1128 /* Avoid propagating a negative, don't-care address */
1129 else if (page_addr < 0)
1130 addr = 0;
1131
1132 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
1133 (unsigned long long)addr);
1134
1135 host->last_cmd = command;
1136 host->last_byte = 0;
1137 host->last_addr = addr;
1138
1139 switch (command) {
1140 case NAND_CMD_RESET:
1141 native_cmd = CMD_FLASH_RESET;
1142 break;
1143 case NAND_CMD_STATUS:
1144 native_cmd = CMD_STATUS_READ;
1145 break;
1146 case NAND_CMD_READID:
1147 native_cmd = CMD_DEVICE_ID_READ;
1148 break;
1149 case NAND_CMD_READOOB:
1150 native_cmd = CMD_SPARE_AREA_READ;
1151 break;
1152 case NAND_CMD_ERASE1:
1153 native_cmd = CMD_BLOCK_ERASE;
1154 brcmnand_wp(mtd, 0);
1155 break;
1156 case NAND_CMD_PARAM:
1157 native_cmd = CMD_PARAMETER_READ;
1158 break;
1159 case NAND_CMD_SET_FEATURES:
1160 case NAND_CMD_GET_FEATURES:
1161 brcmnand_low_level_op(host, LL_OP_CMD, command, false);
1162 brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
1163 break;
1164 case NAND_CMD_RNDOUT:
1165 native_cmd = CMD_PARAMETER_CHANGE_COL;
1166 addr &= ~((u64)(FC_BYTES - 1));
1167 /*
1168 * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
1169 * NB: hwcfg.sector_size_1k may not be initialized yet
1170 */
1171 if (brcmnand_get_sector_size_1k(host)) {
1172 host->hwcfg.sector_size_1k =
1173 brcmnand_get_sector_size_1k(host);
1174 brcmnand_set_sector_size_1k(host, 0);
1175 }
1176 break;
1177 }
1178
1179 if (!native_cmd)
1180 return;
1181
1182 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1183 (host->cs << 16) | ((addr >> 32) & 0xffff));
1184 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1185 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr));
1186 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1187
1188 brcmnand_send_cmd(host, native_cmd);
1189 brcmnand_waitfunc(mtd, chip);
1190
1191 if (native_cmd == CMD_PARAMETER_READ ||
1192 native_cmd == CMD_PARAMETER_CHANGE_COL) {
d618baf9
BN		 1193 /* Copy flash cache word-wise */
1194 u32 *flash_cache = (u32 *)ctrl->flash_cache;
27c5b17c 1195 int i;
c26211d3
BN		 1196
1197 brcmnand_soc_data_bus_prepare(ctrl->soc);
1198
27c5b17c
BN		 1199 /*
1200 * Must cache the FLASH_CACHE now, since changes in
1201 * SECTOR_SIZE_1K may invalidate it
1202 */
1203 for (i = 0; i < FC_WORDS; i++)
d618baf9
BN		 1204 /*
1205 * Flash cache is big endian for parameter pages, at
1206 * least on STB SoCs
1207 */
1208 flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i));
c26211d3
BN		 1209
1210 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1211
27c5b17c
BN		 1212 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
1213 if (host->hwcfg.sector_size_1k)
1214 brcmnand_set_sector_size_1k(host,
1215 host->hwcfg.sector_size_1k);
1216 }
1217
1218 /* Re-enable protection is necessary only after erase */
1219 if (command == NAND_CMD_ERASE1)
1220 brcmnand_wp(mtd, 1);
1221}
1222
1223static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
1224{
4bd4ebcc 1225 struct nand_chip *chip = mtd_to_nand(mtd);
27c5b17c
BN		 1226 struct brcmnand_host *host = chip->priv;
1227 struct brcmnand_controller *ctrl = host->ctrl;
1228 uint8_t ret = 0;
1229 int addr, offs;
1230
1231 switch (host->last_cmd) {
1232 case NAND_CMD_READID:
1233 if (host->last_byte < 4)
1234 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
1235 (24 - (host->last_byte << 3));
1236 else if (host->last_byte < 8)
1237 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
1238 (56 - (host->last_byte << 3));
1239 break;
1240
1241 case NAND_CMD_READOOB:
1242 ret = oob_reg_read(ctrl, host->last_byte);
1243 break;
1244
1245 case NAND_CMD_STATUS:
1246 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1247 INTFC_FLASH_STATUS;
1248 if (wp_on) /* hide WP status */
1249 ret |= NAND_STATUS_WP;
1250 break;
1251
1252 case NAND_CMD_PARAM:
1253 case NAND_CMD_RNDOUT:
1254 addr = host->last_addr + host->last_byte;
1255 offs = addr & (FC_BYTES - 1);
1256
1257 /* At FC_BYTES boundary, switch to next column */
1258 if (host->last_byte > 0 && offs == 0)
1259 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, addr, -1);
1260
d618baf9 1261 ret = ctrl->flash_cache[offs];
27c5b17c
BN		 1262 break;
1263 case NAND_CMD_GET_FEATURES:
1264 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
1265 ret = 0;
1266 } else {
1267 bool last = host->last_byte ==
1268 ONFI_SUBFEATURE_PARAM_LEN - 1;
1269 brcmnand_low_level_op(host, LL_OP_RD, 0, last);
1270 ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
1271 }
1272 }
1273
1274 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
1275 host->last_byte++;
1276
1277 return ret;
1278}
1279
1280static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1281{
1282 int i;
1283
1284 for (i = 0; i < len; i++, buf++)
1285 *buf = brcmnand_read_byte(mtd);
1286}
1287
1288static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
1289 int len)
1290{
1291 int i;
4bd4ebcc 1292 struct nand_chip *chip = mtd_to_nand(mtd);
27c5b17c
BN		 1293 struct brcmnand_host *host = chip->priv;
1294
1295 switch (host->last_cmd) {
1296 case NAND_CMD_SET_FEATURES:
1297 for (i = 0; i < len; i++)
1298 brcmnand_low_level_op(host, LL_OP_WR, buf[i],
1299 (i + 1) == len);
1300 break;
1301 default:
1302 BUG();
1303 break;
1304 }
1305}
1306
1307/**
1308 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1309 * following ahead of time:
1310 * - Is this descriptor the beginning or end of a linked list?
1311 * - What is the (DMA) address of the next descriptor in the linked list?
1312 */
1313static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
1314 struct brcm_nand_dma_desc *desc, u64 addr,
1315 dma_addr_t buf, u32 len, u8 dma_cmd,
1316 bool begin, bool end,
1317 dma_addr_t next_desc)
1318{
1319 memset(desc, 0, sizeof(*desc));
1320 /* Descriptors are written in native byte order (wordwise) */
1321 desc->next_desc = lower_32_bits(next_desc);
1322 desc->next_desc_ext = upper_32_bits(next_desc);
1323 desc->cmd_irq = (dma_cmd << 24) |
1324 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
1325 (!!begin) | ((!!end) << 1); /* head, tail */
1326#ifdef CONFIG_CPU_BIG_ENDIAN
1327 desc->cmd_irq |= 0x01 << 12;
1328#endif
1329 desc->dram_addr = lower_32_bits(buf);
1330 desc->dram_addr_ext = upper_32_bits(buf);
1331 desc->tfr_len = len;
1332 desc->total_len = len;
1333 desc->flash_addr = lower_32_bits(addr);
1334 desc->flash_addr_ext = upper_32_bits(addr);
1335 desc->cs = host->cs;
1336 desc->status_valid = 0x01;
1337 return 0;
1338}
1339
1340/**
1341 * Kick the FLASH_DMA engine, with a given DMA descriptor
1342 */
1343static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
1344{
1345 struct brcmnand_controller *ctrl = host->ctrl;
1346 unsigned long timeo = msecs_to_jiffies(100);
1347
1348 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
1349 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
1350 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
1351 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
1352
1353 /* Start FLASH_DMA engine */
1354 ctrl->dma_pending = true;
1355 mb(); /* flush previous writes */
1356 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
1357
1358 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
1359 dev_err(ctrl->dev,
1360 "timeout waiting for DMA; status %#x, error status %#x\n",
1361 flash_dma_readl(ctrl, FLASH_DMA_STATUS),
1362 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
1363 }
1364 ctrl->dma_pending = false;
1365 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
1366}
1367
1368static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1369 u32 len, u8 dma_cmd)
1370{
1371 struct brcmnand_controller *ctrl = host->ctrl;
1372 dma_addr_t buf_pa;
1373 int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1374
1375 buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
1376 if (dma_mapping_error(ctrl->dev, buf_pa)) {
1377 dev_err(ctrl->dev, "unable to map buffer for DMA\n");
1378 return -ENOMEM;
1379 }
1380
1381 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
1382 dma_cmd, true, true, 0);
1383
1384 brcmnand_dma_run(host, ctrl->dma_pa);
1385
1386 dma_unmap_single(ctrl->dev, buf_pa, len, dir);
1387
1388 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
1389 return -EBADMSG;
1390 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
1391 return -EUCLEAN;
1392
1393 return 0;
1394}
1395
1396/*
1397 * Assumes proper CS is already set
1398 */
1399static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
1400 u64 addr, unsigned int trans, u32 *buf,
1401 u8 *oob, u64 *err_addr)
1402{
1403 struct brcmnand_host *host = chip->priv;
1404 struct brcmnand_controller *ctrl = host->ctrl;
1405 int i, j, ret = 0;
1406
1407 /* Clear error addresses */
1408 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
1409 brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
04016697
SA		 1410 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0);
1411 brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0);
27c5b17c
BN		 1412
1413 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1414 (host->cs << 16) | ((addr >> 32) & 0xffff));
1415 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1416
1417 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1418 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1419 lower_32_bits(addr));
1420 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1421 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1422 brcmnand_send_cmd(host, CMD_PAGE_READ);
1423 brcmnand_waitfunc(mtd, chip);
1424
c26211d3
BN		 1425 if (likely(buf)) {
1426 brcmnand_soc_data_bus_prepare(ctrl->soc);
1427
27c5b17c
BN		 1428 for (j = 0; j < FC_WORDS; j++, buf++)
1429 *buf = brcmnand_read_fc(ctrl, j);
1430
c26211d3
BN		 1431 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1432 }
1433
27c5b17c
BN		 1434 if (oob)
1435 oob += read_oob_from_regs(ctrl, i, oob,
1436 mtd->oobsize / trans,
1437 host->hwcfg.sector_size_1k);
1438
1439 if (!ret) {
1440 *err_addr = brcmnand_read_reg(ctrl,
1441 BRCMNAND_UNCORR_ADDR) |
1442 ((u64)(brcmnand_read_reg(ctrl,
1443 BRCMNAND_UNCORR_EXT_ADDR)
1444 & 0xffff) << 32);
1445 if (*err_addr)
1446 ret = -EBADMSG;
1447 }
1448
1449 if (!ret) {
1450 *err_addr = brcmnand_read_reg(ctrl,
1451 BRCMNAND_CORR_ADDR) |
1452 ((u64)(brcmnand_read_reg(ctrl,
1453 BRCMNAND_CORR_EXT_ADDR)
1454 & 0xffff) << 32);
1455 if (*err_addr)
1456 ret = -EUCLEAN;
1457 }
1458 }
1459
1460 return ret;
1461}
1462
1463static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
1464 u64 addr, unsigned int trans, u32 *buf, u8 *oob)
1465{
1466 struct brcmnand_host *host = chip->priv;
1467 struct brcmnand_controller *ctrl = host->ctrl;
1468 u64 err_addr = 0;
1469 int err;
1470
1471 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
1472
1473 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0);
1474
1475 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1476 err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
1477 CMD_PAGE_READ);
1478 if (err) {
1479 if (mtd_is_bitflip_or_eccerr(err))
1480 err_addr = addr;
1481 else
1482 return -EIO;
1483 }
1484 } else {
1485 if (oob)
1486 memset(oob, 0x99, mtd->oobsize);
1487
1488 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
1489 oob, &err_addr);
1490 }
1491
1492 if (mtd_is_eccerr(err)) {
1493 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
1494 (unsigned long long)err_addr);
1495 mtd->ecc_stats.failed++;
1496 /* NAND layer expects zero on ECC errors */
1497 return 0;
1498 }
1499
1500 if (mtd_is_bitflip(err)) {
1501 unsigned int corrected = brcmnand_count_corrected(ctrl);
1502
1503 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
1504 (unsigned long long)err_addr);
1505 mtd->ecc_stats.corrected += corrected;
1506 /* Always exceed the software-imposed threshold */
1507 return max(mtd->bitflip_threshold, corrected);
1508 }
1509
1510 return 0;
1511}
1512
1513static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1514 uint8_t *buf, int oob_required, int page)
1515{
1516 struct brcmnand_host *host = chip->priv;
1517 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1518
1519 return brcmnand_read(mtd, chip, host->last_addr,
1520 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1521}
1522
1523static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1524 uint8_t *buf, int oob_required, int page)
1525{
1526 struct brcmnand_host *host = chip->priv;
1527 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1528 int ret;
1529
1530 brcmnand_set_ecc_enabled(host, 0);
1531 ret = brcmnand_read(mtd, chip, host->last_addr,
1532 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1533 brcmnand_set_ecc_enabled(host, 1);
1534 return ret;
1535}
1536
1537static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1538 int page)
1539{
1540 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1541 mtd->writesize >> FC_SHIFT,
1542 NULL, (u8 *)chip->oob_poi);
1543}
1544
1545static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1546 int page)
1547{
1548 struct brcmnand_host *host = chip->priv;
1549
1550 brcmnand_set_ecc_enabled(host, 0);
1551 brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1552 mtd->writesize >> FC_SHIFT,
1553 NULL, (u8 *)chip->oob_poi);
1554 brcmnand_set_ecc_enabled(host, 1);
1555 return 0;
1556}
1557
27c5b17c
BN		 1558static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
1559 u64 addr, const u32 *buf, u8 *oob)
1560{
1561 struct brcmnand_host *host = chip->priv;
1562 struct brcmnand_controller *ctrl = host->ctrl;
1563 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
1564 int status, ret = 0;
1565
1566 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
1567
3f08b8ba 1568 if (unlikely((unsigned long)buf & 0x03)) {
27c5b17c 1569 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
3f08b8ba 1570 buf = (u32 *)((unsigned long)buf & ~0x03);
27c5b17c
BN		 1571 }
1572
1573 brcmnand_wp(mtd, 0);
1574
1575 for (i = 0; i < ctrl->max_oob; i += 4)
1576 oob_reg_write(ctrl, i, 0xffffffff);
1577
1578 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1579 if (brcmnand_dma_trans(host, addr, (u32 *)buf,
1580 mtd->writesize, CMD_PROGRAM_PAGE))
1581 ret = -EIO;
1582 goto out;
1583 }
1584
1585 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1586 (host->cs << 16) | ((addr >> 32) & 0xffff));
1587 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1588
1589 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1590 /* full address MUST be set before populating FC */
1591 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1592 lower_32_bits(addr));
1593 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1594
c26211d3
BN		 1595 if (buf) {
1596 brcmnand_soc_data_bus_prepare(ctrl->soc);
1597
27c5b17c
BN		 1598 for (j = 0; j < FC_WORDS; j++, buf++)
1599 brcmnand_write_fc(ctrl, j, *buf);
c26211d3
BN		 1600
1601 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1602 } else if (oob) {
27c5b17c
BN		 1603 for (j = 0; j < FC_WORDS; j++)
1604 brcmnand_write_fc(ctrl, j, 0xffffffff);
c26211d3 1605 }
27c5b17c
BN		 1606
1607 if (oob) {
1608 oob += write_oob_to_regs(ctrl, i, oob,
1609 mtd->oobsize / trans,
1610 host->hwcfg.sector_size_1k);
1611 }
1612
1613 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
1614 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
1615 status = brcmnand_waitfunc(mtd, chip);
1616
1617 if (status & NAND_STATUS_FAIL) {
1618 dev_info(ctrl->dev, "program failed at %llx\n",
1619 (unsigned long long)addr);
1620 ret = -EIO;
1621 goto out;
1622 }
1623 }
1624out:
1625 brcmnand_wp(mtd, 1);
1626 return ret;
1627}
1628
1629static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
45aaeff9 1630 const uint8_t *buf, int oob_required, int page)
27c5b17c
BN		 1631{
1632 struct brcmnand_host *host = chip->priv;
1633 void *oob = oob_required ? chip->oob_poi : NULL;
1634
1635 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1636 return 0;
1637}
1638
1639static int brcmnand_write_page_raw(struct mtd_info *mtd,
1640 struct nand_chip *chip, const uint8_t *buf,
45aaeff9 1641 int oob_required, int page)
27c5b17c
BN		 1642{
1643 struct brcmnand_host *host = chip->priv;
1644 void *oob = oob_required ? chip->oob_poi : NULL;
1645
1646 brcmnand_set_ecc_enabled(host, 0);
1647 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1648 brcmnand_set_ecc_enabled(host, 1);
1649 return 0;
1650}
1651
1652static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1653 int page)
1654{
1655 return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
1656 NULL, chip->oob_poi);
1657}
1658
1659static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1660 int page)
1661{
1662 struct brcmnand_host *host = chip->priv;
1663 int ret;
1664
1665 brcmnand_set_ecc_enabled(host, 0);
1666 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
1667 (u8 *)chip->oob_poi);
1668 brcmnand_set_ecc_enabled(host, 1);
1669
1670 return ret;
1671}
1672
1673/***********************************************************************
1674 * Per-CS setup (1 NAND device)
1675 ***********************************************************************/
1676
1677static int brcmnand_set_cfg(struct brcmnand_host *host,
1678 struct brcmnand_cfg *cfg)
1679{
1680 struct brcmnand_controller *ctrl = host->ctrl;
1681 struct nand_chip *chip = &host->chip;
1682 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1683 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
1684 BRCMNAND_CS_CFG_EXT);
1685 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1686 BRCMNAND_CS_ACC_CONTROL);
1687 u8 block_size = 0, page_size = 0, device_size = 0;
1688 u32 tmp;
1689
1690 if (ctrl->block_sizes) {
1691 int i, found;
1692
1693 for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
1694 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
1695 block_size = i;
1696 found = 1;
1697 }
1698 if (!found) {
1699 dev_warn(ctrl->dev, "invalid block size %u\n",
1700 cfg->block_size);
1701 return -EINVAL;
1702 }
1703 } else {
1704 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
1705 }
1706
1707 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
1708 cfg->block_size > ctrl->max_block_size)) {
1709 dev_warn(ctrl->dev, "invalid block size %u\n",
1710 cfg->block_size);
1711 block_size = 0;
1712 }
1713
1714 if (ctrl->page_sizes) {
1715 int i, found;
1716
1717 for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
1718 if (ctrl->page_sizes[i] == cfg->page_size) {
1719 page_size = i;
1720 found = 1;
1721 }
1722 if (!found) {
1723 dev_warn(ctrl->dev, "invalid page size %u\n",
1724 cfg->page_size);
1725 return -EINVAL;
1726 }
1727 } else {
1728 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
1729 }
1730
1731 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
1732 cfg->page_size > ctrl->max_page_size)) {
1733 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
1734 return -EINVAL;
1735 }
1736
1737 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
1738 dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
1739 (unsigned long long)cfg->device_size);
1740 return -EINVAL;
1741 }
1742 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
1743
3f06d2a9
BN		 1744 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) |
1745 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) |
1746 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) |
1747 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
1748 (device_size << CFG_DEVICE_SIZE_SHIFT);
27c5b17c 1749 if (cfg_offs == cfg_ext_offs) {
3f06d2a9
BN		 1750 tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
1751 (block_size << CFG_BLK_SIZE_SHIFT);
27c5b17c
BN		 1752 nand_writereg(ctrl, cfg_offs, tmp);
1753 } else {
1754 nand_writereg(ctrl, cfg_offs, tmp);
3f06d2a9
BN		 1755 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) |
1756 (block_size << CFG_EXT_BLK_SIZE_SHIFT);
27c5b17c
BN		 1757 nand_writereg(ctrl, cfg_ext_offs, tmp);
1758 }
1759
1760 tmp = nand_readreg(ctrl, acc_control_offs);
1761 tmp &= ~brcmnand_ecc_level_mask(ctrl);
1762 tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
1763 tmp &= ~brcmnand_spare_area_mask(ctrl);
1764 tmp |= cfg->spare_area_size;
1765 nand_writereg(ctrl, acc_control_offs, tmp);
1766
1767 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
1768
1769 /* threshold = ceil(BCH-level * 0.75) */
1770 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
1771
1772 return 0;
1773}
1774
1775static void brcmnand_print_cfg(char *buf, struct brcmnand_cfg *cfg)
1776{
1777 buf += sprintf(buf,
1778 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
1779 (unsigned long long)cfg->device_size >> 20,
1780 cfg->block_size >> 10,
1781 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
1782 cfg->page_size >= 1024 ? "KiB" : "B",
1783 cfg->spare_area_size, cfg->device_width);
1784
1785 /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
1786 if (is_hamming_ecc(cfg))
1787 sprintf(buf, ", Hamming ECC");
1788 else if (cfg->sector_size_1k)
1789 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
1790 else
80204124 1791 sprintf(buf, ", BCH-%u", cfg->ecc_level);
27c5b17c
BN		 1792}
1793
1794/*
1795 * Minimum number of bytes to address a page. Calculated as:
1796 * roundup(log2(size / page-size) / 8)
1797 *
1798 * NB: the following does not "round up" for non-power-of-2 'size'; but this is
1799 * OK because many other things will break if 'size' is irregular...
1800 */
1801static inline int get_blk_adr_bytes(u64 size, u32 writesize)
1802{
1803 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
1804}
1805
1806static int brcmnand_setup_dev(struct brcmnand_host *host)
1807{
f1c4c999 1808 struct mtd_info *mtd = nand_to_mtd(&host->chip);
27c5b17c
BN		 1809 struct nand_chip *chip = &host->chip;
1810 struct brcmnand_controller *ctrl = host->ctrl;
1811 struct brcmnand_cfg *cfg = &host->hwcfg;
1812 char msg[128];
1813 u32 offs, tmp, oob_sector;
1814 int ret;
1815
1816 memset(cfg, 0, sizeof(*cfg));
1817
44ec23c9 1818 ret = of_property_read_u32(nand_get_flash_node(chip),
61528d88 1819 "brcm,nand-oob-sector-size",
27c5b17c
BN		 1820 &oob_sector);
1821 if (ret) {
1822 /* Use detected size */
1823 cfg->spare_area_size = mtd->oobsize /
1824 (mtd->writesize >> FC_SHIFT);
1825 } else {
1826 cfg->spare_area_size = oob_sector;
1827 }
1828 if (cfg->spare_area_size > ctrl->max_oob)
1829 cfg->spare_area_size = ctrl->max_oob;
1830 /*
1831 * Set oobsize to be consistent with controller's spare_area_size, as
1832 * the rest is inaccessible.
1833 */
1834 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
1835
1836 cfg->device_size = mtd->size;
1837 cfg->block_size = mtd->erasesize;
1838 cfg->page_size = mtd->writesize;
1839 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
1840 cfg->col_adr_bytes = 2;
1841 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
1842
1843 switch (chip->ecc.size) {
1844 case 512:
1845 if (chip->ecc.strength == 1) /* Hamming */
1846 cfg->ecc_level = 15;
1847 else
1848 cfg->ecc_level = chip->ecc.strength;
1849 cfg->sector_size_1k = 0;
1850 break;
1851 case 1024:
1852 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
1853 dev_err(ctrl->dev, "1KB sectors not supported\n");
1854 return -EINVAL;
1855 }
1856 if (chip->ecc.strength & 0x1) {
1857 dev_err(ctrl->dev,
1858 "odd ECC not supported with 1KB sectors\n");
1859 return -EINVAL;
1860 }
1861
1862 cfg->ecc_level = chip->ecc.strength >> 1;
1863 cfg->sector_size_1k = 1;
1864 break;
1865 default:
1866 dev_err(ctrl->dev, "unsupported ECC size: %d\n",
1867 chip->ecc.size);
1868 return -EINVAL;
1869 }
1870
1871 cfg->ful_adr_bytes = cfg->blk_adr_bytes;
1872 if (mtd->writesize > 512)
1873 cfg->ful_adr_bytes += cfg->col_adr_bytes;
1874 else
1875 cfg->ful_adr_bytes += 1;
1876
1877 ret = brcmnand_set_cfg(host, cfg);
1878 if (ret)
1879 return ret;
1880
1881 brcmnand_set_ecc_enabled(host, 1);
1882
1883 brcmnand_print_cfg(msg, cfg);
1884 dev_info(ctrl->dev, "detected %s\n", msg);
1885
1886 /* Configure ACC_CONTROL */
1887 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
1888 tmp = nand_readreg(ctrl, offs);
1889 tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
1890 tmp &= ~ACC_CONTROL_RD_ERASED;
1891 tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
1892 if (ctrl->features & BRCMNAND_HAS_PREFETCH) {
1893 /*
1894 * FIXME: Flash DMA + prefetch may see spurious erased-page ECC
1895 * errors
1896 */
1897 if (has_flash_dma(ctrl))
1898 tmp &= ~ACC_CONTROL_PREFETCH;
1899 else
1900 tmp |= ACC_CONTROL_PREFETCH;
1901 }
1902 nand_writereg(ctrl, offs, tmp);
1903
1904 return 0;
1905}
1906
d121b66d 1907static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
27c5b17c
BN		 1908{
1909 struct brcmnand_controller *ctrl = host->ctrl;
27c5b17c
BN		 1910 struct platform_device *pdev = host->pdev;
1911 struct mtd_info *mtd;
1912 struct nand_chip *chip;
5e65d48b 1913 int ret;
4d1ea982 1914 u16 cfg_offs;
27c5b17c
BN		 1915
1916 ret = of_property_read_u32(dn, "reg", &host->cs);
1917 if (ret) {
1918 dev_err(&pdev->dev, "can't get chip-select\n");
1919 return -ENXIO;
1920 }
1921
f1c4c999 1922 mtd = nand_to_mtd(&host->chip);
27c5b17c
BN		 1923 chip = &host->chip;
1924
63752199 1925 nand_set_flash_node(chip, dn);
27c5b17c 1926 chip->priv = host;
27c5b17c
BN		 1927 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
1928 host->cs);
1929 mtd->owner = THIS_MODULE;
1930 mtd->dev.parent = &pdev->dev;
1931
1932 chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
1933 chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
1934
1935 chip->cmd_ctrl = brcmnand_cmd_ctrl;
1936 chip->cmdfunc = brcmnand_cmdfunc;
1937 chip->waitfunc = brcmnand_waitfunc;
1938 chip->read_byte = brcmnand_read_byte;
1939 chip->read_buf = brcmnand_read_buf;
1940 chip->write_buf = brcmnand_write_buf;
1941
1942 chip->ecc.mode = NAND_ECC_HW;
1943 chip->ecc.read_page = brcmnand_read_page;
27c5b17c
BN		 1944 chip->ecc.write_page = brcmnand_write_page;
1945 chip->ecc.read_page_raw = brcmnand_read_page_raw;
1946 chip->ecc.write_page_raw = brcmnand_write_page_raw;
1947 chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
1948 chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
1949 chip->ecc.read_oob = brcmnand_read_oob;
1950 chip->ecc.write_oob = brcmnand_write_oob;
1951
1952 chip->controller = &ctrl->controller;
1953
4d1ea982
AP		 1954 /*
1955 * The bootloader might have configured 16bit mode but
1956 * NAND READID command only works in 8bit mode. We force
1957 * 8bit mode here to ensure that NAND READID commands works.
1958 */
1959 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1960 nand_writereg(ctrl, cfg_offs,
1961 nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
1962
27c5b17c
BN		 1963 if (nand_scan_ident(mtd, 1, NULL))
1964 return -ENXIO;
1965
1966 chip->options |= NAND_NO_SUBPAGE_WRITE;
1967 /*
1968 * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
1969 * to/from, and have nand_base pass us a bounce buffer instead, as
1970 * needed.
1971 */
1972 chip->options |= NAND_USE_BOUNCE_BUFFER;
1973
1974 if (of_get_nand_on_flash_bbt(dn))
1975 chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1976
1977 if (brcmnand_setup_dev(host))
1978 return -ENXIO;
1979
1980 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
1981 /* only use our internal HW threshold */
1982 mtd->bitflip_threshold = 1;
1983
1984 chip->ecc.layout = brcmstb_choose_ecc_layout(host);
1985 if (!chip->ecc.layout)
1986 return -ENXIO;
1987
1988 if (nand_scan_tail(mtd))
1989 return -ENXIO;
1990
a61ae81a 1991 return mtd_device_register(mtd, NULL, 0);
27c5b17c
BN		 1992}
1993
1994static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
1995 int restore)
1996{
1997 struct brcmnand_controller *ctrl = host->ctrl;
1998 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1999 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
2000 BRCMNAND_CS_CFG_EXT);
2001 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
2002 BRCMNAND_CS_ACC_CONTROL);
2003 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
2004 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
2005
2006 if (restore) {
2007 nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
2008 if (cfg_offs != cfg_ext_offs)
2009 nand_writereg(ctrl, cfg_ext_offs,
2010 host->hwcfg.config_ext);
2011 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
2012 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
2013 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
2014 } else {
2015 host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
2016 if (cfg_offs != cfg_ext_offs)
2017 host->hwcfg.config_ext =
2018 nand_readreg(ctrl, cfg_ext_offs);
2019 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
2020 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
2021 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
2022 }
2023}
2024
2025static int brcmnand_suspend(struct device *dev)
2026{
2027 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2028 struct brcmnand_host *host;
2029
2030 list_for_each_entry(host, &ctrl->host_list, node)
2031 brcmnand_save_restore_cs_config(host, 0);
2032
2033 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
2034 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
2035 ctrl->corr_stat_threshold =
2036 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
2037
2038 if (has_flash_dma(ctrl))
2039 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
2040
2041 return 0;
2042}
2043
2044static int brcmnand_resume(struct device *dev)
2045{
2046 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2047 struct brcmnand_host *host;
2048
2049 if (has_flash_dma(ctrl)) {
2050 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
2051 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2052 }
2053
2054 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
2055 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
2056 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
2057 ctrl->corr_stat_threshold);
c26211d3
BN		 2058 if (ctrl->soc) {
2059 /* Clear/re-enable interrupt */
2060 ctrl->soc->ctlrdy_ack(ctrl->soc);
2061 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2062 }
27c5b17c
BN		 2063
2064 list_for_each_entry(host, &ctrl->host_list, node) {
f1c4c999
BB		 2065 struct nand_chip *chip = &host->chip;
2066 struct mtd_info *mtd = nand_to_mtd(chip);
27c5b17c
BN		 2067
2068 brcmnand_save_restore_cs_config(host, 1);
2069
2070 /* Reset the chip, required by some chips after power-up */
2071 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2072 }
2073
2074 return 0;
2075}
2076
2077const struct dev_pm_ops brcmnand_pm_ops = {
2078 .suspend = brcmnand_suspend,
2079 .resume = brcmnand_resume,
2080};
2081EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2082
2083static const struct of_device_id brcmnand_of_match[] = {
2084 { .compatible = "brcm,brcmnand-v4.0" },
2085 { .compatible = "brcm,brcmnand-v5.0" },
2086 { .compatible = "brcm,brcmnand-v6.0" },
2087 { .compatible = "brcm,brcmnand-v6.1" },
2088 { .compatible = "brcm,brcmnand-v7.0" },
2089 { .compatible = "brcm,brcmnand-v7.1" },
2090 {},
2091};
2092MODULE_DEVICE_TABLE(of, brcmnand_of_match);
2093
2094/***********************************************************************
2095 * Platform driver setup (per controller)
2096 ***********************************************************************/
2097
2098int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
2099{
2100 struct device *dev = &pdev->dev;
2101 struct device_node *dn = dev->of_node, *child;
bcb83a19 2102 struct brcmnand_controller *ctrl;
27c5b17c
BN		 2103 struct resource *res;
2104 int ret;
2105
2106 /* We only support device-tree instantiation */
2107 if (!dn)
2108 return -ENODEV;
2109
2110 if (!of_match_node(brcmnand_of_match, dn))
2111 return -ENODEV;
2112
2113 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2114 if (!ctrl)
2115 return -ENOMEM;
2116
2117 dev_set_drvdata(dev, ctrl);
2118 ctrl->dev = dev;
2119
2120 init_completion(&ctrl->done);
2121 init_completion(&ctrl->dma_done);
2122 spin_lock_init(&ctrl->controller.lock);
2123 init_waitqueue_head(&ctrl->controller.wq);
2124 INIT_LIST_HEAD(&ctrl->host_list);
2125
2126 /* NAND register range */
2127 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2128 ctrl->nand_base = devm_ioremap_resource(dev, res);
2129 if (IS_ERR(ctrl->nand_base))
2130 return PTR_ERR(ctrl->nand_base);
2131
5c05bc00
SA		 2132 /* Enable clock before using NAND registers */
2133 ctrl->clk = devm_clk_get(dev, "nand");
2134 if (!IS_ERR(ctrl->clk)) {
2135 ret = clk_prepare_enable(ctrl->clk);
2136 if (ret)
2137 return ret;
2138 } else {
2139 ret = PTR_ERR(ctrl->clk);
2140 if (ret == -EPROBE_DEFER)
2141 return ret;
2142
2143 ctrl->clk = NULL;
2144 }
2145
27c5b17c
BN		 2146 /* Initialize NAND revision */
2147 ret = brcmnand_revision_init(ctrl);
2148 if (ret)
5c05bc00 2149 goto err;
27c5b17c
BN		 2150
2151 /*
2152 * Most chips have this cache at a fixed offset within 'nand' block.
2153 * Some must specify this region separately.
2154 */
2155 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
2156 if (res) {
2157 ctrl->nand_fc = devm_ioremap_resource(dev, res);
5c05bc00
SA		 2158 if (IS_ERR(ctrl->nand_fc)) {
2159 ret = PTR_ERR(ctrl->nand_fc);
2160 goto err;
2161 }
27c5b17c
BN		 2162 } else {
2163 ctrl->nand_fc = ctrl->nand_base +
2164 ctrl->reg_offsets[BRCMNAND_FC_BASE];
2165 }
2166
2167 /* FLASH_DMA */
2168 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
2169 if (res) {
2170 ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
5c05bc00
SA		 2171 if (IS_ERR(ctrl->flash_dma_base)) {
2172 ret = PTR_ERR(ctrl->flash_dma_base);
2173 goto err;
2174 }
27c5b17c
BN		 2175
2176 flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
2177 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2178
2179 /* Allocate descriptor(s) */
2180 ctrl->dma_desc = dmam_alloc_coherent(dev,
2181 sizeof(*ctrl->dma_desc),
2182 &ctrl->dma_pa, GFP_KERNEL);
5c05bc00
SA		 2183 if (!ctrl->dma_desc) {
2184 ret = -ENOMEM;
2185 goto err;
2186 }
27c5b17c
BN		 2187
2188 ctrl->dma_irq = platform_get_irq(pdev, 1);
2189 if ((int)ctrl->dma_irq < 0) {
2190 dev_err(dev, "missing FLASH_DMA IRQ\n");
5c05bc00
SA		 2191 ret = -ENODEV;
2192 goto err;
27c5b17c
BN		 2193 }
2194
2195 ret = devm_request_irq(dev, ctrl->dma_irq,
2196 brcmnand_dma_irq, 0, DRV_NAME,
2197 ctrl);
2198 if (ret < 0) {
2199 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2200 ctrl->dma_irq, ret);
5c05bc00 2201 goto err;
27c5b17c
BN		 2202 }
2203
2204 dev_info(dev, "enabling FLASH_DMA\n");
2205 }
2206
2207 /* Disable automatic device ID config, direct addressing */
2208 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
2209 CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
2210 /* Disable XOR addressing */
2211 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
2212
2213 if (ctrl->features & BRCMNAND_HAS_WP) {
2214 /* Permanently disable write protection */
2215 if (wp_on == 2)
2216 brcmnand_set_wp(ctrl, false);
2217 } else {
2218 wp_on = 0;
2219 }
2220
2221 /* IRQ */
2222 ctrl->irq = platform_get_irq(pdev, 0);
2223 if ((int)ctrl->irq < 0) {
2224 dev_err(dev, "no IRQ defined\n");
5c05bc00
SA		 2225 ret = -ENODEV;
2226 goto err;
27c5b17c
BN		 2227 }
2228
c26211d3
BN		 2229 /*
2230 * Some SoCs integrate this controller (e.g., its interrupt bits) in
2231 * interesting ways
2232 */
2233 if (soc) {
2234 ctrl->soc = soc;
2235
2236 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
2237 DRV_NAME, ctrl);
2238
2239 /* Enable interrupt */
2240 ctrl->soc->ctlrdy_ack(ctrl->soc);
2241 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2242 } else {
2243 /* Use standard interrupt infrastructure */
2244 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
2245 DRV_NAME, ctrl);
2246 }
27c5b17c
BN		 2247 if (ret < 0) {
2248 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2249 ctrl->irq, ret);
5c05bc00 2250 goto err;
27c5b17c
BN		 2251 }
2252
2253 for_each_available_child_of_node(dn, child) {
2254 if (of_device_is_compatible(child, "brcm,nandcs")) {
2255 struct brcmnand_host *host;
2256
2257 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
081976bc
JL		 2258 if (!host) {
2259 of_node_put(child);
5c05bc00
SA		 2260 ret = -ENOMEM;
2261 goto err;
081976bc 2262 }
27c5b17c
BN		 2263 host->pdev = pdev;
2264 host->ctrl = ctrl;
27c5b17c 2265
d121b66d 2266 ret = brcmnand_init_cs(host, child);
081976bc
JL		 2267 if (ret) {
2268 devm_kfree(dev, host);
27c5b17c 2269 continue; /* Try all chip-selects */
081976bc 2270 }
27c5b17c
BN		 2271
2272 list_add_tail(&host->node, &ctrl->host_list);
2273 }
2274 }
2275
2276 /* No chip-selects could initialize properly */
5c05bc00
SA		 2277 if (list_empty(&ctrl->host_list)) {
2278 ret = -ENODEV;
2279 goto err;
2280 }
27c5b17c
BN		 2281
2282 return 0;
5c05bc00
SA		 2283
2284err:
2285 clk_disable_unprepare(ctrl->clk);
2286 return ret;
2287
27c5b17c
BN		 2288}
2289EXPORT_SYMBOL_GPL(brcmnand_probe);
2290
2291int brcmnand_remove(struct platform_device *pdev)
2292{
2293 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2294 struct brcmnand_host *host;
2295
2296 list_for_each_entry(host, &ctrl->host_list, node)
f1c4c999 2297 nand_release(nand_to_mtd(&host->chip));
27c5b17c 2298
5c05bc00
SA		 2299 clk_disable_unprepare(ctrl->clk);
2300
27c5b17c
BN		 2301 dev_set_drvdata(&pdev->dev, NULL);
2302
2303 return 0;
2304}
2305EXPORT_SYMBOL_GPL(brcmnand_remove);
2306
2307MODULE_LICENSE("GPL v2");
2308MODULE_AUTHOR("Kevin Cernekee");
2309MODULE_AUTHOR("Brian Norris");
2310MODULE_DESCRIPTION("NAND driver for Broadcom chips");
2311MODULE_ALIAS("platform:brcmnand");
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