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Commit | Line | Data |
---|---|---|
c9ac5977 | 1 | /* |
fbad5696 | 2 | * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01 |
5467fb02 DW |
3 | * |
4 | * Copyright © 2006 Red Hat, Inc. | |
5 | * Copyright © 2006 David Woodhouse <dwmw2@infradead.org> | |
6 | */ | |
7 | ||
8dd851de | 8 | #define DEBUG |
5467fb02 DW |
9 | |
10 | #include <linux/device.h> | |
11 | #undef DEBUG | |
12 | #include <linux/mtd/mtd.h> | |
13 | #include <linux/mtd/nand.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/interrupt.h> | |
a1274302 | 17 | #include <linux/dma-mapping.h> |
5467fb02 DW |
18 | #include <asm/io.h> |
19 | ||
20 | #define CAFE_NAND_CTRL1 0x00 | |
21 | #define CAFE_NAND_CTRL2 0x04 | |
22 | #define CAFE_NAND_CTRL3 0x08 | |
23 | #define CAFE_NAND_STATUS 0x0c | |
24 | #define CAFE_NAND_IRQ 0x10 | |
25 | #define CAFE_NAND_IRQ_MASK 0x14 | |
26 | #define CAFE_NAND_DATA_LEN 0x18 | |
27 | #define CAFE_NAND_ADDR1 0x1c | |
28 | #define CAFE_NAND_ADDR2 0x20 | |
29 | #define CAFE_NAND_TIMING1 0x24 | |
30 | #define CAFE_NAND_TIMING2 0x28 | |
31 | #define CAFE_NAND_TIMING3 0x2c | |
32 | #define CAFE_NAND_NONMEM 0x30 | |
04459d7c | 33 | #define CAFE_NAND_ECC_RESULT 0x3C |
fbad5696 DW |
34 | #define CAFE_NAND_DMA_CTRL 0x40 |
35 | #define CAFE_NAND_DMA_ADDR0 0x44 | |
36 | #define CAFE_NAND_DMA_ADDR1 0x48 | |
04459d7c DW |
37 | #define CAFE_NAND_ECC_SYN01 0x50 |
38 | #define CAFE_NAND_ECC_SYN23 0x54 | |
39 | #define CAFE_NAND_ECC_SYN45 0x58 | |
40 | #define CAFE_NAND_ECC_SYN67 0x5c | |
5467fb02 DW |
41 | #define CAFE_NAND_READ_DATA 0x1000 |
42 | #define CAFE_NAND_WRITE_DATA 0x2000 | |
43 | ||
195a253b DW |
44 | #define CAFE_GLOBAL_CTRL 0x3004 |
45 | #define CAFE_GLOBAL_IRQ 0x3008 | |
46 | #define CAFE_GLOBAL_IRQ_MASK 0x300c | |
47 | #define CAFE_NAND_RESET 0x3034 | |
48 | ||
04459d7c DW |
49 | int cafe_correct_ecc(unsigned char *buf, |
50 | unsigned short *chk_syndrome_list); | |
51 | ||
5467fb02 DW |
52 | struct cafe_priv { |
53 | struct nand_chip nand; | |
54 | struct pci_dev *pdev; | |
55 | void __iomem *mmio; | |
56 | uint32_t ctl1; | |
57 | uint32_t ctl2; | |
58 | int datalen; | |
59 | int nr_data; | |
60 | int data_pos; | |
61 | int page_addr; | |
62 | dma_addr_t dmaaddr; | |
63 | unsigned char *dmabuf; | |
5467fb02 DW |
64 | }; |
65 | ||
b478c775 | 66 | static int usedma = 1; |
5467fb02 DW |
67 | module_param(usedma, int, 0644); |
68 | ||
8dd851de DW |
69 | static int skipbbt = 0; |
70 | module_param(skipbbt, int, 0644); | |
71 | ||
72 | static int debug = 0; | |
73 | module_param(debug, int, 0644); | |
74 | ||
be8444bd DW |
75 | static int regdebug = 0; |
76 | module_param(regdebug, int, 0644); | |
77 | ||
b478c775 | 78 | static int checkecc = 1; |
470b0a90 DW |
79 | module_param(checkecc, int, 0644); |
80 | ||
527a4f45 DW |
81 | static int numtimings; |
82 | static int timing[3]; | |
83 | module_param_array(timing, int, &numtimings, 0644); | |
b478c775 | 84 | |
04459d7c | 85 | /* Hrm. Why isn't this already conditional on something in the struct device? */ |
8dd851de DW |
86 | #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0) |
87 | ||
195a253b DW |
88 | /* Make it easier to switch to PIO if we need to */ |
89 | #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr) | |
90 | #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr) | |
8dd851de | 91 | |
5467fb02 DW |
92 | static int cafe_device_ready(struct mtd_info *mtd) |
93 | { | |
94 | struct cafe_priv *cafe = mtd->priv; | |
195a253b DW |
95 | int result = !!(cafe_readl(cafe, NAND_STATUS) | 0x40000000); |
96 | uint32_t irqs = cafe_readl(cafe, NAND_IRQ); | |
fbad5696 | 97 | |
195a253b | 98 | cafe_writel(cafe, irqs, NAND_IRQ); |
fbad5696 | 99 | |
8dd851de | 100 | cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n", |
195a253b DW |
101 | result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ), |
102 | cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK)); | |
fbad5696 | 103 | |
5467fb02 DW |
104 | return result; |
105 | } | |
106 | ||
107 | ||
108 | static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
109 | { | |
110 | struct cafe_priv *cafe = mtd->priv; | |
111 | ||
112 | if (usedma) | |
113 | memcpy(cafe->dmabuf + cafe->datalen, buf, len); | |
114 | else | |
115 | memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len); | |
fbad5696 | 116 | |
5467fb02 DW |
117 | cafe->datalen += len; |
118 | ||
8dd851de | 119 | cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n", |
5467fb02 DW |
120 | len, cafe->datalen); |
121 | } | |
122 | ||
123 | static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
124 | { | |
125 | struct cafe_priv *cafe = mtd->priv; | |
126 | ||
127 | if (usedma) | |
128 | memcpy(buf, cafe->dmabuf + cafe->datalen, len); | |
129 | else | |
130 | memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len); | |
131 | ||
8dd851de | 132 | cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n", |
5467fb02 DW |
133 | len, cafe->datalen); |
134 | cafe->datalen += len; | |
135 | } | |
136 | ||
137 | static uint8_t cafe_read_byte(struct mtd_info *mtd) | |
138 | { | |
139 | struct cafe_priv *cafe = mtd->priv; | |
140 | uint8_t d; | |
141 | ||
142 | cafe_read_buf(mtd, &d, 1); | |
8dd851de | 143 | cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d); |
5467fb02 DW |
144 | |
145 | return d; | |
146 | } | |
147 | ||
148 | static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command, | |
149 | int column, int page_addr) | |
150 | { | |
151 | struct cafe_priv *cafe = mtd->priv; | |
152 | int adrbytes = 0; | |
153 | uint32_t ctl1; | |
154 | uint32_t doneint = 0x80000000; | |
5467fb02 | 155 | |
8dd851de | 156 | cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n", |
5467fb02 DW |
157 | command, column, page_addr); |
158 | ||
159 | if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) { | |
160 | /* Second half of a command we already calculated */ | |
195a253b | 161 | cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2); |
5467fb02 | 162 | ctl1 = cafe->ctl1; |
cad40654 | 163 | cafe->ctl2 &= ~(1<<30); |
8dd851de | 164 | cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n", |
5467fb02 DW |
165 | cafe->ctl1, cafe->nr_data); |
166 | goto do_command; | |
167 | } | |
168 | /* Reset ECC engine */ | |
195a253b | 169 | cafe_writel(cafe, 0, NAND_CTRL2); |
5467fb02 DW |
170 | |
171 | /* Emulate NAND_CMD_READOOB on large-page chips */ | |
172 | if (mtd->writesize > 512 && | |
173 | command == NAND_CMD_READOOB) { | |
174 | column += mtd->writesize; | |
175 | command = NAND_CMD_READ0; | |
176 | } | |
177 | ||
178 | /* FIXME: Do we need to send read command before sending data | |
179 | for small-page chips, to position the buffer correctly? */ | |
180 | ||
181 | if (column != -1) { | |
195a253b | 182 | cafe_writel(cafe, column, NAND_ADDR1); |
5467fb02 DW |
183 | adrbytes = 2; |
184 | if (page_addr != -1) | |
185 | goto write_adr2; | |
186 | } else if (page_addr != -1) { | |
195a253b | 187 | cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1); |
5467fb02 DW |
188 | page_addr >>= 16; |
189 | write_adr2: | |
195a253b | 190 | cafe_writel(cafe, page_addr, NAND_ADDR2); |
5467fb02 DW |
191 | adrbytes += 2; |
192 | if (mtd->size > mtd->writesize << 16) | |
193 | adrbytes++; | |
194 | } | |
195 | ||
196 | cafe->data_pos = cafe->datalen = 0; | |
197 | ||
198 | /* Set command valid bit */ | |
199 | ctl1 = 0x80000000 | command; | |
200 | ||
201 | /* Set RD or WR bits as appropriate */ | |
202 | if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) { | |
203 | ctl1 |= (1<<26); /* rd */ | |
204 | /* Always 5 bytes, for now */ | |
8dd851de | 205 | cafe->datalen = 4; |
5467fb02 DW |
206 | /* And one address cycle -- even for STATUS, since the controller doesn't work without */ |
207 | adrbytes = 1; | |
208 | } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 || | |
209 | command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) { | |
210 | ctl1 |= 1<<26; /* rd */ | |
211 | /* For now, assume just read to end of page */ | |
212 | cafe->datalen = mtd->writesize + mtd->oobsize - column; | |
213 | } else if (command == NAND_CMD_SEQIN) | |
214 | ctl1 |= 1<<25; /* wr */ | |
215 | ||
216 | /* Set number of address bytes */ | |
217 | if (adrbytes) | |
218 | ctl1 |= ((adrbytes-1)|8) << 27; | |
219 | ||
220 | if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) { | |
c9ac5977 | 221 | /* Ignore the first command of a pair; the hardware |
5467fb02 DW |
222 | deals with them both at once, later */ |
223 | cafe->ctl1 = ctl1; | |
8dd851de | 224 | cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n", |
5467fb02 DW |
225 | cafe->ctl1, cafe->datalen); |
226 | return; | |
227 | } | |
228 | /* RNDOUT and READ0 commands need a following byte */ | |
229 | if (command == NAND_CMD_RNDOUT) | |
195a253b | 230 | cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2); |
5467fb02 | 231 | else if (command == NAND_CMD_READ0 && mtd->writesize > 512) |
195a253b | 232 | cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2); |
5467fb02 DW |
233 | |
234 | do_command: | |
c9ac5977 | 235 | cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n", |
195a253b | 236 | cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2)); |
fbad5696 | 237 | |
5467fb02 | 238 | /* NB: The datasheet lies -- we really should be subtracting 1 here */ |
195a253b DW |
239 | cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN); |
240 | cafe_writel(cafe, 0x90000000, NAND_IRQ); | |
5467fb02 DW |
241 | if (usedma && (ctl1 & (3<<25))) { |
242 | uint32_t dmactl = 0xc0000000 + cafe->datalen; | |
243 | /* If WR or RD bits set, set up DMA */ | |
244 | if (ctl1 & (1<<26)) { | |
245 | /* It's a read */ | |
246 | dmactl |= (1<<29); | |
247 | /* ... so it's done when the DMA is done, not just | |
248 | the command. */ | |
249 | doneint = 0x10000000; | |
250 | } | |
195a253b | 251 | cafe_writel(cafe, dmactl, NAND_DMA_CTRL); |
5467fb02 | 252 | } |
5467fb02 DW |
253 | cafe->datalen = 0; |
254 | ||
be8444bd DW |
255 | if (unlikely(regdebug)) { |
256 | int i; | |
257 | printk("About to write command %08x to register 0\n", ctl1); | |
258 | for (i=4; i< 0x5c; i+=4) | |
259 | printk("Register %x: %08x\n", i, readl(cafe->mmio + i)); | |
fbad5696 | 260 | } |
be8444bd | 261 | |
195a253b | 262 | cafe_writel(cafe, ctl1, NAND_CTRL1); |
5467fb02 DW |
263 | /* Apply this short delay always to ensure that we do wait tWB in |
264 | * any case on any machine. */ | |
265 | ndelay(100); | |
266 | ||
267 | if (1) { | |
2a7295b2 | 268 | int c; |
5467fb02 DW |
269 | uint32_t irqs; |
270 | ||
2a7295b2 | 271 | for (c = 500000; c != 0; c--) { |
195a253b | 272 | irqs = cafe_readl(cafe, NAND_IRQ); |
5467fb02 DW |
273 | if (irqs & doneint) |
274 | break; | |
275 | udelay(1); | |
8dd851de DW |
276 | if (!(c % 100000)) |
277 | cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs); | |
5467fb02 DW |
278 | cpu_relax(); |
279 | } | |
195a253b | 280 | cafe_writel(cafe, doneint, NAND_IRQ); |
a020727b | 281 | cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n", |
195a253b | 282 | command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ)); |
5467fb02 DW |
283 | } |
284 | ||
cad40654 | 285 | WARN_ON(cafe->ctl2 & (1<<30)); |
5467fb02 DW |
286 | |
287 | switch (command) { | |
288 | ||
289 | case NAND_CMD_CACHEDPROG: | |
290 | case NAND_CMD_PAGEPROG: | |
291 | case NAND_CMD_ERASE1: | |
292 | case NAND_CMD_ERASE2: | |
293 | case NAND_CMD_SEQIN: | |
294 | case NAND_CMD_RNDIN: | |
295 | case NAND_CMD_STATUS: | |
296 | case NAND_CMD_DEPLETE1: | |
297 | case NAND_CMD_RNDOUT: | |
298 | case NAND_CMD_STATUS_ERROR: | |
299 | case NAND_CMD_STATUS_ERROR0: | |
300 | case NAND_CMD_STATUS_ERROR1: | |
301 | case NAND_CMD_STATUS_ERROR2: | |
302 | case NAND_CMD_STATUS_ERROR3: | |
195a253b | 303 | cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); |
5467fb02 DW |
304 | return; |
305 | } | |
306 | nand_wait_ready(mtd); | |
195a253b | 307 | cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); |
5467fb02 DW |
308 | } |
309 | ||
310 | static void cafe_select_chip(struct mtd_info *mtd, int chipnr) | |
311 | { | |
312 | //struct cafe_priv *cafe = mtd->priv; | |
8dd851de | 313 | // cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr); |
5467fb02 | 314 | } |
fbad5696 | 315 | |
28bdd4a7 | 316 | static int cafe_nand_interrupt(int irq, void *id) |
5467fb02 DW |
317 | { |
318 | struct mtd_info *mtd = id; | |
319 | struct cafe_priv *cafe = mtd->priv; | |
195a253b DW |
320 | uint32_t irqs = cafe_readl(cafe, NAND_IRQ); |
321 | cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ); | |
5467fb02 DW |
322 | if (!irqs) |
323 | return IRQ_NONE; | |
324 | ||
195a253b | 325 | cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ)); |
5467fb02 DW |
326 | return IRQ_HANDLED; |
327 | } | |
328 | ||
329 | static void cafe_nand_bug(struct mtd_info *mtd) | |
330 | { | |
331 | BUG(); | |
332 | } | |
333 | ||
334 | static int cafe_nand_write_oob(struct mtd_info *mtd, | |
335 | struct nand_chip *chip, int page) | |
336 | { | |
337 | int status = 0; | |
338 | ||
5467fb02 DW |
339 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); |
340 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
341 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
342 | status = chip->waitfunc(mtd, chip); | |
343 | ||
344 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
345 | } | |
346 | ||
347 | /* Don't use -- use nand_read_oob_std for now */ | |
348 | static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, | |
349 | int page, int sndcmd) | |
350 | { | |
351 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
352 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
353 | return 1; | |
354 | } | |
355 | /** | |
356 | * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read | |
357 | * @mtd: mtd info structure | |
358 | * @chip: nand chip info structure | |
359 | * @buf: buffer to store read data | |
360 | * | |
361 | * The hw generator calculates the error syndrome automatically. Therefor | |
362 | * we need a special oob layout and handling. | |
363 | */ | |
364 | static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |
365 | uint8_t *buf) | |
366 | { | |
367 | struct cafe_priv *cafe = mtd->priv; | |
368 | ||
fbad5696 | 369 | cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n", |
195a253b DW |
370 | cafe_readl(cafe, NAND_ECC_RESULT), |
371 | cafe_readl(cafe, NAND_ECC_SYN01)); | |
5467fb02 DW |
372 | |
373 | chip->read_buf(mtd, buf, mtd->writesize); | |
374 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
375 | ||
195a253b | 376 | if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) { |
04459d7c DW |
377 | unsigned short syn[8]; |
378 | int i; | |
379 | ||
380 | for (i=0; i<8; i+=2) { | |
195a253b | 381 | uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2)); |
04459d7c DW |
382 | syn[i] = tmp & 0xfff; |
383 | syn[i+1] = (tmp >> 16) & 0xfff; | |
c9ac5977 | 384 | } |
04459d7c | 385 | |
63a14237 | 386 | if ((i = cafe_correct_ecc(buf, syn)) < 0) { |
be8444bd DW |
387 | dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n", |
388 | cafe_readl(cafe, NAND_ADDR2) * 2048); | |
389 | for (i=0; i< 0x5c; i+=4) | |
390 | printk("Register %x: %08x\n", i, readl(cafe->mmio + i)); | |
04459d7c DW |
391 | mtd->ecc_stats.failed++; |
392 | } else { | |
393 | dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", i); | |
394 | mtd->ecc_stats.corrected += i; | |
395 | } | |
396 | } | |
397 | ||
398 | ||
5467fb02 DW |
399 | return 0; |
400 | } | |
401 | ||
8dd851de DW |
402 | static struct nand_ecclayout cafe_oobinfo_2048 = { |
403 | .eccbytes = 14, | |
404 | .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, | |
405 | .oobfree = {{14, 50}} | |
406 | }; | |
407 | ||
c9ac5977 | 408 | /* Ick. The BBT code really ought to be able to work this bit out |
fbad5696 DW |
409 | for itself from the above, at least for the 2KiB case */ |
410 | static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' }; | |
411 | static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' }; | |
412 | ||
413 | static uint8_t cafe_bbt_pattern_512[] = { 0xBB }; | |
414 | static uint8_t cafe_mirror_pattern_512[] = { 0xBC }; | |
415 | ||
8dd851de DW |
416 | |
417 | static struct nand_bbt_descr cafe_bbt_main_descr_2048 = { | |
418 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
419 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
420 | .offs = 14, | |
421 | .len = 4, | |
422 | .veroffs = 18, | |
423 | .maxblocks = 4, | |
fbad5696 | 424 | .pattern = cafe_bbt_pattern_2048 |
8dd851de DW |
425 | }; |
426 | ||
427 | static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = { | |
428 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
429 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
430 | .offs = 14, | |
431 | .len = 4, | |
432 | .veroffs = 18, | |
433 | .maxblocks = 4, | |
fbad5696 | 434 | .pattern = cafe_mirror_pattern_2048 |
8dd851de DW |
435 | }; |
436 | ||
437 | static struct nand_ecclayout cafe_oobinfo_512 = { | |
438 | .eccbytes = 14, | |
439 | .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, | |
440 | .oobfree = {{14, 2}} | |
441 | }; | |
442 | ||
fbad5696 DW |
443 | static struct nand_bbt_descr cafe_bbt_main_descr_512 = { |
444 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
445 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
446 | .offs = 14, | |
447 | .len = 1, | |
448 | .veroffs = 15, | |
449 | .maxblocks = 4, | |
450 | .pattern = cafe_bbt_pattern_512 | |
451 | }; | |
452 | ||
453 | static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = { | |
454 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
455 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
456 | .offs = 14, | |
457 | .len = 1, | |
458 | .veroffs = 15, | |
459 | .maxblocks = 4, | |
460 | .pattern = cafe_mirror_pattern_512 | |
461 | }; | |
462 | ||
463 | ||
5467fb02 DW |
464 | static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd, |
465 | struct nand_chip *chip, const uint8_t *buf) | |
466 | { | |
467 | struct cafe_priv *cafe = mtd->priv; | |
468 | ||
5467fb02 | 469 | chip->write_buf(mtd, buf, mtd->writesize); |
8dd851de | 470 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); |
5467fb02 DW |
471 | |
472 | /* Set up ECC autogeneration */ | |
cad40654 | 473 | cafe->ctl2 |= (1<<30); |
5467fb02 DW |
474 | } |
475 | ||
476 | static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
477 | const uint8_t *buf, int page, int cached, int raw) | |
478 | { | |
479 | int status; | |
480 | ||
5467fb02 DW |
481 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); |
482 | ||
483 | if (unlikely(raw)) | |
484 | chip->ecc.write_page_raw(mtd, chip, buf); | |
485 | else | |
486 | chip->ecc.write_page(mtd, chip, buf); | |
487 | ||
488 | /* | |
489 | * Cached progamming disabled for now, Not sure if its worth the | |
490 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s) | |
491 | */ | |
492 | cached = 0; | |
493 | ||
494 | if (!cached || !(chip->options & NAND_CACHEPRG)) { | |
495 | ||
496 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
497 | status = chip->waitfunc(mtd, chip); | |
498 | /* | |
499 | * See if operation failed and additional status checks are | |
500 | * available | |
501 | */ | |
502 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
503 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
504 | page); | |
505 | ||
506 | if (status & NAND_STATUS_FAIL) | |
507 | return -EIO; | |
508 | } else { | |
509 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
510 | status = chip->waitfunc(mtd, chip); | |
511 | } | |
512 | ||
513 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE | |
514 | /* Send command to read back the data */ | |
515 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
516 | ||
517 | if (chip->verify_buf(mtd, buf, mtd->writesize)) | |
518 | return -EIO; | |
519 | #endif | |
520 | return 0; | |
521 | } | |
522 | ||
8dd851de DW |
523 | static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) |
524 | { | |
525 | return 0; | |
526 | } | |
5467fb02 DW |
527 | |
528 | static int __devinit cafe_nand_probe(struct pci_dev *pdev, | |
529 | const struct pci_device_id *ent) | |
530 | { | |
531 | struct mtd_info *mtd; | |
532 | struct cafe_priv *cafe; | |
527a4f45 | 533 | uint32_t timing1, timing2, timing3; |
5467fb02 DW |
534 | uint32_t ctrl; |
535 | int err = 0; | |
536 | ||
537 | err = pci_enable_device(pdev); | |
538 | if (err) | |
539 | return err; | |
540 | ||
541 | pci_set_master(pdev); | |
542 | ||
543 | mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL); | |
544 | if (!mtd) { | |
545 | dev_warn(&pdev->dev, "failed to alloc mtd_info\n"); | |
546 | return -ENOMEM; | |
547 | } | |
548 | cafe = (void *)(&mtd[1]); | |
549 | ||
550 | mtd->priv = cafe; | |
551 | mtd->owner = THIS_MODULE; | |
552 | ||
553 | cafe->pdev = pdev; | |
554 | cafe->mmio = pci_iomap(pdev, 0, 0); | |
555 | if (!cafe->mmio) { | |
556 | dev_warn(&pdev->dev, "failed to iomap\n"); | |
557 | err = -ENOMEM; | |
558 | goto out_free_mtd; | |
559 | } | |
560 | cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers), | |
561 | &cafe->dmaaddr, GFP_KERNEL); | |
562 | if (!cafe->dmabuf) { | |
563 | err = -ENOMEM; | |
564 | goto out_ior; | |
565 | } | |
566 | cafe->nand.buffers = (void *)cafe->dmabuf + 2112; | |
567 | ||
568 | cafe->nand.cmdfunc = cafe_nand_cmdfunc; | |
569 | cafe->nand.dev_ready = cafe_device_ready; | |
570 | cafe->nand.read_byte = cafe_read_byte; | |
571 | cafe->nand.read_buf = cafe_read_buf; | |
572 | cafe->nand.write_buf = cafe_write_buf; | |
573 | cafe->nand.select_chip = cafe_select_chip; | |
574 | ||
575 | cafe->nand.chip_delay = 0; | |
576 | ||
577 | /* Enable the following for a flash based bad block table */ | |
578 | cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS; | |
8dd851de DW |
579 | |
580 | if (skipbbt) { | |
581 | cafe->nand.options |= NAND_SKIP_BBTSCAN; | |
582 | cafe->nand.block_bad = cafe_nand_block_bad; | |
583 | } | |
c9ac5977 | 584 | |
527a4f45 DW |
585 | if (numtimings && numtimings != 3) { |
586 | dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings); | |
587 | } | |
588 | ||
589 | if (numtimings == 3) { | |
590 | timing1 = timing[0]; | |
591 | timing2 = timing[1]; | |
592 | timing3 = timing[2]; | |
593 | cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n", | |
594 | timing1, timing2, timing3); | |
595 | } else { | |
596 | timing1 = cafe_readl(cafe, NAND_TIMING1); | |
597 | timing2 = cafe_readl(cafe, NAND_TIMING2); | |
598 | timing3 = cafe_readl(cafe, NAND_TIMING3); | |
599 | ||
600 | if (timing1 | timing2 | timing3) { | |
601 | cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n", timing1, timing2, timing3); | |
602 | } else { | |
603 | dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n"); | |
604 | timing1 = timing2 = timing3 = 0xffffffff; | |
605 | } | |
606 | } | |
607 | ||
dcc41bc8 | 608 | /* Start off by resetting the NAND controller completely */ |
195a253b DW |
609 | cafe_writel(cafe, 1, NAND_RESET); |
610 | cafe_writel(cafe, 0, NAND_RESET); | |
dcc41bc8 | 611 | |
527a4f45 DW |
612 | cafe_writel(cafe, timing1, NAND_TIMING1); |
613 | cafe_writel(cafe, timing2, NAND_TIMING2); | |
614 | cafe_writel(cafe, timing3, NAND_TIMING3); | |
b478c775 | 615 | |
195a253b | 616 | cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK); |
2db6346f TG |
617 | err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED, |
618 | "CAFE NAND", mtd); | |
5467fb02 DW |
619 | if (err) { |
620 | dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq); | |
5467fb02 DW |
621 | goto out_free_dma; |
622 | } | |
f7c37d7b | 623 | |
5467fb02 | 624 | /* Disable master reset, enable NAND clock */ |
195a253b | 625 | ctrl = cafe_readl(cafe, GLOBAL_CTRL); |
5467fb02 DW |
626 | ctrl &= 0xffffeff0; |
627 | ctrl |= 0x00007000; | |
195a253b DW |
628 | cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL); |
629 | cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL); | |
630 | cafe_writel(cafe, 0, NAND_DMA_CTRL); | |
5467fb02 | 631 | |
195a253b DW |
632 | cafe_writel(cafe, 0x7006, GLOBAL_CTRL); |
633 | cafe_writel(cafe, 0x700a, GLOBAL_CTRL); | |
5467fb02 DW |
634 | |
635 | /* Set up DMA address */ | |
195a253b | 636 | cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0); |
5467fb02 | 637 | if (sizeof(cafe->dmaaddr) > 4) |
fbad5696 | 638 | /* Shift in two parts to shut the compiler up */ |
195a253b | 639 | cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1); |
5467fb02 | 640 | else |
195a253b | 641 | cafe_writel(cafe, 0, NAND_DMA_ADDR1); |
fbad5696 | 642 | |
8dd851de | 643 | cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n", |
195a253b | 644 | cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf); |
5467fb02 DW |
645 | |
646 | /* Enable NAND IRQ in global IRQ mask register */ | |
195a253b | 647 | cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK); |
8dd851de | 648 | cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n", |
195a253b | 649 | cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK)); |
f7c37d7b DW |
650 | |
651 | /* Scan to find existence of the device */ | |
5467fb02 DW |
652 | if (nand_scan_ident(mtd, 1)) { |
653 | err = -ENXIO; | |
654 | goto out_irq; | |
655 | } | |
656 | ||
657 | cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */ | |
658 | if (mtd->writesize == 2048) | |
659 | cafe->ctl2 |= 1<<29; /* 2KiB page size */ | |
660 | ||
661 | /* Set up ECC according to the type of chip we found */ | |
fbad5696 | 662 | if (mtd->writesize == 2048) { |
8dd851de DW |
663 | cafe->nand.ecc.layout = &cafe_oobinfo_2048; |
664 | cafe->nand.bbt_td = &cafe_bbt_main_descr_2048; | |
665 | cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048; | |
fbad5696 DW |
666 | } else if (mtd->writesize == 512) { |
667 | cafe->nand.ecc.layout = &cafe_oobinfo_512; | |
668 | cafe->nand.bbt_td = &cafe_bbt_main_descr_512; | |
669 | cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512; | |
5467fb02 | 670 | } else { |
fbad5696 | 671 | printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n", |
5467fb02 | 672 | mtd->writesize); |
fbad5696 | 673 | goto out_irq; |
5467fb02 | 674 | } |
fbad5696 DW |
675 | cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME; |
676 | cafe->nand.ecc.size = mtd->writesize; | |
677 | cafe->nand.ecc.bytes = 14; | |
678 | cafe->nand.ecc.hwctl = (void *)cafe_nand_bug; | |
679 | cafe->nand.ecc.calculate = (void *)cafe_nand_bug; | |
680 | cafe->nand.ecc.correct = (void *)cafe_nand_bug; | |
681 | cafe->nand.write_page = cafe_nand_write_page; | |
682 | cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel; | |
683 | cafe->nand.ecc.write_oob = cafe_nand_write_oob; | |
684 | cafe->nand.ecc.read_page = cafe_nand_read_page; | |
685 | cafe->nand.ecc.read_oob = cafe_nand_read_oob; | |
5467fb02 DW |
686 | |
687 | err = nand_scan_tail(mtd); | |
688 | if (err) | |
689 | goto out_irq; | |
690 | ||
5467fb02 DW |
691 | pci_set_drvdata(pdev, mtd); |
692 | add_mtd_device(mtd); | |
693 | goto out; | |
694 | ||
695 | out_irq: | |
696 | /* Disable NAND IRQ in global IRQ mask register */ | |
195a253b | 697 | cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK); |
5467fb02 DW |
698 | free_irq(pdev->irq, mtd); |
699 | out_free_dma: | |
700 | dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr); | |
701 | out_ior: | |
702 | pci_iounmap(pdev, cafe->mmio); | |
703 | out_free_mtd: | |
704 | kfree(mtd); | |
705 | out: | |
706 | return err; | |
707 | } | |
708 | ||
709 | static void __devexit cafe_nand_remove(struct pci_dev *pdev) | |
710 | { | |
711 | struct mtd_info *mtd = pci_get_drvdata(pdev); | |
712 | struct cafe_priv *cafe = mtd->priv; | |
713 | ||
714 | del_mtd_device(mtd); | |
715 | /* Disable NAND IRQ in global IRQ mask register */ | |
195a253b | 716 | cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK); |
5467fb02 DW |
717 | free_irq(pdev->irq, mtd); |
718 | nand_release(mtd); | |
719 | pci_iounmap(pdev, cafe->mmio); | |
720 | dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr); | |
721 | kfree(mtd); | |
722 | } | |
723 | ||
724 | static struct pci_device_id cafe_nand_tbl[] = { | |
725 | { 0x11ab, 0x4100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MEMORY_FLASH << 8, 0xFFFF0 } | |
726 | }; | |
727 | ||
728 | MODULE_DEVICE_TABLE(pci, cafe_nand_tbl); | |
729 | ||
730 | static struct pci_driver cafe_nand_pci_driver = { | |
731 | .name = "CAFÉ NAND", | |
732 | .id_table = cafe_nand_tbl, | |
733 | .probe = cafe_nand_probe, | |
734 | .remove = __devexit_p(cafe_nand_remove), | |
735 | #ifdef CONFIG_PMx | |
736 | .suspend = cafe_nand_suspend, | |
737 | .resume = cafe_nand_resume, | |
738 | #endif | |
739 | }; | |
740 | ||
741 | static int cafe_nand_init(void) | |
742 | { | |
743 | return pci_register_driver(&cafe_nand_pci_driver); | |
744 | } | |
745 | ||
746 | static void cafe_nand_exit(void) | |
747 | { | |
748 | pci_unregister_driver(&cafe_nand_pci_driver); | |
749 | } | |
750 | module_init(cafe_nand_init); | |
751 | module_exit(cafe_nand_exit); | |
752 | ||
753 | MODULE_LICENSE("GPL"); | |
754 | MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>"); | |
f7c37d7b | 755 | MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip"); |