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Merge tag 'for-linus-4.13b-rc5-tag' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-artful-kernel.git] / drivers / mtd / nand / cafe_nand.c
CommitLineData
c9ac5977 1/*
fbad5696 2 * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
5467fb02 3 *
514fca43 4 * The data sheet for this device can be found at:
631dd1a8 5 * http://wiki.laptop.org/go/Datasheets
514fca43 6 *
5467fb02
DW		 7 * Copyright © 2006 Red Hat, Inc.
8 * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
9 */
10
8dd851de 11#define DEBUG
5467fb02
DW		 12
13#include <linux/device.h>
14#undef DEBUG
15#include <linux/mtd/mtd.h>
16#include <linux/mtd/nand.h>
9c37f332 17#include <linux/mtd/partitions.h>
8c61b7a7 18#include <linux/rslib.h>
5467fb02
DW		 19#include <linux/pci.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
a1274302 22#include <linux/dma-mapping.h>
5a0e3ad6 23#include <linux/slab.h>
a0e5cc58 24#include <linux/module.h>
5467fb02
DW		 25#include <asm/io.h>
26
27#define CAFE_NAND_CTRL1 0x00
28#define CAFE_NAND_CTRL2 0x04
29#define CAFE_NAND_CTRL3 0x08
30#define CAFE_NAND_STATUS 0x0c
31#define CAFE_NAND_IRQ 0x10
32#define CAFE_NAND_IRQ_MASK 0x14
33#define CAFE_NAND_DATA_LEN 0x18
34#define CAFE_NAND_ADDR1 0x1c
35#define CAFE_NAND_ADDR2 0x20
36#define CAFE_NAND_TIMING1 0x24
37#define CAFE_NAND_TIMING2 0x28
38#define CAFE_NAND_TIMING3 0x2c
39#define CAFE_NAND_NONMEM 0x30
04459d7c 40#define CAFE_NAND_ECC_RESULT 0x3C
fbad5696
DW		 41#define CAFE_NAND_DMA_CTRL 0x40
42#define CAFE_NAND_DMA_ADDR0 0x44
43#define CAFE_NAND_DMA_ADDR1 0x48
04459d7c
DW		 44#define CAFE_NAND_ECC_SYN01 0x50
45#define CAFE_NAND_ECC_SYN23 0x54
46#define CAFE_NAND_ECC_SYN45 0x58
47#define CAFE_NAND_ECC_SYN67 0x5c
5467fb02
DW		 48#define CAFE_NAND_READ_DATA 0x1000
49#define CAFE_NAND_WRITE_DATA 0x2000
50
195a253b
DW		 51#define CAFE_GLOBAL_CTRL 0x3004
52#define CAFE_GLOBAL_IRQ 0x3008
53#define CAFE_GLOBAL_IRQ_MASK 0x300c
54#define CAFE_NAND_RESET 0x3034
55
048c37b4
DW		 56/* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */
57#define CTRL1_CHIPSELECT (1<<19)
58
5467fb02
DW		 59struct cafe_priv {
60 struct nand_chip nand;
61 struct pci_dev *pdev;
62 void __iomem *mmio;
8c61b7a7 63 struct rs_control *rs;
5467fb02
DW		 64 uint32_t ctl1;
65 uint32_t ctl2;
66 int datalen;
67 int nr_data;
68 int data_pos;
69 int page_addr;
70 dma_addr_t dmaaddr;
71 unsigned char *dmabuf;
5467fb02
DW		 72};
73
b478c775 74static int usedma = 1;
5467fb02
DW		 75module_param(usedma, int, 0644);
76
8dd851de
DW		 77static int skipbbt = 0;
78module_param(skipbbt, int, 0644);
79
80static int debug = 0;
81module_param(debug, int, 0644);
82
be8444bd
DW		 83static int regdebug = 0;
84module_param(regdebug, int, 0644);
85
b478c775 86static int checkecc = 1;
470b0a90
DW		 87module_param(checkecc, int, 0644);
88
64a6f950 89static unsigned int numtimings;
527a4f45
DW		 90static int timing[3];
91module_param_array(timing, int, &numtimings, 0644);
b478c775 92
68874414 93static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
9c37f332 94
04459d7c 95/* Hrm. Why isn't this already conditional on something in the struct device? */
8dd851de
DW		 96#define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
97
195a253b
DW		 98/* Make it easier to switch to PIO if we need to */
99#define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
100#define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
8dd851de 101
5467fb02
DW		 102static int cafe_device_ready(struct mtd_info *mtd)
103{
4bd4ebcc 104 struct nand_chip *chip = mtd_to_nand(mtd);
d699ed25 105 struct cafe_priv *cafe = nand_get_controller_data(chip);
48f8b641 106 int result = !!(cafe_readl(cafe, NAND_STATUS) & 0x40000000);
195a253b 107 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
fbad5696 108
195a253b 109 cafe_writel(cafe, irqs, NAND_IRQ);
fbad5696 110
8dd851de 111 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
195a253b
DW		 112 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
113 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
fbad5696 114
5467fb02
DW		 115 return result;
116}
117
118
119static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
120{
4bd4ebcc 121 struct nand_chip *chip = mtd_to_nand(mtd);
d699ed25 122 struct cafe_priv *cafe = nand_get_controller_data(chip);
5467fb02
DW		 123
124 if (usedma)
125 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
126 else
127 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
fbad5696 128
5467fb02
DW		 129 cafe->datalen += len;
130
8dd851de 131 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
5467fb02
DW		 132 len, cafe->datalen);
133}
134
135static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
136{
4bd4ebcc 137 struct nand_chip *chip = mtd_to_nand(mtd);
d699ed25 138 struct cafe_priv *cafe = nand_get_controller_data(chip);
5467fb02
DW		 139
140 if (usedma)
141 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
142 else
143 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
144
8dd851de 145 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
5467fb02
DW		 146 len, cafe->datalen);
147 cafe->datalen += len;
148}
149
150static uint8_t cafe_read_byte(struct mtd_info *mtd)
151{
4bd4ebcc 152 struct nand_chip *chip = mtd_to_nand(mtd);
d699ed25 153 struct cafe_priv *cafe = nand_get_controller_data(chip);
5467fb02
DW		 154 uint8_t d;
155
156 cafe_read_buf(mtd, &d, 1);
8dd851de 157 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
5467fb02
DW		 158
159 return d;
160}
161
162static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
163 int column, int page_addr)
164{
4bd4ebcc 165 struct nand_chip *chip = mtd_to_nand(mtd);
d699ed25 166 struct cafe_priv *cafe = nand_get_controller_data(chip);
5467fb02
DW		 167 int adrbytes = 0;
168 uint32_t ctl1;
169 uint32_t doneint = 0x80000000;
5467fb02 170
8dd851de 171 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
5467fb02
DW		 172 command, column, page_addr);
173
174 if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
175 /* Second half of a command we already calculated */
195a253b 176 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
5467fb02 177 ctl1 = cafe->ctl1;
cad40654 178 cafe->ctl2 &= ~(1<<30);
8dd851de 179 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
5467fb02
DW		 180 cafe->ctl1, cafe->nr_data);
181 goto do_command;
182 }
183 /* Reset ECC engine */
195a253b 184 cafe_writel(cafe, 0, NAND_CTRL2);
5467fb02
DW		 185
186 /* Emulate NAND_CMD_READOOB on large-page chips */
187 if (mtd->writesize > 512 &&
188 command == NAND_CMD_READOOB) {
189 column += mtd->writesize;
190 command = NAND_CMD_READ0;
191 }
192
193 /* FIXME: Do we need to send read command before sending data
194 for small-page chips, to position the buffer correctly? */
195
196 if (column != -1) {
195a253b 197 cafe_writel(cafe, column, NAND_ADDR1);
5467fb02
DW		 198 adrbytes = 2;
199 if (page_addr != -1)
200 goto write_adr2;
201 } else if (page_addr != -1) {
195a253b 202 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
5467fb02
DW		 203 page_addr >>= 16;
204 write_adr2:
195a253b 205 cafe_writel(cafe, page_addr, NAND_ADDR2);
5467fb02
DW		 206 adrbytes += 2;
207 if (mtd->size > mtd->writesize << 16)
208 adrbytes++;
209 }
210
211 cafe->data_pos = cafe->datalen = 0;
212
048c37b4
DW		 213 /* Set command valid bit, mask in the chip select bit */
214 ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT);
5467fb02
DW		 215
216 /* Set RD or WR bits as appropriate */
217 if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
218 ctl1 |= (1<<26); /* rd */
219 /* Always 5 bytes, for now */
8dd851de 220 cafe->datalen = 4;
5467fb02
DW		 221 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
222 adrbytes = 1;
223 } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
224 command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
225 ctl1 |= 1<<26; /* rd */
226 /* For now, assume just read to end of page */
227 cafe->datalen = mtd->writesize + mtd->oobsize - column;
228 } else if (command == NAND_CMD_SEQIN)
229 ctl1 |= 1<<25; /* wr */
230
231 /* Set number of address bytes */
232 if (adrbytes)
233 ctl1 |= ((adrbytes-1)|8) << 27;
234
235 if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
c9ac5977 236 /* Ignore the first command of a pair; the hardware
5467fb02
DW		 237 deals with them both at once, later */
238 cafe->ctl1 = ctl1;
8dd851de 239 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
5467fb02
DW		 240 cafe->ctl1, cafe->datalen);
241 return;
242 }
243 /* RNDOUT and READ0 commands need a following byte */
244 if (command == NAND_CMD_RNDOUT)
195a253b 245 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
5467fb02 246 else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
195a253b 247 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
5467fb02
DW		 248
249 do_command:
c9ac5977 250 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
195a253b 251 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
fbad5696 252
5467fb02 253 /* NB: The datasheet lies -- we really should be subtracting 1 here */
195a253b
DW		 254 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
255 cafe_writel(cafe, 0x90000000, NAND_IRQ);
5467fb02
DW		 256 if (usedma && (ctl1 & (3<<25))) {
257 uint32_t dmactl = 0xc0000000 + cafe->datalen;
258 /* If WR or RD bits set, set up DMA */
259 if (ctl1 & (1<<26)) {
260 /* It's a read */
261 dmactl |= (1<<29);
262 /* ... so it's done when the DMA is done, not just
263 the command. */
264 doneint = 0x10000000;
265 }
195a253b 266 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
5467fb02 267 }
5467fb02
DW		 268 cafe->datalen = 0;
269
be8444bd
DW		 270 if (unlikely(regdebug)) {
271 int i;
272 printk("About to write command %08x to register 0\n", ctl1);
273 for (i=4; i< 0x5c; i+=4)
274 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
fbad5696 275 }
be8444bd 276
195a253b 277 cafe_writel(cafe, ctl1, NAND_CTRL1);
5467fb02
DW		 278 /* Apply this short delay always to ensure that we do wait tWB in
279 * any case on any machine. */
280 ndelay(100);
281
282 if (1) {
2a7295b2 283 int c;
5467fb02
DW		 284 uint32_t irqs;
285
2a7295b2 286 for (c = 500000; c != 0; c--) {
195a253b 287 irqs = cafe_readl(cafe, NAND_IRQ);
5467fb02
DW		 288 if (irqs & doneint)
289 break;
290 udelay(1);
8dd851de
DW		 291 if (!(c % 100000))
292 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
5467fb02
DW		 293 cpu_relax();
294 }
195a253b 295 cafe_writel(cafe, doneint, NAND_IRQ);
a020727b 296 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
195a253b 297 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
5467fb02
DW		 298 }
299
cad40654 300 WARN_ON(cafe->ctl2 & (1<<30));
5467fb02
DW		 301
302 switch (command) {
303
304 case NAND_CMD_CACHEDPROG:
305 case NAND_CMD_PAGEPROG:
306 case NAND_CMD_ERASE1:
307 case NAND_CMD_ERASE2:
308 case NAND_CMD_SEQIN:
309 case NAND_CMD_RNDIN:
310 case NAND_CMD_STATUS:
5467fb02 311 case NAND_CMD_RNDOUT:
195a253b 312 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
5467fb02
DW		 313 return;
314 }
315 nand_wait_ready(mtd);
195a253b 316 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
5467fb02
DW		 317}
318
319static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
320{
4bd4ebcc 321 struct nand_chip *chip = mtd_to_nand(mtd);
d699ed25 322 struct cafe_priv *cafe = nand_get_controller_data(chip);
048c37b4
DW		 323
324 cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
325
326 /* Mask the appropriate bit into the stored value of ctl1
327 which will be used by cafe_nand_cmdfunc() */
328 if (chipnr)
329 cafe->ctl1 |= CTRL1_CHIPSELECT;
330 else
331 cafe->ctl1 &= ~CTRL1_CHIPSELECT;
5467fb02 332}
fbad5696 333
67cd724f 334static irqreturn_t cafe_nand_interrupt(int irq, void *id)
5467fb02
DW		 335{
336 struct mtd_info *mtd = id;
4bd4ebcc 337 struct nand_chip *chip = mtd_to_nand(mtd);
d699ed25 338 struct cafe_priv *cafe = nand_get_controller_data(chip);
195a253b
DW		 339 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
340 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
5467fb02
DW		 341 if (!irqs)
342 return IRQ_NONE;
343
195a253b 344 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
5467fb02
DW		 345 return IRQ_HANDLED;
346}
347
348static void cafe_nand_bug(struct mtd_info *mtd)
349{
350 BUG();
351}
352
353static int cafe_nand_write_oob(struct mtd_info *mtd,
354 struct nand_chip *chip, int page)
355{
356 int status = 0;
357
5467fb02
DW		 358 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
359 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
360 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
361 status = chip->waitfunc(mtd, chip);
362
363 return status & NAND_STATUS_FAIL ? -EIO : 0;
364}
365
366/* Don't use -- use nand_read_oob_std for now */
367static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 368 int page)
5467fb02
DW		 369{
370 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
371 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
5c2ffb11 372 return 0;
5467fb02
DW		 373}
374/**
7854d3f7 375 * cafe_nand_read_page_syndrome - [REPLACEABLE] hardware ecc syndrome based page read
5467fb02
DW		 376 * @mtd: mtd info structure
377 * @chip: nand chip info structure
378 * @buf: buffer to store read data
1fbb938d 379 * @oob_required: caller expects OOB data read to chip->oob_poi
5467fb02 380 *
b9bc815c 381 * The hw generator calculates the error syndrome automatically. Therefore
5467fb02
DW		 382 * we need a special oob layout and handling.
383 */
384static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 385 uint8_t *buf, int oob_required, int page)
5467fb02 386{
d699ed25 387 struct cafe_priv *cafe = nand_get_controller_data(chip);
3f91e94f 388 unsigned int max_bitflips = 0;
5467fb02 389
fbad5696 390 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
195a253b
DW		 391 cafe_readl(cafe, NAND_ECC_RESULT),
392 cafe_readl(cafe, NAND_ECC_SYN01));
5467fb02
DW		 393
394 chip->read_buf(mtd, buf, mtd->writesize);
395 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
396
195a253b 397 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
8c61b7a7
SB		 398 unsigned short syn[8], pat[4];
399 int pos[4];
400 u8 *oob = chip->oob_poi;
401 int i, n;
04459d7c
DW		 402
403 for (i=0; i<8; i+=2) {
195a253b 404 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
8c61b7a7
SB		 405 syn[i] = cafe->rs->index_of[tmp & 0xfff];
406 syn[i+1] = cafe->rs->index_of[(tmp >> 16) & 0xfff];
407 }
408
409 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
410 pat);
411
412 for (i = 0; i < n; i++) {
413 int p = pos[i];
414
415 /* The 12-bit symbols are mapped to bytes here */
416
417 if (p > 1374) {
418 /* out of range */
419 n = -1374;
420 } else if (p == 0) {
421 /* high four bits do not correspond to data */
422 if (pat[i] > 0xff)
423 n = -2048;
424 else
425 buf[0] ^= pat[i];
426 } else if (p == 1365) {
427 buf[2047] ^= pat[i] >> 4;
428 oob[0] ^= pat[i] << 4;
429 } else if (p > 1365) {
430 if ((p & 1) == 1) {
431 oob[3*p/2 - 2048] ^= pat[i] >> 4;
432 oob[3*p/2 - 2047] ^= pat[i] << 4;
433 } else {
434 oob[3*p/2 - 2049] ^= pat[i] >> 8;
435 oob[3*p/2 - 2048] ^= pat[i];
436 }
437 } else if ((p & 1) == 1) {
438 buf[3*p/2] ^= pat[i] >> 4;
439 buf[3*p/2 + 1] ^= pat[i] << 4;
440 } else {
441 buf[3*p/2 - 1] ^= pat[i] >> 8;
442 buf[3*p/2] ^= pat[i];
443 }
c9ac5977 444 }
04459d7c 445
8c61b7a7 446 if (n < 0) {
be8444bd
DW		 447 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
448 cafe_readl(cafe, NAND_ADDR2) * 2048);
8c61b7a7 449 for (i = 0; i < 0x5c; i += 4)
be8444bd 450 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
04459d7c
DW		 451 mtd->ecc_stats.failed++;
452 } else {
8c61b7a7
SB		 453 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
454 mtd->ecc_stats.corrected += n;
3f91e94f 455 max_bitflips = max_t(unsigned int, max_bitflips, n);
04459d7c
DW		 456 }
457 }
458
3f91e94f 459 return max_bitflips;
5467fb02
DW		 460}
461
a8ed6e66
BB		 462static int cafe_ooblayout_ecc(struct mtd_info *mtd, int section,
463 struct mtd_oob_region *oobregion)
464{
465 struct nand_chip *chip = mtd_to_nand(mtd);
466
467 if (section)
468 return -ERANGE;
469
470 oobregion->offset = 0;
471 oobregion->length = chip->ecc.total;
472
473 return 0;
474}
475
476static int cafe_ooblayout_free(struct mtd_info *mtd, int section,
477 struct mtd_oob_region *oobregion)
478{
479 struct nand_chip *chip = mtd_to_nand(mtd);
480
481 if (section)
482 return -ERANGE;
483
484 oobregion->offset = chip->ecc.total;
485 oobregion->length = mtd->oobsize - chip->ecc.total;
486
487 return 0;
488}
489
490static const struct mtd_ooblayout_ops cafe_ooblayout_ops = {
491 .ecc = cafe_ooblayout_ecc,
492 .free = cafe_ooblayout_free,
8dd851de
DW		 493};
494
c9ac5977 495/* Ick. The BBT code really ought to be able to work this bit out
fbad5696
DW		 496 for itself from the above, at least for the 2KiB case */
497static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
498static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
499
500static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
501static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
502
8dd851de
DW		 503
504static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
505 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
048c37b4 506 | NAND_BBT_2BIT | NAND_BBT_VERSION,
8dd851de
DW		 507 .offs = 14,
508 .len = 4,
509 .veroffs = 18,
510 .maxblocks = 4,
fbad5696 511 .pattern = cafe_bbt_pattern_2048
8dd851de
DW		 512};
513
514static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
515 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
048c37b4 516 | NAND_BBT_2BIT | NAND_BBT_VERSION,
8dd851de
DW		 517 .offs = 14,
518 .len = 4,
519 .veroffs = 18,
520 .maxblocks = 4,
fbad5696 521 .pattern = cafe_mirror_pattern_2048
8dd851de
DW		 522};
523
fbad5696
DW		 524static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
525 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
048c37b4 526 | NAND_BBT_2BIT | NAND_BBT_VERSION,
fbad5696
DW		 527 .offs = 14,
528 .len = 1,
529 .veroffs = 15,
530 .maxblocks = 4,
531 .pattern = cafe_bbt_pattern_512
532};
533
534static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
535 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
048c37b4 536 | NAND_BBT_2BIT | NAND_BBT_VERSION,
fbad5696
DW		 537 .offs = 14,
538 .len = 1,
539 .veroffs = 15,
540 .maxblocks = 4,
541 .pattern = cafe_mirror_pattern_512
542};
543
544
fdbad98d 545static int cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
1fbb938d 546 struct nand_chip *chip,
45aaeff9
BB		 547 const uint8_t *buf, int oob_required,
548 int page)
5467fb02 549{
d699ed25 550 struct cafe_priv *cafe = nand_get_controller_data(chip);
5467fb02 551
5467fb02 552 chip->write_buf(mtd, buf, mtd->writesize);
8dd851de 553 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
5467fb02
DW		 554
555 /* Set up ECC autogeneration */
cad40654 556 cafe->ctl2 |= (1<<30);
fdbad98d
JW		 557
558 return 0;
5467fb02
DW		 559}
560
9f3e0429 561static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
8dd851de
DW		 562{
563 return 0;
564}
5467fb02 565
8c61b7a7 566/* F_2[X]/(X**6+X+1) */
06f25510 567static unsigned short gf64_mul(u8 a, u8 b)
8c61b7a7
SB		 568{
569 u8 c;
570 unsigned int i;
571
572 c = 0;
573 for (i = 0; i < 6; i++) {
574 if (a & 1)
575 c ^= b;
576 a >>= 1;
577 b <<= 1;
578 if ((b & 0x40) != 0)
579 b ^= 0x43;
580 }
581
582 return c;
583}
584
585/* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X] */
06f25510 586static u16 gf4096_mul(u16 a, u16 b)
8c61b7a7
SB		 587{
588 u8 ah, al, bh, bl, ch, cl;
589
590 ah = a >> 6;
591 al = a & 0x3f;
592 bh = b >> 6;
593 bl = b & 0x3f;
594
595 ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl);
596 cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl);
597
598 return (ch << 6) ^ cl;
599}
600
06f25510 601static int cafe_mul(int x)
8c61b7a7
SB		 602{
603 if (x == 0)
604 return 1;
605 return gf4096_mul(x, 0xe01);
606}
607
06f25510 608static int cafe_nand_probe(struct pci_dev *pdev,
5467fb02
DW		 609 const struct pci_device_id *ent)
610{
611 struct mtd_info *mtd;
612 struct cafe_priv *cafe;
613 uint32_t ctrl;
614 int err = 0;
f02ea4e6
HS		 615 int old_dma;
616 struct nand_buffers *nbuf;
5467fb02 617
06ed24e5
DW		 618 /* Very old versions shared the same PCI ident for all three
619 functions on the chip. Verify the class too... */
620 if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH)
621 return -ENODEV;
622
5467fb02
DW		 623 err = pci_enable_device(pdev);
624 if (err)
625 return err;
626
627 pci_set_master(pdev);
628
e787dfd1
BB		 629 cafe = kzalloc(sizeof(*cafe), GFP_KERNEL);
630 if (!cafe)
5467fb02 631 return -ENOMEM;
5467fb02 632
e787dfd1 633 mtd = nand_to_mtd(&cafe->nand);
c451c7c4 634 mtd->dev.parent = &pdev->dev;
d699ed25 635 nand_set_controller_data(&cafe->nand, cafe);
5467fb02
DW		 636
637 cafe->pdev = pdev;
638 cafe->mmio = pci_iomap(pdev, 0, 0);
639 if (!cafe->mmio) {
640 dev_warn(&pdev->dev, "failed to iomap\n");
641 err = -ENOMEM;
642 goto out_free_mtd;
643 }
5467fb02 644
8c61b7a7
SB		 645 cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
646 if (!cafe->rs) {
647 err = -ENOMEM;
648 goto out_ior;
649 }
650
5467fb02
DW		 651 cafe->nand.cmdfunc = cafe_nand_cmdfunc;
652 cafe->nand.dev_ready = cafe_device_ready;
653 cafe->nand.read_byte = cafe_read_byte;
654 cafe->nand.read_buf = cafe_read_buf;
655 cafe->nand.write_buf = cafe_write_buf;
656 cafe->nand.select_chip = cafe_select_chip;
4a78cc64
BB		 657 cafe->nand.onfi_set_features = nand_onfi_get_set_features_notsupp;
658 cafe->nand.onfi_get_features = nand_onfi_get_set_features_notsupp;
5467fb02
DW		 659
660 cafe->nand.chip_delay = 0;
661
662 /* Enable the following for a flash based bad block table */
bb9ebd4e 663 cafe->nand.bbt_options = NAND_BBT_USE_FLASH;
1826dbcc 664 cafe->nand.options = NAND_OWN_BUFFERS;
8dd851de
DW		 665
666 if (skipbbt) {
667 cafe->nand.options |= NAND_SKIP_BBTSCAN;
668 cafe->nand.block_bad = cafe_nand_block_bad;
669 }
c9ac5977 670
527a4f45
DW		 671 if (numtimings && numtimings != 3) {
672 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
673 }
674
675 if (numtimings == 3) {
527a4f45 676 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
8e5368a1 677 timing[0], timing[1], timing[2]);
527a4f45 678 } else {
8e5368a1
DW		 679 timing[0] = cafe_readl(cafe, NAND_TIMING1);
680 timing[1] = cafe_readl(cafe, NAND_TIMING2);
681 timing[2] = cafe_readl(cafe, NAND_TIMING3);
527a4f45 682
8e5368a1
DW		 683 if (timing[0] | timing[1] | timing[2]) {
684 cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
685 timing[0], timing[1], timing[2]);
527a4f45
DW		 686 } else {
687 dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
8e5368a1 688 timing[0] = timing[1] = timing[2] = 0xffffffff;
527a4f45
DW		 689 }
690 }
691
dcc41bc8 692 /* Start off by resetting the NAND controller completely */
195a253b
DW		 693 cafe_writel(cafe, 1, NAND_RESET);
694 cafe_writel(cafe, 0, NAND_RESET);
dcc41bc8 695
8e5368a1
DW		 696 cafe_writel(cafe, timing[0], NAND_TIMING1);
697 cafe_writel(cafe, timing[1], NAND_TIMING2);
698 cafe_writel(cafe, timing[2], NAND_TIMING3);
b478c775 699
195a253b 700 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
2db6346f
TG		 701 err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED,
702 "CAFE NAND", mtd);
5467fb02
DW		 703 if (err) {
704 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
f02ea4e6 705 goto out_ior;
5467fb02 706 }
f7c37d7b 707
5467fb02 708 /* Disable master reset, enable NAND clock */
195a253b 709 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
5467fb02
DW		 710 ctrl &= 0xffffeff0;
711 ctrl |= 0x00007000;
195a253b
DW		 712 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
713 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
714 cafe_writel(cafe, 0, NAND_DMA_CTRL);
5467fb02 715
195a253b
DW		 716 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
717 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
5467fb02 718
f02ea4e6
HS		 719 /* Enable NAND IRQ in global IRQ mask register */
720 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
721 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
722 cafe_readl(cafe, GLOBAL_CTRL),
723 cafe_readl(cafe, GLOBAL_IRQ_MASK));
724
725 /* Do not use the DMA for the nand_scan_ident() */
726 old_dma = usedma;
727 usedma = 0;
728
729 /* Scan to find existence of the device */
72480e4e
MY		 730 err = nand_scan_ident(mtd, 2, NULL);
731 if (err)
f02ea4e6 732 goto out_irq;
f02ea4e6
HS		 733
734 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev,
735 2112 + sizeof(struct nand_buffers) +
736 mtd->writesize + mtd->oobsize,
737 &cafe->dmaaddr, GFP_KERNEL);
738 if (!cafe->dmabuf) {
739 err = -ENOMEM;
740 goto out_irq;
741 }
742 cafe->nand.buffers = nbuf = (void *)cafe->dmabuf + 2112;
743
5467fb02 744 /* Set up DMA address */
195a253b 745 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
5467fb02 746 if (sizeof(cafe->dmaaddr) > 4)
fbad5696 747 /* Shift in two parts to shut the compiler up */
195a253b 748 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
5467fb02 749 else
195a253b 750 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
fbad5696 751
8dd851de 752 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
195a253b 753 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
5467fb02 754
f02ea4e6
HS		 755 /* this driver does not need the @ecccalc and @ecccode */
756 nbuf->ecccalc = NULL;
757 nbuf->ecccode = NULL;
758 nbuf->databuf = (uint8_t *)(nbuf + 1);
f7c37d7b 759
f02ea4e6
HS		 760 /* Restore the DMA flag */
761 usedma = old_dma;
5467fb02
DW		 762
763 cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
764 if (mtd->writesize == 2048)
765 cafe->ctl2 |= 1<<29; /* 2KiB page size */
766
767 /* Set up ECC according to the type of chip we found */
a8ed6e66 768 mtd_set_ooblayout(mtd, &cafe_ooblayout_ops);
fbad5696 769 if (mtd->writesize == 2048) {
8dd851de
DW		 770 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
771 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
fbad5696 772 } else if (mtd->writesize == 512) {
fbad5696
DW		 773 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
774 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
5467fb02 775 } else {
fbad5696 776 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
5467fb02 777 mtd->writesize);
f02ea4e6 778 goto out_free_dma;
5467fb02 779 }
fbad5696
DW		 780 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
781 cafe->nand.ecc.size = mtd->writesize;
782 cafe->nand.ecc.bytes = 14;
6a918bad 783 cafe->nand.ecc.strength = 4;
fbad5696
DW		 784 cafe->nand.ecc.hwctl = (void *)cafe_nand_bug;
785 cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
786 cafe->nand.ecc.correct = (void *)cafe_nand_bug;
fbad5696
DW		 787 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
788 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
789 cafe->nand.ecc.read_page = cafe_nand_read_page;
790 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
5467fb02
DW		 791
792 err = nand_scan_tail(mtd);
793 if (err)
f02ea4e6 794 goto out_free_dma;
5467fb02 795
5467fb02 796 pci_set_drvdata(pdev, mtd);
9c37f332 797
68874414 798 mtd->name = "cafe_nand";
42d7fbe2 799 mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
4d32de81 800
5467fb02
DW		 801 goto out;
802
f02ea4e6
HS		 803 out_free_dma:
804 dma_free_coherent(&cafe->pdev->dev,
805 2112 + sizeof(struct nand_buffers) +
806 mtd->writesize + mtd->oobsize,
807 cafe->dmabuf, cafe->dmaaddr);
5467fb02
DW		 808 out_irq:
809 /* Disable NAND IRQ in global IRQ mask register */
195a253b 810 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
5467fb02 811 free_irq(pdev->irq, mtd);
5467fb02
DW		 812 out_ior:
813 pci_iounmap(pdev, cafe->mmio);
814 out_free_mtd:
e787dfd1 815 kfree(cafe);
5467fb02
DW		 816 out:
817 return err;
818}
819
810b7e06 820static void cafe_nand_remove(struct pci_dev *pdev)
5467fb02
DW		 821{
822 struct mtd_info *mtd = pci_get_drvdata(pdev);
4bd4ebcc 823 struct nand_chip *chip = mtd_to_nand(mtd);
d699ed25 824 struct cafe_priv *cafe = nand_get_controller_data(chip);
5467fb02 825
5467fb02 826 /* Disable NAND IRQ in global IRQ mask register */
195a253b 827 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
5467fb02
DW		 828 free_irq(pdev->irq, mtd);
829 nand_release(mtd);
8c61b7a7 830 free_rs(cafe->rs);
5467fb02 831 pci_iounmap(pdev, cafe->mmio);
f02ea4e6
HS		 832 dma_free_coherent(&cafe->pdev->dev,
833 2112 + sizeof(struct nand_buffers) +
834 mtd->writesize + mtd->oobsize,
835 cafe->dmabuf, cafe->dmaaddr);
e787dfd1 836 kfree(cafe);
5467fb02
DW		 837}
838
377ace08 839static const struct pci_device_id cafe_nand_tbl[] = {
514fca43
DW		 840 { PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND,
841 PCI_ANY_ID, PCI_ANY_ID },
06ed24e5 842 { }
5467fb02
DW		 843};
844
845MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
846
1fcf8ce5
DW		 847static int cafe_nand_resume(struct pci_dev *pdev)
848{
849 uint32_t ctrl;
850 struct mtd_info *mtd = pci_get_drvdata(pdev);
4bd4ebcc 851 struct nand_chip *chip = mtd_to_nand(mtd);
d699ed25 852 struct cafe_priv *cafe = nand_get_controller_data(chip);
1fcf8ce5
DW		 853
854 /* Start off by resetting the NAND controller completely */
855 cafe_writel(cafe, 1, NAND_RESET);
856 cafe_writel(cafe, 0, NAND_RESET);
857 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
858
859 /* Restore timing configuration */
860 cafe_writel(cafe, timing[0], NAND_TIMING1);
861 cafe_writel(cafe, timing[1], NAND_TIMING2);
862 cafe_writel(cafe, timing[2], NAND_TIMING3);
863
864 /* Disable master reset, enable NAND clock */
865 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
866 ctrl &= 0xffffeff0;
867 ctrl |= 0x00007000;
868 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
869 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
870 cafe_writel(cafe, 0, NAND_DMA_CTRL);
871 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
872 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
873
874 /* Set up DMA address */
875 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
876 if (sizeof(cafe->dmaaddr) > 4)
877 /* Shift in two parts to shut the compiler up */
878 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
879 else
880 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
881
882 /* Enable NAND IRQ in global IRQ mask register */
883 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
884 return 0;
885}
886
5467fb02
DW		 887static struct pci_driver cafe_nand_pci_driver = {
888 .name = "CAFÉ NAND",
889 .id_table = cafe_nand_tbl,
890 .probe = cafe_nand_probe,
5153b88c 891 .remove = cafe_nand_remove,
5467fb02 892 .resume = cafe_nand_resume,
5467fb02
DW		 893};
894
4d16cd65 895module_pci_driver(cafe_nand_pci_driver);
5467fb02
DW		 896
897MODULE_LICENSE("GPL");
898MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
f7c37d7b 899MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");
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