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ff4569c7 DB |
1 | /* |
2 | * davinci_nand.c - NAND Flash Driver for DaVinci family chips | |
3 | * | |
4 | * Copyright © 2006 Texas Instruments. | |
5 | * | |
6 | * Port to 2.6.23 Copyright © 2008 by: | |
7 | * Sander Huijsen <Shuijsen@optelecom-nkf.com> | |
8 | * Troy Kisky <troy.kisky@boundarydevices.com> | |
9 | * Dirk Behme <Dirk.Behme@gmail.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/err.h> | |
31 | #include <linux/clk.h> | |
32 | #include <linux/io.h> | |
33 | #include <linux/mtd/nand.h> | |
34 | #include <linux/mtd/partitions.h> | |
35 | ||
ff4569c7 DB |
36 | #include <mach/nand.h> |
37 | ||
38 | #include <asm/mach-types.h> | |
39 | ||
40 | ||
ff4569c7 DB |
41 | /* |
42 | * This is a device driver for the NAND flash controller found on the | |
43 | * various DaVinci family chips. It handles up to four SoC chipselects, | |
44 | * and some flavors of secondary chipselect (e.g. based on A12) as used | |
45 | * with multichip packages. | |
46 | * | |
6a4123e5 | 47 | * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC |
ff4569c7 DB |
48 | * available on chips like the DM355 and OMAP-L137 and needed with the |
49 | * more error-prone MLC NAND chips. | |
50 | * | |
51 | * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY | |
52 | * outputs in a "wire-AND" configuration, with no per-chip signals. | |
53 | */ | |
54 | struct davinci_nand_info { | |
55 | struct mtd_info mtd; | |
56 | struct nand_chip chip; | |
6a4123e5 | 57 | struct nand_ecclayout ecclayout; |
ff4569c7 DB |
58 | |
59 | struct device *dev; | |
60 | struct clk *clk; | |
61 | bool partitioned; | |
62 | ||
6a4123e5 DB |
63 | bool is_readmode; |
64 | ||
ff4569c7 DB |
65 | void __iomem *base; |
66 | void __iomem *vaddr; | |
67 | ||
68 | uint32_t ioaddr; | |
69 | uint32_t current_cs; | |
70 | ||
71 | uint32_t mask_chipsel; | |
72 | uint32_t mask_ale; | |
73 | uint32_t mask_cle; | |
74 | ||
75 | uint32_t core_chipsel; | |
76 | }; | |
77 | ||
78 | static DEFINE_SPINLOCK(davinci_nand_lock); | |
6a4123e5 | 79 | static bool ecc4_busy; |
ff4569c7 DB |
80 | |
81 | #define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd) | |
82 | ||
83 | ||
84 | static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info, | |
85 | int offset) | |
86 | { | |
87 | return __raw_readl(info->base + offset); | |
88 | } | |
89 | ||
90 | static inline void davinci_nand_writel(struct davinci_nand_info *info, | |
91 | int offset, unsigned long value) | |
92 | { | |
93 | __raw_writel(value, info->base + offset); | |
94 | } | |
95 | ||
96 | /*----------------------------------------------------------------------*/ | |
97 | ||
98 | /* | |
99 | * Access to hardware control lines: ALE, CLE, secondary chipselect. | |
100 | */ | |
101 | ||
102 | static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, | |
103 | unsigned int ctrl) | |
104 | { | |
105 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
106 | uint32_t addr = info->current_cs; | |
107 | struct nand_chip *nand = mtd->priv; | |
108 | ||
109 | /* Did the control lines change? */ | |
110 | if (ctrl & NAND_CTRL_CHANGE) { | |
111 | if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE) | |
112 | addr |= info->mask_cle; | |
113 | else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE) | |
114 | addr |= info->mask_ale; | |
115 | ||
116 | nand->IO_ADDR_W = (void __iomem __force *)addr; | |
117 | } | |
118 | ||
119 | if (cmd != NAND_CMD_NONE) | |
120 | iowrite8(cmd, nand->IO_ADDR_W); | |
121 | } | |
122 | ||
123 | static void nand_davinci_select_chip(struct mtd_info *mtd, int chip) | |
124 | { | |
125 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
126 | uint32_t addr = info->ioaddr; | |
127 | ||
128 | /* maybe kick in a second chipselect */ | |
129 | if (chip > 0) | |
130 | addr |= info->mask_chipsel; | |
131 | info->current_cs = addr; | |
132 | ||
133 | info->chip.IO_ADDR_W = (void __iomem __force *)addr; | |
134 | info->chip.IO_ADDR_R = info->chip.IO_ADDR_W; | |
135 | } | |
136 | ||
137 | /*----------------------------------------------------------------------*/ | |
138 | ||
139 | /* | |
140 | * 1-bit hardware ECC ... context maintained for each core chipselect | |
141 | */ | |
142 | ||
143 | static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd) | |
144 | { | |
145 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
146 | ||
147 | return davinci_nand_readl(info, NANDF1ECC_OFFSET | |
148 | + 4 * info->core_chipsel); | |
149 | } | |
150 | ||
151 | static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode) | |
152 | { | |
153 | struct davinci_nand_info *info; | |
154 | uint32_t nandcfr; | |
155 | unsigned long flags; | |
156 | ||
157 | info = to_davinci_nand(mtd); | |
158 | ||
159 | /* Reset ECC hardware */ | |
160 | nand_davinci_readecc_1bit(mtd); | |
161 | ||
162 | spin_lock_irqsave(&davinci_nand_lock, flags); | |
163 | ||
164 | /* Restart ECC hardware */ | |
165 | nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET); | |
166 | nandcfr |= BIT(8 + info->core_chipsel); | |
167 | davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr); | |
168 | ||
169 | spin_unlock_irqrestore(&davinci_nand_lock, flags); | |
170 | } | |
171 | ||
172 | /* | |
173 | * Read hardware ECC value and pack into three bytes | |
174 | */ | |
175 | static int nand_davinci_calculate_1bit(struct mtd_info *mtd, | |
176 | const u_char *dat, u_char *ecc_code) | |
177 | { | |
178 | unsigned int ecc_val = nand_davinci_readecc_1bit(mtd); | |
179 | unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4); | |
180 | ||
181 | /* invert so that erased block ecc is correct */ | |
182 | ecc24 = ~ecc24; | |
183 | ecc_code[0] = (u_char)(ecc24); | |
184 | ecc_code[1] = (u_char)(ecc24 >> 8); | |
185 | ecc_code[2] = (u_char)(ecc24 >> 16); | |
186 | ||
187 | return 0; | |
188 | } | |
189 | ||
190 | static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat, | |
191 | u_char *read_ecc, u_char *calc_ecc) | |
192 | { | |
193 | struct nand_chip *chip = mtd->priv; | |
194 | uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) | | |
195 | (read_ecc[2] << 16); | |
196 | uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) | | |
197 | (calc_ecc[2] << 16); | |
198 | uint32_t diff = eccCalc ^ eccNand; | |
199 | ||
200 | if (diff) { | |
201 | if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) { | |
202 | /* Correctable error */ | |
203 | if ((diff >> (12 + 3)) < chip->ecc.size) { | |
204 | dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7); | |
205 | return 1; | |
206 | } else { | |
207 | return -1; | |
208 | } | |
209 | } else if (!(diff & (diff - 1))) { | |
210 | /* Single bit ECC error in the ECC itself, | |
211 | * nothing to fix */ | |
212 | return 1; | |
213 | } else { | |
214 | /* Uncorrectable error */ | |
215 | return -1; | |
216 | } | |
217 | ||
218 | } | |
219 | return 0; | |
220 | } | |
221 | ||
222 | /*----------------------------------------------------------------------*/ | |
223 | ||
6a4123e5 DB |
224 | /* |
225 | * 4-bit hardware ECC ... context maintained over entire AEMIF | |
226 | * | |
227 | * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME | |
228 | * since that forces use of a problematic "infix OOB" layout. | |
229 | * Among other things, it trashes manufacturer bad block markers. | |
230 | * Also, and specific to this hardware, it ECC-protects the "prepad" | |
231 | * in the OOB ... while having ECC protection for parts of OOB would | |
232 | * seem useful, the current MTD stack sometimes wants to update the | |
233 | * OOB without recomputing ECC. | |
234 | */ | |
235 | ||
236 | static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode) | |
237 | { | |
238 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
239 | unsigned long flags; | |
240 | u32 val; | |
241 | ||
242 | spin_lock_irqsave(&davinci_nand_lock, flags); | |
243 | ||
244 | /* Start 4-bit ECC calculation for read/write */ | |
245 | val = davinci_nand_readl(info, NANDFCR_OFFSET); | |
246 | val &= ~(0x03 << 4); | |
247 | val |= (info->core_chipsel << 4) | BIT(12); | |
248 | davinci_nand_writel(info, NANDFCR_OFFSET, val); | |
249 | ||
250 | info->is_readmode = (mode == NAND_ECC_READ); | |
251 | ||
252 | spin_unlock_irqrestore(&davinci_nand_lock, flags); | |
253 | } | |
254 | ||
255 | /* Read raw ECC code after writing to NAND. */ | |
256 | static void | |
257 | nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4]) | |
258 | { | |
259 | const u32 mask = 0x03ff03ff; | |
260 | ||
261 | code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask; | |
262 | code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask; | |
263 | code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask; | |
264 | code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask; | |
265 | } | |
266 | ||
267 | /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */ | |
268 | static int nand_davinci_calculate_4bit(struct mtd_info *mtd, | |
269 | const u_char *dat, u_char *ecc_code) | |
270 | { | |
271 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
272 | u32 raw_ecc[4], *p; | |
273 | unsigned i; | |
274 | ||
275 | /* After a read, terminate ECC calculation by a dummy read | |
276 | * of some 4-bit ECC register. ECC covers everything that | |
277 | * was read; correct() just uses the hardware state, so | |
278 | * ecc_code is not needed. | |
279 | */ | |
280 | if (info->is_readmode) { | |
281 | davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET); | |
282 | return 0; | |
283 | } | |
284 | ||
285 | /* Pack eight raw 10-bit ecc values into ten bytes, making | |
286 | * two passes which each convert four values (in upper and | |
287 | * lower halves of two 32-bit words) into five bytes. The | |
288 | * ROM boot loader uses this same packing scheme. | |
289 | */ | |
290 | nand_davinci_readecc_4bit(info, raw_ecc); | |
291 | for (i = 0, p = raw_ecc; i < 2; i++, p += 2) { | |
292 | *ecc_code++ = p[0] & 0xff; | |
293 | *ecc_code++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc); | |
294 | *ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0); | |
295 | *ecc_code++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0); | |
296 | *ecc_code++ = (p[1] >> 18) & 0xff; | |
297 | } | |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
302 | /* Correct up to 4 bits in data we just read, using state left in the | |
303 | * hardware plus the ecc_code computed when it was first written. | |
304 | */ | |
305 | static int nand_davinci_correct_4bit(struct mtd_info *mtd, | |
306 | u_char *data, u_char *ecc_code, u_char *null) | |
307 | { | |
308 | int i; | |
309 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
310 | unsigned short ecc10[8]; | |
311 | unsigned short *ecc16; | |
312 | u32 syndrome[4]; | |
313 | unsigned num_errors, corrected; | |
314 | ||
315 | /* All bytes 0xff? It's an erased page; ignore its ECC. */ | |
316 | for (i = 0; i < 10; i++) { | |
317 | if (ecc_code[i] != 0xff) | |
318 | goto compare; | |
319 | } | |
320 | return 0; | |
321 | ||
322 | compare: | |
323 | /* Unpack ten bytes into eight 10 bit values. We know we're | |
324 | * little-endian, and use type punning for less shifting/masking. | |
325 | */ | |
326 | if (WARN_ON(0x01 & (unsigned) ecc_code)) | |
327 | return -EINVAL; | |
328 | ecc16 = (unsigned short *)ecc_code; | |
329 | ||
330 | ecc10[0] = (ecc16[0] >> 0) & 0x3ff; | |
331 | ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0); | |
332 | ecc10[2] = (ecc16[1] >> 4) & 0x3ff; | |
333 | ecc10[3] = ((ecc16[1] >> 14) & 0x3) | ((ecc16[2] << 2) & 0x3fc); | |
334 | ecc10[4] = (ecc16[2] >> 8) | ((ecc16[3] << 8) & 0x300); | |
335 | ecc10[5] = (ecc16[3] >> 2) & 0x3ff; | |
336 | ecc10[6] = ((ecc16[3] >> 12) & 0xf) | ((ecc16[4] << 4) & 0x3f0); | |
337 | ecc10[7] = (ecc16[4] >> 6) & 0x3ff; | |
338 | ||
339 | /* Tell ECC controller about the expected ECC codes. */ | |
340 | for (i = 7; i >= 0; i--) | |
341 | davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]); | |
342 | ||
343 | /* Allow time for syndrome calculation ... then read it. | |
344 | * A syndrome of all zeroes 0 means no detected errors. | |
345 | */ | |
346 | davinci_nand_readl(info, NANDFSR_OFFSET); | |
347 | nand_davinci_readecc_4bit(info, syndrome); | |
348 | if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3])) | |
349 | return 0; | |
350 | ||
f12a9473 SN |
351 | /* |
352 | * Clear any previous address calculation by doing a dummy read of an | |
353 | * error address register. | |
354 | */ | |
355 | davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET); | |
356 | ||
6a4123e5 DB |
357 | /* Start address calculation, and wait for it to complete. |
358 | * We _could_ start reading more data while this is working, | |
359 | * to speed up the overall page read. | |
360 | */ | |
361 | davinci_nand_writel(info, NANDFCR_OFFSET, | |
362 | davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13)); | |
363 | for (;;) { | |
364 | u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET); | |
365 | ||
366 | switch ((fsr >> 8) & 0x0f) { | |
367 | case 0: /* no error, should not happen */ | |
f12a9473 | 368 | davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET); |
6a4123e5 DB |
369 | return 0; |
370 | case 1: /* five or more errors detected */ | |
f12a9473 | 371 | davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET); |
6a4123e5 DB |
372 | return -EIO; |
373 | case 2: /* error addresses computed */ | |
374 | case 3: | |
375 | num_errors = 1 + ((fsr >> 16) & 0x03); | |
376 | goto correct; | |
377 | default: /* still working on it */ | |
378 | cpu_relax(); | |
379 | continue; | |
380 | } | |
381 | } | |
382 | ||
383 | correct: | |
384 | /* correct each error */ | |
385 | for (i = 0, corrected = 0; i < num_errors; i++) { | |
386 | int error_address, error_value; | |
387 | ||
388 | if (i > 1) { | |
389 | error_address = davinci_nand_readl(info, | |
390 | NAND_ERR_ADD2_OFFSET); | |
391 | error_value = davinci_nand_readl(info, | |
392 | NAND_ERR_ERRVAL2_OFFSET); | |
393 | } else { | |
394 | error_address = davinci_nand_readl(info, | |
395 | NAND_ERR_ADD1_OFFSET); | |
396 | error_value = davinci_nand_readl(info, | |
397 | NAND_ERR_ERRVAL1_OFFSET); | |
398 | } | |
399 | ||
400 | if (i & 1) { | |
401 | error_address >>= 16; | |
402 | error_value >>= 16; | |
403 | } | |
404 | error_address &= 0x3ff; | |
405 | error_address = (512 + 7) - error_address; | |
406 | ||
407 | if (error_address < 512) { | |
408 | data[error_address] ^= error_value; | |
409 | corrected++; | |
410 | } | |
411 | } | |
412 | ||
413 | return corrected; | |
414 | } | |
415 | ||
416 | /*----------------------------------------------------------------------*/ | |
417 | ||
ff4569c7 DB |
418 | /* |
419 | * NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's | |
420 | * how these chips are normally wired. This translates to both 8 and 16 | |
421 | * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4). | |
422 | * | |
423 | * For now we assume that configuration, or any other one which ignores | |
424 | * the two LSBs for NAND access ... so we can issue 32-bit reads/writes | |
425 | * and have that transparently morphed into multiple NAND operations. | |
426 | */ | |
427 | static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
428 | { | |
429 | struct nand_chip *chip = mtd->priv; | |
430 | ||
431 | if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0) | |
432 | ioread32_rep(chip->IO_ADDR_R, buf, len >> 2); | |
433 | else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0) | |
434 | ioread16_rep(chip->IO_ADDR_R, buf, len >> 1); | |
435 | else | |
436 | ioread8_rep(chip->IO_ADDR_R, buf, len); | |
437 | } | |
438 | ||
439 | static void nand_davinci_write_buf(struct mtd_info *mtd, | |
440 | const uint8_t *buf, int len) | |
441 | { | |
442 | struct nand_chip *chip = mtd->priv; | |
443 | ||
444 | if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0) | |
445 | iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2); | |
446 | else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0) | |
447 | iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1); | |
448 | else | |
449 | iowrite8_rep(chip->IO_ADDR_R, buf, len); | |
450 | } | |
451 | ||
452 | /* | |
453 | * Check hardware register for wait status. Returns 1 if device is ready, | |
454 | * 0 if it is still busy. | |
455 | */ | |
456 | static int nand_davinci_dev_ready(struct mtd_info *mtd) | |
457 | { | |
458 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
459 | ||
460 | return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0); | |
461 | } | |
462 | ||
463 | static void __init nand_dm6446evm_flash_init(struct davinci_nand_info *info) | |
464 | { | |
465 | uint32_t regval, a1cr; | |
466 | ||
467 | /* | |
468 | * NAND FLASH timings @ PLL1 == 459 MHz | |
469 | * - AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz | |
470 | * - AEMIF.CLK period = 1/76.5 MHz = 13.1 ns | |
471 | */ | |
472 | regval = 0 | |
473 | | (0 << 31) /* selectStrobe */ | |
474 | | (0 << 30) /* extWait (never with NAND) */ | |
475 | | (1 << 26) /* writeSetup 10 ns */ | |
476 | | (3 << 20) /* writeStrobe 40 ns */ | |
477 | | (1 << 17) /* writeHold 10 ns */ | |
478 | | (0 << 13) /* readSetup 10 ns */ | |
479 | | (3 << 7) /* readStrobe 60 ns */ | |
480 | | (0 << 4) /* readHold 10 ns */ | |
481 | | (3 << 2) /* turnAround ?? ns */ | |
482 | | (0 << 0) /* asyncSize 8-bit bus */ | |
483 | ; | |
484 | a1cr = davinci_nand_readl(info, A1CR_OFFSET); | |
485 | if (a1cr != regval) { | |
486 | dev_dbg(info->dev, "Warning: NAND config: Set A1CR " \ | |
487 | "reg to 0x%08x, was 0x%08x, should be done by " \ | |
488 | "bootloader.\n", regval, a1cr); | |
489 | davinci_nand_writel(info, A1CR_OFFSET, regval); | |
490 | } | |
491 | } | |
492 | ||
493 | /*----------------------------------------------------------------------*/ | |
494 | ||
6a4123e5 DB |
495 | /* An ECC layout for using 4-bit ECC with small-page flash, storing |
496 | * ten ECC bytes plus the manufacturer's bad block marker byte, and | |
497 | * and not overlapping the default BBT markers. | |
498 | */ | |
499 | static struct nand_ecclayout hwecc4_small __initconst = { | |
500 | .eccbytes = 10, | |
501 | .eccpos = { 0, 1, 2, 3, 4, | |
502 | /* offset 5 holds the badblock marker */ | |
503 | 6, 7, | |
504 | 13, 14, 15, }, | |
505 | .oobfree = { | |
506 | {.offset = 8, .length = 5, }, | |
507 | {.offset = 16, }, | |
508 | }, | |
509 | }; | |
510 | ||
f12a9473 SN |
511 | /* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash, |
512 | * storing ten ECC bytes plus the manufacturer's bad block marker byte, | |
513 | * and not overlapping the default BBT markers. | |
514 | */ | |
515 | static struct nand_ecclayout hwecc4_2048 __initconst = { | |
516 | .eccbytes = 40, | |
517 | .eccpos = { | |
518 | /* at the end of spare sector */ | |
519 | 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, | |
520 | 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, | |
521 | 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, | |
522 | 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, | |
523 | }, | |
524 | .oobfree = { | |
525 | /* 2 bytes at offset 0 hold manufacturer badblock markers */ | |
526 | {.offset = 2, .length = 22, }, | |
527 | /* 5 bytes at offset 8 hold BBT markers */ | |
528 | /* 8 bytes at offset 16 hold JFFS2 clean markers */ | |
529 | }, | |
530 | }; | |
6a4123e5 | 531 | |
ff4569c7 DB |
532 | static int __init nand_davinci_probe(struct platform_device *pdev) |
533 | { | |
534 | struct davinci_nand_pdata *pdata = pdev->dev.platform_data; | |
535 | struct davinci_nand_info *info; | |
536 | struct resource *res1; | |
537 | struct resource *res2; | |
538 | void __iomem *vaddr; | |
539 | void __iomem *base; | |
540 | int ret; | |
541 | uint32_t val; | |
542 | nand_ecc_modes_t ecc_mode; | |
543 | ||
533a0149 DB |
544 | /* insist on board-specific configuration */ |
545 | if (!pdata) | |
546 | return -ENODEV; | |
547 | ||
ff4569c7 DB |
548 | /* which external chipselect will we be managing? */ |
549 | if (pdev->id < 0 || pdev->id > 3) | |
550 | return -ENODEV; | |
551 | ||
552 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
553 | if (!info) { | |
554 | dev_err(&pdev->dev, "unable to allocate memory\n"); | |
555 | ret = -ENOMEM; | |
556 | goto err_nomem; | |
557 | } | |
558 | ||
559 | platform_set_drvdata(pdev, info); | |
560 | ||
561 | res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
562 | res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
563 | if (!res1 || !res2) { | |
564 | dev_err(&pdev->dev, "resource missing\n"); | |
565 | ret = -EINVAL; | |
566 | goto err_nomem; | |
567 | } | |
568 | ||
569 | vaddr = ioremap(res1->start, res1->end - res1->start); | |
570 | base = ioremap(res2->start, res2->end - res2->start); | |
571 | if (!vaddr || !base) { | |
572 | dev_err(&pdev->dev, "ioremap failed\n"); | |
573 | ret = -EINVAL; | |
574 | goto err_ioremap; | |
575 | } | |
576 | ||
577 | info->dev = &pdev->dev; | |
578 | info->base = base; | |
579 | info->vaddr = vaddr; | |
580 | ||
581 | info->mtd.priv = &info->chip; | |
582 | info->mtd.name = dev_name(&pdev->dev); | |
583 | info->mtd.owner = THIS_MODULE; | |
584 | ||
87f39f04 DB |
585 | info->mtd.dev.parent = &pdev->dev; |
586 | ||
ff4569c7 DB |
587 | info->chip.IO_ADDR_R = vaddr; |
588 | info->chip.IO_ADDR_W = vaddr; | |
589 | info->chip.chip_delay = 0; | |
590 | info->chip.select_chip = nand_davinci_select_chip; | |
591 | ||
592 | /* options such as NAND_USE_FLASH_BBT or 16-bit widths */ | |
533a0149 | 593 | info->chip.options = pdata->options; |
f611a79f MG |
594 | info->chip.bbt_td = pdata->bbt_td; |
595 | info->chip.bbt_md = pdata->bbt_md; | |
ff4569c7 DB |
596 | |
597 | info->ioaddr = (uint32_t __force) vaddr; | |
598 | ||
599 | info->current_cs = info->ioaddr; | |
600 | info->core_chipsel = pdev->id; | |
601 | info->mask_chipsel = pdata->mask_chipsel; | |
602 | ||
603 | /* use nandboot-capable ALE/CLE masks by default */ | |
5cd0be8e | 604 | info->mask_ale = pdata->mask_ale ? : MASK_ALE; |
533a0149 | 605 | info->mask_cle = pdata->mask_cle ? : MASK_CLE; |
ff4569c7 DB |
606 | |
607 | /* Set address of hardware control function */ | |
608 | info->chip.cmd_ctrl = nand_davinci_hwcontrol; | |
609 | info->chip.dev_ready = nand_davinci_dev_ready; | |
610 | ||
611 | /* Speed up buffer I/O */ | |
612 | info->chip.read_buf = nand_davinci_read_buf; | |
613 | info->chip.write_buf = nand_davinci_write_buf; | |
614 | ||
533a0149 DB |
615 | /* Use board-specific ECC config */ |
616 | ecc_mode = pdata->ecc_mode; | |
ff4569c7 | 617 | |
6a4123e5 | 618 | ret = -EINVAL; |
ff4569c7 DB |
619 | switch (ecc_mode) { |
620 | case NAND_ECC_NONE: | |
621 | case NAND_ECC_SOFT: | |
6a4123e5 | 622 | pdata->ecc_bits = 0; |
ff4569c7 DB |
623 | break; |
624 | case NAND_ECC_HW: | |
6a4123e5 DB |
625 | if (pdata->ecc_bits == 4) { |
626 | /* No sanity checks: CPUs must support this, | |
627 | * and the chips may not use NAND_BUSWIDTH_16. | |
628 | */ | |
629 | ||
630 | /* No sharing 4-bit hardware between chipselects yet */ | |
631 | spin_lock_irq(&davinci_nand_lock); | |
632 | if (ecc4_busy) | |
633 | ret = -EBUSY; | |
634 | else | |
635 | ecc4_busy = true; | |
636 | spin_unlock_irq(&davinci_nand_lock); | |
637 | ||
638 | if (ret == -EBUSY) | |
639 | goto err_ecc; | |
640 | ||
641 | info->chip.ecc.calculate = nand_davinci_calculate_4bit; | |
642 | info->chip.ecc.correct = nand_davinci_correct_4bit; | |
643 | info->chip.ecc.hwctl = nand_davinci_hwctl_4bit; | |
644 | info->chip.ecc.bytes = 10; | |
645 | } else { | |
646 | info->chip.ecc.calculate = nand_davinci_calculate_1bit; | |
647 | info->chip.ecc.correct = nand_davinci_correct_1bit; | |
648 | info->chip.ecc.hwctl = nand_davinci_hwctl_1bit; | |
649 | info->chip.ecc.bytes = 3; | |
650 | } | |
ff4569c7 | 651 | info->chip.ecc.size = 512; |
ff4569c7 | 652 | break; |
ff4569c7 DB |
653 | default: |
654 | ret = -EINVAL; | |
655 | goto err_ecc; | |
656 | } | |
657 | info->chip.ecc.mode = ecc_mode; | |
658 | ||
cd24f8c1 | 659 | info->clk = clk_get(&pdev->dev, "aemif"); |
ff4569c7 DB |
660 | if (IS_ERR(info->clk)) { |
661 | ret = PTR_ERR(info->clk); | |
cd24f8c1 | 662 | dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret); |
ff4569c7 DB |
663 | goto err_clk; |
664 | } | |
665 | ||
666 | ret = clk_enable(info->clk); | |
667 | if (ret < 0) { | |
cd24f8c1 KH |
668 | dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n", |
669 | ret); | |
ff4569c7 DB |
670 | goto err_clk_enable; |
671 | } | |
672 | ||
673 | /* EMIF timings should normally be set by the boot loader, | |
674 | * especially after boot-from-NAND. The *only* reason to | |
675 | * have this special casing for the DM6446 EVM is to work | |
676 | * with boot-from-NOR ... with CS0 manually re-jumpered | |
677 | * (after startup) so it addresses the NAND flash, not NOR. | |
678 | * Even for dev boards, that's unusually rude... | |
679 | */ | |
680 | if (machine_is_davinci_evm()) | |
681 | nand_dm6446evm_flash_init(info); | |
682 | ||
683 | spin_lock_irq(&davinci_nand_lock); | |
684 | ||
685 | /* put CSxNAND into NAND mode */ | |
686 | val = davinci_nand_readl(info, NANDFCR_OFFSET); | |
687 | val |= BIT(info->core_chipsel); | |
688 | davinci_nand_writel(info, NANDFCR_OFFSET, val); | |
689 | ||
690 | spin_unlock_irq(&davinci_nand_lock); | |
691 | ||
692 | /* Scan to find existence of the device(s) */ | |
6a4123e5 | 693 | ret = nand_scan_ident(&info->mtd, pdata->mask_chipsel ? 2 : 1); |
ff4569c7 DB |
694 | if (ret < 0) { |
695 | dev_dbg(&pdev->dev, "no NAND chip(s) found\n"); | |
696 | goto err_scan; | |
697 | } | |
698 | ||
6a4123e5 DB |
699 | /* Update ECC layout if needed ... for 1-bit HW ECC, the default |
700 | * is OK, but it allocates 6 bytes when only 3 are needed (for | |
701 | * each 512 bytes). For the 4-bit HW ECC, that default is not | |
702 | * usable: 10 bytes are needed, not 6. | |
703 | */ | |
704 | if (pdata->ecc_bits == 4) { | |
705 | int chunks = info->mtd.writesize / 512; | |
706 | ||
707 | if (!chunks || info->mtd.oobsize < 16) { | |
708 | dev_dbg(&pdev->dev, "too small\n"); | |
709 | ret = -EINVAL; | |
710 | goto err_scan; | |
711 | } | |
712 | ||
713 | /* For small page chips, preserve the manufacturer's | |
714 | * badblock marking data ... and make sure a flash BBT | |
715 | * table marker fits in the free bytes. | |
716 | */ | |
717 | if (chunks == 1) { | |
718 | info->ecclayout = hwecc4_small; | |
719 | info->ecclayout.oobfree[1].length = | |
720 | info->mtd.oobsize - 16; | |
721 | goto syndrome_done; | |
722 | } | |
f12a9473 SN |
723 | if (chunks == 4) { |
724 | info->ecclayout = hwecc4_2048; | |
725 | info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST; | |
726 | goto syndrome_done; | |
727 | } | |
6a4123e5 | 728 | |
f12a9473 SN |
729 | /* 4KiB page chips are not yet supported. The eccpos from |
730 | * nand_ecclayout cannot hold 80 bytes and change to eccpos[] | |
731 | * breaks userspace ioctl interface with mtd-utils. Once we | |
732 | * resolve this issue, NAND_ECC_HW_OOB_FIRST mode can be used | |
733 | * for the 4KiB page chips. | |
6a4123e5 DB |
734 | */ |
735 | dev_warn(&pdev->dev, "no 4-bit ECC support yet " | |
f12a9473 | 736 | "for 4KiB-page NAND\n"); |
6a4123e5 DB |
737 | ret = -EIO; |
738 | goto err_scan; | |
739 | ||
740 | syndrome_done: | |
741 | info->chip.ecc.layout = &info->ecclayout; | |
742 | } | |
743 | ||
744 | ret = nand_scan_tail(&info->mtd); | |
745 | if (ret < 0) | |
746 | goto err_scan; | |
747 | ||
ff4569c7 DB |
748 | if (mtd_has_partitions()) { |
749 | struct mtd_partition *mtd_parts = NULL; | |
750 | int mtd_parts_nb = 0; | |
751 | ||
752 | if (mtd_has_cmdlinepart()) { | |
753 | static const char *probes[] __initconst = | |
754 | { "cmdlinepart", NULL }; | |
755 | ||
ff4569c7 DB |
756 | mtd_parts_nb = parse_mtd_partitions(&info->mtd, probes, |
757 | &mtd_parts, 0); | |
ff4569c7 DB |
758 | } |
759 | ||
533a0149 | 760 | if (mtd_parts_nb <= 0) { |
ff4569c7 DB |
761 | mtd_parts = pdata->parts; |
762 | mtd_parts_nb = pdata->nr_parts; | |
763 | } | |
764 | ||
765 | /* Register any partitions */ | |
766 | if (mtd_parts_nb > 0) { | |
767 | ret = add_mtd_partitions(&info->mtd, | |
768 | mtd_parts, mtd_parts_nb); | |
769 | if (ret == 0) | |
770 | info->partitioned = true; | |
771 | } | |
772 | ||
533a0149 | 773 | } else if (pdata->nr_parts) { |
ff4569c7 DB |
774 | dev_warn(&pdev->dev, "ignoring %d default partitions on %s\n", |
775 | pdata->nr_parts, info->mtd.name); | |
776 | } | |
777 | ||
778 | /* If there's no partition info, just package the whole chip | |
779 | * as a single MTD device. | |
780 | */ | |
781 | if (!info->partitioned) | |
782 | ret = add_mtd_device(&info->mtd) ? -ENODEV : 0; | |
783 | ||
784 | if (ret < 0) | |
785 | goto err_scan; | |
786 | ||
787 | val = davinci_nand_readl(info, NRCSR_OFFSET); | |
788 | dev_info(&pdev->dev, "controller rev. %d.%d\n", | |
789 | (val >> 8) & 0xff, val & 0xff); | |
790 | ||
791 | return 0; | |
792 | ||
793 | err_scan: | |
794 | clk_disable(info->clk); | |
795 | ||
796 | err_clk_enable: | |
797 | clk_put(info->clk); | |
798 | ||
6a4123e5 DB |
799 | spin_lock_irq(&davinci_nand_lock); |
800 | if (ecc_mode == NAND_ECC_HW_SYNDROME) | |
801 | ecc4_busy = false; | |
802 | spin_unlock_irq(&davinci_nand_lock); | |
803 | ||
ff4569c7 DB |
804 | err_ecc: |
805 | err_clk: | |
806 | err_ioremap: | |
807 | if (base) | |
808 | iounmap(base); | |
809 | if (vaddr) | |
810 | iounmap(vaddr); | |
811 | ||
812 | err_nomem: | |
813 | kfree(info); | |
814 | return ret; | |
815 | } | |
816 | ||
817 | static int __exit nand_davinci_remove(struct platform_device *pdev) | |
818 | { | |
819 | struct davinci_nand_info *info = platform_get_drvdata(pdev); | |
820 | int status; | |
821 | ||
822 | if (mtd_has_partitions() && info->partitioned) | |
823 | status = del_mtd_partitions(&info->mtd); | |
824 | else | |
825 | status = del_mtd_device(&info->mtd); | |
826 | ||
6a4123e5 DB |
827 | spin_lock_irq(&davinci_nand_lock); |
828 | if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME) | |
829 | ecc4_busy = false; | |
830 | spin_unlock_irq(&davinci_nand_lock); | |
831 | ||
ff4569c7 DB |
832 | iounmap(info->base); |
833 | iounmap(info->vaddr); | |
834 | ||
835 | nand_release(&info->mtd); | |
836 | ||
837 | clk_disable(info->clk); | |
838 | clk_put(info->clk); | |
839 | ||
840 | kfree(info); | |
841 | ||
842 | return 0; | |
843 | } | |
844 | ||
845 | static struct platform_driver nand_davinci_driver = { | |
846 | .remove = __exit_p(nand_davinci_remove), | |
847 | .driver = { | |
848 | .name = "davinci_nand", | |
849 | }, | |
850 | }; | |
851 | MODULE_ALIAS("platform:davinci_nand"); | |
852 | ||
853 | static int __init nand_davinci_init(void) | |
854 | { | |
855 | return platform_driver_probe(&nand_davinci_driver, nand_davinci_probe); | |
856 | } | |
857 | module_init(nand_davinci_init); | |
858 | ||
859 | static void __exit nand_davinci_exit(void) | |
860 | { | |
861 | platform_driver_unregister(&nand_davinci_driver); | |
862 | } | |
863 | module_exit(nand_davinci_exit); | |
864 | ||
865 | MODULE_LICENSE("GPL"); | |
866 | MODULE_AUTHOR("Texas Instruments"); | |
867 | MODULE_DESCRIPTION("Davinci NAND flash driver"); | |
868 |