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Commit | Line | Data |
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ce082596 JR |
1 | /* |
2 | * NAND Flash Controller Device Driver | |
3 | * Copyright © 2009-2010, Intel Corporation and its suppliers. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | */ | |
ce082596 JR |
19 | #include <linux/interrupt.h> |
20 | #include <linux/delay.h> | |
84457949 | 21 | #include <linux/dma-mapping.h> |
ce082596 JR |
22 | #include <linux/wait.h> |
23 | #include <linux/mutex.h> | |
ce082596 JR |
24 | #include <linux/mtd/mtd.h> |
25 | #include <linux/module.h> | |
7d370b2c | 26 | #include <linux/slab.h> |
ce082596 JR |
27 | |
28 | #include "denali.h" | |
29 | ||
30 | MODULE_LICENSE("GPL"); | |
31 | ||
ce082596 JR |
32 | #define DENALI_NAND_NAME "denali-nand" |
33 | ||
0d3a966d MY |
34 | /* Host Data/Command Interface */ |
35 | #define DENALI_HOST_ADDR 0x00 | |
36 | #define DENALI_HOST_DATA 0x10 | |
37 | ||
38 | #define DENALI_MAP00 (0 << 26) /* direct access to buffer */ | |
39 | #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */ | |
40 | #define DENALI_MAP10 (2 << 26) /* high-level control plane */ | |
41 | #define DENALI_MAP11 (3 << 26) /* direct controller access */ | |
42 | ||
43 | /* MAP11 access cycle type */ | |
44 | #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */ | |
45 | #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */ | |
46 | #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */ | |
47 | ||
48 | /* MAP10 commands */ | |
49 | #define DENALI_ERASE 0x01 | |
50 | ||
51 | #define DENALI_BANK(denali) ((denali)->active_bank << 24) | |
ce082596 | 52 | |
0d3a966d | 53 | #define DENALI_INVALID_BANK -1 |
c19e31d0 MY |
54 | #define DENALI_NR_BANKS 4 |
55 | ||
43914a2d | 56 | /* |
1bb88666 MY |
57 | * The bus interface clock, clk_x, is phase aligned with the core clock. The |
58 | * clk_x is an integral multiple N of the core clk. The value N is configured | |
59 | * at IP delivery time, and its available value is 4, 5, or 6. We need to align | |
60 | * to the largest value to make it work with any possible configuration. | |
43914a2d | 61 | */ |
1bb88666 | 62 | #define DENALI_CLK_X_MULT 6 |
ce082596 | 63 | |
43914a2d MY |
64 | /* |
65 | * this macro allows us to convert from an MTD structure to our own | |
ce082596 JR |
66 | * device context (denali) structure. |
67 | */ | |
442f201b BB |
68 | static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) |
69 | { | |
70 | return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); | |
71 | } | |
ce082596 | 72 | |
0d3a966d MY |
73 | static void denali_host_write(struct denali_nand_info *denali, |
74 | uint32_t addr, uint32_t data) | |
ce082596 | 75 | { |
0d3a966d MY |
76 | iowrite32(addr, denali->host + DENALI_HOST_ADDR); |
77 | iowrite32(data, denali->host + DENALI_HOST_DATA); | |
ce082596 JR |
78 | } |
79 | ||
c89eeda8 JI |
80 | /* |
81 | * Use the configuration feature register to determine the maximum number of | |
82 | * banks that the hardware supports. | |
83 | */ | |
84 | static void detect_max_banks(struct denali_nand_info *denali) | |
85 | { | |
0d3a966d | 86 | uint32_t features = ioread32(denali->reg + FEATURES); |
c89eeda8 | 87 | |
e7beeeec MY |
88 | denali->max_banks = 1 << (features & FEATURES__N_BANKS); |
89 | ||
90 | /* the encoding changed from rev 5.0 to 5.1 */ | |
91 | if (denali->revision < 0x0501) | |
92 | denali->max_banks <<= 1; | |
c89eeda8 JI |
93 | } |
94 | ||
c19e31d0 | 95 | static void denali_enable_irq(struct denali_nand_info *denali) |
ce082596 | 96 | { |
c19e31d0 | 97 | int i; |
ce082596 | 98 | |
c19e31d0 | 99 | for (i = 0; i < DENALI_NR_BANKS; i++) |
0d3a966d MY |
100 | iowrite32(U32_MAX, denali->reg + INTR_EN(i)); |
101 | iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE); | |
ce082596 JR |
102 | } |
103 | ||
c19e31d0 | 104 | static void denali_disable_irq(struct denali_nand_info *denali) |
ce082596 | 105 | { |
9589bf5b | 106 | int i; |
ce082596 | 107 | |
c19e31d0 | 108 | for (i = 0; i < DENALI_NR_BANKS; i++) |
0d3a966d MY |
109 | iowrite32(0, denali->reg + INTR_EN(i)); |
110 | iowrite32(0, denali->reg + GLOBAL_INT_ENABLE); | |
ce082596 JR |
111 | } |
112 | ||
c19e31d0 MY |
113 | static void denali_clear_irq(struct denali_nand_info *denali, |
114 | int bank, uint32_t irq_status) | |
ce082596 | 115 | { |
c19e31d0 | 116 | /* write one to clear bits */ |
0d3a966d | 117 | iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); |
ce082596 JR |
118 | } |
119 | ||
c19e31d0 | 120 | static void denali_clear_irq_all(struct denali_nand_info *denali) |
ce082596 | 121 | { |
9589bf5b JI |
122 | int i; |
123 | ||
c19e31d0 MY |
124 | for (i = 0; i < DENALI_NR_BANKS; i++) |
125 | denali_clear_irq(denali, i, U32_MAX); | |
ce082596 JR |
126 | } |
127 | ||
c19e31d0 | 128 | static irqreturn_t denali_isr(int irq, void *dev_id) |
ce082596 | 129 | { |
c19e31d0 MY |
130 | struct denali_nand_info *denali = dev_id; |
131 | irqreturn_t ret = IRQ_NONE; | |
132 | uint32_t irq_status; | |
133 | int i; | |
ce082596 | 134 | |
c19e31d0 | 135 | spin_lock(&denali->irq_lock); |
ce082596 | 136 | |
c19e31d0 | 137 | for (i = 0; i < DENALI_NR_BANKS; i++) { |
0d3a966d | 138 | irq_status = ioread32(denali->reg + INTR_STATUS(i)); |
c19e31d0 MY |
139 | if (irq_status) |
140 | ret = IRQ_HANDLED; | |
ce082596 | 141 | |
c19e31d0 | 142 | denali_clear_irq(denali, i, irq_status); |
ce082596 | 143 | |
0d3a966d | 144 | if (i != denali->active_bank) |
c19e31d0 MY |
145 | continue; |
146 | ||
147 | denali->irq_status |= irq_status; | |
5637b69d | 148 | |
c19e31d0 MY |
149 | if (denali->irq_status & denali->irq_mask) |
150 | complete(&denali->complete); | |
151 | } | |
ce082596 | 152 | |
c19e31d0 | 153 | spin_unlock(&denali->irq_lock); |
ce082596 | 154 | |
c19e31d0 | 155 | return ret; |
ce082596 JR |
156 | } |
157 | ||
c19e31d0 | 158 | static void denali_reset_irq(struct denali_nand_info *denali) |
ce082596 | 159 | { |
c19e31d0 | 160 | unsigned long flags; |
ce082596 | 161 | |
c19e31d0 MY |
162 | spin_lock_irqsave(&denali->irq_lock, flags); |
163 | denali->irq_status = 0; | |
164 | denali->irq_mask = 0; | |
165 | spin_unlock_irqrestore(&denali->irq_lock, flags); | |
ce082596 JR |
166 | } |
167 | ||
c19e31d0 MY |
168 | static uint32_t denali_wait_for_irq(struct denali_nand_info *denali, |
169 | uint32_t irq_mask) | |
ce082596 | 170 | { |
c19e31d0 | 171 | unsigned long time_left, flags; |
5637b69d | 172 | uint32_t irq_status; |
ce082596 | 173 | |
c19e31d0 | 174 | spin_lock_irqsave(&denali->irq_lock, flags); |
ce082596 | 175 | |
c19e31d0 MY |
176 | irq_status = denali->irq_status; |
177 | ||
178 | if (irq_mask & irq_status) { | |
179 | /* return immediately if the IRQ has already happened. */ | |
180 | spin_unlock_irqrestore(&denali->irq_lock, flags); | |
181 | return irq_status; | |
ce082596 | 182 | } |
c19e31d0 MY |
183 | |
184 | denali->irq_mask = irq_mask; | |
185 | reinit_completion(&denali->complete); | |
186 | spin_unlock_irqrestore(&denali->irq_lock, flags); | |
187 | ||
188 | time_left = wait_for_completion_timeout(&denali->complete, | |
189 | msecs_to_jiffies(1000)); | |
190 | if (!time_left) { | |
191 | dev_err(denali->dev, "timeout while waiting for irq 0x%x\n", | |
192 | denali->irq_mask); | |
193 | return 0; | |
194 | } | |
195 | ||
196 | return denali->irq_status; | |
ce082596 | 197 | } |
ce082596 | 198 | |
fa6134e5 | 199 | static uint32_t denali_check_irq(struct denali_nand_info *denali) |
ce082596 | 200 | { |
fa6134e5 | 201 | unsigned long flags; |
c19e31d0 | 202 | uint32_t irq_status; |
ce082596 | 203 | |
fa6134e5 MY |
204 | spin_lock_irqsave(&denali->irq_lock, flags); |
205 | irq_status = denali->irq_status; | |
206 | spin_unlock_irqrestore(&denali->irq_lock, flags); | |
ce082596 | 207 | |
fa6134e5 | 208 | return irq_status; |
ce082596 JR |
209 | } |
210 | ||
43914a2d MY |
211 | /* |
212 | * This helper function setups the registers for ECC and whether or not | |
213 | * the spare area will be transferred. | |
214 | */ | |
5bac3acf | 215 | static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, |
ce082596 JR |
216 | bool transfer_spare) |
217 | { | |
5637b69d | 218 | int ecc_en_flag, transfer_spare_flag; |
ce082596 JR |
219 | |
220 | /* set ECC, transfer spare bits if needed */ | |
221 | ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; | |
222 | transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0; | |
223 | ||
224 | /* Enable spare area/ECC per user's request. */ | |
0d3a966d MY |
225 | iowrite32(ecc_en_flag, denali->reg + ECC_ENABLE); |
226 | iowrite32(transfer_spare_flag, denali->reg + TRANSFER_SPARE_REG); | |
ce082596 JR |
227 | } |
228 | ||
fa6134e5 MY |
229 | static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
230 | { | |
231 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
232 | int i; | |
233 | ||
0d3a966d MY |
234 | iowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali), |
235 | denali->host + DENALI_HOST_ADDR); | |
fa6134e5 MY |
236 | |
237 | for (i = 0; i < len; i++) | |
0d3a966d | 238 | buf[i] = ioread32(denali->host + DENALI_HOST_DATA); |
fa6134e5 MY |
239 | } |
240 | ||
241 | static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
242 | { | |
243 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
244 | int i; | |
245 | ||
0d3a966d MY |
246 | iowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali), |
247 | denali->host + DENALI_HOST_ADDR); | |
fa6134e5 MY |
248 | |
249 | for (i = 0; i < len; i++) | |
0d3a966d | 250 | iowrite32(buf[i], denali->host + DENALI_HOST_DATA); |
fa6134e5 MY |
251 | } |
252 | ||
253 | static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) | |
254 | { | |
255 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
256 | uint16_t *buf16 = (uint16_t *)buf; | |
257 | int i; | |
258 | ||
0d3a966d MY |
259 | iowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali), |
260 | denali->host + DENALI_HOST_ADDR); | |
fa6134e5 MY |
261 | |
262 | for (i = 0; i < len / 2; i++) | |
0d3a966d | 263 | buf16[i] = ioread32(denali->host + DENALI_HOST_DATA); |
fa6134e5 MY |
264 | } |
265 | ||
266 | static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf, | |
267 | int len) | |
268 | { | |
269 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
270 | const uint16_t *buf16 = (const uint16_t *)buf; | |
271 | int i; | |
272 | ||
0d3a966d MY |
273 | iowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali), |
274 | denali->host + DENALI_HOST_ADDR); | |
fa6134e5 MY |
275 | |
276 | for (i = 0; i < len / 2; i++) | |
0d3a966d | 277 | iowrite32(buf16[i], denali->host + DENALI_HOST_DATA); |
fa6134e5 MY |
278 | } |
279 | ||
280 | static uint8_t denali_read_byte(struct mtd_info *mtd) | |
281 | { | |
282 | uint8_t byte; | |
283 | ||
284 | denali_read_buf(mtd, &byte, 1); | |
285 | ||
286 | return byte; | |
287 | } | |
288 | ||
289 | static void denali_write_byte(struct mtd_info *mtd, uint8_t byte) | |
290 | { | |
291 | denali_write_buf(mtd, &byte, 1); | |
292 | } | |
293 | ||
294 | static uint16_t denali_read_word(struct mtd_info *mtd) | |
295 | { | |
296 | uint16_t word; | |
297 | ||
298 | denali_read_buf16(mtd, (uint8_t *)&word, 2); | |
299 | ||
300 | return word; | |
301 | } | |
302 | ||
303 | static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) | |
304 | { | |
305 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
306 | uint32_t type; | |
307 | ||
308 | if (ctrl & NAND_CLE) | |
0d3a966d | 309 | type = DENALI_MAP11_CMD; |
fa6134e5 | 310 | else if (ctrl & NAND_ALE) |
0d3a966d | 311 | type = DENALI_MAP11_ADDR; |
fa6134e5 MY |
312 | else |
313 | return; | |
314 | ||
315 | /* | |
316 | * Some commands are followed by chip->dev_ready or chip->waitfunc. | |
317 | * irq_status must be cleared here to catch the R/B# interrupt later. | |
318 | */ | |
319 | if (ctrl & NAND_CTRL_CHANGE) | |
320 | denali_reset_irq(denali); | |
321 | ||
0d3a966d | 322 | denali_host_write(denali, DENALI_BANK(denali) | type, dat); |
fa6134e5 MY |
323 | } |
324 | ||
325 | static int denali_dev_ready(struct mtd_info *mtd) | |
326 | { | |
327 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
328 | ||
329 | return !!(denali_check_irq(denali) & INTR__INT_ACT); | |
330 | } | |
331 | ||
d29109be MY |
332 | static int denali_check_erased_page(struct mtd_info *mtd, |
333 | struct nand_chip *chip, uint8_t *buf, | |
334 | unsigned long uncor_ecc_flags, | |
335 | unsigned int max_bitflips) | |
ce082596 | 336 | { |
d29109be MY |
337 | uint8_t *ecc_code = chip->buffers->ecccode; |
338 | int ecc_steps = chip->ecc.steps; | |
339 | int ecc_size = chip->ecc.size; | |
340 | int ecc_bytes = chip->ecc.bytes; | |
341 | int i, ret, stat; | |
342 | ||
343 | ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, | |
344 | chip->ecc.total); | |
345 | if (ret) | |
346 | return ret; | |
347 | ||
348 | for (i = 0; i < ecc_steps; i++) { | |
349 | if (!(uncor_ecc_flags & BIT(i))) | |
350 | continue; | |
351 | ||
352 | stat = nand_check_erased_ecc_chunk(buf, ecc_size, | |
353 | ecc_code, ecc_bytes, | |
354 | NULL, 0, | |
355 | chip->ecc.strength); | |
356 | if (stat < 0) { | |
357 | mtd->ecc_stats.failed++; | |
358 | } else { | |
359 | mtd->ecc_stats.corrected += stat; | |
360 | max_bitflips = max_t(unsigned int, max_bitflips, stat); | |
361 | } | |
362 | ||
363 | buf += ecc_size; | |
364 | ecc_code += ecc_bytes; | |
365 | } | |
8125450c | 366 | |
d29109be | 367 | return max_bitflips; |
ce082596 | 368 | } |
d29109be | 369 | |
24715c74 MY |
370 | static int denali_hw_ecc_fixup(struct mtd_info *mtd, |
371 | struct denali_nand_info *denali, | |
372 | unsigned long *uncor_ecc_flags) | |
373 | { | |
374 | struct nand_chip *chip = mtd_to_nand(mtd); | |
0d3a966d | 375 | int bank = denali->active_bank; |
24715c74 MY |
376 | uint32_t ecc_cor; |
377 | unsigned int max_bitflips; | |
378 | ||
0d3a966d | 379 | ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank)); |
24715c74 MY |
380 | ecc_cor >>= ECC_COR_INFO__SHIFT(bank); |
381 | ||
382 | if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) { | |
383 | /* | |
384 | * This flag is set when uncorrectable error occurs at least in | |
385 | * one ECC sector. We can not know "how many sectors", or | |
386 | * "which sector(s)". We need erase-page check for all sectors. | |
387 | */ | |
388 | *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0); | |
389 | return 0; | |
390 | } | |
391 | ||
392 | max_bitflips = ecc_cor & ECC_COR_INFO__MAX_ERRORS; | |
393 | ||
394 | /* | |
395 | * The register holds the maximum of per-sector corrected bitflips. | |
396 | * This is suitable for the return value of the ->read_page() callback. | |
397 | * Unfortunately, we can not know the total number of corrected bits in | |
398 | * the page. Increase the stats by max_bitflips. (compromised solution) | |
399 | */ | |
400 | mtd->ecc_stats.corrected += max_bitflips; | |
401 | ||
402 | return max_bitflips; | |
403 | } | |
404 | ||
ce082596 JR |
405 | #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12) |
406 | #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET)) | |
407 | #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK) | |
20d48595 | 408 | #define ECC_ERROR_UNCORRECTABLE(x) ((x) & ERR_CORRECTION_INFO__ERROR_TYPE) |
8ae61ebd | 409 | #define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8) |
ce082596 JR |
410 | #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO) |
411 | ||
24715c74 MY |
412 | static int denali_sw_ecc_fixup(struct mtd_info *mtd, |
413 | struct denali_nand_info *denali, | |
414 | unsigned long *uncor_ecc_flags, uint8_t *buf) | |
ce082596 | 415 | { |
7de117fd | 416 | unsigned int ecc_size = denali->nand.ecc.size; |
3f91e94f | 417 | unsigned int bitflips = 0; |
20d48595 MY |
418 | unsigned int max_bitflips = 0; |
419 | uint32_t err_addr, err_cor_info; | |
420 | unsigned int err_byte, err_sector, err_device; | |
421 | uint8_t err_cor_value; | |
422 | unsigned int prev_sector = 0; | |
c19e31d0 | 423 | uint32_t irq_status; |
ce082596 | 424 | |
c19e31d0 | 425 | denali_reset_irq(denali); |
20d48595 MY |
426 | |
427 | do { | |
0d3a966d | 428 | err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS); |
20d48595 MY |
429 | err_sector = ECC_SECTOR(err_addr); |
430 | err_byte = ECC_BYTE(err_addr); | |
431 | ||
0d3a966d | 432 | err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO); |
20d48595 MY |
433 | err_cor_value = ECC_CORRECTION_VALUE(err_cor_info); |
434 | err_device = ECC_ERR_DEVICE(err_cor_info); | |
435 | ||
436 | /* reset the bitflip counter when crossing ECC sector */ | |
437 | if (err_sector != prev_sector) | |
438 | bitflips = 0; | |
439 | ||
440 | if (ECC_ERROR_UNCORRECTABLE(err_cor_info)) { | |
441 | /* | |
d29109be MY |
442 | * Check later if this is a real ECC error, or |
443 | * an erased sector. | |
20d48595 | 444 | */ |
d29109be | 445 | *uncor_ecc_flags |= BIT(err_sector); |
7de117fd | 446 | } else if (err_byte < ecc_size) { |
20d48595 | 447 | /* |
7de117fd | 448 | * If err_byte is larger than ecc_size, means error |
20d48595 MY |
449 | * happened in OOB, so we ignore it. It's no need for |
450 | * us to correct it err_device is represented the NAND | |
451 | * error bits are happened in if there are more than | |
452 | * one NAND connected. | |
453 | */ | |
454 | int offset; | |
455 | unsigned int flips_in_byte; | |
456 | ||
7de117fd | 457 | offset = (err_sector * ecc_size + err_byte) * |
0d3a966d | 458 | denali->devs_per_cs + err_device; |
20d48595 MY |
459 | |
460 | /* correct the ECC error */ | |
461 | flips_in_byte = hweight8(buf[offset] ^ err_cor_value); | |
462 | buf[offset] ^= err_cor_value; | |
463 | mtd->ecc_stats.corrected += flips_in_byte; | |
464 | bitflips += flips_in_byte; | |
465 | ||
466 | max_bitflips = max(max_bitflips, bitflips); | |
467 | } | |
468 | ||
469 | prev_sector = err_sector; | |
470 | } while (!ECC_LAST_ERR(err_cor_info)); | |
471 | ||
472 | /* | |
473 | * Once handle all ecc errors, controller will trigger a | |
474 | * ECC_TRANSACTION_DONE interrupt, so here just wait for | |
475 | * a while for this interrupt | |
476 | */ | |
c19e31d0 MY |
477 | irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE); |
478 | if (!(irq_status & INTR__ECC_TRANSACTION_DONE)) | |
479 | return -EIO; | |
20d48595 MY |
480 | |
481 | return max_bitflips; | |
ce082596 JR |
482 | } |
483 | ||
484 | /* programs the controller to either enable/disable DMA transfers */ | |
aadff49c | 485 | static void denali_enable_dma(struct denali_nand_info *denali, bool en) |
ce082596 | 486 | { |
0d3a966d MY |
487 | iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->reg + DMA_ENABLE); |
488 | ioread32(denali->reg + DMA_ENABLE); | |
ce082596 JR |
489 | } |
490 | ||
2291cb89 | 491 | static void denali_setup_dma64(struct denali_nand_info *denali, |
96a376bd | 492 | dma_addr_t dma_addr, int page, int write) |
210a2c87 MY |
493 | { |
494 | uint32_t mode; | |
495 | const int page_count = 1; | |
210a2c87 | 496 | |
0d3a966d | 497 | mode = DENALI_MAP10 | DENALI_BANK(denali) | page; |
210a2c87 MY |
498 | |
499 | /* DMA is a three step process */ | |
500 | ||
501 | /* | |
502 | * 1. setup transfer type, interrupt when complete, | |
503 | * burst len = 64 bytes, the number of pages | |
504 | */ | |
0d3a966d MY |
505 | denali_host_write(denali, mode, |
506 | 0x01002000 | (64 << 16) | (write << 8) | page_count); | |
210a2c87 MY |
507 | |
508 | /* 2. set memory low address */ | |
0d3a966d | 509 | denali_host_write(denali, mode, dma_addr); |
210a2c87 MY |
510 | |
511 | /* 3. set memory high address */ | |
0d3a966d | 512 | denali_host_write(denali, mode, (uint64_t)dma_addr >> 32); |
210a2c87 MY |
513 | } |
514 | ||
2291cb89 | 515 | static void denali_setup_dma32(struct denali_nand_info *denali, |
96a376bd | 516 | dma_addr_t dma_addr, int page, int write) |
ce082596 | 517 | { |
5637b69d | 518 | uint32_t mode; |
ce082596 | 519 | const int page_count = 1; |
ce082596 | 520 | |
0d3a966d | 521 | mode = DENALI_MAP10 | DENALI_BANK(denali); |
ce082596 JR |
522 | |
523 | /* DMA is a four step process */ | |
524 | ||
525 | /* 1. setup transfer type and # of pages */ | |
0d3a966d MY |
526 | denali_host_write(denali, mode | page, |
527 | 0x2000 | (write << 8) | page_count); | |
ce082596 JR |
528 | |
529 | /* 2. set memory high address bits 23:8 */ | |
0d3a966d | 530 | denali_host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200); |
ce082596 JR |
531 | |
532 | /* 3. set memory low address bits 23:8 */ | |
0d3a966d | 533 | denali_host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300); |
ce082596 | 534 | |
43914a2d | 535 | /* 4. interrupt when complete, burst len = 64 bytes */ |
0d3a966d | 536 | denali_host_write(denali, mode | 0x14000, 0x2400); |
ce082596 JR |
537 | } |
538 | ||
2291cb89 | 539 | static void denali_setup_dma(struct denali_nand_info *denali, |
96a376bd | 540 | dma_addr_t dma_addr, int page, int write) |
210a2c87 MY |
541 | { |
542 | if (denali->caps & DENALI_CAP_DMA_64BIT) | |
96a376bd | 543 | denali_setup_dma64(denali, dma_addr, page, write); |
210a2c87 | 544 | else |
96a376bd | 545 | denali_setup_dma32(denali, dma_addr, page, write); |
210a2c87 MY |
546 | } |
547 | ||
26d266e1 MY |
548 | static int denali_pio_read(struct denali_nand_info *denali, void *buf, |
549 | size_t size, int page, int raw) | |
ce082596 | 550 | { |
0d3a966d | 551 | uint32_t addr = DENALI_BANK(denali) | page; |
26d266e1 MY |
552 | uint32_t *buf32 = (uint32_t *)buf; |
553 | uint32_t irq_status, ecc_err_mask; | |
554 | int i; | |
b21ff825 | 555 | |
26d266e1 MY |
556 | if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) |
557 | ecc_err_mask = INTR__ECC_UNCOR_ERR; | |
558 | else | |
559 | ecc_err_mask = INTR__ECC_ERR; | |
ce082596 | 560 | |
26d266e1 | 561 | denali_reset_irq(denali); |
ce082596 | 562 | |
0d3a966d | 563 | iowrite32(DENALI_MAP01 | addr, denali->host + DENALI_HOST_ADDR); |
26d266e1 | 564 | for (i = 0; i < size / 4; i++) |
0d3a966d | 565 | *buf32++ = ioread32(denali->host + DENALI_HOST_DATA); |
26d266e1 MY |
566 | |
567 | irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC); | |
568 | if (!(irq_status & INTR__PAGE_XFER_INC)) | |
569 | return -EIO; | |
ce082596 | 570 | |
57a4d8b5 MY |
571 | if (irq_status & INTR__ERASED_PAGE) |
572 | memset(buf, 0xff, size); | |
573 | ||
26d266e1 MY |
574 | return irq_status & ecc_err_mask ? -EBADMSG : 0; |
575 | } | |
576 | ||
577 | static int denali_pio_write(struct denali_nand_info *denali, | |
578 | const void *buf, size_t size, int page, int raw) | |
579 | { | |
0d3a966d | 580 | uint32_t addr = DENALI_BANK(denali) | page; |
26d266e1 MY |
581 | const uint32_t *buf32 = (uint32_t *)buf; |
582 | uint32_t irq_status; | |
583 | int i; | |
ce082596 | 584 | |
c19e31d0 | 585 | denali_reset_irq(denali); |
26d266e1 | 586 | |
0d3a966d | 587 | iowrite32(DENALI_MAP01 | addr, denali->host + DENALI_HOST_ADDR); |
26d266e1 | 588 | for (i = 0; i < size / 4; i++) |
0d3a966d | 589 | iowrite32(*buf32++, denali->host + DENALI_HOST_DATA); |
26d266e1 MY |
590 | |
591 | irq_status = denali_wait_for_irq(denali, | |
592 | INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL); | |
593 | if (!(irq_status & INTR__PROGRAM_COMP)) | |
594 | return -EIO; | |
595 | ||
596 | return 0; | |
597 | } | |
598 | ||
599 | static int denali_pio_xfer(struct denali_nand_info *denali, void *buf, | |
600 | size_t size, int page, int raw, int write) | |
601 | { | |
602 | if (write) | |
603 | return denali_pio_write(denali, buf, size, page, raw); | |
604 | else | |
605 | return denali_pio_read(denali, buf, size, page, raw); | |
606 | } | |
607 | ||
608 | static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, | |
609 | size_t size, int page, int raw, int write) | |
610 | { | |
997cde2a | 611 | dma_addr_t dma_addr; |
26d266e1 MY |
612 | uint32_t irq_mask, irq_status, ecc_err_mask; |
613 | enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
614 | int ret = 0; | |
615 | ||
997cde2a MY |
616 | dma_addr = dma_map_single(denali->dev, buf, size, dir); |
617 | if (dma_mapping_error(denali->dev, dma_addr)) { | |
618 | dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n"); | |
619 | return denali_pio_xfer(denali, buf, size, page, raw, write); | |
620 | } | |
26d266e1 MY |
621 | |
622 | if (write) { | |
623 | /* | |
624 | * INTR__PROGRAM_COMP is never asserted for the DMA transfer. | |
625 | * We can use INTR__DMA_CMD_COMP instead. This flag is asserted | |
626 | * when the page program is completed. | |
627 | */ | |
628 | irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL; | |
629 | ecc_err_mask = 0; | |
630 | } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) { | |
631 | irq_mask = INTR__DMA_CMD_COMP; | |
632 | ecc_err_mask = INTR__ECC_UNCOR_ERR; | |
633 | } else { | |
634 | irq_mask = INTR__DMA_CMD_COMP; | |
635 | ecc_err_mask = INTR__ECC_ERR; | |
636 | } | |
637 | ||
5bac3acf | 638 | denali_enable_dma(denali, true); |
ce082596 | 639 | |
26d266e1 MY |
640 | denali_reset_irq(denali); |
641 | denali_setup_dma(denali, dma_addr, page, write); | |
ce082596 JR |
642 | |
643 | /* wait for operation to complete */ | |
c19e31d0 | 644 | irq_status = denali_wait_for_irq(denali, irq_mask); |
26d266e1 | 645 | if (!(irq_status & INTR__DMA_CMD_COMP)) |
b21ff825 | 646 | ret = -EIO; |
26d266e1 MY |
647 | else if (irq_status & ecc_err_mask) |
648 | ret = -EBADMSG; | |
ce082596 | 649 | |
5bac3acf | 650 | denali_enable_dma(denali, false); |
997cde2a | 651 | dma_unmap_single(denali->dev, dma_addr, size, dir); |
fdbad98d | 652 | |
57a4d8b5 MY |
653 | if (irq_status & INTR__ERASED_PAGE) |
654 | memset(buf, 0xff, size); | |
655 | ||
b21ff825 | 656 | return ret; |
ce082596 JR |
657 | } |
658 | ||
26d266e1 MY |
659 | static int denali_data_xfer(struct denali_nand_info *denali, void *buf, |
660 | size_t size, int page, int raw, int write) | |
ce082596 | 661 | { |
26d266e1 MY |
662 | setup_ecc_for_xfer(denali, !raw, raw); |
663 | ||
664 | if (denali->dma_avail) | |
665 | return denali_dma_xfer(denali, buf, size, page, raw, write); | |
666 | else | |
667 | return denali_pio_xfer(denali, buf, size, page, raw, write); | |
ce082596 JR |
668 | } |
669 | ||
26d266e1 MY |
670 | static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip, |
671 | int page, int write) | |
ce082596 | 672 | { |
26d266e1 MY |
673 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
674 | unsigned int start_cmd = write ? NAND_CMD_SEQIN : NAND_CMD_READ0; | |
675 | unsigned int rnd_cmd = write ? NAND_CMD_RNDIN : NAND_CMD_RNDOUT; | |
676 | int writesize = mtd->writesize; | |
677 | int oobsize = mtd->oobsize; | |
678 | uint8_t *bufpoi = chip->oob_poi; | |
679 | int ecc_steps = chip->ecc.steps; | |
680 | int ecc_size = chip->ecc.size; | |
681 | int ecc_bytes = chip->ecc.bytes; | |
0d3a966d | 682 | int oob_skip = denali->oob_skip_bytes; |
26d266e1 MY |
683 | size_t size = writesize + oobsize; |
684 | int i, pos, len; | |
685 | ||
686 | /* BBM at the beginning of the OOB area */ | |
687 | chip->cmdfunc(mtd, start_cmd, writesize, page); | |
688 | if (write) | |
689 | chip->write_buf(mtd, bufpoi, oob_skip); | |
690 | else | |
691 | chip->read_buf(mtd, bufpoi, oob_skip); | |
692 | bufpoi += oob_skip; | |
693 | ||
694 | /* OOB ECC */ | |
695 | for (i = 0; i < ecc_steps; i++) { | |
696 | pos = ecc_size + i * (ecc_size + ecc_bytes); | |
697 | len = ecc_bytes; | |
698 | ||
699 | if (pos >= writesize) | |
700 | pos += oob_skip; | |
701 | else if (pos + len > writesize) | |
702 | len = writesize - pos; | |
703 | ||
704 | chip->cmdfunc(mtd, rnd_cmd, pos, -1); | |
705 | if (write) | |
706 | chip->write_buf(mtd, bufpoi, len); | |
707 | else | |
708 | chip->read_buf(mtd, bufpoi, len); | |
709 | bufpoi += len; | |
710 | if (len < ecc_bytes) { | |
711 | len = ecc_bytes - len; | |
712 | chip->cmdfunc(mtd, rnd_cmd, writesize + oob_skip, -1); | |
713 | if (write) | |
714 | chip->write_buf(mtd, bufpoi, len); | |
715 | else | |
716 | chip->read_buf(mtd, bufpoi, len); | |
717 | bufpoi += len; | |
718 | } | |
719 | } | |
720 | ||
721 | /* OOB free */ | |
722 | len = oobsize - (bufpoi - chip->oob_poi); | |
723 | chip->cmdfunc(mtd, rnd_cmd, size - len, -1); | |
724 | if (write) | |
725 | chip->write_buf(mtd, bufpoi, len); | |
726 | else | |
727 | chip->read_buf(mtd, bufpoi, len); | |
ce082596 JR |
728 | } |
729 | ||
26d266e1 MY |
730 | static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
731 | uint8_t *buf, int oob_required, int page) | |
ce082596 | 732 | { |
26d266e1 MY |
733 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
734 | int writesize = mtd->writesize; | |
735 | int oobsize = mtd->oobsize; | |
736 | int ecc_steps = chip->ecc.steps; | |
737 | int ecc_size = chip->ecc.size; | |
738 | int ecc_bytes = chip->ecc.bytes; | |
739 | void *dma_buf = denali->buf; | |
0d3a966d | 740 | int oob_skip = denali->oob_skip_bytes; |
26d266e1 MY |
741 | size_t size = writesize + oobsize; |
742 | int ret, i, pos, len; | |
743 | ||
744 | ret = denali_data_xfer(denali, dma_buf, size, page, 1, 0); | |
745 | if (ret) | |
746 | return ret; | |
747 | ||
748 | /* Arrange the buffer for syndrome payload/ecc layout */ | |
749 | if (buf) { | |
750 | for (i = 0; i < ecc_steps; i++) { | |
751 | pos = i * (ecc_size + ecc_bytes); | |
752 | len = ecc_size; | |
753 | ||
754 | if (pos >= writesize) | |
755 | pos += oob_skip; | |
756 | else if (pos + len > writesize) | |
757 | len = writesize - pos; | |
758 | ||
759 | memcpy(buf, dma_buf + pos, len); | |
760 | buf += len; | |
761 | if (len < ecc_size) { | |
762 | len = ecc_size - len; | |
763 | memcpy(buf, dma_buf + writesize + oob_skip, | |
764 | len); | |
765 | buf += len; | |
766 | } | |
767 | } | |
768 | } | |
769 | ||
770 | if (oob_required) { | |
771 | uint8_t *oob = chip->oob_poi; | |
772 | ||
773 | /* BBM at the beginning of the OOB area */ | |
774 | memcpy(oob, dma_buf + writesize, oob_skip); | |
775 | oob += oob_skip; | |
776 | ||
777 | /* OOB ECC */ | |
778 | for (i = 0; i < ecc_steps; i++) { | |
779 | pos = ecc_size + i * (ecc_size + ecc_bytes); | |
780 | len = ecc_bytes; | |
781 | ||
782 | if (pos >= writesize) | |
783 | pos += oob_skip; | |
784 | else if (pos + len > writesize) | |
785 | len = writesize - pos; | |
786 | ||
787 | memcpy(oob, dma_buf + pos, len); | |
788 | oob += len; | |
789 | if (len < ecc_bytes) { | |
790 | len = ecc_bytes - len; | |
791 | memcpy(oob, dma_buf + writesize + oob_skip, | |
792 | len); | |
793 | oob += len; | |
794 | } | |
795 | } | |
796 | ||
797 | /* OOB free */ | |
798 | len = oobsize - (oob - chip->oob_poi); | |
799 | memcpy(oob, dma_buf + size - len, len); | |
800 | } | |
801 | ||
802 | return 0; | |
ce082596 JR |
803 | } |
804 | ||
5bac3acf | 805 | static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, |
5c2ffb11 | 806 | int page) |
ce082596 | 807 | { |
26d266e1 | 808 | denali_oob_xfer(mtd, chip, page, 0); |
ce082596 | 809 | |
5c2ffb11 | 810 | return 0; |
ce082596 JR |
811 | } |
812 | ||
26d266e1 MY |
813 | static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, |
814 | int page) | |
ce082596 JR |
815 | { |
816 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
26d266e1 | 817 | int status; |
ce082596 | 818 | |
26d266e1 | 819 | denali_reset_irq(denali); |
ce082596 | 820 | |
26d266e1 | 821 | denali_oob_xfer(mtd, chip, page, 1); |
ce082596 | 822 | |
26d266e1 MY |
823 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); |
824 | status = chip->waitfunc(mtd, chip); | |
ce082596 | 825 | |
26d266e1 MY |
826 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
827 | } | |
828 | ||
829 | static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |
830 | uint8_t *buf, int oob_required, int page) | |
831 | { | |
832 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
833 | unsigned long uncor_ecc_flags = 0; | |
834 | int stat = 0; | |
835 | int ret; | |
ce082596 | 836 | |
997cde2a | 837 | ret = denali_data_xfer(denali, buf, mtd->writesize, page, 0, 0); |
26d266e1 MY |
838 | if (ret && ret != -EBADMSG) |
839 | return ret; | |
ce082596 | 840 | |
24715c74 MY |
841 | if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) |
842 | stat = denali_hw_ecc_fixup(mtd, denali, &uncor_ecc_flags); | |
26d266e1 | 843 | else if (ret == -EBADMSG) |
24715c74 | 844 | stat = denali_sw_ecc_fixup(mtd, denali, &uncor_ecc_flags, buf); |
ce082596 | 845 | |
d29109be MY |
846 | if (stat < 0) |
847 | return stat; | |
848 | ||
849 | if (uncor_ecc_flags) { | |
26d266e1 MY |
850 | ret = denali_read_oob(mtd, chip, page); |
851 | if (ret) | |
852 | return ret; | |
ce082596 | 853 | |
d29109be MY |
854 | stat = denali_check_erased_page(mtd, chip, buf, |
855 | uncor_ecc_flags, stat); | |
ce082596 | 856 | } |
d29109be MY |
857 | |
858 | return stat; | |
ce082596 JR |
859 | } |
860 | ||
26d266e1 MY |
861 | static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
862 | const uint8_t *buf, int oob_required, int page) | |
ce082596 JR |
863 | { |
864 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
26d266e1 MY |
865 | int writesize = mtd->writesize; |
866 | int oobsize = mtd->oobsize; | |
867 | int ecc_steps = chip->ecc.steps; | |
868 | int ecc_size = chip->ecc.size; | |
869 | int ecc_bytes = chip->ecc.bytes; | |
870 | void *dma_buf = denali->buf; | |
0d3a966d | 871 | int oob_skip = denali->oob_skip_bytes; |
26d266e1 MY |
872 | size_t size = writesize + oobsize; |
873 | int i, pos, len; | |
ce082596 | 874 | |
26d266e1 MY |
875 | /* |
876 | * Fill the buffer with 0xff first except the full page transfer. | |
877 | * This simplifies the logic. | |
878 | */ | |
879 | if (!buf || !oob_required) | |
880 | memset(dma_buf, 0xff, size); | |
881 | ||
882 | /* Arrange the buffer for syndrome payload/ecc layout */ | |
883 | if (buf) { | |
884 | for (i = 0; i < ecc_steps; i++) { | |
885 | pos = i * (ecc_size + ecc_bytes); | |
886 | len = ecc_size; | |
887 | ||
888 | if (pos >= writesize) | |
889 | pos += oob_skip; | |
890 | else if (pos + len > writesize) | |
891 | len = writesize - pos; | |
892 | ||
893 | memcpy(dma_buf + pos, buf, len); | |
894 | buf += len; | |
895 | if (len < ecc_size) { | |
896 | len = ecc_size - len; | |
897 | memcpy(dma_buf + writesize + oob_skip, buf, | |
898 | len); | |
899 | buf += len; | |
900 | } | |
901 | } | |
902 | } | |
ce082596 | 903 | |
26d266e1 MY |
904 | if (oob_required) { |
905 | const uint8_t *oob = chip->oob_poi; | |
906 | ||
907 | /* BBM at the beginning of the OOB area */ | |
908 | memcpy(dma_buf + writesize, oob, oob_skip); | |
909 | oob += oob_skip; | |
910 | ||
911 | /* OOB ECC */ | |
912 | for (i = 0; i < ecc_steps; i++) { | |
913 | pos = ecc_size + i * (ecc_size + ecc_bytes); | |
914 | len = ecc_bytes; | |
915 | ||
916 | if (pos >= writesize) | |
917 | pos += oob_skip; | |
918 | else if (pos + len > writesize) | |
919 | len = writesize - pos; | |
920 | ||
921 | memcpy(dma_buf + pos, oob, len); | |
922 | oob += len; | |
923 | if (len < ecc_bytes) { | |
924 | len = ecc_bytes - len; | |
925 | memcpy(dma_buf + writesize + oob_skip, oob, | |
926 | len); | |
927 | oob += len; | |
928 | } | |
929 | } | |
ce082596 | 930 | |
26d266e1 MY |
931 | /* OOB free */ |
932 | len = oobsize - (oob - chip->oob_poi); | |
933 | memcpy(dma_buf + size - len, oob, len); | |
934 | } | |
ce082596 | 935 | |
26d266e1 MY |
936 | return denali_data_xfer(denali, dma_buf, size, page, 1, 1); |
937 | } | |
ce082596 | 938 | |
26d266e1 MY |
939 | static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
940 | const uint8_t *buf, int oob_required, int page) | |
941 | { | |
942 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ce082596 | 943 | |
997cde2a MY |
944 | return denali_data_xfer(denali, (void *)buf, mtd->writesize, |
945 | page, 0, 1); | |
ce082596 JR |
946 | } |
947 | ||
ce082596 JR |
948 | static void denali_select_chip(struct mtd_info *mtd, int chip) |
949 | { | |
950 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
7cfffac0 | 951 | |
0d3a966d | 952 | denali->active_bank = chip; |
ce082596 JR |
953 | } |
954 | ||
955 | static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) | |
956 | { | |
fa6134e5 MY |
957 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
958 | uint32_t irq_status; | |
959 | ||
960 | /* R/B# pin transitioned from low to high? */ | |
961 | irq_status = denali_wait_for_irq(denali, INTR__INT_ACT); | |
962 | ||
963 | return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL; | |
ce082596 JR |
964 | } |
965 | ||
49c50b97 | 966 | static int denali_erase(struct mtd_info *mtd, int page) |
ce082596 JR |
967 | { |
968 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
0d3a966d | 969 | uint32_t irq_status; |
ce082596 | 970 | |
c19e31d0 | 971 | denali_reset_irq(denali); |
ce082596 | 972 | |
0d3a966d MY |
973 | denali_host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page, |
974 | DENALI_ERASE); | |
ce082596 JR |
975 | |
976 | /* wait for erase to complete or failure to occur */ | |
c19e31d0 MY |
977 | irq_status = denali_wait_for_irq(denali, |
978 | INTR__ERASE_COMP | INTR__ERASE_FAIL); | |
ce082596 | 979 | |
c19e31d0 | 980 | return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL; |
ce082596 JR |
981 | } |
982 | ||
1bb88666 MY |
983 | static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, |
984 | const struct nand_data_interface *conf) | |
985 | { | |
986 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
987 | const struct nand_sdr_timings *timings; | |
988 | unsigned long t_clk; | |
989 | int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data; | |
990 | int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup; | |
991 | int addr_2_data_mask; | |
992 | uint32_t tmp; | |
993 | ||
994 | timings = nand_get_sdr_timings(conf); | |
995 | if (IS_ERR(timings)) | |
996 | return PTR_ERR(timings); | |
997 | ||
998 | /* clk_x period in picoseconds */ | |
999 | t_clk = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate); | |
1000 | if (!t_clk) | |
1001 | return -EINVAL; | |
1002 | ||
1003 | if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) | |
1004 | return 0; | |
1005 | ||
1006 | /* tREA -> ACC_CLKS */ | |
1007 | acc_clks = DIV_ROUND_UP(timings->tREA_max, t_clk); | |
1008 | acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE); | |
1009 | ||
0d3a966d | 1010 | tmp = ioread32(denali->reg + ACC_CLKS); |
1bb88666 MY |
1011 | tmp &= ~ACC_CLKS__VALUE; |
1012 | tmp |= acc_clks; | |
0d3a966d | 1013 | iowrite32(tmp, denali->reg + ACC_CLKS); |
1bb88666 MY |
1014 | |
1015 | /* tRWH -> RE_2_WE */ | |
1016 | re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_clk); | |
1017 | re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE); | |
1018 | ||
0d3a966d | 1019 | tmp = ioread32(denali->reg + RE_2_WE); |
1bb88666 MY |
1020 | tmp &= ~RE_2_WE__VALUE; |
1021 | tmp |= re_2_we; | |
0d3a966d | 1022 | iowrite32(tmp, denali->reg + RE_2_WE); |
1bb88666 MY |
1023 | |
1024 | /* tRHZ -> RE_2_RE */ | |
1025 | re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_clk); | |
1026 | re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE); | |
1027 | ||
0d3a966d | 1028 | tmp = ioread32(denali->reg + RE_2_RE); |
1bb88666 MY |
1029 | tmp &= ~RE_2_RE__VALUE; |
1030 | tmp |= re_2_re; | |
0d3a966d | 1031 | iowrite32(tmp, denali->reg + RE_2_RE); |
1bb88666 MY |
1032 | |
1033 | /* tWHR -> WE_2_RE */ | |
1034 | we_2_re = DIV_ROUND_UP(timings->tWHR_min, t_clk); | |
1035 | we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE); | |
1036 | ||
0d3a966d | 1037 | tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); |
1bb88666 MY |
1038 | tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE; |
1039 | tmp |= we_2_re; | |
0d3a966d | 1040 | iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE); |
1bb88666 MY |
1041 | |
1042 | /* tADL -> ADDR_2_DATA */ | |
1043 | ||
1044 | /* for older versions, ADDR_2_DATA is only 6 bit wide */ | |
1045 | addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA; | |
1046 | if (denali->revision < 0x0501) | |
1047 | addr_2_data_mask >>= 1; | |
1048 | ||
1049 | addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_clk); | |
1050 | addr_2_data = min_t(int, addr_2_data, addr_2_data_mask); | |
1051 | ||
0d3a966d | 1052 | tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA); |
1bb88666 MY |
1053 | tmp &= ~addr_2_data_mask; |
1054 | tmp |= addr_2_data; | |
0d3a966d | 1055 | iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA); |
1bb88666 MY |
1056 | |
1057 | /* tREH, tWH -> RDWR_EN_HI_CNT */ | |
1058 | rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min), | |
1059 | t_clk); | |
1060 | rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE); | |
1061 | ||
0d3a966d | 1062 | tmp = ioread32(denali->reg + RDWR_EN_HI_CNT); |
1bb88666 MY |
1063 | tmp &= ~RDWR_EN_HI_CNT__VALUE; |
1064 | tmp |= rdwr_en_hi; | |
0d3a966d | 1065 | iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT); |
1bb88666 MY |
1066 | |
1067 | /* tRP, tWP -> RDWR_EN_LO_CNT */ | |
1068 | rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), | |
1069 | t_clk); | |
1070 | rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min), | |
1071 | t_clk); | |
1072 | rdwr_en_lo_hi = max(rdwr_en_lo_hi, DENALI_CLK_X_MULT); | |
1073 | rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi); | |
1074 | rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE); | |
1075 | ||
0d3a966d | 1076 | tmp = ioread32(denali->reg + RDWR_EN_LO_CNT); |
1bb88666 MY |
1077 | tmp &= ~RDWR_EN_LO_CNT__VALUE; |
1078 | tmp |= rdwr_en_lo; | |
0d3a966d | 1079 | iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT); |
1bb88666 MY |
1080 | |
1081 | /* tCS, tCEA -> CS_SETUP_CNT */ | |
1082 | cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_clk) - rdwr_en_lo, | |
1083 | (int)DIV_ROUND_UP(timings->tCEA_max, t_clk) - acc_clks, | |
1084 | 0); | |
1085 | cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE); | |
1086 | ||
0d3a966d | 1087 | tmp = ioread32(denali->reg + CS_SETUP_CNT); |
1bb88666 MY |
1088 | tmp &= ~CS_SETUP_CNT__VALUE; |
1089 | tmp |= cs_setup; | |
0d3a966d | 1090 | iowrite32(tmp, denali->reg + CS_SETUP_CNT); |
1bb88666 MY |
1091 | |
1092 | return 0; | |
1093 | } | |
ce082596 | 1094 | |
f486287d MY |
1095 | static void denali_reset_banks(struct denali_nand_info *denali) |
1096 | { | |
d49f5790 | 1097 | u32 irq_status; |
f486287d MY |
1098 | int i; |
1099 | ||
f486287d | 1100 | for (i = 0; i < denali->max_banks; i++) { |
0d3a966d | 1101 | denali->active_bank = i; |
d49f5790 MY |
1102 | |
1103 | denali_reset_irq(denali); | |
1104 | ||
1105 | iowrite32(DEVICE_RESET__BANK(i), | |
0d3a966d | 1106 | denali->reg + DEVICE_RESET); |
d49f5790 MY |
1107 | |
1108 | irq_status = denali_wait_for_irq(denali, | |
1109 | INTR__RST_COMP | INTR__INT_ACT | INTR__TIME_OUT); | |
1110 | if (!(irq_status & INTR__INT_ACT)) | |
f486287d MY |
1111 | break; |
1112 | } | |
1113 | ||
1114 | dev_dbg(denali->dev, "%d chips connected\n", i); | |
1115 | denali->max_banks = i; | |
f486287d MY |
1116 | } |
1117 | ||
ce082596 JR |
1118 | static void denali_hw_init(struct denali_nand_info *denali) |
1119 | { | |
e7beeeec MY |
1120 | /* |
1121 | * The REVISION register may not be reliable. Platforms are allowed to | |
1122 | * override it. | |
1123 | */ | |
1124 | if (!denali->revision) | |
0d3a966d | 1125 | denali->revision = swab16(ioread32(denali->reg + REVISION)); |
e7beeeec | 1126 | |
43914a2d MY |
1127 | /* |
1128 | * tell driver how many bit controller will skip before | |
db9a3210 CD |
1129 | * writing ECC code in OOB, this register may be already |
1130 | * set by firmware. So we read this value out. | |
1131 | * if this value is 0, just let it be. | |
43914a2d | 1132 | */ |
0d3a966d | 1133 | denali->oob_skip_bytes = ioread32(denali->reg + SPARE_AREA_SKIP_BYTES); |
bc27ede3 | 1134 | detect_max_banks(denali); |
0d3a966d MY |
1135 | iowrite32(0x0F, denali->reg + RB_PIN_ENABLED); |
1136 | iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE); | |
ce082596 | 1137 | |
0d3a966d | 1138 | iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER); |
ce082596 JR |
1139 | |
1140 | /* Should set value for these registers when init */ | |
0d3a966d MY |
1141 | iowrite32(0, denali->reg + TWO_ROW_ADDR_CYCLES); |
1142 | iowrite32(1, denali->reg + ECC_ENABLE); | |
ce082596 JR |
1143 | } |
1144 | ||
7de117fd MY |
1145 | int denali_calc_ecc_bytes(int step_size, int strength) |
1146 | { | |
1147 | /* BCH code. Denali requires ecc.bytes to be multiple of 2 */ | |
1148 | return DIV_ROUND_UP(strength * fls(step_size * 8), 16) * 2; | |
1149 | } | |
1150 | EXPORT_SYMBOL(denali_calc_ecc_bytes); | |
1151 | ||
1152 | static int denali_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip, | |
1153 | struct denali_nand_info *denali) | |
1154 | { | |
0d3a966d | 1155 | int oobavail = mtd->oobsize - denali->oob_skip_bytes; |
7de117fd MY |
1156 | int ret; |
1157 | ||
1158 | /* | |
1159 | * If .size and .strength are already set (usually by DT), | |
1160 | * check if they are supported by this controller. | |
1161 | */ | |
1162 | if (chip->ecc.size && chip->ecc.strength) | |
1163 | return nand_check_ecc_caps(chip, denali->ecc_caps, oobavail); | |
1164 | ||
1165 | /* | |
1166 | * We want .size and .strength closest to the chip's requirement | |
1167 | * unless NAND_ECC_MAXIMIZE is requested. | |
1168 | */ | |
1169 | if (!(chip->ecc.options & NAND_ECC_MAXIMIZE)) { | |
1170 | ret = nand_match_ecc_req(chip, denali->ecc_caps, oobavail); | |
1171 | if (!ret) | |
1172 | return 0; | |
1173 | } | |
1174 | ||
1175 | /* Max ECC strength is the last thing we can do */ | |
1176 | return nand_maximize_ecc(chip, denali->ecc_caps, oobavail); | |
1177 | } | |
14fad62b BB |
1178 | |
1179 | static int denali_ooblayout_ecc(struct mtd_info *mtd, int section, | |
1180 | struct mtd_oob_region *oobregion) | |
1181 | { | |
1182 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1183 | struct nand_chip *chip = mtd_to_nand(mtd); | |
1184 | ||
1185 | if (section) | |
1186 | return -ERANGE; | |
1187 | ||
0d3a966d | 1188 | oobregion->offset = denali->oob_skip_bytes; |
14fad62b BB |
1189 | oobregion->length = chip->ecc.total; |
1190 | ||
1191 | return 0; | |
1192 | } | |
1193 | ||
1194 | static int denali_ooblayout_free(struct mtd_info *mtd, int section, | |
1195 | struct mtd_oob_region *oobregion) | |
1196 | { | |
1197 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1198 | struct nand_chip *chip = mtd_to_nand(mtd); | |
1199 | ||
1200 | if (section) | |
1201 | return -ERANGE; | |
1202 | ||
0d3a966d | 1203 | oobregion->offset = chip->ecc.total + denali->oob_skip_bytes; |
14fad62b BB |
1204 | oobregion->length = mtd->oobsize - oobregion->offset; |
1205 | ||
1206 | return 0; | |
1207 | } | |
1208 | ||
1209 | static const struct mtd_ooblayout_ops denali_ooblayout_ops = { | |
1210 | .ecc = denali_ooblayout_ecc, | |
1211 | .free = denali_ooblayout_free, | |
ce082596 JR |
1212 | }; |
1213 | ||
421f91d2 | 1214 | /* initialize driver data structures */ |
8c519436 | 1215 | static void denali_drv_init(struct denali_nand_info *denali) |
ce082596 | 1216 | { |
43914a2d MY |
1217 | /* |
1218 | * the completion object will be used to notify | |
1219 | * the callee that the interrupt is done | |
1220 | */ | |
ce082596 JR |
1221 | init_completion(&denali->complete); |
1222 | ||
43914a2d MY |
1223 | /* |
1224 | * the spinlock will be used to synchronize the ISR with any | |
1225 | * element that might be access shared data (interrupt status) | |
1226 | */ | |
ce082596 | 1227 | spin_lock_init(&denali->irq_lock); |
ce082596 JR |
1228 | } |
1229 | ||
e93c1640 | 1230 | static int denali_multidev_fixup(struct denali_nand_info *denali) |
6da27b46 MY |
1231 | { |
1232 | struct nand_chip *chip = &denali->nand; | |
1233 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1234 | ||
1235 | /* | |
1236 | * Support for multi device: | |
1237 | * When the IP configuration is x16 capable and two x8 chips are | |
1238 | * connected in parallel, DEVICES_CONNECTED should be set to 2. | |
1239 | * In this case, the core framework knows nothing about this fact, | |
1240 | * so we should tell it the _logical_ pagesize and anything necessary. | |
1241 | */ | |
0d3a966d | 1242 | denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED); |
6da27b46 | 1243 | |
cc5d8031 MY |
1244 | /* |
1245 | * On some SoCs, DEVICES_CONNECTED is not auto-detected. | |
1246 | * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case. | |
1247 | */ | |
0d3a966d MY |
1248 | if (denali->devs_per_cs == 0) { |
1249 | denali->devs_per_cs = 1; | |
1250 | iowrite32(1, denali->reg + DEVICES_CONNECTED); | |
cc5d8031 MY |
1251 | } |
1252 | ||
0d3a966d | 1253 | if (denali->devs_per_cs == 1) |
e93c1640 MY |
1254 | return 0; |
1255 | ||
0d3a966d | 1256 | if (denali->devs_per_cs != 2) { |
e93c1640 | 1257 | dev_err(denali->dev, "unsupported number of devices %d\n", |
0d3a966d | 1258 | denali->devs_per_cs); |
e93c1640 MY |
1259 | return -EINVAL; |
1260 | } | |
1261 | ||
1262 | /* 2 chips in parallel */ | |
1263 | mtd->size <<= 1; | |
1264 | mtd->erasesize <<= 1; | |
1265 | mtd->writesize <<= 1; | |
1266 | mtd->oobsize <<= 1; | |
1267 | chip->chipsize <<= 1; | |
1268 | chip->page_shift += 1; | |
1269 | chip->phys_erase_shift += 1; | |
1270 | chip->bbt_erase_shift += 1; | |
1271 | chip->chip_shift += 1; | |
1272 | chip->pagemask <<= 1; | |
1273 | chip->ecc.size <<= 1; | |
1274 | chip->ecc.bytes <<= 1; | |
1275 | chip->ecc.strength <<= 1; | |
0d3a966d | 1276 | denali->oob_skip_bytes <<= 1; |
e93c1640 MY |
1277 | |
1278 | return 0; | |
6da27b46 MY |
1279 | } |
1280 | ||
2a0a288e | 1281 | int denali_init(struct denali_nand_info *denali) |
ce082596 | 1282 | { |
1394a726 MY |
1283 | struct nand_chip *chip = &denali->nand; |
1284 | struct mtd_info *mtd = nand_to_mtd(chip); | |
2a0a288e | 1285 | int ret; |
ce082596 | 1286 | |
442f201b | 1287 | mtd->dev.parent = denali->dev; |
ce082596 JR |
1288 | denali_hw_init(denali); |
1289 | denali_drv_init(denali); | |
1290 | ||
c19e31d0 MY |
1291 | denali_clear_irq_all(denali); |
1292 | ||
7ebb8d06 MY |
1293 | /* Request IRQ after all the hardware initialization is finished */ |
1294 | ret = devm_request_irq(denali->dev, denali->irq, denali_isr, | |
1295 | IRQF_SHARED, DENALI_NAND_NAME, denali); | |
1296 | if (ret) { | |
789ccf17 | 1297 | dev_err(denali->dev, "Unable to request IRQ\n"); |
7ebb8d06 | 1298 | return ret; |
ce082596 JR |
1299 | } |
1300 | ||
c19e31d0 | 1301 | denali_enable_irq(denali); |
d49f5790 MY |
1302 | denali_reset_banks(denali); |
1303 | ||
0d3a966d | 1304 | denali->active_bank = DENALI_INVALID_BANK; |
c19e31d0 | 1305 | |
63757d46 | 1306 | nand_set_flash_node(chip, denali->dev->of_node); |
8aabdf37 MY |
1307 | /* Fallback to the default name if DT did not give "label" property */ |
1308 | if (!mtd->name) | |
1309 | mtd->name = "denali-nand"; | |
ce082596 JR |
1310 | |
1311 | /* register the driver with the NAND core subsystem */ | |
1394a726 | 1312 | chip->select_chip = denali_select_chip; |
1394a726 | 1313 | chip->read_byte = denali_read_byte; |
fa6134e5 MY |
1314 | chip->write_byte = denali_write_byte; |
1315 | chip->read_word = denali_read_word; | |
1316 | chip->cmd_ctrl = denali_cmd_ctrl; | |
1317 | chip->dev_ready = denali_dev_ready; | |
1394a726 | 1318 | chip->waitfunc = denali_waitfunc; |
ce082596 | 1319 | |
1bb88666 MY |
1320 | /* clk rate info is needed for setup_data_interface */ |
1321 | if (denali->clk_x_rate) | |
1322 | chip->setup_data_interface = denali_setup_data_interface; | |
1323 | ||
43914a2d MY |
1324 | /* |
1325 | * scan for NAND devices attached to the controller | |
ce082596 | 1326 | * this is the first stage in a two step process to register |
43914a2d MY |
1327 | * with the nand subsystem |
1328 | */ | |
a227d4e4 MY |
1329 | ret = nand_scan_ident(mtd, denali->max_banks, NULL); |
1330 | if (ret) | |
c19e31d0 | 1331 | goto disable_irq; |
5bac3acf | 1332 | |
0d3a966d | 1333 | if (ioread32(denali->reg + FEATURES) & FEATURES__DMA) |
26d266e1 MY |
1334 | denali->dma_avail = 1; |
1335 | ||
1336 | if (denali->dma_avail) { | |
1337 | int dma_bit = denali->caps & DENALI_CAP_DMA_64BIT ? 64 : 32; | |
1338 | ||
1339 | ret = dma_set_mask(denali->dev, DMA_BIT_MASK(dma_bit)); | |
1340 | if (ret) { | |
1341 | dev_info(denali->dev, | |
1342 | "Failed to set DMA mask. Disabling DMA.\n"); | |
1343 | denali->dma_avail = 0; | |
1344 | } | |
e07caa36 HS |
1345 | } |
1346 | ||
26d266e1 | 1347 | if (denali->dma_avail) { |
997cde2a MY |
1348 | chip->options |= NAND_USE_BOUNCE_BUFFER; |
1349 | chip->buf_align = 16; | |
66406524 CD |
1350 | } |
1351 | ||
43914a2d MY |
1352 | /* |
1353 | * second stage of the NAND scan | |
5bac3acf | 1354 | * this stage requires information regarding ECC and |
43914a2d MY |
1355 | * bad block management. |
1356 | */ | |
ce082596 | 1357 | |
1394a726 | 1358 | chip->bbt_options |= NAND_BBT_USE_FLASH; |
777f2d49 MY |
1359 | chip->bbt_options |= NAND_BBT_NO_OOB; |
1360 | ||
1394a726 | 1361 | chip->ecc.mode = NAND_ECC_HW_SYNDROME; |
ce082596 | 1362 | |
d99d7282 | 1363 | /* no subpage writes on denali */ |
1394a726 | 1364 | chip->options |= NAND_NO_SUBPAGE_WRITE; |
d99d7282 | 1365 | |
7de117fd MY |
1366 | ret = denali_ecc_setup(mtd, chip, denali); |
1367 | if (ret) { | |
1368 | dev_err(denali->dev, "Failed to setup ECC settings.\n"); | |
c19e31d0 | 1369 | goto disable_irq; |
ce082596 JR |
1370 | } |
1371 | ||
7de117fd MY |
1372 | dev_dbg(denali->dev, |
1373 | "chosen ECC settings: step=%d, strength=%d, bytes=%d\n", | |
1374 | chip->ecc.size, chip->ecc.strength, chip->ecc.bytes); | |
1375 | ||
57a4d8b5 | 1376 | iowrite32(MAKE_ECC_CORRECTION(chip->ecc.strength, 1), |
0d3a966d | 1377 | denali->reg + ECC_CORRECTION); |
0615e7ad | 1378 | iowrite32(mtd->erasesize / mtd->writesize, |
0d3a966d | 1379 | denali->reg + PAGES_PER_BLOCK); |
0615e7ad | 1380 | iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0, |
0d3a966d MY |
1381 | denali->reg + DEVICE_WIDTH); |
1382 | iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE); | |
1383 | iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE); | |
7de117fd | 1384 | |
0d3a966d MY |
1385 | iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE); |
1386 | iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE); | |
7de117fd MY |
1387 | /* chip->ecc.steps is set by nand_scan_tail(); not available here */ |
1388 | iowrite32(mtd->writesize / chip->ecc.size, | |
0d3a966d | 1389 | denali->reg + CFG_NUM_DATA_BLOCKS); |
7de117fd | 1390 | |
14fad62b | 1391 | mtd_set_ooblayout(mtd, &denali_ooblayout_ops); |
db9a3210 | 1392 | |
fa6134e5 MY |
1393 | if (chip->options & NAND_BUSWIDTH_16) { |
1394 | chip->read_buf = denali_read_buf16; | |
1395 | chip->write_buf = denali_write_buf16; | |
1396 | } else { | |
1397 | chip->read_buf = denali_read_buf; | |
1398 | chip->write_buf = denali_write_buf; | |
1399 | } | |
b21ff825 | 1400 | chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS; |
1394a726 MY |
1401 | chip->ecc.read_page = denali_read_page; |
1402 | chip->ecc.read_page_raw = denali_read_page_raw; | |
1403 | chip->ecc.write_page = denali_write_page; | |
1404 | chip->ecc.write_page_raw = denali_write_page_raw; | |
1405 | chip->ecc.read_oob = denali_read_oob; | |
1406 | chip->ecc.write_oob = denali_write_oob; | |
1407 | chip->erase = denali_erase; | |
ce082596 | 1408 | |
e93c1640 MY |
1409 | ret = denali_multidev_fixup(denali); |
1410 | if (ret) | |
c19e31d0 | 1411 | goto disable_irq; |
6da27b46 | 1412 | |
7d370b2c MY |
1413 | /* |
1414 | * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not | |
1415 | * use devm_kmalloc() because the memory allocated by devm_ does not | |
1416 | * guarantee DMA-safe alignment. | |
1417 | */ | |
1418 | denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL); | |
1419 | if (!denali->buf) { | |
1420 | ret = -ENOMEM; | |
1421 | goto disable_irq; | |
1422 | } | |
1423 | ||
a227d4e4 MY |
1424 | ret = nand_scan_tail(mtd); |
1425 | if (ret) | |
7d370b2c | 1426 | goto free_buf; |
ce082596 | 1427 | |
442f201b | 1428 | ret = mtd_device_register(mtd, NULL, 0); |
ce082596 | 1429 | if (ret) { |
789ccf17 | 1430 | dev_err(denali->dev, "Failed to register MTD: %d\n", ret); |
7d370b2c | 1431 | goto free_buf; |
ce082596 JR |
1432 | } |
1433 | return 0; | |
1434 | ||
7d370b2c MY |
1435 | free_buf: |
1436 | kfree(denali->buf); | |
c19e31d0 MY |
1437 | disable_irq: |
1438 | denali_disable_irq(denali); | |
2a0a288e | 1439 | |
ce082596 JR |
1440 | return ret; |
1441 | } | |
2a0a288e | 1442 | EXPORT_SYMBOL(denali_init); |
ce082596 JR |
1443 | |
1444 | /* driver exit point */ | |
2a0a288e | 1445 | void denali_remove(struct denali_nand_info *denali) |
ce082596 | 1446 | { |
442f201b | 1447 | struct mtd_info *mtd = nand_to_mtd(&denali->nand); |
320092a0 | 1448 | |
442f201b | 1449 | nand_release(mtd); |
7d370b2c | 1450 | kfree(denali->buf); |
c19e31d0 | 1451 | denali_disable_irq(denali); |
ce082596 | 1452 | } |
2a0a288e | 1453 | EXPORT_SYMBOL(denali_remove); |