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Commit | Line | Data |
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ce082596 JR |
1 | /* |
2 | * NAND Flash Controller Device Driver | |
3 | * Copyright © 2009-2010, Intel Corporation and its suppliers. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | */ | |
ce082596 JR |
19 | #include <linux/interrupt.h> |
20 | #include <linux/delay.h> | |
84457949 | 21 | #include <linux/dma-mapping.h> |
ce082596 JR |
22 | #include <linux/wait.h> |
23 | #include <linux/mutex.h> | |
ce082596 JR |
24 | #include <linux/mtd/mtd.h> |
25 | #include <linux/module.h> | |
26 | ||
27 | #include "denali.h" | |
28 | ||
29 | MODULE_LICENSE("GPL"); | |
30 | ||
43914a2d MY |
31 | /* |
32 | * We define a module parameter that allows the user to override | |
ce082596 JR |
33 | * the hardware and decide what timing mode should be used. |
34 | */ | |
35 | #define NAND_DEFAULT_TIMINGS -1 | |
36 | ||
37 | static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; | |
38 | module_param(onfi_timing_mode, int, S_IRUGO); | |
8125450c MY |
39 | MODULE_PARM_DESC(onfi_timing_mode, |
40 | "Overrides default ONFI setting. -1 indicates use default timings"); | |
ce082596 JR |
41 | |
42 | #define DENALI_NAND_NAME "denali-nand" | |
43 | ||
43914a2d MY |
44 | /* |
45 | * We define a macro here that combines all interrupts this driver uses into | |
46 | * a single constant value, for convenience. | |
47 | */ | |
9589bf5b JI |
48 | #define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \ |
49 | INTR_STATUS__ECC_TRANSACTION_DONE | \ | |
50 | INTR_STATUS__ECC_ERR | \ | |
51 | INTR_STATUS__PROGRAM_FAIL | \ | |
52 | INTR_STATUS__LOAD_COMP | \ | |
53 | INTR_STATUS__PROGRAM_COMP | \ | |
54 | INTR_STATUS__TIME_OUT | \ | |
55 | INTR_STATUS__ERASE_FAIL | \ | |
56 | INTR_STATUS__RST_COMP | \ | |
57 | INTR_STATUS__ERASE_COMP) | |
ce082596 | 58 | |
43914a2d MY |
59 | /* |
60 | * indicates whether or not the internal value for the flash bank is | |
61 | * valid or not | |
62 | */ | |
5bac3acf | 63 | #define CHIP_SELECT_INVALID -1 |
ce082596 JR |
64 | |
65 | #define SUPPORT_8BITECC 1 | |
66 | ||
43914a2d MY |
67 | /* |
68 | * This macro divides two integers and rounds fractional values up | |
69 | * to the nearest integer value. | |
70 | */ | |
ce082596 JR |
71 | #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y))) |
72 | ||
43914a2d MY |
73 | /* |
74 | * this macro allows us to convert from an MTD structure to our own | |
ce082596 JR |
75 | * device context (denali) structure. |
76 | */ | |
442f201b BB |
77 | static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) |
78 | { | |
79 | return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); | |
80 | } | |
ce082596 | 81 | |
43914a2d MY |
82 | /* |
83 | * These constants are defined by the driver to enable common driver | |
84 | * configuration options. | |
85 | */ | |
ce082596 JR |
86 | #define SPARE_ACCESS 0x41 |
87 | #define MAIN_ACCESS 0x42 | |
88 | #define MAIN_SPARE_ACCESS 0x43 | |
2902330e | 89 | #define PIPELINE_ACCESS 0x2000 |
ce082596 JR |
90 | |
91 | #define DENALI_READ 0 | |
92 | #define DENALI_WRITE 0x100 | |
93 | ||
43914a2d MY |
94 | /* |
95 | * this is a helper macro that allows us to | |
96 | * format the bank into the proper bits for the controller | |
97 | */ | |
ce082596 JR |
98 | #define BANK(x) ((x) << 24) |
99 | ||
ce082596 JR |
100 | /* forward declarations */ |
101 | static void clear_interrupts(struct denali_nand_info *denali); | |
bdca6dae CD |
102 | static uint32_t wait_for_irq(struct denali_nand_info *denali, |
103 | uint32_t irq_mask); | |
104 | static void denali_irq_enable(struct denali_nand_info *denali, | |
105 | uint32_t int_mask); | |
ce082596 JR |
106 | static uint32_t read_interrupt_status(struct denali_nand_info *denali); |
107 | ||
43914a2d MY |
108 | /* |
109 | * Certain operations for the denali NAND controller use an indexed mode to | |
110 | * read/write data. The operation is performed by writing the address value | |
111 | * of the command to the device memory followed by the data. This function | |
bdca6dae | 112 | * abstracts this common operation. |
43914a2d | 113 | */ |
bdca6dae CD |
114 | static void index_addr(struct denali_nand_info *denali, |
115 | uint32_t address, uint32_t data) | |
ce082596 | 116 | { |
24c3fa36 CD |
117 | iowrite32(address, denali->flash_mem); |
118 | iowrite32(data, denali->flash_mem + 0x10); | |
ce082596 JR |
119 | } |
120 | ||
121 | /* Perform an indexed read of the device */ | |
122 | static void index_addr_read_data(struct denali_nand_info *denali, | |
123 | uint32_t address, uint32_t *pdata) | |
124 | { | |
24c3fa36 | 125 | iowrite32(address, denali->flash_mem); |
ce082596 JR |
126 | *pdata = ioread32(denali->flash_mem + 0x10); |
127 | } | |
128 | ||
43914a2d MY |
129 | /* |
130 | * We need to buffer some data for some of the NAND core routines. | |
131 | * The operations manage buffering that data. | |
132 | */ | |
ce082596 JR |
133 | static void reset_buf(struct denali_nand_info *denali) |
134 | { | |
135 | denali->buf.head = denali->buf.tail = 0; | |
136 | } | |
137 | ||
138 | static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte) | |
139 | { | |
ce082596 JR |
140 | denali->buf.buf[denali->buf.tail++] = byte; |
141 | } | |
142 | ||
143 | /* reads the status of the device */ | |
144 | static void read_status(struct denali_nand_info *denali) | |
145 | { | |
5637b69d | 146 | uint32_t cmd; |
ce082596 JR |
147 | |
148 | /* initialize the data buffer to store status */ | |
149 | reset_buf(denali); | |
150 | ||
f0bc0c77 CD |
151 | cmd = ioread32(denali->flash_reg + WRITE_PROTECT); |
152 | if (cmd) | |
153 | write_byte_to_buf(denali, NAND_STATUS_WP); | |
154 | else | |
155 | write_byte_to_buf(denali, 0); | |
ce082596 JR |
156 | } |
157 | ||
158 | /* resets a specific device connected to the core */ | |
159 | static void reset_bank(struct denali_nand_info *denali) | |
160 | { | |
5637b69d | 161 | uint32_t irq_status; |
8125450c | 162 | uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT; |
ce082596 JR |
163 | |
164 | clear_interrupts(denali); | |
165 | ||
9589bf5b | 166 | iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET); |
ce082596 JR |
167 | |
168 | irq_status = wait_for_irq(denali, irq_mask); | |
5bac3acf | 169 | |
9589bf5b | 170 | if (irq_status & INTR_STATUS__TIME_OUT) |
84457949 | 171 | dev_err(denali->dev, "reset bank failed.\n"); |
ce082596 JR |
172 | } |
173 | ||
174 | /* Reset the flash controller */ | |
eda936ef | 175 | static uint16_t denali_nand_reset(struct denali_nand_info *denali) |
ce082596 | 176 | { |
93e3c8ad | 177 | int i; |
ce082596 | 178 | |
8125450c | 179 | for (i = 0; i < denali->max_banks; i++) |
9589bf5b JI |
180 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
181 | denali->flash_reg + INTR_STATUS(i)); | |
ce082596 | 182 | |
8125450c | 183 | for (i = 0; i < denali->max_banks; i++) { |
9589bf5b | 184 | iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); |
8125450c | 185 | while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & |
9589bf5b | 186 | (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT))) |
628bfd41 | 187 | cpu_relax(); |
9589bf5b JI |
188 | if (ioread32(denali->flash_reg + INTR_STATUS(i)) & |
189 | INTR_STATUS__TIME_OUT) | |
84457949 | 190 | dev_dbg(denali->dev, |
ce082596 JR |
191 | "NAND Reset operation timed out on bank %d\n", i); |
192 | } | |
193 | ||
c89eeda8 | 194 | for (i = 0; i < denali->max_banks; i++) |
9589bf5b | 195 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
8125450c | 196 | denali->flash_reg + INTR_STATUS(i)); |
ce082596 JR |
197 | |
198 | return PASS; | |
199 | } | |
200 | ||
43914a2d MY |
201 | /* |
202 | * this routine calculates the ONFI timing values for a given mode and | |
bdca6dae CD |
203 | * programs the clocking register accordingly. The mode is determined by |
204 | * the get_onfi_nand_para routine. | |
ce082596 | 205 | */ |
eda936ef | 206 | static void nand_onfi_timing_set(struct denali_nand_info *denali, |
bdca6dae | 207 | uint16_t mode) |
ce082596 JR |
208 | { |
209 | uint16_t Trea[6] = {40, 30, 25, 20, 20, 16}; | |
210 | uint16_t Trp[6] = {50, 25, 17, 15, 12, 10}; | |
211 | uint16_t Treh[6] = {30, 15, 15, 10, 10, 7}; | |
212 | uint16_t Trc[6] = {100, 50, 35, 30, 25, 20}; | |
213 | uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15}; | |
214 | uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5}; | |
215 | uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25}; | |
216 | uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70}; | |
217 | uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100}; | |
218 | uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100}; | |
219 | uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60}; | |
220 | uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15}; | |
221 | ||
ce082596 JR |
222 | uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid; |
223 | uint16_t dv_window = 0; | |
224 | uint16_t en_lo, en_hi; | |
225 | uint16_t acc_clks; | |
226 | uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; | |
227 | ||
ce082596 JR |
228 | en_lo = CEIL_DIV(Trp[mode], CLK_X); |
229 | en_hi = CEIL_DIV(Treh[mode], CLK_X); | |
230 | #if ONFI_BLOOM_TIME | |
231 | if ((en_hi * CLK_X) < (Treh[mode] + 2)) | |
232 | en_hi++; | |
233 | #endif | |
234 | ||
235 | if ((en_lo + en_hi) * CLK_X < Trc[mode]) | |
236 | en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X); | |
237 | ||
238 | if ((en_lo + en_hi) < CLK_MULTI) | |
239 | en_lo += CLK_MULTI - en_lo - en_hi; | |
240 | ||
241 | while (dv_window < 8) { | |
242 | data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode]; | |
243 | ||
244 | data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode]; | |
245 | ||
8125450c MY |
246 | data_invalid = data_invalid_rhoh < data_invalid_rloh ? |
247 | data_invalid_rhoh : data_invalid_rloh; | |
ce082596 JR |
248 | |
249 | dv_window = data_invalid - Trea[mode]; | |
250 | ||
251 | if (dv_window < 8) | |
252 | en_lo++; | |
253 | } | |
254 | ||
255 | acc_clks = CEIL_DIV(Trea[mode], CLK_X); | |
256 | ||
7d14ecd0 | 257 | while (acc_clks * CLK_X - Trea[mode] < 3) |
ce082596 JR |
258 | acc_clks++; |
259 | ||
7d14ecd0 | 260 | if (data_invalid - acc_clks * CLK_X < 2) |
84457949 | 261 | dev_warn(denali->dev, "%s, Line %d: Warning!\n", |
8125450c | 262 | __FILE__, __LINE__); |
ce082596 JR |
263 | |
264 | addr_2_data = CEIL_DIV(Tadl[mode], CLK_X); | |
265 | re_2_we = CEIL_DIV(Trhw[mode], CLK_X); | |
266 | re_2_re = CEIL_DIV(Trhz[mode], CLK_X); | |
267 | we_2_re = CEIL_DIV(Twhr[mode], CLK_X); | |
268 | cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X); | |
ce082596 JR |
269 | if (cs_cnt == 0) |
270 | cs_cnt = 1; | |
271 | ||
272 | if (Tcea[mode]) { | |
7d14ecd0 | 273 | while (cs_cnt * CLK_X + Trea[mode] < Tcea[mode]) |
ce082596 JR |
274 | cs_cnt++; |
275 | } | |
276 | ||
277 | #if MODE5_WORKAROUND | |
278 | if (mode == 5) | |
279 | acc_clks = 5; | |
280 | #endif | |
281 | ||
282 | /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */ | |
7d14ecd0 MY |
283 | if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 && |
284 | ioread32(denali->flash_reg + DEVICE_ID) == 0x88) | |
ce082596 JR |
285 | acc_clks = 6; |
286 | ||
24c3fa36 CD |
287 | iowrite32(acc_clks, denali->flash_reg + ACC_CLKS); |
288 | iowrite32(re_2_we, denali->flash_reg + RE_2_WE); | |
289 | iowrite32(re_2_re, denali->flash_reg + RE_2_RE); | |
290 | iowrite32(we_2_re, denali->flash_reg + WE_2_RE); | |
291 | iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA); | |
292 | iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT); | |
293 | iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT); | |
294 | iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT); | |
ce082596 JR |
295 | } |
296 | ||
ce082596 JR |
297 | /* queries the NAND device to see what ONFI modes it supports. */ |
298 | static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) | |
299 | { | |
300 | int i; | |
43914a2d MY |
301 | |
302 | /* | |
303 | * we needn't to do a reset here because driver has already | |
4c03bbdf | 304 | * reset all the banks before |
43914a2d | 305 | */ |
ce082596 JR |
306 | if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
307 | ONFI_TIMING_MODE__VALUE)) | |
308 | return FAIL; | |
309 | ||
310 | for (i = 5; i > 0; i--) { | |
bdca6dae CD |
311 | if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
312 | (0x01 << i)) | |
ce082596 JR |
313 | break; |
314 | } | |
315 | ||
eda936ef | 316 | nand_onfi_timing_set(denali, i); |
ce082596 | 317 | |
43914a2d MY |
318 | /* |
319 | * By now, all the ONFI devices we know support the page cache | |
320 | * rw feature. So here we enable the pipeline_rw_ahead feature | |
321 | */ | |
ce082596 JR |
322 | /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */ |
323 | /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */ | |
324 | ||
325 | return PASS; | |
326 | } | |
327 | ||
4c03bbdf CD |
328 | static void get_samsung_nand_para(struct denali_nand_info *denali, |
329 | uint8_t device_id) | |
ce082596 | 330 | { |
4c03bbdf | 331 | if (device_id == 0xd3) { /* Samsung K9WAG08U1A */ |
ce082596 | 332 | /* Set timing register values according to datasheet */ |
24c3fa36 CD |
333 | iowrite32(5, denali->flash_reg + ACC_CLKS); |
334 | iowrite32(20, denali->flash_reg + RE_2_WE); | |
335 | iowrite32(12, denali->flash_reg + WE_2_RE); | |
336 | iowrite32(14, denali->flash_reg + ADDR_2_DATA); | |
337 | iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT); | |
338 | iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT); | |
339 | iowrite32(2, denali->flash_reg + CS_SETUP_CNT); | |
ce082596 | 340 | } |
ce082596 JR |
341 | } |
342 | ||
343 | static void get_toshiba_nand_para(struct denali_nand_info *denali) | |
344 | { | |
ce082596 JR |
345 | uint32_t tmp; |
346 | ||
43914a2d MY |
347 | /* |
348 | * Workaround to fix a controller bug which reports a wrong | |
349 | * spare area size for some kind of Toshiba NAND device | |
350 | */ | |
ce082596 JR |
351 | if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && |
352 | (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { | |
24c3fa36 | 353 | iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); |
ce082596 JR |
354 | tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) * |
355 | ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
24c3fa36 | 356 | iowrite32(tmp, |
bdca6dae | 357 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
ce082596 | 358 | #if SUPPORT_15BITECC |
24c3fa36 | 359 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 360 | #elif SUPPORT_8BITECC |
24c3fa36 | 361 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 JR |
362 | #endif |
363 | } | |
ce082596 JR |
364 | } |
365 | ||
ef41e1bb CD |
366 | static void get_hynix_nand_para(struct denali_nand_info *denali, |
367 | uint8_t device_id) | |
ce082596 | 368 | { |
ce082596 JR |
369 | uint32_t main_size, spare_size; |
370 | ||
ef41e1bb | 371 | switch (device_id) { |
ce082596 JR |
372 | case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */ |
373 | case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */ | |
24c3fa36 CD |
374 | iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK); |
375 | iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); | |
376 | iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
bdca6dae CD |
377 | main_size = 4096 * |
378 | ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
379 | spare_size = 224 * | |
380 | ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
24c3fa36 | 381 | iowrite32(main_size, |
bdca6dae | 382 | denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); |
24c3fa36 | 383 | iowrite32(spare_size, |
bdca6dae | 384 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
24c3fa36 | 385 | iowrite32(0, denali->flash_reg + DEVICE_WIDTH); |
ce082596 | 386 | #if SUPPORT_15BITECC |
24c3fa36 | 387 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 388 | #elif SUPPORT_8BITECC |
24c3fa36 | 389 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 390 | #endif |
ce082596 JR |
391 | break; |
392 | default: | |
84457949 | 393 | dev_warn(denali->dev, |
789ccf17 | 394 | "Unknown Hynix NAND (Device ID: 0x%x).\n" |
8125450c MY |
395 | "Will use default parameter values instead.\n", |
396 | device_id); | |
ce082596 JR |
397 | } |
398 | } | |
399 | ||
43914a2d MY |
400 | /* |
401 | * determines how many NAND chips are connected to the controller. Note for | |
b292c341 | 402 | * Intel CE4100 devices we don't support more than one device. |
ce082596 JR |
403 | */ |
404 | static void find_valid_banks(struct denali_nand_info *denali) | |
405 | { | |
c89eeda8 | 406 | uint32_t id[denali->max_banks]; |
ce082596 JR |
407 | int i; |
408 | ||
409 | denali->total_used_banks = 1; | |
c89eeda8 | 410 | for (i = 0; i < denali->max_banks; i++) { |
3157d1ed MY |
411 | index_addr(denali, MODE_11 | (i << 24) | 0, 0x90); |
412 | index_addr(denali, MODE_11 | (i << 24) | 1, 0); | |
8125450c | 413 | index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]); |
ce082596 | 414 | |
84457949 | 415 | dev_dbg(denali->dev, |
ce082596 JR |
416 | "Return 1st ID for bank[%d]: %x\n", i, id[i]); |
417 | ||
418 | if (i == 0) { | |
419 | if (!(id[i] & 0x0ff)) | |
420 | break; /* WTF? */ | |
421 | } else { | |
422 | if ((id[i] & 0x0ff) == (id[0] & 0x0ff)) | |
423 | denali->total_used_banks++; | |
424 | else | |
425 | break; | |
426 | } | |
427 | } | |
428 | ||
345b1d3b | 429 | if (denali->platform == INTEL_CE4100) { |
43914a2d MY |
430 | /* |
431 | * Platform limitations of the CE4100 device limit | |
ce082596 | 432 | * users to a single chip solution for NAND. |
5bac3acf C |
433 | * Multichip support is not enabled. |
434 | */ | |
345b1d3b | 435 | if (denali->total_used_banks != 1) { |
84457949 | 436 | dev_err(denali->dev, |
8125450c | 437 | "Sorry, Intel CE4100 only supports a single NAND device.\n"); |
ce082596 JR |
438 | BUG(); |
439 | } | |
440 | } | |
84457949 | 441 | dev_dbg(denali->dev, |
ce082596 JR |
442 | "denali->total_used_banks: %d\n", denali->total_used_banks); |
443 | } | |
444 | ||
c89eeda8 JI |
445 | /* |
446 | * Use the configuration feature register to determine the maximum number of | |
447 | * banks that the hardware supports. | |
448 | */ | |
449 | static void detect_max_banks(struct denali_nand_info *denali) | |
450 | { | |
451 | uint32_t features = ioread32(denali->flash_reg + FEATURES); | |
271707b1 GM |
452 | /* |
453 | * Read the revision register, so we can calculate the max_banks | |
454 | * properly: the encoding changed from rev 5.0 to 5.1 | |
455 | */ | |
456 | u32 revision = MAKE_COMPARABLE_REVISION( | |
457 | ioread32(denali->flash_reg + REVISION)); | |
c89eeda8 | 458 | |
271707b1 GM |
459 | if (revision < REVISION_5_1) |
460 | denali->max_banks = 2 << (features & FEATURES__N_BANKS); | |
461 | else | |
462 | denali->max_banks = 1 << (features & FEATURES__N_BANKS); | |
c89eeda8 JI |
463 | } |
464 | ||
eda936ef | 465 | static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) |
ce082596 JR |
466 | { |
467 | uint16_t status = PASS; | |
d68a5c3d | 468 | uint32_t id_bytes[8], addr; |
93e3c8ad MY |
469 | uint8_t maf_id, device_id; |
470 | int i; | |
ce082596 | 471 | |
43914a2d MY |
472 | /* |
473 | * Use read id method to get device ID and other params. | |
474 | * For some NAND chips, controller can't report the correct | |
475 | * device ID by reading from DEVICE_ID register | |
476 | */ | |
3157d1ed MY |
477 | addr = MODE_11 | BANK(denali->flash_bank); |
478 | index_addr(denali, addr | 0, 0x90); | |
479 | index_addr(denali, addr | 1, 0); | |
d68a5c3d | 480 | for (i = 0; i < 8; i++) |
ef41e1bb CD |
481 | index_addr_read_data(denali, addr | 2, &id_bytes[i]); |
482 | maf_id = id_bytes[0]; | |
483 | device_id = id_bytes[1]; | |
ce082596 JR |
484 | |
485 | if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & | |
486 | ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ | |
487 | if (FAIL == get_onfi_nand_para(denali)) | |
488 | return FAIL; | |
ef41e1bb | 489 | } else if (maf_id == 0xEC) { /* Samsung NAND */ |
4c03bbdf | 490 | get_samsung_nand_para(denali, device_id); |
ef41e1bb | 491 | } else if (maf_id == 0x98) { /* Toshiba NAND */ |
ce082596 | 492 | get_toshiba_nand_para(denali); |
ef41e1bb CD |
493 | } else if (maf_id == 0xAD) { /* Hynix NAND */ |
494 | get_hynix_nand_para(denali, device_id); | |
ce082596 JR |
495 | } |
496 | ||
84457949 | 497 | dev_info(denali->dev, |
8125450c | 498 | "Dump timing register values:\n" |
7cfffac0 CD |
499 | "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" |
500 | "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" | |
ce082596 JR |
501 | "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", |
502 | ioread32(denali->flash_reg + ACC_CLKS), | |
503 | ioread32(denali->flash_reg + RE_2_WE), | |
7cfffac0 | 504 | ioread32(denali->flash_reg + RE_2_RE), |
ce082596 JR |
505 | ioread32(denali->flash_reg + WE_2_RE), |
506 | ioread32(denali->flash_reg + ADDR_2_DATA), | |
507 | ioread32(denali->flash_reg + RDWR_EN_LO_CNT), | |
508 | ioread32(denali->flash_reg + RDWR_EN_HI_CNT), | |
509 | ioread32(denali->flash_reg + CS_SETUP_CNT)); | |
510 | ||
ce082596 JR |
511 | find_valid_banks(denali); |
512 | ||
43914a2d MY |
513 | /* |
514 | * If the user specified to override the default timings | |
5bac3acf | 515 | * with a specific ONFI mode, we apply those changes here. |
ce082596 JR |
516 | */ |
517 | if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) | |
eda936ef | 518 | nand_onfi_timing_set(denali, onfi_timing_mode); |
ce082596 JR |
519 | |
520 | return status; | |
521 | } | |
522 | ||
eda936ef | 523 | static void denali_set_intr_modes(struct denali_nand_info *denali, |
ce082596 JR |
524 | uint16_t INT_ENABLE) |
525 | { | |
ce082596 | 526 | if (INT_ENABLE) |
24c3fa36 | 527 | iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE); |
ce082596 | 528 | else |
24c3fa36 | 529 | iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE); |
ce082596 JR |
530 | } |
531 | ||
43914a2d MY |
532 | /* |
533 | * validation function to verify that the controlling software is making | |
b292c341 | 534 | * a valid request |
ce082596 JR |
535 | */ |
536 | static inline bool is_flash_bank_valid(int flash_bank) | |
537 | { | |
7d14ecd0 | 538 | return flash_bank >= 0 && flash_bank < 4; |
ce082596 JR |
539 | } |
540 | ||
541 | static void denali_irq_init(struct denali_nand_info *denali) | |
542 | { | |
5637b69d | 543 | uint32_t int_mask; |
9589bf5b | 544 | int i; |
ce082596 JR |
545 | |
546 | /* Disable global interrupts */ | |
eda936ef | 547 | denali_set_intr_modes(denali, false); |
ce082596 JR |
548 | |
549 | int_mask = DENALI_IRQ_ALL; | |
550 | ||
551 | /* Clear all status bits */ | |
c89eeda8 | 552 | for (i = 0; i < denali->max_banks; ++i) |
9589bf5b | 553 | iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i)); |
ce082596 JR |
554 | |
555 | denali_irq_enable(denali, int_mask); | |
556 | } | |
557 | ||
558 | static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali) | |
559 | { | |
eda936ef | 560 | denali_set_intr_modes(denali, false); |
ce082596 JR |
561 | } |
562 | ||
bdca6dae CD |
563 | static void denali_irq_enable(struct denali_nand_info *denali, |
564 | uint32_t int_mask) | |
ce082596 | 565 | { |
9589bf5b JI |
566 | int i; |
567 | ||
c89eeda8 | 568 | for (i = 0; i < denali->max_banks; ++i) |
9589bf5b | 569 | iowrite32(int_mask, denali->flash_reg + INTR_EN(i)); |
ce082596 JR |
570 | } |
571 | ||
43914a2d MY |
572 | /* |
573 | * This function only returns when an interrupt that this driver cares about | |
5bac3acf | 574 | * occurs. This is to reduce the overhead of servicing interrupts |
ce082596 JR |
575 | */ |
576 | static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) | |
577 | { | |
a99d1796 | 578 | return read_interrupt_status(denali) & DENALI_IRQ_ALL; |
ce082596 JR |
579 | } |
580 | ||
581 | /* Interrupts are cleared by writing a 1 to the appropriate status bit */ | |
bdca6dae CD |
582 | static inline void clear_interrupt(struct denali_nand_info *denali, |
583 | uint32_t irq_mask) | |
ce082596 | 584 | { |
5637b69d | 585 | uint32_t intr_status_reg; |
ce082596 | 586 | |
9589bf5b | 587 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
ce082596 | 588 | |
24c3fa36 | 589 | iowrite32(irq_mask, denali->flash_reg + intr_status_reg); |
ce082596 JR |
590 | } |
591 | ||
592 | static void clear_interrupts(struct denali_nand_info *denali) | |
593 | { | |
5637b69d MY |
594 | uint32_t status; |
595 | ||
ce082596 JR |
596 | spin_lock_irq(&denali->irq_lock); |
597 | ||
598 | status = read_interrupt_status(denali); | |
8ae61ebd | 599 | clear_interrupt(denali, status); |
ce082596 | 600 | |
ce082596 JR |
601 | denali->irq_status = 0x0; |
602 | spin_unlock_irq(&denali->irq_lock); | |
603 | } | |
604 | ||
605 | static uint32_t read_interrupt_status(struct denali_nand_info *denali) | |
606 | { | |
5637b69d | 607 | uint32_t intr_status_reg; |
ce082596 | 608 | |
9589bf5b | 609 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
ce082596 JR |
610 | |
611 | return ioread32(denali->flash_reg + intr_status_reg); | |
612 | } | |
613 | ||
43914a2d MY |
614 | /* |
615 | * This is the interrupt service routine. It handles all interrupts | |
616 | * sent to this device. Note that on CE4100, this is a shared interrupt. | |
ce082596 JR |
617 | */ |
618 | static irqreturn_t denali_isr(int irq, void *dev_id) | |
619 | { | |
620 | struct denali_nand_info *denali = dev_id; | |
5637b69d | 621 | uint32_t irq_status; |
ce082596 JR |
622 | irqreturn_t result = IRQ_NONE; |
623 | ||
624 | spin_lock(&denali->irq_lock); | |
625 | ||
43914a2d | 626 | /* check to see if a valid NAND chip has been selected. */ |
345b1d3b | 627 | if (is_flash_bank_valid(denali->flash_bank)) { |
43914a2d MY |
628 | /* |
629 | * check to see if controller generated the interrupt, | |
630 | * since this is a shared interrupt | |
631 | */ | |
bdca6dae CD |
632 | irq_status = denali_irq_detected(denali); |
633 | if (irq_status != 0) { | |
ce082596 JR |
634 | /* handle interrupt */ |
635 | /* first acknowledge it */ | |
636 | clear_interrupt(denali, irq_status); | |
43914a2d MY |
637 | /* |
638 | * store the status in the device context for someone | |
639 | * to read | |
640 | */ | |
ce082596 JR |
641 | denali->irq_status |= irq_status; |
642 | /* notify anyone who cares that it happened */ | |
643 | complete(&denali->complete); | |
644 | /* tell the OS that we've handled this */ | |
645 | result = IRQ_HANDLED; | |
646 | } | |
647 | } | |
648 | spin_unlock(&denali->irq_lock); | |
649 | return result; | |
650 | } | |
ce082596 JR |
651 | |
652 | static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) | |
653 | { | |
5637b69d MY |
654 | unsigned long comp_res; |
655 | uint32_t intr_status; | |
ce082596 JR |
656 | unsigned long timeout = msecs_to_jiffies(1000); |
657 | ||
345b1d3b | 658 | do { |
bdca6dae CD |
659 | comp_res = |
660 | wait_for_completion_timeout(&denali->complete, timeout); | |
ce082596 JR |
661 | spin_lock_irq(&denali->irq_lock); |
662 | intr_status = denali->irq_status; | |
663 | ||
345b1d3b | 664 | if (intr_status & irq_mask) { |
ce082596 JR |
665 | denali->irq_status &= ~irq_mask; |
666 | spin_unlock_irq(&denali->irq_lock); | |
ce082596 JR |
667 | /* our interrupt was detected */ |
668 | break; | |
ce082596 | 669 | } |
8125450c MY |
670 | |
671 | /* | |
672 | * these are not the interrupts you are looking for - | |
673 | * need to wait again | |
674 | */ | |
675 | spin_unlock_irq(&denali->irq_lock); | |
ce082596 JR |
676 | } while (comp_res != 0); |
677 | ||
345b1d3b | 678 | if (comp_res == 0) { |
ce082596 | 679 | /* timeout */ |
2a0a288e | 680 | pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n", |
5bac3acf | 681 | intr_status, irq_mask); |
ce082596 JR |
682 | |
683 | intr_status = 0; | |
684 | } | |
685 | return intr_status; | |
686 | } | |
687 | ||
43914a2d MY |
688 | /* |
689 | * This helper function setups the registers for ECC and whether or not | |
690 | * the spare area will be transferred. | |
691 | */ | |
5bac3acf | 692 | static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, |
ce082596 JR |
693 | bool transfer_spare) |
694 | { | |
5637b69d | 695 | int ecc_en_flag, transfer_spare_flag; |
ce082596 JR |
696 | |
697 | /* set ECC, transfer spare bits if needed */ | |
698 | ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; | |
699 | transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0; | |
700 | ||
701 | /* Enable spare area/ECC per user's request. */ | |
24c3fa36 | 702 | iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE); |
8125450c | 703 | iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG); |
ce082596 JR |
704 | } |
705 | ||
43914a2d MY |
706 | /* |
707 | * sends a pipeline command operation to the controller. See the Denali NAND | |
b292c341 | 708 | * controller's user guide for more information (section 4.2.3.6). |
ce082596 | 709 | */ |
bdca6dae | 710 | static int denali_send_pipeline_cmd(struct denali_nand_info *denali, |
8125450c MY |
711 | bool ecc_en, bool transfer_spare, |
712 | int access_type, int op) | |
ce082596 JR |
713 | { |
714 | int status = PASS; | |
5637b69d MY |
715 | uint32_t page_count = 1; |
716 | uint32_t addr, cmd, irq_status, irq_mask; | |
ce082596 | 717 | |
a99d1796 | 718 | if (op == DENALI_READ) |
9589bf5b | 719 | irq_mask = INTR_STATUS__LOAD_COMP; |
a99d1796 CD |
720 | else if (op == DENALI_WRITE) |
721 | irq_mask = 0; | |
722 | else | |
723 | BUG(); | |
ce082596 JR |
724 | |
725 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); | |
726 | ||
5bac3acf | 727 | clear_interrupts(denali); |
ce082596 JR |
728 | |
729 | addr = BANK(denali->flash_bank) | denali->page; | |
730 | ||
345b1d3b | 731 | if (op == DENALI_WRITE && access_type != SPARE_ACCESS) { |
5bac3acf | 732 | cmd = MODE_01 | addr; |
24c3fa36 | 733 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 734 | } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) { |
ce082596 | 735 | /* read spare area */ |
5bac3acf | 736 | cmd = MODE_10 | addr; |
3157d1ed | 737 | index_addr(denali, cmd, access_type); |
ce082596 | 738 | |
5bac3acf | 739 | cmd = MODE_01 | addr; |
24c3fa36 | 740 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 741 | } else if (op == DENALI_READ) { |
ce082596 | 742 | /* setup page read request for access type */ |
5bac3acf | 743 | cmd = MODE_10 | addr; |
3157d1ed | 744 | index_addr(denali, cmd, access_type); |
ce082596 | 745 | |
43914a2d MY |
746 | /* |
747 | * page 33 of the NAND controller spec indicates we should not | |
748 | * use the pipeline commands in Spare area only mode. | |
749 | * So we don't. | |
ce082596 | 750 | */ |
345b1d3b | 751 | if (access_type == SPARE_ACCESS) { |
ce082596 | 752 | cmd = MODE_01 | addr; |
24c3fa36 | 753 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 754 | } else { |
3157d1ed | 755 | index_addr(denali, cmd, |
2902330e | 756 | PIPELINE_ACCESS | op | page_count); |
5bac3acf | 757 | |
43914a2d MY |
758 | /* |
759 | * wait for command to be accepted | |
bdca6dae | 760 | * can always use status0 bit as the |
43914a2d MY |
761 | * mask is identical for each bank. |
762 | */ | |
ce082596 JR |
763 | irq_status = wait_for_irq(denali, irq_mask); |
764 | ||
345b1d3b | 765 | if (irq_status == 0) { |
84457949 | 766 | dev_err(denali->dev, |
8125450c MY |
767 | "cmd, page, addr on timeout (0x%x, 0x%x, 0x%x)\n", |
768 | cmd, denali->page, addr); | |
ce082596 | 769 | status = FAIL; |
345b1d3b | 770 | } else { |
ce082596 | 771 | cmd = MODE_01 | addr; |
24c3fa36 | 772 | iowrite32(cmd, denali->flash_mem); |
ce082596 JR |
773 | } |
774 | } | |
775 | } | |
776 | return status; | |
777 | } | |
778 | ||
779 | /* helper function that simply writes a buffer to the flash */ | |
bdca6dae | 780 | static int write_data_to_flash_mem(struct denali_nand_info *denali, |
8125450c | 781 | const uint8_t *buf, int len) |
ce082596 | 782 | { |
93e3c8ad MY |
783 | uint32_t *buf32; |
784 | int i; | |
ce082596 | 785 | |
43914a2d MY |
786 | /* |
787 | * verify that the len is a multiple of 4. | |
788 | * see comment in read_data_from_flash_mem() | |
789 | */ | |
ce082596 JR |
790 | BUG_ON((len % 4) != 0); |
791 | ||
792 | /* write the data to the flash memory */ | |
793 | buf32 = (uint32_t *)buf; | |
794 | for (i = 0; i < len / 4; i++) | |
24c3fa36 | 795 | iowrite32(*buf32++, denali->flash_mem + 0x10); |
8125450c | 796 | return i * 4; /* intent is to return the number of bytes read */ |
ce082596 JR |
797 | } |
798 | ||
799 | /* helper function that simply reads a buffer from the flash */ | |
bdca6dae | 800 | static int read_data_from_flash_mem(struct denali_nand_info *denali, |
8125450c | 801 | uint8_t *buf, int len) |
ce082596 | 802 | { |
93e3c8ad MY |
803 | uint32_t *buf32; |
804 | int i; | |
ce082596 | 805 | |
43914a2d MY |
806 | /* |
807 | * we assume that len will be a multiple of 4, if not it would be nice | |
808 | * to know about it ASAP rather than have random failures... | |
809 | * This assumption is based on the fact that this function is designed | |
810 | * to be used to read flash pages, which are typically multiples of 4. | |
ce082596 | 811 | */ |
ce082596 JR |
812 | BUG_ON((len % 4) != 0); |
813 | ||
814 | /* transfer the data from the flash */ | |
815 | buf32 = (uint32_t *)buf; | |
816 | for (i = 0; i < len / 4; i++) | |
ce082596 | 817 | *buf32++ = ioread32(denali->flash_mem + 0x10); |
8125450c | 818 | return i * 4; /* intent is to return the number of bytes read */ |
ce082596 JR |
819 | } |
820 | ||
821 | /* writes OOB data to the device */ | |
822 | static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
823 | { | |
824 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
5637b69d | 825 | uint32_t irq_status; |
9589bf5b JI |
826 | uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | |
827 | INTR_STATUS__PROGRAM_FAIL; | |
ce082596 JR |
828 | int status = 0; |
829 | ||
830 | denali->page = page; | |
831 | ||
5bac3acf | 832 | if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS, |
345b1d3b | 833 | DENALI_WRITE) == PASS) { |
ce082596 JR |
834 | write_data_to_flash_mem(denali, buf, mtd->oobsize); |
835 | ||
ce082596 JR |
836 | /* wait for operation to complete */ |
837 | irq_status = wait_for_irq(denali, irq_mask); | |
838 | ||
345b1d3b | 839 | if (irq_status == 0) { |
84457949 | 840 | dev_err(denali->dev, "OOB write failed\n"); |
ce082596 JR |
841 | status = -EIO; |
842 | } | |
345b1d3b | 843 | } else { |
84457949 | 844 | dev_err(denali->dev, "unable to send pipeline command\n"); |
5bac3acf | 845 | status = -EIO; |
ce082596 JR |
846 | } |
847 | return status; | |
848 | } | |
849 | ||
850 | /* reads OOB data from the device */ | |
851 | static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
852 | { | |
853 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
5637b69d MY |
854 | uint32_t irq_mask = INTR_STATUS__LOAD_COMP; |
855 | uint32_t irq_status, addr, cmd; | |
ce082596 JR |
856 | |
857 | denali->page = page; | |
858 | ||
5bac3acf | 859 | if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, |
345b1d3b | 860 | DENALI_READ) == PASS) { |
5bac3acf | 861 | read_data_from_flash_mem(denali, buf, mtd->oobsize); |
ce082596 | 862 | |
43914a2d MY |
863 | /* |
864 | * wait for command to be accepted | |
865 | * can always use status0 bit as the | |
866 | * mask is identical for each bank. | |
867 | */ | |
ce082596 JR |
868 | irq_status = wait_for_irq(denali, irq_mask); |
869 | ||
870 | if (irq_status == 0) | |
84457949 | 871 | dev_err(denali->dev, "page on OOB timeout %d\n", |
bdca6dae | 872 | denali->page); |
ce082596 | 873 | |
43914a2d MY |
874 | /* |
875 | * We set the device back to MAIN_ACCESS here as I observed | |
ce082596 JR |
876 | * instability with the controller if you do a block erase |
877 | * and the last transaction was a SPARE_ACCESS. Block erase | |
878 | * is reliable (according to the MTD test infrastructure) | |
5bac3acf | 879 | * if you are in MAIN_ACCESS. |
ce082596 JR |
880 | */ |
881 | addr = BANK(denali->flash_bank) | denali->page; | |
5bac3acf | 882 | cmd = MODE_10 | addr; |
3157d1ed | 883 | index_addr(denali, cmd, MAIN_ACCESS); |
ce082596 JR |
884 | } |
885 | } | |
886 | ||
43914a2d MY |
887 | /* |
888 | * this function examines buffers to see if they contain data that | |
ce082596 JR |
889 | * indicate that the buffer is part of an erased region of flash. |
890 | */ | |
919193ce | 891 | static bool is_erased(uint8_t *buf, int len) |
ce082596 | 892 | { |
5637b69d | 893 | int i; |
8125450c | 894 | |
ce082596 | 895 | for (i = 0; i < len; i++) |
ce082596 | 896 | if (buf[i] != 0xFF) |
ce082596 | 897 | return false; |
ce082596 JR |
898 | return true; |
899 | } | |
900 | #define ECC_SECTOR_SIZE 512 | |
901 | ||
902 | #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12) | |
903 | #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET)) | |
904 | #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK) | |
8ae61ebd CD |
905 | #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE)) |
906 | #define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8) | |
ce082596 JR |
907 | #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO) |
908 | ||
5bac3acf | 909 | static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, |
3f91e94f | 910 | uint32_t irq_status, unsigned int *max_bitflips) |
ce082596 JR |
911 | { |
912 | bool check_erased_page = false; | |
3f91e94f | 913 | unsigned int bitflips = 0; |
ce082596 | 914 | |
9589bf5b | 915 | if (irq_status & INTR_STATUS__ECC_ERR) { |
ce082596 | 916 | /* read the ECC errors. we'll ignore them for now */ |
5637b69d MY |
917 | uint32_t err_address, err_correction_info, err_byte, |
918 | err_sector, err_device, err_correction_value; | |
8ae61ebd | 919 | denali_set_intr_modes(denali, false); |
ce082596 | 920 | |
345b1d3b | 921 | do { |
5bac3acf | 922 | err_address = ioread32(denali->flash_reg + |
ce082596 JR |
923 | ECC_ERROR_ADDRESS); |
924 | err_sector = ECC_SECTOR(err_address); | |
925 | err_byte = ECC_BYTE(err_address); | |
926 | ||
5bac3acf | 927 | err_correction_info = ioread32(denali->flash_reg + |
ce082596 | 928 | ERR_CORRECTION_INFO); |
5bac3acf | 929 | err_correction_value = |
ce082596 JR |
930 | ECC_CORRECTION_VALUE(err_correction_info); |
931 | err_device = ECC_ERR_DEVICE(err_correction_info); | |
932 | ||
345b1d3b | 933 | if (ECC_ERROR_CORRECTABLE(err_correction_info)) { |
43914a2d MY |
934 | /* |
935 | * If err_byte is larger than ECC_SECTOR_SIZE, | |
25985edc | 936 | * means error happened in OOB, so we ignore |
8ae61ebd CD |
937 | * it. It's no need for us to correct it |
938 | * err_device is represented the NAND error | |
939 | * bits are happened in if there are more | |
940 | * than one NAND connected. | |
43914a2d | 941 | */ |
8ae61ebd | 942 | if (err_byte < ECC_SECTOR_SIZE) { |
442f201b BB |
943 | struct mtd_info *mtd = |
944 | nand_to_mtd(&denali->nand); | |
8ae61ebd | 945 | int offset; |
8125450c | 946 | |
8ae61ebd CD |
947 | offset = (err_sector * |
948 | ECC_SECTOR_SIZE + | |
949 | err_byte) * | |
950 | denali->devnum + | |
951 | err_device; | |
ce082596 JR |
952 | /* correct the ECC error */ |
953 | buf[offset] ^= err_correction_value; | |
442f201b | 954 | mtd->ecc_stats.corrected++; |
3f91e94f | 955 | bitflips++; |
ce082596 | 956 | } |
345b1d3b | 957 | } else { |
43914a2d MY |
958 | /* |
959 | * if the error is not correctable, need to | |
bdca6dae CD |
960 | * look at the page to see if it is an erased |
961 | * page. if so, then it's not a real ECC error | |
43914a2d | 962 | */ |
ce082596 JR |
963 | check_erased_page = true; |
964 | } | |
ce082596 | 965 | } while (!ECC_LAST_ERR(err_correction_info)); |
43914a2d MY |
966 | /* |
967 | * Once handle all ecc errors, controller will triger | |
8ae61ebd CD |
968 | * a ECC_TRANSACTION_DONE interrupt, so here just wait |
969 | * for a while for this interrupt | |
43914a2d | 970 | */ |
8ae61ebd | 971 | while (!(read_interrupt_status(denali) & |
9589bf5b | 972 | INTR_STATUS__ECC_TRANSACTION_DONE)) |
8ae61ebd CD |
973 | cpu_relax(); |
974 | clear_interrupts(denali); | |
975 | denali_set_intr_modes(denali, true); | |
ce082596 | 976 | } |
3f91e94f | 977 | *max_bitflips = bitflips; |
ce082596 JR |
978 | return check_erased_page; |
979 | } | |
980 | ||
981 | /* programs the controller to either enable/disable DMA transfers */ | |
aadff49c | 982 | static void denali_enable_dma(struct denali_nand_info *denali, bool en) |
ce082596 | 983 | { |
5637b69d | 984 | iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE); |
ce082596 JR |
985 | ioread32(denali->flash_reg + DMA_ENABLE); |
986 | } | |
987 | ||
988 | /* setups the HW to perform the data DMA */ | |
aadff49c | 989 | static void denali_setup_dma(struct denali_nand_info *denali, int op) |
ce082596 | 990 | { |
5637b69d | 991 | uint32_t mode; |
ce082596 | 992 | const int page_count = 1; |
3157d1ed | 993 | uint32_t addr = denali->buf.dma_buf; |
ce082596 JR |
994 | |
995 | mode = MODE_10 | BANK(denali->flash_bank); | |
996 | ||
997 | /* DMA is a four step process */ | |
998 | ||
999 | /* 1. setup transfer type and # of pages */ | |
1000 | index_addr(denali, mode | denali->page, 0x2000 | op | page_count); | |
1001 | ||
1002 | /* 2. set memory high address bits 23:8 */ | |
3157d1ed | 1003 | index_addr(denali, mode | ((addr >> 16) << 8), 0x2200); |
ce082596 JR |
1004 | |
1005 | /* 3. set memory low address bits 23:8 */ | |
7c272ac5 | 1006 | index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300); |
ce082596 | 1007 | |
43914a2d | 1008 | /* 4. interrupt when complete, burst len = 64 bytes */ |
ce082596 JR |
1009 | index_addr(denali, mode | 0x14000, 0x2400); |
1010 | } | |
1011 | ||
43914a2d MY |
1012 | /* |
1013 | * writes a page. user specifies type, and this function handles the | |
1014 | * configuration details. | |
1015 | */ | |
fdbad98d | 1016 | static int write_page(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1017 | const uint8_t *buf, bool raw_xfer) |
1018 | { | |
1019 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ce082596 | 1020 | dma_addr_t addr = denali->buf.dma_buf; |
442f201b | 1021 | size_t size = mtd->writesize + mtd->oobsize; |
5637b69d | 1022 | uint32_t irq_status; |
9589bf5b JI |
1023 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP | |
1024 | INTR_STATUS__PROGRAM_FAIL; | |
ce082596 | 1025 | |
43914a2d MY |
1026 | /* |
1027 | * if it is a raw xfer, we want to disable ecc and send the spare area. | |
ce082596 JR |
1028 | * !raw_xfer - enable ecc |
1029 | * raw_xfer - transfer spare | |
1030 | */ | |
1031 | setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer); | |
1032 | ||
1033 | /* copy buffer into DMA buffer */ | |
1034 | memcpy(denali->buf.buf, buf, mtd->writesize); | |
1035 | ||
345b1d3b | 1036 | if (raw_xfer) { |
ce082596 | 1037 | /* transfer the data to the spare area */ |
5bac3acf C |
1038 | memcpy(denali->buf.buf + mtd->writesize, |
1039 | chip->oob_poi, | |
1040 | mtd->oobsize); | |
ce082596 JR |
1041 | } |
1042 | ||
84457949 | 1043 | dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE); |
ce082596 JR |
1044 | |
1045 | clear_interrupts(denali); | |
5bac3acf | 1046 | denali_enable_dma(denali, true); |
ce082596 | 1047 | |
aadff49c | 1048 | denali_setup_dma(denali, DENALI_WRITE); |
ce082596 JR |
1049 | |
1050 | /* wait for operation to complete */ | |
1051 | irq_status = wait_for_irq(denali, irq_mask); | |
1052 | ||
345b1d3b | 1053 | if (irq_status == 0) { |
8125450c MY |
1054 | dev_err(denali->dev, "timeout on write_page (type = %d)\n", |
1055 | raw_xfer); | |
c115add9 | 1056 | denali->status = NAND_STATUS_FAIL; |
ce082596 JR |
1057 | } |
1058 | ||
5bac3acf | 1059 | denali_enable_dma(denali, false); |
84457949 | 1060 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE); |
fdbad98d JW |
1061 | |
1062 | return 0; | |
ce082596 JR |
1063 | } |
1064 | ||
1065 | /* NAND core entry points */ | |
1066 | ||
43914a2d MY |
1067 | /* |
1068 | * this is the callback that the NAND core calls to write a page. Since | |
b292c341 CD |
1069 | * writing a page with ECC or without is similar, all the work is done |
1070 | * by write_page above. | |
43914a2d | 1071 | */ |
fdbad98d | 1072 | static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 | 1073 | const uint8_t *buf, int oob_required, int page) |
ce082596 | 1074 | { |
43914a2d MY |
1075 | /* |
1076 | * for regular page writes, we let HW handle all the ECC | |
1077 | * data written to the device. | |
1078 | */ | |
fdbad98d | 1079 | return write_page(mtd, chip, buf, false); |
ce082596 JR |
1080 | } |
1081 | ||
43914a2d MY |
1082 | /* |
1083 | * This is the callback that the NAND core calls to write a page without ECC. | |
25985edc | 1084 | * raw access is similar to ECC page writes, so all the work is done in the |
b292c341 | 1085 | * write_page() function above. |
ce082596 | 1086 | */ |
fdbad98d | 1087 | static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 BB |
1088 | const uint8_t *buf, int oob_required, |
1089 | int page) | |
ce082596 | 1090 | { |
43914a2d MY |
1091 | /* |
1092 | * for raw page writes, we want to disable ECC and simply write | |
1093 | * whatever data is in the buffer. | |
1094 | */ | |
fdbad98d | 1095 | return write_page(mtd, chip, buf, true); |
ce082596 JR |
1096 | } |
1097 | ||
5bac3acf | 1098 | static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1099 | int page) |
1100 | { | |
5bac3acf | 1101 | return write_oob_data(mtd, chip->oob_poi, page); |
ce082596 JR |
1102 | } |
1103 | ||
5bac3acf | 1104 | static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, |
5c2ffb11 | 1105 | int page) |
ce082596 JR |
1106 | { |
1107 | read_oob_data(mtd, chip->oob_poi, page); | |
1108 | ||
5c2ffb11 | 1109 | return 0; |
ce082596 JR |
1110 | } |
1111 | ||
1112 | static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1113 | uint8_t *buf, int oob_required, int page) |
ce082596 | 1114 | { |
3f91e94f | 1115 | unsigned int max_bitflips; |
ce082596 | 1116 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
ce082596 JR |
1117 | |
1118 | dma_addr_t addr = denali->buf.dma_buf; | |
442f201b | 1119 | size_t size = mtd->writesize + mtd->oobsize; |
ce082596 | 1120 | |
5637b69d | 1121 | uint32_t irq_status; |
9589bf5b JI |
1122 | uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE | |
1123 | INTR_STATUS__ECC_ERR; | |
ce082596 JR |
1124 | bool check_erased_page = false; |
1125 | ||
7d8a26fd | 1126 | if (page != denali->page) { |
8125450c MY |
1127 | dev_err(denali->dev, |
1128 | "IN %s: page %d is not equal to denali->page %d", | |
1129 | __func__, page, denali->page); | |
7d8a26fd CD |
1130 | BUG(); |
1131 | } | |
1132 | ||
ce082596 JR |
1133 | setup_ecc_for_xfer(denali, true, false); |
1134 | ||
aadff49c | 1135 | denali_enable_dma(denali, true); |
84457949 | 1136 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1137 | |
1138 | clear_interrupts(denali); | |
aadff49c | 1139 | denali_setup_dma(denali, DENALI_READ); |
ce082596 JR |
1140 | |
1141 | /* wait for operation to complete */ | |
1142 | irq_status = wait_for_irq(denali, irq_mask); | |
1143 | ||
84457949 | 1144 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1145 | |
1146 | memcpy(buf, denali->buf.buf, mtd->writesize); | |
5bac3acf | 1147 | |
3f91e94f | 1148 | check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips); |
aadff49c | 1149 | denali_enable_dma(denali, false); |
ce082596 | 1150 | |
345b1d3b | 1151 | if (check_erased_page) { |
442f201b | 1152 | read_oob_data(mtd, chip->oob_poi, denali->page); |
ce082596 JR |
1153 | |
1154 | /* check ECC failures that may have occurred on erased pages */ | |
345b1d3b | 1155 | if (check_erased_page) { |
442f201b BB |
1156 | if (!is_erased(buf, mtd->writesize)) |
1157 | mtd->ecc_stats.failed++; | |
1158 | if (!is_erased(buf, mtd->oobsize)) | |
1159 | mtd->ecc_stats.failed++; | |
5bac3acf | 1160 | } |
ce082596 | 1161 | } |
3f91e94f | 1162 | return max_bitflips; |
ce082596 JR |
1163 | } |
1164 | ||
1165 | static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1166 | uint8_t *buf, int oob_required, int page) |
ce082596 JR |
1167 | { |
1168 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ce082596 | 1169 | dma_addr_t addr = denali->buf.dma_buf; |
442f201b | 1170 | size_t size = mtd->writesize + mtd->oobsize; |
9589bf5b | 1171 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; |
5bac3acf | 1172 | |
7d8a26fd | 1173 | if (page != denali->page) { |
8125450c MY |
1174 | dev_err(denali->dev, |
1175 | "IN %s: page %d is not equal to denali->page %d", | |
1176 | __func__, page, denali->page); | |
7d8a26fd CD |
1177 | BUG(); |
1178 | } | |
1179 | ||
ce082596 | 1180 | setup_ecc_for_xfer(denali, false, true); |
aadff49c | 1181 | denali_enable_dma(denali, true); |
ce082596 | 1182 | |
84457949 | 1183 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1184 | |
1185 | clear_interrupts(denali); | |
aadff49c | 1186 | denali_setup_dma(denali, DENALI_READ); |
ce082596 JR |
1187 | |
1188 | /* wait for operation to complete */ | |
ba5f2bc2 | 1189 | wait_for_irq(denali, irq_mask); |
ce082596 | 1190 | |
84457949 | 1191 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 | 1192 | |
aadff49c | 1193 | denali_enable_dma(denali, false); |
ce082596 JR |
1194 | |
1195 | memcpy(buf, denali->buf.buf, mtd->writesize); | |
1196 | memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize); | |
1197 | ||
1198 | return 0; | |
1199 | } | |
1200 | ||
1201 | static uint8_t denali_read_byte(struct mtd_info *mtd) | |
1202 | { | |
1203 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1204 | uint8_t result = 0xff; | |
1205 | ||
1206 | if (denali->buf.head < denali->buf.tail) | |
ce082596 | 1207 | result = denali->buf.buf[denali->buf.head++]; |
ce082596 | 1208 | |
ce082596 JR |
1209 | return result; |
1210 | } | |
1211 | ||
1212 | static void denali_select_chip(struct mtd_info *mtd, int chip) | |
1213 | { | |
1214 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
7cfffac0 | 1215 | |
ce082596 JR |
1216 | spin_lock_irq(&denali->irq_lock); |
1217 | denali->flash_bank = chip; | |
1218 | spin_unlock_irq(&denali->irq_lock); | |
1219 | } | |
1220 | ||
1221 | static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) | |
1222 | { | |
1223 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1224 | int status = denali->status; | |
8125450c | 1225 | |
ce082596 JR |
1226 | denali->status = 0; |
1227 | ||
ce082596 JR |
1228 | return status; |
1229 | } | |
1230 | ||
49c50b97 | 1231 | static int denali_erase(struct mtd_info *mtd, int page) |
ce082596 JR |
1232 | { |
1233 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1234 | ||
5637b69d | 1235 | uint32_t cmd, irq_status; |
ce082596 | 1236 | |
5bac3acf | 1237 | clear_interrupts(denali); |
ce082596 JR |
1238 | |
1239 | /* setup page read request for access type */ | |
1240 | cmd = MODE_10 | BANK(denali->flash_bank) | page; | |
3157d1ed | 1241 | index_addr(denali, cmd, 0x1); |
ce082596 JR |
1242 | |
1243 | /* wait for erase to complete or failure to occur */ | |
9589bf5b JI |
1244 | irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | |
1245 | INTR_STATUS__ERASE_FAIL); | |
ce082596 | 1246 | |
7d14ecd0 | 1247 | return irq_status & INTR_STATUS__ERASE_FAIL ? NAND_STATUS_FAIL : PASS; |
ce082596 JR |
1248 | } |
1249 | ||
5bac3acf | 1250 | static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, |
ce082596 JR |
1251 | int page) |
1252 | { | |
1253 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ef41e1bb CD |
1254 | uint32_t addr, id; |
1255 | int i; | |
ce082596 | 1256 | |
345b1d3b | 1257 | switch (cmd) { |
a99d1796 CD |
1258 | case NAND_CMD_PAGEPROG: |
1259 | break; | |
1260 | case NAND_CMD_STATUS: | |
1261 | read_status(denali); | |
1262 | break; | |
1263 | case NAND_CMD_READID: | |
42af8b58 | 1264 | case NAND_CMD_PARAM: |
a99d1796 | 1265 | reset_buf(denali); |
43914a2d MY |
1266 | /* |
1267 | * sometimes ManufactureId read from register is not right | |
ef41e1bb CD |
1268 | * e.g. some of Micron MT29F32G08QAA MLC NAND chips |
1269 | * So here we send READID cmd to NAND insteand | |
43914a2d | 1270 | */ |
3157d1ed MY |
1271 | addr = MODE_11 | BANK(denali->flash_bank); |
1272 | index_addr(denali, addr | 0, 0x90); | |
9c07d094 | 1273 | index_addr(denali, addr | 1, col); |
d68a5c3d | 1274 | for (i = 0; i < 8; i++) { |
8125450c | 1275 | index_addr_read_data(denali, addr | 2, &id); |
ef41e1bb | 1276 | write_byte_to_buf(denali, id); |
a99d1796 CD |
1277 | } |
1278 | break; | |
1279 | case NAND_CMD_READ0: | |
1280 | case NAND_CMD_SEQIN: | |
1281 | denali->page = page; | |
1282 | break; | |
1283 | case NAND_CMD_RESET: | |
1284 | reset_bank(denali); | |
1285 | break; | |
1286 | case NAND_CMD_READOOB: | |
1287 | /* TODO: Read OOB data */ | |
1288 | break; | |
1289 | default: | |
2a0a288e | 1290 | pr_err(": unsupported command received 0x%x\n", cmd); |
a99d1796 | 1291 | break; |
ce082596 JR |
1292 | } |
1293 | } | |
ce082596 JR |
1294 | /* end NAND core entry points */ |
1295 | ||
1296 | /* Initialization code to bring the device up to a known good state */ | |
1297 | static void denali_hw_init(struct denali_nand_info *denali) | |
1298 | { | |
43914a2d MY |
1299 | /* |
1300 | * tell driver how many bit controller will skip before | |
db9a3210 CD |
1301 | * writing ECC code in OOB, this register may be already |
1302 | * set by firmware. So we read this value out. | |
1303 | * if this value is 0, just let it be. | |
43914a2d | 1304 | */ |
db9a3210 CD |
1305 | denali->bbtskipbytes = ioread32(denali->flash_reg + |
1306 | SPARE_AREA_SKIP_BYTES); | |
bc27ede3 | 1307 | detect_max_banks(denali); |
eda936ef | 1308 | denali_nand_reset(denali); |
24c3fa36 CD |
1309 | iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED); |
1310 | iowrite32(CHIP_EN_DONT_CARE__FLAG, | |
bdca6dae | 1311 | denali->flash_reg + CHIP_ENABLE_DONT_CARE); |
ce082596 | 1312 | |
24c3fa36 | 1313 | iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER); |
ce082596 JR |
1314 | |
1315 | /* Should set value for these registers when init */ | |
24c3fa36 CD |
1316 | iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES); |
1317 | iowrite32(1, denali->flash_reg + ECC_ENABLE); | |
5eab6aaa CD |
1318 | denali_nand_timing_set(denali); |
1319 | denali_irq_init(denali); | |
ce082596 JR |
1320 | } |
1321 | ||
43914a2d MY |
1322 | /* |
1323 | * Althogh controller spec said SLC ECC is forceb to be 4bit, | |
db9a3210 CD |
1324 | * but denali controller in MRST only support 15bit and 8bit ECC |
1325 | * correction | |
43914a2d | 1326 | */ |
db9a3210 | 1327 | #define ECC_8BITS 14 |
db9a3210 | 1328 | #define ECC_15BITS 26 |
14fad62b BB |
1329 | |
1330 | static int denali_ooblayout_ecc(struct mtd_info *mtd, int section, | |
1331 | struct mtd_oob_region *oobregion) | |
1332 | { | |
1333 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1334 | struct nand_chip *chip = mtd_to_nand(mtd); | |
1335 | ||
1336 | if (section) | |
1337 | return -ERANGE; | |
1338 | ||
1339 | oobregion->offset = denali->bbtskipbytes; | |
1340 | oobregion->length = chip->ecc.total; | |
1341 | ||
1342 | return 0; | |
1343 | } | |
1344 | ||
1345 | static int denali_ooblayout_free(struct mtd_info *mtd, int section, | |
1346 | struct mtd_oob_region *oobregion) | |
1347 | { | |
1348 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1349 | struct nand_chip *chip = mtd_to_nand(mtd); | |
1350 | ||
1351 | if (section) | |
1352 | return -ERANGE; | |
1353 | ||
1354 | oobregion->offset = chip->ecc.total + denali->bbtskipbytes; | |
1355 | oobregion->length = mtd->oobsize - oobregion->offset; | |
1356 | ||
1357 | return 0; | |
1358 | } | |
1359 | ||
1360 | static const struct mtd_ooblayout_ops denali_ooblayout_ops = { | |
1361 | .ecc = denali_ooblayout_ecc, | |
1362 | .free = denali_ooblayout_free, | |
ce082596 JR |
1363 | }; |
1364 | ||
1365 | static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; | |
1366 | static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
1367 | ||
1368 | static struct nand_bbt_descr bbt_main_descr = { | |
1369 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1370 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1371 | .offs = 8, | |
1372 | .len = 4, | |
1373 | .veroffs = 12, | |
1374 | .maxblocks = 4, | |
1375 | .pattern = bbt_pattern, | |
1376 | }; | |
1377 | ||
1378 | static struct nand_bbt_descr bbt_mirror_descr = { | |
1379 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1380 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1381 | .offs = 8, | |
1382 | .len = 4, | |
1383 | .veroffs = 12, | |
1384 | .maxblocks = 4, | |
1385 | .pattern = mirror_pattern, | |
1386 | }; | |
1387 | ||
421f91d2 | 1388 | /* initialize driver data structures */ |
8c519436 | 1389 | static void denali_drv_init(struct denali_nand_info *denali) |
ce082596 | 1390 | { |
43914a2d MY |
1391 | /* |
1392 | * the completion object will be used to notify | |
1393 | * the callee that the interrupt is done | |
1394 | */ | |
ce082596 JR |
1395 | init_completion(&denali->complete); |
1396 | ||
43914a2d MY |
1397 | /* |
1398 | * the spinlock will be used to synchronize the ISR with any | |
1399 | * element that might be access shared data (interrupt status) | |
1400 | */ | |
ce082596 JR |
1401 | spin_lock_init(&denali->irq_lock); |
1402 | ||
1403 | /* indicate that MTD has not selected a valid bank yet */ | |
1404 | denali->flash_bank = CHIP_SELECT_INVALID; | |
1405 | ||
1406 | /* initialize our irq_status variable to indicate no interrupts */ | |
1407 | denali->irq_status = 0; | |
1408 | } | |
1409 | ||
2a0a288e | 1410 | int denali_init(struct denali_nand_info *denali) |
ce082596 | 1411 | { |
442f201b | 1412 | struct mtd_info *mtd = nand_to_mtd(&denali->nand); |
2a0a288e | 1413 | int ret; |
ce082596 | 1414 | |
2a0a288e | 1415 | if (denali->platform == INTEL_CE4100) { |
43914a2d MY |
1416 | /* |
1417 | * Due to a silicon limitation, we can only support | |
5bac3acf C |
1418 | * ONFI timing mode 1 and below. |
1419 | */ | |
345b1d3b | 1420 | if (onfi_timing_mode < -1 || onfi_timing_mode > 1) { |
2a0a288e DN |
1421 | pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n"); |
1422 | return -EINVAL; | |
ce082596 JR |
1423 | } |
1424 | } | |
1425 | ||
e07caa36 HS |
1426 | /* allocate a temporary buffer for nand_scan_ident() */ |
1427 | denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE, | |
1428 | GFP_DMA | GFP_KERNEL); | |
1429 | if (!denali->buf.buf) | |
1430 | return -ENOMEM; | |
ce082596 | 1431 | |
442f201b | 1432 | mtd->dev.parent = denali->dev; |
ce082596 JR |
1433 | denali_hw_init(denali); |
1434 | denali_drv_init(denali); | |
1435 | ||
7ebb8d06 MY |
1436 | /* Request IRQ after all the hardware initialization is finished */ |
1437 | ret = devm_request_irq(denali->dev, denali->irq, denali_isr, | |
1438 | IRQF_SHARED, DENALI_NAND_NAME, denali); | |
1439 | if (ret) { | |
789ccf17 | 1440 | dev_err(denali->dev, "Unable to request IRQ\n"); |
7ebb8d06 | 1441 | return ret; |
ce082596 JR |
1442 | } |
1443 | ||
1444 | /* now that our ISR is registered, we can enable interrupts */ | |
eda936ef | 1445 | denali_set_intr_modes(denali, true); |
442f201b | 1446 | mtd->name = "denali-nand"; |
ce082596 JR |
1447 | |
1448 | /* register the driver with the NAND core subsystem */ | |
1449 | denali->nand.select_chip = denali_select_chip; | |
1450 | denali->nand.cmdfunc = denali_cmdfunc; | |
1451 | denali->nand.read_byte = denali_read_byte; | |
1452 | denali->nand.waitfunc = denali_waitfunc; | |
1453 | ||
43914a2d MY |
1454 | /* |
1455 | * scan for NAND devices attached to the controller | |
ce082596 | 1456 | * this is the first stage in a two step process to register |
43914a2d MY |
1457 | * with the nand subsystem |
1458 | */ | |
a227d4e4 MY |
1459 | ret = nand_scan_ident(mtd, denali->max_banks, NULL); |
1460 | if (ret) | |
5c0eb900 | 1461 | goto failed_req_irq; |
5bac3acf | 1462 | |
e07caa36 HS |
1463 | /* allocate the right size buffer now */ |
1464 | devm_kfree(denali->dev, denali->buf.buf); | |
1465 | denali->buf.buf = devm_kzalloc(denali->dev, | |
442f201b | 1466 | mtd->writesize + mtd->oobsize, |
e07caa36 HS |
1467 | GFP_KERNEL); |
1468 | if (!denali->buf.buf) { | |
1469 | ret = -ENOMEM; | |
1470 | goto failed_req_irq; | |
1471 | } | |
1472 | ||
1473 | /* Is 32-bit DMA supported? */ | |
1474 | ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32)); | |
1475 | if (ret) { | |
789ccf17 | 1476 | dev_err(denali->dev, "No usable DMA configuration\n"); |
e07caa36 HS |
1477 | goto failed_req_irq; |
1478 | } | |
1479 | ||
1480 | denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf, | |
442f201b | 1481 | mtd->writesize + mtd->oobsize, |
e07caa36 HS |
1482 | DMA_BIDIRECTIONAL); |
1483 | if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) { | |
789ccf17 | 1484 | dev_err(denali->dev, "Failed to map DMA buffer\n"); |
e07caa36 | 1485 | ret = -EIO; |
5c0eb900 | 1486 | goto failed_req_irq; |
66406524 CD |
1487 | } |
1488 | ||
43914a2d MY |
1489 | /* |
1490 | * support for multi nand | |
1491 | * MTD known nothing about multi nand, so we should tell it | |
1492 | * the real pagesize and anything necessery | |
08b9ab99 CD |
1493 | */ |
1494 | denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
01a1d524 MY |
1495 | denali->nand.chipsize <<= denali->devnum - 1; |
1496 | denali->nand.page_shift += denali->devnum - 1; | |
08b9ab99 CD |
1497 | denali->nand.pagemask = (denali->nand.chipsize >> |
1498 | denali->nand.page_shift) - 1; | |
01a1d524 | 1499 | denali->nand.bbt_erase_shift += denali->devnum - 1; |
08b9ab99 | 1500 | denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift; |
01a1d524 MY |
1501 | denali->nand.chip_shift += denali->devnum - 1; |
1502 | mtd->writesize <<= denali->devnum - 1; | |
1503 | mtd->oobsize <<= denali->devnum - 1; | |
1504 | mtd->erasesize <<= denali->devnum - 1; | |
442f201b | 1505 | mtd->size = denali->nand.numchips * denali->nand.chipsize; |
08b9ab99 CD |
1506 | denali->bbtskipbytes *= denali->devnum; |
1507 | ||
43914a2d MY |
1508 | /* |
1509 | * second stage of the NAND scan | |
5bac3acf | 1510 | * this stage requires information regarding ECC and |
43914a2d MY |
1511 | * bad block management. |
1512 | */ | |
ce082596 JR |
1513 | |
1514 | /* Bad block management */ | |
1515 | denali->nand.bbt_td = &bbt_main_descr; | |
1516 | denali->nand.bbt_md = &bbt_mirror_descr; | |
1517 | ||
1518 | /* skip the scan for now until we have OOB read and write support */ | |
bb9ebd4e | 1519 | denali->nand.bbt_options |= NAND_BBT_USE_FLASH; |
a40f7341 | 1520 | denali->nand.options |= NAND_SKIP_BBTSCAN; |
ce082596 JR |
1521 | denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; |
1522 | ||
d99d7282 GM |
1523 | /* no subpage writes on denali */ |
1524 | denali->nand.options |= NAND_NO_SUBPAGE_WRITE; | |
1525 | ||
43914a2d MY |
1526 | /* |
1527 | * Denali Controller only support 15bit and 8bit ECC in MRST, | |
db9a3210 CD |
1528 | * so just let controller do 15bit ECC for MLC and 8bit ECC for |
1529 | * SLC if possible. | |
1530 | * */ | |
1d0ed69d | 1531 | if (!nand_is_slc(&denali->nand) && |
442f201b BB |
1532 | (mtd->oobsize > (denali->bbtskipbytes + |
1533 | ECC_15BITS * (mtd->writesize / | |
db9a3210 CD |
1534 | ECC_SECTOR_SIZE)))) { |
1535 | /* if MLC OOB size is large enough, use 15bit ECC*/ | |
6a918bad | 1536 | denali->nand.ecc.strength = 15; |
db9a3210 | 1537 | denali->nand.ecc.bytes = ECC_15BITS; |
24c3fa36 | 1538 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
442f201b BB |
1539 | } else if (mtd->oobsize < (denali->bbtskipbytes + |
1540 | ECC_8BITS * (mtd->writesize / | |
db9a3210 | 1541 | ECC_SECTOR_SIZE))) { |
8125450c | 1542 | pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes"); |
5c0eb900 | 1543 | goto failed_req_irq; |
db9a3210 | 1544 | } else { |
6a918bad | 1545 | denali->nand.ecc.strength = 8; |
db9a3210 | 1546 | denali->nand.ecc.bytes = ECC_8BITS; |
24c3fa36 | 1547 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 JR |
1548 | } |
1549 | ||
14fad62b | 1550 | mtd_set_ooblayout(mtd, &denali_ooblayout_ops); |
08b9ab99 | 1551 | denali->nand.ecc.bytes *= denali->devnum; |
6a918bad | 1552 | denali->nand.ecc.strength *= denali->devnum; |
db9a3210 | 1553 | |
ce082596 | 1554 | /* override the default read operations */ |
08b9ab99 | 1555 | denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum; |
ce082596 JR |
1556 | denali->nand.ecc.read_page = denali_read_page; |
1557 | denali->nand.ecc.read_page_raw = denali_read_page_raw; | |
1558 | denali->nand.ecc.write_page = denali_write_page; | |
1559 | denali->nand.ecc.write_page_raw = denali_write_page_raw; | |
1560 | denali->nand.ecc.read_oob = denali_read_oob; | |
1561 | denali->nand.ecc.write_oob = denali_write_oob; | |
49c50b97 | 1562 | denali->nand.erase = denali_erase; |
ce082596 | 1563 | |
a227d4e4 MY |
1564 | ret = nand_scan_tail(mtd); |
1565 | if (ret) | |
5c0eb900 | 1566 | goto failed_req_irq; |
ce082596 | 1567 | |
442f201b | 1568 | ret = mtd_device_register(mtd, NULL, 0); |
ce082596 | 1569 | if (ret) { |
789ccf17 | 1570 | dev_err(denali->dev, "Failed to register MTD: %d\n", ret); |
5c0eb900 | 1571 | goto failed_req_irq; |
ce082596 JR |
1572 | } |
1573 | return 0; | |
1574 | ||
5c0eb900 | 1575 | failed_req_irq: |
2a0a288e DN |
1576 | denali_irq_cleanup(denali->irq, denali); |
1577 | ||
ce082596 JR |
1578 | return ret; |
1579 | } | |
2a0a288e | 1580 | EXPORT_SYMBOL(denali_init); |
ce082596 JR |
1581 | |
1582 | /* driver exit point */ | |
2a0a288e | 1583 | void denali_remove(struct denali_nand_info *denali) |
ce082596 | 1584 | { |
442f201b | 1585 | struct mtd_info *mtd = nand_to_mtd(&denali->nand); |
320092a0 BB |
1586 | /* |
1587 | * Pre-compute DMA buffer size to avoid any problems in case | |
1588 | * nand_release() ever changes in a way that mtd->writesize and | |
1589 | * mtd->oobsize are not reliable after this call. | |
1590 | */ | |
442f201b | 1591 | int bufsize = mtd->writesize + mtd->oobsize; |
320092a0 | 1592 | |
442f201b | 1593 | nand_release(mtd); |
2a0a288e | 1594 | denali_irq_cleanup(denali->irq, denali); |
320092a0 | 1595 | dma_unmap_single(denali->dev, denali->buf.dma_buf, bufsize, |
8125450c | 1596 | DMA_BIDIRECTIONAL); |
ce082596 | 1597 | } |
2a0a288e | 1598 | EXPORT_SYMBOL(denali_remove); |