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Commit | Line | Data |
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ce082596 JR |
1 | /* |
2 | * NAND Flash Controller Device Driver | |
3 | * Copyright © 2009-2010, Intel Corporation and its suppliers. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | */ | |
ce082596 JR |
19 | #include <linux/interrupt.h> |
20 | #include <linux/delay.h> | |
84457949 | 21 | #include <linux/dma-mapping.h> |
ce082596 JR |
22 | #include <linux/wait.h> |
23 | #include <linux/mutex.h> | |
b8664b37 | 24 | #include <linux/slab.h> |
ce082596 JR |
25 | #include <linux/mtd/mtd.h> |
26 | #include <linux/module.h> | |
27 | ||
28 | #include "denali.h" | |
29 | ||
30 | MODULE_LICENSE("GPL"); | |
31 | ||
43914a2d MY |
32 | /* |
33 | * We define a module parameter that allows the user to override | |
ce082596 JR |
34 | * the hardware and decide what timing mode should be used. |
35 | */ | |
36 | #define NAND_DEFAULT_TIMINGS -1 | |
37 | ||
38 | static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; | |
39 | module_param(onfi_timing_mode, int, S_IRUGO); | |
8125450c MY |
40 | MODULE_PARM_DESC(onfi_timing_mode, |
41 | "Overrides default ONFI setting. -1 indicates use default timings"); | |
ce082596 JR |
42 | |
43 | #define DENALI_NAND_NAME "denali-nand" | |
44 | ||
43914a2d MY |
45 | /* |
46 | * We define a macro here that combines all interrupts this driver uses into | |
47 | * a single constant value, for convenience. | |
48 | */ | |
9589bf5b JI |
49 | #define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \ |
50 | INTR_STATUS__ECC_TRANSACTION_DONE | \ | |
51 | INTR_STATUS__ECC_ERR | \ | |
52 | INTR_STATUS__PROGRAM_FAIL | \ | |
53 | INTR_STATUS__LOAD_COMP | \ | |
54 | INTR_STATUS__PROGRAM_COMP | \ | |
55 | INTR_STATUS__TIME_OUT | \ | |
56 | INTR_STATUS__ERASE_FAIL | \ | |
57 | INTR_STATUS__RST_COMP | \ | |
58 | INTR_STATUS__ERASE_COMP) | |
ce082596 | 59 | |
43914a2d MY |
60 | /* |
61 | * indicates whether or not the internal value for the flash bank is | |
62 | * valid or not | |
63 | */ | |
5bac3acf | 64 | #define CHIP_SELECT_INVALID -1 |
ce082596 JR |
65 | |
66 | #define SUPPORT_8BITECC 1 | |
67 | ||
43914a2d MY |
68 | /* |
69 | * This macro divides two integers and rounds fractional values up | |
70 | * to the nearest integer value. | |
71 | */ | |
ce082596 JR |
72 | #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y))) |
73 | ||
43914a2d MY |
74 | /* |
75 | * this macro allows us to convert from an MTD structure to our own | |
ce082596 JR |
76 | * device context (denali) structure. |
77 | */ | |
78 | #define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd) | |
79 | ||
43914a2d MY |
80 | /* |
81 | * These constants are defined by the driver to enable common driver | |
82 | * configuration options. | |
83 | */ | |
ce082596 JR |
84 | #define SPARE_ACCESS 0x41 |
85 | #define MAIN_ACCESS 0x42 | |
86 | #define MAIN_SPARE_ACCESS 0x43 | |
2902330e | 87 | #define PIPELINE_ACCESS 0x2000 |
ce082596 JR |
88 | |
89 | #define DENALI_READ 0 | |
90 | #define DENALI_WRITE 0x100 | |
91 | ||
92 | /* types of device accesses. We can issue commands and get status */ | |
93 | #define COMMAND_CYCLE 0 | |
94 | #define ADDR_CYCLE 1 | |
95 | #define STATUS_CYCLE 2 | |
96 | ||
43914a2d MY |
97 | /* |
98 | * this is a helper macro that allows us to | |
99 | * format the bank into the proper bits for the controller | |
100 | */ | |
ce082596 JR |
101 | #define BANK(x) ((x) << 24) |
102 | ||
ce082596 JR |
103 | /* forward declarations */ |
104 | static void clear_interrupts(struct denali_nand_info *denali); | |
bdca6dae CD |
105 | static uint32_t wait_for_irq(struct denali_nand_info *denali, |
106 | uint32_t irq_mask); | |
107 | static void denali_irq_enable(struct denali_nand_info *denali, | |
108 | uint32_t int_mask); | |
ce082596 JR |
109 | static uint32_t read_interrupt_status(struct denali_nand_info *denali); |
110 | ||
43914a2d MY |
111 | /* |
112 | * Certain operations for the denali NAND controller use an indexed mode to | |
113 | * read/write data. The operation is performed by writing the address value | |
114 | * of the command to the device memory followed by the data. This function | |
bdca6dae | 115 | * abstracts this common operation. |
43914a2d | 116 | */ |
bdca6dae CD |
117 | static void index_addr(struct denali_nand_info *denali, |
118 | uint32_t address, uint32_t data) | |
ce082596 | 119 | { |
24c3fa36 CD |
120 | iowrite32(address, denali->flash_mem); |
121 | iowrite32(data, denali->flash_mem + 0x10); | |
ce082596 JR |
122 | } |
123 | ||
124 | /* Perform an indexed read of the device */ | |
125 | static void index_addr_read_data(struct denali_nand_info *denali, | |
126 | uint32_t address, uint32_t *pdata) | |
127 | { | |
24c3fa36 | 128 | iowrite32(address, denali->flash_mem); |
ce082596 JR |
129 | *pdata = ioread32(denali->flash_mem + 0x10); |
130 | } | |
131 | ||
43914a2d MY |
132 | /* |
133 | * We need to buffer some data for some of the NAND core routines. | |
134 | * The operations manage buffering that data. | |
135 | */ | |
ce082596 JR |
136 | static void reset_buf(struct denali_nand_info *denali) |
137 | { | |
138 | denali->buf.head = denali->buf.tail = 0; | |
139 | } | |
140 | ||
141 | static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte) | |
142 | { | |
ce082596 JR |
143 | denali->buf.buf[denali->buf.tail++] = byte; |
144 | } | |
145 | ||
146 | /* reads the status of the device */ | |
147 | static void read_status(struct denali_nand_info *denali) | |
148 | { | |
5637b69d | 149 | uint32_t cmd; |
ce082596 JR |
150 | |
151 | /* initialize the data buffer to store status */ | |
152 | reset_buf(denali); | |
153 | ||
f0bc0c77 CD |
154 | cmd = ioread32(denali->flash_reg + WRITE_PROTECT); |
155 | if (cmd) | |
156 | write_byte_to_buf(denali, NAND_STATUS_WP); | |
157 | else | |
158 | write_byte_to_buf(denali, 0); | |
ce082596 JR |
159 | } |
160 | ||
161 | /* resets a specific device connected to the core */ | |
162 | static void reset_bank(struct denali_nand_info *denali) | |
163 | { | |
5637b69d | 164 | uint32_t irq_status; |
8125450c | 165 | uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT; |
ce082596 JR |
166 | |
167 | clear_interrupts(denali); | |
168 | ||
9589bf5b | 169 | iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET); |
ce082596 JR |
170 | |
171 | irq_status = wait_for_irq(denali, irq_mask); | |
5bac3acf | 172 | |
9589bf5b | 173 | if (irq_status & INTR_STATUS__TIME_OUT) |
84457949 | 174 | dev_err(denali->dev, "reset bank failed.\n"); |
ce082596 JR |
175 | } |
176 | ||
177 | /* Reset the flash controller */ | |
eda936ef | 178 | static uint16_t denali_nand_reset(struct denali_nand_info *denali) |
ce082596 | 179 | { |
93e3c8ad | 180 | int i; |
ce082596 | 181 | |
84457949 | 182 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
8125450c | 183 | __FILE__, __LINE__, __func__); |
ce082596 | 184 | |
8125450c | 185 | for (i = 0; i < denali->max_banks; i++) |
9589bf5b JI |
186 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
187 | denali->flash_reg + INTR_STATUS(i)); | |
ce082596 | 188 | |
8125450c | 189 | for (i = 0; i < denali->max_banks; i++) { |
9589bf5b | 190 | iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); |
8125450c | 191 | while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & |
9589bf5b | 192 | (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT))) |
628bfd41 | 193 | cpu_relax(); |
9589bf5b JI |
194 | if (ioread32(denali->flash_reg + INTR_STATUS(i)) & |
195 | INTR_STATUS__TIME_OUT) | |
84457949 | 196 | dev_dbg(denali->dev, |
ce082596 JR |
197 | "NAND Reset operation timed out on bank %d\n", i); |
198 | } | |
199 | ||
c89eeda8 | 200 | for (i = 0; i < denali->max_banks; i++) |
9589bf5b | 201 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
8125450c | 202 | denali->flash_reg + INTR_STATUS(i)); |
ce082596 JR |
203 | |
204 | return PASS; | |
205 | } | |
206 | ||
43914a2d MY |
207 | /* |
208 | * this routine calculates the ONFI timing values for a given mode and | |
bdca6dae CD |
209 | * programs the clocking register accordingly. The mode is determined by |
210 | * the get_onfi_nand_para routine. | |
ce082596 | 211 | */ |
eda936ef | 212 | static void nand_onfi_timing_set(struct denali_nand_info *denali, |
bdca6dae | 213 | uint16_t mode) |
ce082596 JR |
214 | { |
215 | uint16_t Trea[6] = {40, 30, 25, 20, 20, 16}; | |
216 | uint16_t Trp[6] = {50, 25, 17, 15, 12, 10}; | |
217 | uint16_t Treh[6] = {30, 15, 15, 10, 10, 7}; | |
218 | uint16_t Trc[6] = {100, 50, 35, 30, 25, 20}; | |
219 | uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15}; | |
220 | uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5}; | |
221 | uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25}; | |
222 | uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70}; | |
223 | uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100}; | |
224 | uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100}; | |
225 | uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60}; | |
226 | uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15}; | |
227 | ||
ce082596 JR |
228 | uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid; |
229 | uint16_t dv_window = 0; | |
230 | uint16_t en_lo, en_hi; | |
231 | uint16_t acc_clks; | |
232 | uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; | |
233 | ||
84457949 | 234 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
8125450c | 235 | __FILE__, __LINE__, __func__); |
ce082596 JR |
236 | |
237 | en_lo = CEIL_DIV(Trp[mode], CLK_X); | |
238 | en_hi = CEIL_DIV(Treh[mode], CLK_X); | |
239 | #if ONFI_BLOOM_TIME | |
240 | if ((en_hi * CLK_X) < (Treh[mode] + 2)) | |
241 | en_hi++; | |
242 | #endif | |
243 | ||
244 | if ((en_lo + en_hi) * CLK_X < Trc[mode]) | |
245 | en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X); | |
246 | ||
247 | if ((en_lo + en_hi) < CLK_MULTI) | |
248 | en_lo += CLK_MULTI - en_lo - en_hi; | |
249 | ||
250 | while (dv_window < 8) { | |
251 | data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode]; | |
252 | ||
253 | data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode]; | |
254 | ||
8125450c MY |
255 | data_invalid = data_invalid_rhoh < data_invalid_rloh ? |
256 | data_invalid_rhoh : data_invalid_rloh; | |
ce082596 JR |
257 | |
258 | dv_window = data_invalid - Trea[mode]; | |
259 | ||
260 | if (dv_window < 8) | |
261 | en_lo++; | |
262 | } | |
263 | ||
264 | acc_clks = CEIL_DIV(Trea[mode], CLK_X); | |
265 | ||
7d14ecd0 | 266 | while (acc_clks * CLK_X - Trea[mode] < 3) |
ce082596 JR |
267 | acc_clks++; |
268 | ||
7d14ecd0 | 269 | if (data_invalid - acc_clks * CLK_X < 2) |
84457949 | 270 | dev_warn(denali->dev, "%s, Line %d: Warning!\n", |
8125450c | 271 | __FILE__, __LINE__); |
ce082596 JR |
272 | |
273 | addr_2_data = CEIL_DIV(Tadl[mode], CLK_X); | |
274 | re_2_we = CEIL_DIV(Trhw[mode], CLK_X); | |
275 | re_2_re = CEIL_DIV(Trhz[mode], CLK_X); | |
276 | we_2_re = CEIL_DIV(Twhr[mode], CLK_X); | |
277 | cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X); | |
ce082596 JR |
278 | if (cs_cnt == 0) |
279 | cs_cnt = 1; | |
280 | ||
281 | if (Tcea[mode]) { | |
7d14ecd0 | 282 | while (cs_cnt * CLK_X + Trea[mode] < Tcea[mode]) |
ce082596 JR |
283 | cs_cnt++; |
284 | } | |
285 | ||
286 | #if MODE5_WORKAROUND | |
287 | if (mode == 5) | |
288 | acc_clks = 5; | |
289 | #endif | |
290 | ||
291 | /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */ | |
7d14ecd0 MY |
292 | if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 && |
293 | ioread32(denali->flash_reg + DEVICE_ID) == 0x88) | |
ce082596 JR |
294 | acc_clks = 6; |
295 | ||
24c3fa36 CD |
296 | iowrite32(acc_clks, denali->flash_reg + ACC_CLKS); |
297 | iowrite32(re_2_we, denali->flash_reg + RE_2_WE); | |
298 | iowrite32(re_2_re, denali->flash_reg + RE_2_RE); | |
299 | iowrite32(we_2_re, denali->flash_reg + WE_2_RE); | |
300 | iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA); | |
301 | iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT); | |
302 | iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT); | |
303 | iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT); | |
ce082596 JR |
304 | } |
305 | ||
ce082596 JR |
306 | /* queries the NAND device to see what ONFI modes it supports. */ |
307 | static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) | |
308 | { | |
309 | int i; | |
43914a2d MY |
310 | |
311 | /* | |
312 | * we needn't to do a reset here because driver has already | |
4c03bbdf | 313 | * reset all the banks before |
43914a2d | 314 | */ |
ce082596 JR |
315 | if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
316 | ONFI_TIMING_MODE__VALUE)) | |
317 | return FAIL; | |
318 | ||
319 | for (i = 5; i > 0; i--) { | |
bdca6dae CD |
320 | if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
321 | (0x01 << i)) | |
ce082596 JR |
322 | break; |
323 | } | |
324 | ||
eda936ef | 325 | nand_onfi_timing_set(denali, i); |
ce082596 | 326 | |
43914a2d MY |
327 | /* |
328 | * By now, all the ONFI devices we know support the page cache | |
329 | * rw feature. So here we enable the pipeline_rw_ahead feature | |
330 | */ | |
ce082596 JR |
331 | /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */ |
332 | /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */ | |
333 | ||
334 | return PASS; | |
335 | } | |
336 | ||
4c03bbdf CD |
337 | static void get_samsung_nand_para(struct denali_nand_info *denali, |
338 | uint8_t device_id) | |
ce082596 | 339 | { |
4c03bbdf | 340 | if (device_id == 0xd3) { /* Samsung K9WAG08U1A */ |
ce082596 | 341 | /* Set timing register values according to datasheet */ |
24c3fa36 CD |
342 | iowrite32(5, denali->flash_reg + ACC_CLKS); |
343 | iowrite32(20, denali->flash_reg + RE_2_WE); | |
344 | iowrite32(12, denali->flash_reg + WE_2_RE); | |
345 | iowrite32(14, denali->flash_reg + ADDR_2_DATA); | |
346 | iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT); | |
347 | iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT); | |
348 | iowrite32(2, denali->flash_reg + CS_SETUP_CNT); | |
ce082596 | 349 | } |
ce082596 JR |
350 | } |
351 | ||
352 | static void get_toshiba_nand_para(struct denali_nand_info *denali) | |
353 | { | |
ce082596 JR |
354 | uint32_t tmp; |
355 | ||
43914a2d MY |
356 | /* |
357 | * Workaround to fix a controller bug which reports a wrong | |
358 | * spare area size for some kind of Toshiba NAND device | |
359 | */ | |
ce082596 JR |
360 | if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && |
361 | (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { | |
24c3fa36 | 362 | iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); |
ce082596 JR |
363 | tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) * |
364 | ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
24c3fa36 | 365 | iowrite32(tmp, |
bdca6dae | 366 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
ce082596 | 367 | #if SUPPORT_15BITECC |
24c3fa36 | 368 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 369 | #elif SUPPORT_8BITECC |
24c3fa36 | 370 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 JR |
371 | #endif |
372 | } | |
ce082596 JR |
373 | } |
374 | ||
ef41e1bb CD |
375 | static void get_hynix_nand_para(struct denali_nand_info *denali, |
376 | uint8_t device_id) | |
ce082596 | 377 | { |
ce082596 JR |
378 | uint32_t main_size, spare_size; |
379 | ||
ef41e1bb | 380 | switch (device_id) { |
ce082596 JR |
381 | case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */ |
382 | case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */ | |
24c3fa36 CD |
383 | iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK); |
384 | iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); | |
385 | iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
bdca6dae CD |
386 | main_size = 4096 * |
387 | ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
388 | spare_size = 224 * | |
389 | ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
24c3fa36 | 390 | iowrite32(main_size, |
bdca6dae | 391 | denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); |
24c3fa36 | 392 | iowrite32(spare_size, |
bdca6dae | 393 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
24c3fa36 | 394 | iowrite32(0, denali->flash_reg + DEVICE_WIDTH); |
ce082596 | 395 | #if SUPPORT_15BITECC |
24c3fa36 | 396 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 397 | #elif SUPPORT_8BITECC |
24c3fa36 | 398 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 399 | #endif |
ce082596 JR |
400 | break; |
401 | default: | |
84457949 | 402 | dev_warn(denali->dev, |
8125450c MY |
403 | "Spectra: Unknown Hynix NAND (Device ID: 0x%x).\n" |
404 | "Will use default parameter values instead.\n", | |
405 | device_id); | |
ce082596 JR |
406 | } |
407 | } | |
408 | ||
43914a2d MY |
409 | /* |
410 | * determines how many NAND chips are connected to the controller. Note for | |
b292c341 | 411 | * Intel CE4100 devices we don't support more than one device. |
ce082596 JR |
412 | */ |
413 | static void find_valid_banks(struct denali_nand_info *denali) | |
414 | { | |
c89eeda8 | 415 | uint32_t id[denali->max_banks]; |
ce082596 JR |
416 | int i; |
417 | ||
418 | denali->total_used_banks = 1; | |
c89eeda8 | 419 | for (i = 0; i < denali->max_banks; i++) { |
3157d1ed MY |
420 | index_addr(denali, MODE_11 | (i << 24) | 0, 0x90); |
421 | index_addr(denali, MODE_11 | (i << 24) | 1, 0); | |
8125450c | 422 | index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]); |
ce082596 | 423 | |
84457949 | 424 | dev_dbg(denali->dev, |
ce082596 JR |
425 | "Return 1st ID for bank[%d]: %x\n", i, id[i]); |
426 | ||
427 | if (i == 0) { | |
428 | if (!(id[i] & 0x0ff)) | |
429 | break; /* WTF? */ | |
430 | } else { | |
431 | if ((id[i] & 0x0ff) == (id[0] & 0x0ff)) | |
432 | denali->total_used_banks++; | |
433 | else | |
434 | break; | |
435 | } | |
436 | } | |
437 | ||
345b1d3b | 438 | if (denali->platform == INTEL_CE4100) { |
43914a2d MY |
439 | /* |
440 | * Platform limitations of the CE4100 device limit | |
ce082596 | 441 | * users to a single chip solution for NAND. |
5bac3acf C |
442 | * Multichip support is not enabled. |
443 | */ | |
345b1d3b | 444 | if (denali->total_used_banks != 1) { |
84457949 | 445 | dev_err(denali->dev, |
8125450c | 446 | "Sorry, Intel CE4100 only supports a single NAND device.\n"); |
ce082596 JR |
447 | BUG(); |
448 | } | |
449 | } | |
84457949 | 450 | dev_dbg(denali->dev, |
ce082596 JR |
451 | "denali->total_used_banks: %d\n", denali->total_used_banks); |
452 | } | |
453 | ||
c89eeda8 JI |
454 | /* |
455 | * Use the configuration feature register to determine the maximum number of | |
456 | * banks that the hardware supports. | |
457 | */ | |
458 | static void detect_max_banks(struct denali_nand_info *denali) | |
459 | { | |
460 | uint32_t features = ioread32(denali->flash_reg + FEATURES); | |
461 | ||
462 | denali->max_banks = 2 << (features & FEATURES__N_BANKS); | |
463 | } | |
464 | ||
ce082596 JR |
465 | static void detect_partition_feature(struct denali_nand_info *denali) |
466 | { | |
43914a2d MY |
467 | /* |
468 | * For MRST platform, denali->fwblks represent the | |
66406524 CD |
469 | * number of blocks firmware is taken, |
470 | * FW is in protect partition and MTD driver has no | |
471 | * permission to access it. So let driver know how many | |
472 | * blocks it can't touch. | |
43914a2d | 473 | */ |
ce082596 | 474 | if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) { |
9589bf5b JI |
475 | if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) & |
476 | PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) { | |
66406524 | 477 | denali->fwblks = |
9589bf5b JI |
478 | ((ioread32(denali->flash_reg + MIN_MAX_BANK(1)) & |
479 | MIN_MAX_BANK__MIN_VALUE) * | |
66406524 | 480 | denali->blksperchip) |
ce082596 | 481 | + |
9589bf5b JI |
482 | (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) & |
483 | MIN_BLK_ADDR__VALUE); | |
8125450c | 484 | } else { |
66406524 | 485 | denali->fwblks = SPECTRA_START_BLOCK; |
8125450c MY |
486 | } |
487 | } else { | |
66406524 | 488 | denali->fwblks = SPECTRA_START_BLOCK; |
8125450c | 489 | } |
ce082596 JR |
490 | } |
491 | ||
eda936ef | 492 | static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) |
ce082596 JR |
493 | { |
494 | uint16_t status = PASS; | |
d68a5c3d | 495 | uint32_t id_bytes[8], addr; |
93e3c8ad MY |
496 | uint8_t maf_id, device_id; |
497 | int i; | |
ce082596 | 498 | |
8125450c | 499 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
7cfffac0 | 500 | __FILE__, __LINE__, __func__); |
ce082596 | 501 | |
43914a2d MY |
502 | /* |
503 | * Use read id method to get device ID and other params. | |
504 | * For some NAND chips, controller can't report the correct | |
505 | * device ID by reading from DEVICE_ID register | |
506 | */ | |
3157d1ed MY |
507 | addr = MODE_11 | BANK(denali->flash_bank); |
508 | index_addr(denali, addr | 0, 0x90); | |
509 | index_addr(denali, addr | 1, 0); | |
d68a5c3d | 510 | for (i = 0; i < 8; i++) |
ef41e1bb CD |
511 | index_addr_read_data(denali, addr | 2, &id_bytes[i]); |
512 | maf_id = id_bytes[0]; | |
513 | device_id = id_bytes[1]; | |
ce082596 JR |
514 | |
515 | if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & | |
516 | ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ | |
517 | if (FAIL == get_onfi_nand_para(denali)) | |
518 | return FAIL; | |
ef41e1bb | 519 | } else if (maf_id == 0xEC) { /* Samsung NAND */ |
4c03bbdf | 520 | get_samsung_nand_para(denali, device_id); |
ef41e1bb | 521 | } else if (maf_id == 0x98) { /* Toshiba NAND */ |
ce082596 | 522 | get_toshiba_nand_para(denali); |
ef41e1bb CD |
523 | } else if (maf_id == 0xAD) { /* Hynix NAND */ |
524 | get_hynix_nand_para(denali, device_id); | |
ce082596 JR |
525 | } |
526 | ||
84457949 | 527 | dev_info(denali->dev, |
8125450c | 528 | "Dump timing register values:\n" |
7cfffac0 CD |
529 | "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" |
530 | "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" | |
ce082596 JR |
531 | "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", |
532 | ioread32(denali->flash_reg + ACC_CLKS), | |
533 | ioread32(denali->flash_reg + RE_2_WE), | |
7cfffac0 | 534 | ioread32(denali->flash_reg + RE_2_RE), |
ce082596 JR |
535 | ioread32(denali->flash_reg + WE_2_RE), |
536 | ioread32(denali->flash_reg + ADDR_2_DATA), | |
537 | ioread32(denali->flash_reg + RDWR_EN_LO_CNT), | |
538 | ioread32(denali->flash_reg + RDWR_EN_HI_CNT), | |
539 | ioread32(denali->flash_reg + CS_SETUP_CNT)); | |
540 | ||
ce082596 JR |
541 | find_valid_banks(denali); |
542 | ||
543 | detect_partition_feature(denali); | |
544 | ||
43914a2d MY |
545 | /* |
546 | * If the user specified to override the default timings | |
5bac3acf | 547 | * with a specific ONFI mode, we apply those changes here. |
ce082596 JR |
548 | */ |
549 | if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) | |
eda936ef | 550 | nand_onfi_timing_set(denali, onfi_timing_mode); |
ce082596 JR |
551 | |
552 | return status; | |
553 | } | |
554 | ||
eda936ef | 555 | static void denali_set_intr_modes(struct denali_nand_info *denali, |
ce082596 JR |
556 | uint16_t INT_ENABLE) |
557 | { | |
84457949 | 558 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
8125450c | 559 | __FILE__, __LINE__, __func__); |
ce082596 JR |
560 | |
561 | if (INT_ENABLE) | |
24c3fa36 | 562 | iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE); |
ce082596 | 563 | else |
24c3fa36 | 564 | iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE); |
ce082596 JR |
565 | } |
566 | ||
43914a2d MY |
567 | /* |
568 | * validation function to verify that the controlling software is making | |
b292c341 | 569 | * a valid request |
ce082596 JR |
570 | */ |
571 | static inline bool is_flash_bank_valid(int flash_bank) | |
572 | { | |
7d14ecd0 | 573 | return flash_bank >= 0 && flash_bank < 4; |
ce082596 JR |
574 | } |
575 | ||
576 | static void denali_irq_init(struct denali_nand_info *denali) | |
577 | { | |
5637b69d | 578 | uint32_t int_mask; |
9589bf5b | 579 | int i; |
ce082596 JR |
580 | |
581 | /* Disable global interrupts */ | |
eda936ef | 582 | denali_set_intr_modes(denali, false); |
ce082596 JR |
583 | |
584 | int_mask = DENALI_IRQ_ALL; | |
585 | ||
586 | /* Clear all status bits */ | |
c89eeda8 | 587 | for (i = 0; i < denali->max_banks; ++i) |
9589bf5b | 588 | iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i)); |
ce082596 JR |
589 | |
590 | denali_irq_enable(denali, int_mask); | |
591 | } | |
592 | ||
593 | static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali) | |
594 | { | |
eda936ef | 595 | denali_set_intr_modes(denali, false); |
ce082596 JR |
596 | free_irq(irqnum, denali); |
597 | } | |
598 | ||
bdca6dae CD |
599 | static void denali_irq_enable(struct denali_nand_info *denali, |
600 | uint32_t int_mask) | |
ce082596 | 601 | { |
9589bf5b JI |
602 | int i; |
603 | ||
c89eeda8 | 604 | for (i = 0; i < denali->max_banks; ++i) |
9589bf5b | 605 | iowrite32(int_mask, denali->flash_reg + INTR_EN(i)); |
ce082596 JR |
606 | } |
607 | ||
43914a2d MY |
608 | /* |
609 | * This function only returns when an interrupt that this driver cares about | |
5bac3acf | 610 | * occurs. This is to reduce the overhead of servicing interrupts |
ce082596 JR |
611 | */ |
612 | static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) | |
613 | { | |
a99d1796 | 614 | return read_interrupt_status(denali) & DENALI_IRQ_ALL; |
ce082596 JR |
615 | } |
616 | ||
617 | /* Interrupts are cleared by writing a 1 to the appropriate status bit */ | |
bdca6dae CD |
618 | static inline void clear_interrupt(struct denali_nand_info *denali, |
619 | uint32_t irq_mask) | |
ce082596 | 620 | { |
5637b69d | 621 | uint32_t intr_status_reg; |
ce082596 | 622 | |
9589bf5b | 623 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
ce082596 | 624 | |
24c3fa36 | 625 | iowrite32(irq_mask, denali->flash_reg + intr_status_reg); |
ce082596 JR |
626 | } |
627 | ||
628 | static void clear_interrupts(struct denali_nand_info *denali) | |
629 | { | |
5637b69d MY |
630 | uint32_t status; |
631 | ||
ce082596 JR |
632 | spin_lock_irq(&denali->irq_lock); |
633 | ||
634 | status = read_interrupt_status(denali); | |
8ae61ebd | 635 | clear_interrupt(denali, status); |
ce082596 | 636 | |
ce082596 JR |
637 | denali->irq_status = 0x0; |
638 | spin_unlock_irq(&denali->irq_lock); | |
639 | } | |
640 | ||
641 | static uint32_t read_interrupt_status(struct denali_nand_info *denali) | |
642 | { | |
5637b69d | 643 | uint32_t intr_status_reg; |
ce082596 | 644 | |
9589bf5b | 645 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
ce082596 JR |
646 | |
647 | return ioread32(denali->flash_reg + intr_status_reg); | |
648 | } | |
649 | ||
43914a2d MY |
650 | /* |
651 | * This is the interrupt service routine. It handles all interrupts | |
652 | * sent to this device. Note that on CE4100, this is a shared interrupt. | |
ce082596 JR |
653 | */ |
654 | static irqreturn_t denali_isr(int irq, void *dev_id) | |
655 | { | |
656 | struct denali_nand_info *denali = dev_id; | |
5637b69d | 657 | uint32_t irq_status; |
ce082596 JR |
658 | irqreturn_t result = IRQ_NONE; |
659 | ||
660 | spin_lock(&denali->irq_lock); | |
661 | ||
43914a2d | 662 | /* check to see if a valid NAND chip has been selected. */ |
345b1d3b | 663 | if (is_flash_bank_valid(denali->flash_bank)) { |
43914a2d MY |
664 | /* |
665 | * check to see if controller generated the interrupt, | |
666 | * since this is a shared interrupt | |
667 | */ | |
bdca6dae CD |
668 | irq_status = denali_irq_detected(denali); |
669 | if (irq_status != 0) { | |
ce082596 JR |
670 | /* handle interrupt */ |
671 | /* first acknowledge it */ | |
672 | clear_interrupt(denali, irq_status); | |
43914a2d MY |
673 | /* |
674 | * store the status in the device context for someone | |
675 | * to read | |
676 | */ | |
ce082596 JR |
677 | denali->irq_status |= irq_status; |
678 | /* notify anyone who cares that it happened */ | |
679 | complete(&denali->complete); | |
680 | /* tell the OS that we've handled this */ | |
681 | result = IRQ_HANDLED; | |
682 | } | |
683 | } | |
684 | spin_unlock(&denali->irq_lock); | |
685 | return result; | |
686 | } | |
687 | #define BANK(x) ((x) << 24) | |
688 | ||
689 | static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) | |
690 | { | |
5637b69d MY |
691 | unsigned long comp_res; |
692 | uint32_t intr_status; | |
ce082596 JR |
693 | unsigned long timeout = msecs_to_jiffies(1000); |
694 | ||
345b1d3b | 695 | do { |
bdca6dae CD |
696 | comp_res = |
697 | wait_for_completion_timeout(&denali->complete, timeout); | |
ce082596 JR |
698 | spin_lock_irq(&denali->irq_lock); |
699 | intr_status = denali->irq_status; | |
700 | ||
345b1d3b | 701 | if (intr_status & irq_mask) { |
ce082596 JR |
702 | denali->irq_status &= ~irq_mask; |
703 | spin_unlock_irq(&denali->irq_lock); | |
ce082596 JR |
704 | /* our interrupt was detected */ |
705 | break; | |
ce082596 | 706 | } |
8125450c MY |
707 | |
708 | /* | |
709 | * these are not the interrupts you are looking for - | |
710 | * need to wait again | |
711 | */ | |
712 | spin_unlock_irq(&denali->irq_lock); | |
ce082596 JR |
713 | } while (comp_res != 0); |
714 | ||
345b1d3b | 715 | if (comp_res == 0) { |
ce082596 | 716 | /* timeout */ |
2a0a288e | 717 | pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n", |
5bac3acf | 718 | intr_status, irq_mask); |
ce082596 JR |
719 | |
720 | intr_status = 0; | |
721 | } | |
722 | return intr_status; | |
723 | } | |
724 | ||
43914a2d MY |
725 | /* |
726 | * This helper function setups the registers for ECC and whether or not | |
727 | * the spare area will be transferred. | |
728 | */ | |
5bac3acf | 729 | static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, |
ce082596 JR |
730 | bool transfer_spare) |
731 | { | |
5637b69d | 732 | int ecc_en_flag, transfer_spare_flag; |
ce082596 JR |
733 | |
734 | /* set ECC, transfer spare bits if needed */ | |
735 | ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; | |
736 | transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0; | |
737 | ||
738 | /* Enable spare area/ECC per user's request. */ | |
24c3fa36 | 739 | iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE); |
8125450c | 740 | iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG); |
ce082596 JR |
741 | } |
742 | ||
43914a2d MY |
743 | /* |
744 | * sends a pipeline command operation to the controller. See the Denali NAND | |
b292c341 | 745 | * controller's user guide for more information (section 4.2.3.6). |
ce082596 | 746 | */ |
bdca6dae | 747 | static int denali_send_pipeline_cmd(struct denali_nand_info *denali, |
8125450c MY |
748 | bool ecc_en, bool transfer_spare, |
749 | int access_type, int op) | |
ce082596 JR |
750 | { |
751 | int status = PASS; | |
5637b69d MY |
752 | uint32_t page_count = 1; |
753 | uint32_t addr, cmd, irq_status, irq_mask; | |
ce082596 | 754 | |
a99d1796 | 755 | if (op == DENALI_READ) |
9589bf5b | 756 | irq_mask = INTR_STATUS__LOAD_COMP; |
a99d1796 CD |
757 | else if (op == DENALI_WRITE) |
758 | irq_mask = 0; | |
759 | else | |
760 | BUG(); | |
ce082596 JR |
761 | |
762 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); | |
763 | ||
5bac3acf | 764 | clear_interrupts(denali); |
ce082596 JR |
765 | |
766 | addr = BANK(denali->flash_bank) | denali->page; | |
767 | ||
345b1d3b | 768 | if (op == DENALI_WRITE && access_type != SPARE_ACCESS) { |
5bac3acf | 769 | cmd = MODE_01 | addr; |
24c3fa36 | 770 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 771 | } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) { |
ce082596 | 772 | /* read spare area */ |
5bac3acf | 773 | cmd = MODE_10 | addr; |
3157d1ed | 774 | index_addr(denali, cmd, access_type); |
ce082596 | 775 | |
5bac3acf | 776 | cmd = MODE_01 | addr; |
24c3fa36 | 777 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 778 | } else if (op == DENALI_READ) { |
ce082596 | 779 | /* setup page read request for access type */ |
5bac3acf | 780 | cmd = MODE_10 | addr; |
3157d1ed | 781 | index_addr(denali, cmd, access_type); |
ce082596 | 782 | |
43914a2d MY |
783 | /* |
784 | * page 33 of the NAND controller spec indicates we should not | |
785 | * use the pipeline commands in Spare area only mode. | |
786 | * So we don't. | |
ce082596 | 787 | */ |
345b1d3b | 788 | if (access_type == SPARE_ACCESS) { |
ce082596 | 789 | cmd = MODE_01 | addr; |
24c3fa36 | 790 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 791 | } else { |
3157d1ed | 792 | index_addr(denali, cmd, |
2902330e | 793 | PIPELINE_ACCESS | op | page_count); |
5bac3acf | 794 | |
43914a2d MY |
795 | /* |
796 | * wait for command to be accepted | |
bdca6dae | 797 | * can always use status0 bit as the |
43914a2d MY |
798 | * mask is identical for each bank. |
799 | */ | |
ce082596 JR |
800 | irq_status = wait_for_irq(denali, irq_mask); |
801 | ||
345b1d3b | 802 | if (irq_status == 0) { |
84457949 | 803 | dev_err(denali->dev, |
8125450c MY |
804 | "cmd, page, addr on timeout (0x%x, 0x%x, 0x%x)\n", |
805 | cmd, denali->page, addr); | |
ce082596 | 806 | status = FAIL; |
345b1d3b | 807 | } else { |
ce082596 | 808 | cmd = MODE_01 | addr; |
24c3fa36 | 809 | iowrite32(cmd, denali->flash_mem); |
ce082596 JR |
810 | } |
811 | } | |
812 | } | |
813 | return status; | |
814 | } | |
815 | ||
816 | /* helper function that simply writes a buffer to the flash */ | |
bdca6dae | 817 | static int write_data_to_flash_mem(struct denali_nand_info *denali, |
8125450c | 818 | const uint8_t *buf, int len) |
ce082596 | 819 | { |
93e3c8ad MY |
820 | uint32_t *buf32; |
821 | int i; | |
ce082596 | 822 | |
43914a2d MY |
823 | /* |
824 | * verify that the len is a multiple of 4. | |
825 | * see comment in read_data_from_flash_mem() | |
826 | */ | |
ce082596 JR |
827 | BUG_ON((len % 4) != 0); |
828 | ||
829 | /* write the data to the flash memory */ | |
830 | buf32 = (uint32_t *)buf; | |
831 | for (i = 0; i < len / 4; i++) | |
24c3fa36 | 832 | iowrite32(*buf32++, denali->flash_mem + 0x10); |
8125450c | 833 | return i * 4; /* intent is to return the number of bytes read */ |
ce082596 JR |
834 | } |
835 | ||
836 | /* helper function that simply reads a buffer from the flash */ | |
bdca6dae | 837 | static int read_data_from_flash_mem(struct denali_nand_info *denali, |
8125450c | 838 | uint8_t *buf, int len) |
ce082596 | 839 | { |
93e3c8ad MY |
840 | uint32_t *buf32; |
841 | int i; | |
ce082596 | 842 | |
43914a2d MY |
843 | /* |
844 | * we assume that len will be a multiple of 4, if not it would be nice | |
845 | * to know about it ASAP rather than have random failures... | |
846 | * This assumption is based on the fact that this function is designed | |
847 | * to be used to read flash pages, which are typically multiples of 4. | |
ce082596 | 848 | */ |
ce082596 JR |
849 | BUG_ON((len % 4) != 0); |
850 | ||
851 | /* transfer the data from the flash */ | |
852 | buf32 = (uint32_t *)buf; | |
853 | for (i = 0; i < len / 4; i++) | |
ce082596 | 854 | *buf32++ = ioread32(denali->flash_mem + 0x10); |
8125450c | 855 | return i * 4; /* intent is to return the number of bytes read */ |
ce082596 JR |
856 | } |
857 | ||
858 | /* writes OOB data to the device */ | |
859 | static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
860 | { | |
861 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
5637b69d | 862 | uint32_t irq_status; |
9589bf5b JI |
863 | uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | |
864 | INTR_STATUS__PROGRAM_FAIL; | |
ce082596 JR |
865 | int status = 0; |
866 | ||
867 | denali->page = page; | |
868 | ||
5bac3acf | 869 | if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS, |
345b1d3b | 870 | DENALI_WRITE) == PASS) { |
ce082596 JR |
871 | write_data_to_flash_mem(denali, buf, mtd->oobsize); |
872 | ||
ce082596 JR |
873 | /* wait for operation to complete */ |
874 | irq_status = wait_for_irq(denali, irq_mask); | |
875 | ||
345b1d3b | 876 | if (irq_status == 0) { |
84457949 | 877 | dev_err(denali->dev, "OOB write failed\n"); |
ce082596 JR |
878 | status = -EIO; |
879 | } | |
345b1d3b | 880 | } else { |
84457949 | 881 | dev_err(denali->dev, "unable to send pipeline command\n"); |
5bac3acf | 882 | status = -EIO; |
ce082596 JR |
883 | } |
884 | return status; | |
885 | } | |
886 | ||
887 | /* reads OOB data from the device */ | |
888 | static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
889 | { | |
890 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
5637b69d MY |
891 | uint32_t irq_mask = INTR_STATUS__LOAD_COMP; |
892 | uint32_t irq_status, addr, cmd; | |
ce082596 JR |
893 | |
894 | denali->page = page; | |
895 | ||
5bac3acf | 896 | if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, |
345b1d3b | 897 | DENALI_READ) == PASS) { |
5bac3acf | 898 | read_data_from_flash_mem(denali, buf, mtd->oobsize); |
ce082596 | 899 | |
43914a2d MY |
900 | /* |
901 | * wait for command to be accepted | |
902 | * can always use status0 bit as the | |
903 | * mask is identical for each bank. | |
904 | */ | |
ce082596 JR |
905 | irq_status = wait_for_irq(denali, irq_mask); |
906 | ||
907 | if (irq_status == 0) | |
84457949 | 908 | dev_err(denali->dev, "page on OOB timeout %d\n", |
bdca6dae | 909 | denali->page); |
ce082596 | 910 | |
43914a2d MY |
911 | /* |
912 | * We set the device back to MAIN_ACCESS here as I observed | |
ce082596 JR |
913 | * instability with the controller if you do a block erase |
914 | * and the last transaction was a SPARE_ACCESS. Block erase | |
915 | * is reliable (according to the MTD test infrastructure) | |
5bac3acf | 916 | * if you are in MAIN_ACCESS. |
ce082596 JR |
917 | */ |
918 | addr = BANK(denali->flash_bank) | denali->page; | |
5bac3acf | 919 | cmd = MODE_10 | addr; |
3157d1ed | 920 | index_addr(denali, cmd, MAIN_ACCESS); |
ce082596 JR |
921 | } |
922 | } | |
923 | ||
43914a2d MY |
924 | /* |
925 | * this function examines buffers to see if they contain data that | |
ce082596 JR |
926 | * indicate that the buffer is part of an erased region of flash. |
927 | */ | |
919193ce | 928 | static bool is_erased(uint8_t *buf, int len) |
ce082596 | 929 | { |
5637b69d | 930 | int i; |
8125450c | 931 | |
ce082596 | 932 | for (i = 0; i < len; i++) |
ce082596 | 933 | if (buf[i] != 0xFF) |
ce082596 | 934 | return false; |
ce082596 JR |
935 | return true; |
936 | } | |
937 | #define ECC_SECTOR_SIZE 512 | |
938 | ||
939 | #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12) | |
940 | #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET)) | |
941 | #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK) | |
8ae61ebd CD |
942 | #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE)) |
943 | #define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8) | |
ce082596 JR |
944 | #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO) |
945 | ||
5bac3acf | 946 | static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, |
3f91e94f | 947 | uint32_t irq_status, unsigned int *max_bitflips) |
ce082596 JR |
948 | { |
949 | bool check_erased_page = false; | |
3f91e94f | 950 | unsigned int bitflips = 0; |
ce082596 | 951 | |
9589bf5b | 952 | if (irq_status & INTR_STATUS__ECC_ERR) { |
ce082596 | 953 | /* read the ECC errors. we'll ignore them for now */ |
5637b69d MY |
954 | uint32_t err_address, err_correction_info, err_byte, |
955 | err_sector, err_device, err_correction_value; | |
8ae61ebd | 956 | denali_set_intr_modes(denali, false); |
ce082596 | 957 | |
345b1d3b | 958 | do { |
5bac3acf | 959 | err_address = ioread32(denali->flash_reg + |
ce082596 JR |
960 | ECC_ERROR_ADDRESS); |
961 | err_sector = ECC_SECTOR(err_address); | |
962 | err_byte = ECC_BYTE(err_address); | |
963 | ||
5bac3acf | 964 | err_correction_info = ioread32(denali->flash_reg + |
ce082596 | 965 | ERR_CORRECTION_INFO); |
5bac3acf | 966 | err_correction_value = |
ce082596 JR |
967 | ECC_CORRECTION_VALUE(err_correction_info); |
968 | err_device = ECC_ERR_DEVICE(err_correction_info); | |
969 | ||
345b1d3b | 970 | if (ECC_ERROR_CORRECTABLE(err_correction_info)) { |
43914a2d MY |
971 | /* |
972 | * If err_byte is larger than ECC_SECTOR_SIZE, | |
25985edc | 973 | * means error happened in OOB, so we ignore |
8ae61ebd CD |
974 | * it. It's no need for us to correct it |
975 | * err_device is represented the NAND error | |
976 | * bits are happened in if there are more | |
977 | * than one NAND connected. | |
43914a2d | 978 | */ |
8ae61ebd CD |
979 | if (err_byte < ECC_SECTOR_SIZE) { |
980 | int offset; | |
8125450c | 981 | |
8ae61ebd CD |
982 | offset = (err_sector * |
983 | ECC_SECTOR_SIZE + | |
984 | err_byte) * | |
985 | denali->devnum + | |
986 | err_device; | |
ce082596 JR |
987 | /* correct the ECC error */ |
988 | buf[offset] ^= err_correction_value; | |
989 | denali->mtd.ecc_stats.corrected++; | |
3f91e94f | 990 | bitflips++; |
ce082596 | 991 | } |
345b1d3b | 992 | } else { |
43914a2d MY |
993 | /* |
994 | * if the error is not correctable, need to | |
bdca6dae CD |
995 | * look at the page to see if it is an erased |
996 | * page. if so, then it's not a real ECC error | |
43914a2d | 997 | */ |
ce082596 JR |
998 | check_erased_page = true; |
999 | } | |
ce082596 | 1000 | } while (!ECC_LAST_ERR(err_correction_info)); |
43914a2d MY |
1001 | /* |
1002 | * Once handle all ecc errors, controller will triger | |
8ae61ebd CD |
1003 | * a ECC_TRANSACTION_DONE interrupt, so here just wait |
1004 | * for a while for this interrupt | |
43914a2d | 1005 | */ |
8ae61ebd | 1006 | while (!(read_interrupt_status(denali) & |
9589bf5b | 1007 | INTR_STATUS__ECC_TRANSACTION_DONE)) |
8ae61ebd CD |
1008 | cpu_relax(); |
1009 | clear_interrupts(denali); | |
1010 | denali_set_intr_modes(denali, true); | |
ce082596 | 1011 | } |
3f91e94f | 1012 | *max_bitflips = bitflips; |
ce082596 JR |
1013 | return check_erased_page; |
1014 | } | |
1015 | ||
1016 | /* programs the controller to either enable/disable DMA transfers */ | |
aadff49c | 1017 | static void denali_enable_dma(struct denali_nand_info *denali, bool en) |
ce082596 | 1018 | { |
5637b69d | 1019 | iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE); |
ce082596 JR |
1020 | ioread32(denali->flash_reg + DMA_ENABLE); |
1021 | } | |
1022 | ||
1023 | /* setups the HW to perform the data DMA */ | |
aadff49c | 1024 | static void denali_setup_dma(struct denali_nand_info *denali, int op) |
ce082596 | 1025 | { |
5637b69d | 1026 | uint32_t mode; |
ce082596 | 1027 | const int page_count = 1; |
3157d1ed | 1028 | uint32_t addr = denali->buf.dma_buf; |
ce082596 JR |
1029 | |
1030 | mode = MODE_10 | BANK(denali->flash_bank); | |
1031 | ||
1032 | /* DMA is a four step process */ | |
1033 | ||
1034 | /* 1. setup transfer type and # of pages */ | |
1035 | index_addr(denali, mode | denali->page, 0x2000 | op | page_count); | |
1036 | ||
1037 | /* 2. set memory high address bits 23:8 */ | |
3157d1ed | 1038 | index_addr(denali, mode | ((addr >> 16) << 8), 0x2200); |
ce082596 JR |
1039 | |
1040 | /* 3. set memory low address bits 23:8 */ | |
7c272ac5 | 1041 | index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300); |
ce082596 | 1042 | |
43914a2d | 1043 | /* 4. interrupt when complete, burst len = 64 bytes */ |
ce082596 JR |
1044 | index_addr(denali, mode | 0x14000, 0x2400); |
1045 | } | |
1046 | ||
43914a2d MY |
1047 | /* |
1048 | * writes a page. user specifies type, and this function handles the | |
1049 | * configuration details. | |
1050 | */ | |
fdbad98d | 1051 | static int write_page(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1052 | const uint8_t *buf, bool raw_xfer) |
1053 | { | |
1054 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ce082596 JR |
1055 | dma_addr_t addr = denali->buf.dma_buf; |
1056 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | |
5637b69d | 1057 | uint32_t irq_status; |
9589bf5b JI |
1058 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP | |
1059 | INTR_STATUS__PROGRAM_FAIL; | |
ce082596 | 1060 | |
43914a2d MY |
1061 | /* |
1062 | * if it is a raw xfer, we want to disable ecc and send the spare area. | |
ce082596 JR |
1063 | * !raw_xfer - enable ecc |
1064 | * raw_xfer - transfer spare | |
1065 | */ | |
1066 | setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer); | |
1067 | ||
1068 | /* copy buffer into DMA buffer */ | |
1069 | memcpy(denali->buf.buf, buf, mtd->writesize); | |
1070 | ||
345b1d3b | 1071 | if (raw_xfer) { |
ce082596 | 1072 | /* transfer the data to the spare area */ |
5bac3acf C |
1073 | memcpy(denali->buf.buf + mtd->writesize, |
1074 | chip->oob_poi, | |
1075 | mtd->oobsize); | |
ce082596 JR |
1076 | } |
1077 | ||
84457949 | 1078 | dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE); |
ce082596 JR |
1079 | |
1080 | clear_interrupts(denali); | |
5bac3acf | 1081 | denali_enable_dma(denali, true); |
ce082596 | 1082 | |
aadff49c | 1083 | denali_setup_dma(denali, DENALI_WRITE); |
ce082596 JR |
1084 | |
1085 | /* wait for operation to complete */ | |
1086 | irq_status = wait_for_irq(denali, irq_mask); | |
1087 | ||
345b1d3b | 1088 | if (irq_status == 0) { |
8125450c MY |
1089 | dev_err(denali->dev, "timeout on write_page (type = %d)\n", |
1090 | raw_xfer); | |
c115add9 | 1091 | denali->status = NAND_STATUS_FAIL; |
ce082596 JR |
1092 | } |
1093 | ||
5bac3acf | 1094 | denali_enable_dma(denali, false); |
84457949 | 1095 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE); |
fdbad98d JW |
1096 | |
1097 | return 0; | |
ce082596 JR |
1098 | } |
1099 | ||
1100 | /* NAND core entry points */ | |
1101 | ||
43914a2d MY |
1102 | /* |
1103 | * this is the callback that the NAND core calls to write a page. Since | |
b292c341 CD |
1104 | * writing a page with ECC or without is similar, all the work is done |
1105 | * by write_page above. | |
43914a2d | 1106 | */ |
fdbad98d | 1107 | static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1108 | const uint8_t *buf, int oob_required) |
ce082596 | 1109 | { |
43914a2d MY |
1110 | /* |
1111 | * for regular page writes, we let HW handle all the ECC | |
1112 | * data written to the device. | |
1113 | */ | |
fdbad98d | 1114 | return write_page(mtd, chip, buf, false); |
ce082596 JR |
1115 | } |
1116 | ||
43914a2d MY |
1117 | /* |
1118 | * This is the callback that the NAND core calls to write a page without ECC. | |
25985edc | 1119 | * raw access is similar to ECC page writes, so all the work is done in the |
b292c341 | 1120 | * write_page() function above. |
ce082596 | 1121 | */ |
fdbad98d | 1122 | static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1123 | const uint8_t *buf, int oob_required) |
ce082596 | 1124 | { |
43914a2d MY |
1125 | /* |
1126 | * for raw page writes, we want to disable ECC and simply write | |
1127 | * whatever data is in the buffer. | |
1128 | */ | |
fdbad98d | 1129 | return write_page(mtd, chip, buf, true); |
ce082596 JR |
1130 | } |
1131 | ||
5bac3acf | 1132 | static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1133 | int page) |
1134 | { | |
5bac3acf | 1135 | return write_oob_data(mtd, chip->oob_poi, page); |
ce082596 JR |
1136 | } |
1137 | ||
5bac3acf | 1138 | static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, |
5c2ffb11 | 1139 | int page) |
ce082596 JR |
1140 | { |
1141 | read_oob_data(mtd, chip->oob_poi, page); | |
1142 | ||
5c2ffb11 | 1143 | return 0; |
ce082596 JR |
1144 | } |
1145 | ||
1146 | static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1147 | uint8_t *buf, int oob_required, int page) |
ce082596 | 1148 | { |
3f91e94f | 1149 | unsigned int max_bitflips; |
ce082596 | 1150 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
ce082596 JR |
1151 | |
1152 | dma_addr_t addr = denali->buf.dma_buf; | |
1153 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | |
1154 | ||
5637b69d | 1155 | uint32_t irq_status; |
9589bf5b JI |
1156 | uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE | |
1157 | INTR_STATUS__ECC_ERR; | |
ce082596 JR |
1158 | bool check_erased_page = false; |
1159 | ||
7d8a26fd | 1160 | if (page != denali->page) { |
8125450c MY |
1161 | dev_err(denali->dev, |
1162 | "IN %s: page %d is not equal to denali->page %d", | |
1163 | __func__, page, denali->page); | |
7d8a26fd CD |
1164 | BUG(); |
1165 | } | |
1166 | ||
ce082596 JR |
1167 | setup_ecc_for_xfer(denali, true, false); |
1168 | ||
aadff49c | 1169 | denali_enable_dma(denali, true); |
84457949 | 1170 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1171 | |
1172 | clear_interrupts(denali); | |
aadff49c | 1173 | denali_setup_dma(denali, DENALI_READ); |
ce082596 JR |
1174 | |
1175 | /* wait for operation to complete */ | |
1176 | irq_status = wait_for_irq(denali, irq_mask); | |
1177 | ||
84457949 | 1178 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1179 | |
1180 | memcpy(buf, denali->buf.buf, mtd->writesize); | |
5bac3acf | 1181 | |
3f91e94f | 1182 | check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips); |
aadff49c | 1183 | denali_enable_dma(denali, false); |
ce082596 | 1184 | |
345b1d3b | 1185 | if (check_erased_page) { |
ce082596 JR |
1186 | read_oob_data(&denali->mtd, chip->oob_poi, denali->page); |
1187 | ||
1188 | /* check ECC failures that may have occurred on erased pages */ | |
345b1d3b | 1189 | if (check_erased_page) { |
ce082596 | 1190 | if (!is_erased(buf, denali->mtd.writesize)) |
ce082596 | 1191 | denali->mtd.ecc_stats.failed++; |
ce082596 | 1192 | if (!is_erased(buf, denali->mtd.oobsize)) |
ce082596 | 1193 | denali->mtd.ecc_stats.failed++; |
5bac3acf | 1194 | } |
ce082596 | 1195 | } |
3f91e94f | 1196 | return max_bitflips; |
ce082596 JR |
1197 | } |
1198 | ||
1199 | static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1200 | uint8_t *buf, int oob_required, int page) |
ce082596 JR |
1201 | { |
1202 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ce082596 JR |
1203 | dma_addr_t addr = denali->buf.dma_buf; |
1204 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | |
9589bf5b | 1205 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; |
5bac3acf | 1206 | |
7d8a26fd | 1207 | if (page != denali->page) { |
8125450c MY |
1208 | dev_err(denali->dev, |
1209 | "IN %s: page %d is not equal to denali->page %d", | |
1210 | __func__, page, denali->page); | |
7d8a26fd CD |
1211 | BUG(); |
1212 | } | |
1213 | ||
ce082596 | 1214 | setup_ecc_for_xfer(denali, false, true); |
aadff49c | 1215 | denali_enable_dma(denali, true); |
ce082596 | 1216 | |
84457949 | 1217 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1218 | |
1219 | clear_interrupts(denali); | |
aadff49c | 1220 | denali_setup_dma(denali, DENALI_READ); |
ce082596 JR |
1221 | |
1222 | /* wait for operation to complete */ | |
ba5f2bc2 | 1223 | wait_for_irq(denali, irq_mask); |
ce082596 | 1224 | |
84457949 | 1225 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 | 1226 | |
aadff49c | 1227 | denali_enable_dma(denali, false); |
ce082596 JR |
1228 | |
1229 | memcpy(buf, denali->buf.buf, mtd->writesize); | |
1230 | memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize); | |
1231 | ||
1232 | return 0; | |
1233 | } | |
1234 | ||
1235 | static uint8_t denali_read_byte(struct mtd_info *mtd) | |
1236 | { | |
1237 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1238 | uint8_t result = 0xff; | |
1239 | ||
1240 | if (denali->buf.head < denali->buf.tail) | |
ce082596 | 1241 | result = denali->buf.buf[denali->buf.head++]; |
ce082596 | 1242 | |
ce082596 JR |
1243 | return result; |
1244 | } | |
1245 | ||
1246 | static void denali_select_chip(struct mtd_info *mtd, int chip) | |
1247 | { | |
1248 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
7cfffac0 | 1249 | |
ce082596 JR |
1250 | spin_lock_irq(&denali->irq_lock); |
1251 | denali->flash_bank = chip; | |
1252 | spin_unlock_irq(&denali->irq_lock); | |
1253 | } | |
1254 | ||
1255 | static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) | |
1256 | { | |
1257 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1258 | int status = denali->status; | |
8125450c | 1259 | |
ce082596 JR |
1260 | denali->status = 0; |
1261 | ||
ce082596 JR |
1262 | return status; |
1263 | } | |
1264 | ||
49c50b97 | 1265 | static int denali_erase(struct mtd_info *mtd, int page) |
ce082596 JR |
1266 | { |
1267 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1268 | ||
5637b69d | 1269 | uint32_t cmd, irq_status; |
ce082596 | 1270 | |
5bac3acf | 1271 | clear_interrupts(denali); |
ce082596 JR |
1272 | |
1273 | /* setup page read request for access type */ | |
1274 | cmd = MODE_10 | BANK(denali->flash_bank) | page; | |
3157d1ed | 1275 | index_addr(denali, cmd, 0x1); |
ce082596 JR |
1276 | |
1277 | /* wait for erase to complete or failure to occur */ | |
9589bf5b JI |
1278 | irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | |
1279 | INTR_STATUS__ERASE_FAIL); | |
ce082596 | 1280 | |
7d14ecd0 | 1281 | return irq_status & INTR_STATUS__ERASE_FAIL ? NAND_STATUS_FAIL : PASS; |
ce082596 JR |
1282 | } |
1283 | ||
5bac3acf | 1284 | static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, |
ce082596 JR |
1285 | int page) |
1286 | { | |
1287 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ef41e1bb CD |
1288 | uint32_t addr, id; |
1289 | int i; | |
ce082596 | 1290 | |
345b1d3b | 1291 | switch (cmd) { |
a99d1796 CD |
1292 | case NAND_CMD_PAGEPROG: |
1293 | break; | |
1294 | case NAND_CMD_STATUS: | |
1295 | read_status(denali); | |
1296 | break; | |
1297 | case NAND_CMD_READID: | |
42af8b58 | 1298 | case NAND_CMD_PARAM: |
a99d1796 | 1299 | reset_buf(denali); |
43914a2d MY |
1300 | /* |
1301 | * sometimes ManufactureId read from register is not right | |
ef41e1bb CD |
1302 | * e.g. some of Micron MT29F32G08QAA MLC NAND chips |
1303 | * So here we send READID cmd to NAND insteand | |
43914a2d | 1304 | */ |
3157d1ed MY |
1305 | addr = MODE_11 | BANK(denali->flash_bank); |
1306 | index_addr(denali, addr | 0, 0x90); | |
1307 | index_addr(denali, addr | 1, 0); | |
d68a5c3d | 1308 | for (i = 0; i < 8; i++) { |
8125450c | 1309 | index_addr_read_data(denali, addr | 2, &id); |
ef41e1bb | 1310 | write_byte_to_buf(denali, id); |
a99d1796 CD |
1311 | } |
1312 | break; | |
1313 | case NAND_CMD_READ0: | |
1314 | case NAND_CMD_SEQIN: | |
1315 | denali->page = page; | |
1316 | break; | |
1317 | case NAND_CMD_RESET: | |
1318 | reset_bank(denali); | |
1319 | break; | |
1320 | case NAND_CMD_READOOB: | |
1321 | /* TODO: Read OOB data */ | |
1322 | break; | |
1323 | default: | |
2a0a288e | 1324 | pr_err(": unsupported command received 0x%x\n", cmd); |
a99d1796 | 1325 | break; |
ce082596 JR |
1326 | } |
1327 | } | |
ce082596 JR |
1328 | /* end NAND core entry points */ |
1329 | ||
1330 | /* Initialization code to bring the device up to a known good state */ | |
1331 | static void denali_hw_init(struct denali_nand_info *denali) | |
1332 | { | |
43914a2d MY |
1333 | /* |
1334 | * tell driver how many bit controller will skip before | |
db9a3210 CD |
1335 | * writing ECC code in OOB, this register may be already |
1336 | * set by firmware. So we read this value out. | |
1337 | * if this value is 0, just let it be. | |
43914a2d | 1338 | */ |
db9a3210 CD |
1339 | denali->bbtskipbytes = ioread32(denali->flash_reg + |
1340 | SPARE_AREA_SKIP_BYTES); | |
bc27ede3 | 1341 | detect_max_banks(denali); |
eda936ef | 1342 | denali_nand_reset(denali); |
24c3fa36 CD |
1343 | iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED); |
1344 | iowrite32(CHIP_EN_DONT_CARE__FLAG, | |
bdca6dae | 1345 | denali->flash_reg + CHIP_ENABLE_DONT_CARE); |
ce082596 | 1346 | |
24c3fa36 | 1347 | iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER); |
ce082596 JR |
1348 | |
1349 | /* Should set value for these registers when init */ | |
24c3fa36 CD |
1350 | iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES); |
1351 | iowrite32(1, denali->flash_reg + ECC_ENABLE); | |
5eab6aaa CD |
1352 | denali_nand_timing_set(denali); |
1353 | denali_irq_init(denali); | |
ce082596 JR |
1354 | } |
1355 | ||
43914a2d MY |
1356 | /* |
1357 | * Althogh controller spec said SLC ECC is forceb to be 4bit, | |
db9a3210 CD |
1358 | * but denali controller in MRST only support 15bit and 8bit ECC |
1359 | * correction | |
43914a2d | 1360 | */ |
db9a3210 CD |
1361 | #define ECC_8BITS 14 |
1362 | static struct nand_ecclayout nand_8bit_oob = { | |
1363 | .eccbytes = 14, | |
ce082596 JR |
1364 | }; |
1365 | ||
db9a3210 CD |
1366 | #define ECC_15BITS 26 |
1367 | static struct nand_ecclayout nand_15bit_oob = { | |
1368 | .eccbytes = 26, | |
ce082596 JR |
1369 | }; |
1370 | ||
1371 | static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; | |
1372 | static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
1373 | ||
1374 | static struct nand_bbt_descr bbt_main_descr = { | |
1375 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1376 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1377 | .offs = 8, | |
1378 | .len = 4, | |
1379 | .veroffs = 12, | |
1380 | .maxblocks = 4, | |
1381 | .pattern = bbt_pattern, | |
1382 | }; | |
1383 | ||
1384 | static struct nand_bbt_descr bbt_mirror_descr = { | |
1385 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1386 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1387 | .offs = 8, | |
1388 | .len = 4, | |
1389 | .veroffs = 12, | |
1390 | .maxblocks = 4, | |
1391 | .pattern = mirror_pattern, | |
1392 | }; | |
1393 | ||
421f91d2 | 1394 | /* initialize driver data structures */ |
8c519436 | 1395 | static void denali_drv_init(struct denali_nand_info *denali) |
ce082596 JR |
1396 | { |
1397 | denali->idx = 0; | |
1398 | ||
1399 | /* setup interrupt handler */ | |
43914a2d MY |
1400 | /* |
1401 | * the completion object will be used to notify | |
1402 | * the callee that the interrupt is done | |
1403 | */ | |
ce082596 JR |
1404 | init_completion(&denali->complete); |
1405 | ||
43914a2d MY |
1406 | /* |
1407 | * the spinlock will be used to synchronize the ISR with any | |
1408 | * element that might be access shared data (interrupt status) | |
1409 | */ | |
ce082596 JR |
1410 | spin_lock_init(&denali->irq_lock); |
1411 | ||
1412 | /* indicate that MTD has not selected a valid bank yet */ | |
1413 | denali->flash_bank = CHIP_SELECT_INVALID; | |
1414 | ||
1415 | /* initialize our irq_status variable to indicate no interrupts */ | |
1416 | denali->irq_status = 0; | |
1417 | } | |
1418 | ||
2a0a288e | 1419 | int denali_init(struct denali_nand_info *denali) |
ce082596 | 1420 | { |
2a0a288e | 1421 | int ret; |
ce082596 | 1422 | |
2a0a288e | 1423 | if (denali->platform == INTEL_CE4100) { |
43914a2d MY |
1424 | /* |
1425 | * Due to a silicon limitation, we can only support | |
5bac3acf C |
1426 | * ONFI timing mode 1 and below. |
1427 | */ | |
345b1d3b | 1428 | if (onfi_timing_mode < -1 || onfi_timing_mode > 1) { |
2a0a288e DN |
1429 | pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n"); |
1430 | return -EINVAL; | |
ce082596 JR |
1431 | } |
1432 | } | |
1433 | ||
e07caa36 HS |
1434 | /* allocate a temporary buffer for nand_scan_ident() */ |
1435 | denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE, | |
1436 | GFP_DMA | GFP_KERNEL); | |
1437 | if (!denali->buf.buf) | |
1438 | return -ENOMEM; | |
ce082596 | 1439 | |
2a0a288e | 1440 | denali->mtd.dev.parent = denali->dev; |
ce082596 JR |
1441 | denali_hw_init(denali); |
1442 | denali_drv_init(denali); | |
1443 | ||
43914a2d MY |
1444 | /* |
1445 | * denali_isr register is done after all the hardware | |
1446 | * initilization is finished | |
1447 | */ | |
2a0a288e | 1448 | if (request_irq(denali->irq, denali_isr, IRQF_SHARED, |
ce082596 | 1449 | DENALI_NAND_NAME, denali)) { |
2a0a288e DN |
1450 | pr_err("Spectra: Unable to allocate IRQ\n"); |
1451 | return -ENODEV; | |
ce082596 JR |
1452 | } |
1453 | ||
1454 | /* now that our ISR is registered, we can enable interrupts */ | |
eda936ef | 1455 | denali_set_intr_modes(denali, true); |
5eab6aaa | 1456 | denali->mtd.name = "denali-nand"; |
ce082596 JR |
1457 | denali->mtd.owner = THIS_MODULE; |
1458 | denali->mtd.priv = &denali->nand; | |
1459 | ||
1460 | /* register the driver with the NAND core subsystem */ | |
1461 | denali->nand.select_chip = denali_select_chip; | |
1462 | denali->nand.cmdfunc = denali_cmdfunc; | |
1463 | denali->nand.read_byte = denali_read_byte; | |
1464 | denali->nand.waitfunc = denali_waitfunc; | |
1465 | ||
43914a2d MY |
1466 | /* |
1467 | * scan for NAND devices attached to the controller | |
ce082596 | 1468 | * this is the first stage in a two step process to register |
43914a2d MY |
1469 | * with the nand subsystem |
1470 | */ | |
c89eeda8 | 1471 | if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) { |
ce082596 | 1472 | ret = -ENXIO; |
5c0eb900 | 1473 | goto failed_req_irq; |
ce082596 | 1474 | } |
5bac3acf | 1475 | |
e07caa36 HS |
1476 | /* allocate the right size buffer now */ |
1477 | devm_kfree(denali->dev, denali->buf.buf); | |
1478 | denali->buf.buf = devm_kzalloc(denali->dev, | |
1479 | denali->mtd.writesize + denali->mtd.oobsize, | |
1480 | GFP_KERNEL); | |
1481 | if (!denali->buf.buf) { | |
1482 | ret = -ENOMEM; | |
1483 | goto failed_req_irq; | |
1484 | } | |
1485 | ||
1486 | /* Is 32-bit DMA supported? */ | |
1487 | ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32)); | |
1488 | if (ret) { | |
1489 | pr_err("Spectra: no usable DMA configuration\n"); | |
1490 | goto failed_req_irq; | |
1491 | } | |
1492 | ||
1493 | denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf, | |
1494 | denali->mtd.writesize + denali->mtd.oobsize, | |
1495 | DMA_BIDIRECTIONAL); | |
1496 | if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) { | |
1497 | dev_err(denali->dev, "Spectra: failed to map DMA buffer\n"); | |
1498 | ret = -EIO; | |
5c0eb900 | 1499 | goto failed_req_irq; |
66406524 CD |
1500 | } |
1501 | ||
43914a2d MY |
1502 | /* |
1503 | * support for multi nand | |
1504 | * MTD known nothing about multi nand, so we should tell it | |
1505 | * the real pagesize and anything necessery | |
08b9ab99 CD |
1506 | */ |
1507 | denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
1508 | denali->nand.chipsize <<= (denali->devnum - 1); | |
1509 | denali->nand.page_shift += (denali->devnum - 1); | |
1510 | denali->nand.pagemask = (denali->nand.chipsize >> | |
1511 | denali->nand.page_shift) - 1; | |
1512 | denali->nand.bbt_erase_shift += (denali->devnum - 1); | |
1513 | denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift; | |
1514 | denali->nand.chip_shift += (denali->devnum - 1); | |
1515 | denali->mtd.writesize <<= (denali->devnum - 1); | |
1516 | denali->mtd.oobsize <<= (denali->devnum - 1); | |
1517 | denali->mtd.erasesize <<= (denali->devnum - 1); | |
1518 | denali->mtd.size = denali->nand.numchips * denali->nand.chipsize; | |
1519 | denali->bbtskipbytes *= denali->devnum; | |
1520 | ||
43914a2d MY |
1521 | /* |
1522 | * second stage of the NAND scan | |
5bac3acf | 1523 | * this stage requires information regarding ECC and |
43914a2d MY |
1524 | * bad block management. |
1525 | */ | |
ce082596 JR |
1526 | |
1527 | /* Bad block management */ | |
1528 | denali->nand.bbt_td = &bbt_main_descr; | |
1529 | denali->nand.bbt_md = &bbt_mirror_descr; | |
1530 | ||
1531 | /* skip the scan for now until we have OOB read and write support */ | |
bb9ebd4e | 1532 | denali->nand.bbt_options |= NAND_BBT_USE_FLASH; |
a40f7341 | 1533 | denali->nand.options |= NAND_SKIP_BBTSCAN; |
ce082596 JR |
1534 | denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; |
1535 | ||
d99d7282 GM |
1536 | /* no subpage writes on denali */ |
1537 | denali->nand.options |= NAND_NO_SUBPAGE_WRITE; | |
1538 | ||
43914a2d MY |
1539 | /* |
1540 | * Denali Controller only support 15bit and 8bit ECC in MRST, | |
db9a3210 CD |
1541 | * so just let controller do 15bit ECC for MLC and 8bit ECC for |
1542 | * SLC if possible. | |
1543 | * */ | |
1d0ed69d | 1544 | if (!nand_is_slc(&denali->nand) && |
db9a3210 CD |
1545 | (denali->mtd.oobsize > (denali->bbtskipbytes + |
1546 | ECC_15BITS * (denali->mtd.writesize / | |
1547 | ECC_SECTOR_SIZE)))) { | |
1548 | /* if MLC OOB size is large enough, use 15bit ECC*/ | |
6a918bad | 1549 | denali->nand.ecc.strength = 15; |
db9a3210 CD |
1550 | denali->nand.ecc.layout = &nand_15bit_oob; |
1551 | denali->nand.ecc.bytes = ECC_15BITS; | |
24c3fa36 | 1552 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
db9a3210 CD |
1553 | } else if (denali->mtd.oobsize < (denali->bbtskipbytes + |
1554 | ECC_8BITS * (denali->mtd.writesize / | |
1555 | ECC_SECTOR_SIZE))) { | |
8125450c | 1556 | pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes"); |
5c0eb900 | 1557 | goto failed_req_irq; |
db9a3210 | 1558 | } else { |
6a918bad | 1559 | denali->nand.ecc.strength = 8; |
db9a3210 CD |
1560 | denali->nand.ecc.layout = &nand_8bit_oob; |
1561 | denali->nand.ecc.bytes = ECC_8BITS; | |
24c3fa36 | 1562 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 JR |
1563 | } |
1564 | ||
08b9ab99 | 1565 | denali->nand.ecc.bytes *= denali->devnum; |
6a918bad | 1566 | denali->nand.ecc.strength *= denali->devnum; |
db9a3210 CD |
1567 | denali->nand.ecc.layout->eccbytes *= |
1568 | denali->mtd.writesize / ECC_SECTOR_SIZE; | |
1569 | denali->nand.ecc.layout->oobfree[0].offset = | |
1570 | denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes; | |
1571 | denali->nand.ecc.layout->oobfree[0].length = | |
1572 | denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes - | |
1573 | denali->bbtskipbytes; | |
1574 | ||
43914a2d MY |
1575 | /* |
1576 | * Let driver know the total blocks number and how many blocks | |
1577 | * contained by each nand chip. blksperchip will help driver to | |
1578 | * know how many blocks is taken by FW. | |
1579 | */ | |
8125450c | 1580 | denali->totalblks = denali->mtd.size >> denali->nand.phys_erase_shift; |
66406524 CD |
1581 | denali->blksperchip = denali->totalblks / denali->nand.numchips; |
1582 | ||
ce082596 | 1583 | /* override the default read operations */ |
08b9ab99 | 1584 | denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum; |
ce082596 JR |
1585 | denali->nand.ecc.read_page = denali_read_page; |
1586 | denali->nand.ecc.read_page_raw = denali_read_page_raw; | |
1587 | denali->nand.ecc.write_page = denali_write_page; | |
1588 | denali->nand.ecc.write_page_raw = denali_write_page_raw; | |
1589 | denali->nand.ecc.read_oob = denali_read_oob; | |
1590 | denali->nand.ecc.write_oob = denali_write_oob; | |
49c50b97 | 1591 | denali->nand.erase = denali_erase; |
ce082596 | 1592 | |
345b1d3b | 1593 | if (nand_scan_tail(&denali->mtd)) { |
ce082596 | 1594 | ret = -ENXIO; |
5c0eb900 | 1595 | goto failed_req_irq; |
ce082596 JR |
1596 | } |
1597 | ||
ee0e87b1 | 1598 | ret = mtd_device_register(&denali->mtd, NULL, 0); |
ce082596 | 1599 | if (ret) { |
2a0a288e | 1600 | dev_err(denali->dev, "Spectra: Failed to register MTD: %d\n", |
7cfffac0 | 1601 | ret); |
5c0eb900 | 1602 | goto failed_req_irq; |
ce082596 JR |
1603 | } |
1604 | return 0; | |
1605 | ||
5c0eb900 | 1606 | failed_req_irq: |
2a0a288e DN |
1607 | denali_irq_cleanup(denali->irq, denali); |
1608 | ||
ce082596 JR |
1609 | return ret; |
1610 | } | |
2a0a288e | 1611 | EXPORT_SYMBOL(denali_init); |
ce082596 JR |
1612 | |
1613 | /* driver exit point */ | |
2a0a288e | 1614 | void denali_remove(struct denali_nand_info *denali) |
ce082596 | 1615 | { |
2a0a288e | 1616 | denali_irq_cleanup(denali->irq, denali); |
e07caa36 | 1617 | dma_unmap_single(denali->dev, denali->buf.dma_buf, |
8125450c MY |
1618 | denali->mtd.writesize + denali->mtd.oobsize, |
1619 | DMA_BIDIRECTIONAL); | |
ce082596 | 1620 | } |
2a0a288e | 1621 | EXPORT_SYMBOL(denali_remove); |