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ce082596 JR |
1 | /* |
2 | * NAND Flash Controller Device Driver | |
3 | * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | */ | |
19 | ||
a81b4708 MY |
20 | #ifndef __DENALI_H__ |
21 | #define __DENALI_H__ | |
22 | ||
24715c74 | 23 | #include <linux/bitops.h> |
d4092d76 | 24 | #include <linux/mtd/rawnand.h> |
ce082596 JR |
25 | |
26 | #define DEVICE_RESET 0x0 | |
df8b9702 | 27 | #define DEVICE_RESET__BANK(bank) BIT(bank) |
ce082596 JR |
28 | |
29 | #define TRANSFER_SPARE_REG 0x10 | |
df8b9702 | 30 | #define TRANSFER_SPARE_REG__FLAG BIT(0) |
ce082596 JR |
31 | |
32 | #define LOAD_WAIT_CNT 0x20 | |
df8b9702 | 33 | #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0) |
ce082596 JR |
34 | |
35 | #define PROGRAM_WAIT_CNT 0x30 | |
df8b9702 | 36 | #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0) |
ce082596 JR |
37 | |
38 | #define ERASE_WAIT_CNT 0x40 | |
df8b9702 | 39 | #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0) |
ce082596 JR |
40 | |
41 | #define INT_MON_CYCCNT 0x50 | |
df8b9702 | 42 | #define INT_MON_CYCCNT__VALUE GENMASK(15, 0) |
ce082596 JR |
43 | |
44 | #define RB_PIN_ENABLED 0x60 | |
df8b9702 | 45 | #define RB_PIN_ENABLED__BANK(bank) BIT(bank) |
ce082596 JR |
46 | |
47 | #define MULTIPLANE_OPERATION 0x70 | |
df8b9702 | 48 | #define MULTIPLANE_OPERATION__FLAG BIT(0) |
ce082596 JR |
49 | |
50 | #define MULTIPLANE_READ_ENABLE 0x80 | |
df8b9702 | 51 | #define MULTIPLANE_READ_ENABLE__FLAG BIT(0) |
ce082596 JR |
52 | |
53 | #define COPYBACK_DISABLE 0x90 | |
df8b9702 | 54 | #define COPYBACK_DISABLE__FLAG BIT(0) |
ce082596 JR |
55 | |
56 | #define CACHE_WRITE_ENABLE 0xa0 | |
df8b9702 | 57 | #define CACHE_WRITE_ENABLE__FLAG BIT(0) |
ce082596 JR |
58 | |
59 | #define CACHE_READ_ENABLE 0xb0 | |
df8b9702 | 60 | #define CACHE_READ_ENABLE__FLAG BIT(0) |
ce082596 JR |
61 | |
62 | #define PREFETCH_MODE 0xc0 | |
df8b9702 MY |
63 | #define PREFETCH_MODE__PREFETCH_EN BIT(0) |
64 | #define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4) | |
ce082596 JR |
65 | |
66 | #define CHIP_ENABLE_DONT_CARE 0xd0 | |
df8b9702 | 67 | #define CHIP_EN_DONT_CARE__FLAG BIT(0) |
ce082596 JR |
68 | |
69 | #define ECC_ENABLE 0xe0 | |
df8b9702 | 70 | #define ECC_ENABLE__FLAG BIT(0) |
ce082596 JR |
71 | |
72 | #define GLOBAL_INT_ENABLE 0xf0 | |
df8b9702 | 73 | #define GLOBAL_INT_EN_FLAG BIT(0) |
ce082596 | 74 | |
1bb88666 MY |
75 | #define TWHR2_AND_WE_2_RE 0x100 |
76 | #define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0) | |
77 | #define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8) | |
ce082596 | 78 | |
1bb88666 MY |
79 | #define TCWAW_AND_ADDR_2_DATA 0x110 |
80 | /* The width of ADDR_2_DATA is 6 bit for old IP, 7 bit for new IP */ | |
81 | #define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0) | |
82 | #define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8) | |
ce082596 JR |
83 | |
84 | #define RE_2_WE 0x120 | |
df8b9702 | 85 | #define RE_2_WE__VALUE GENMASK(5, 0) |
ce082596 | 86 | |
6ea9ad24 | 87 | #define ACC_CLKS 0x130 |
df8b9702 | 88 | #define ACC_CLKS__VALUE GENMASK(3, 0) |
ce082596 JR |
89 | |
90 | #define NUMBER_OF_PLANES 0x140 | |
df8b9702 | 91 | #define NUMBER_OF_PLANES__VALUE GENMASK(2, 0) |
ce082596 JR |
92 | |
93 | #define PAGES_PER_BLOCK 0x150 | |
df8b9702 | 94 | #define PAGES_PER_BLOCK__VALUE GENMASK(15, 0) |
ce082596 JR |
95 | |
96 | #define DEVICE_WIDTH 0x160 | |
df8b9702 | 97 | #define DEVICE_WIDTH__VALUE GENMASK(1, 0) |
ce082596 JR |
98 | |
99 | #define DEVICE_MAIN_AREA_SIZE 0x170 | |
df8b9702 | 100 | #define DEVICE_MAIN_AREA_SIZE__VALUE GENMASK(15, 0) |
ce082596 JR |
101 | |
102 | #define DEVICE_SPARE_AREA_SIZE 0x180 | |
df8b9702 | 103 | #define DEVICE_SPARE_AREA_SIZE__VALUE GENMASK(15, 0) |
ce082596 JR |
104 | |
105 | #define TWO_ROW_ADDR_CYCLES 0x190 | |
df8b9702 | 106 | #define TWO_ROW_ADDR_CYCLES__FLAG BIT(0) |
ce082596 JR |
107 | |
108 | #define MULTIPLANE_ADDR_RESTRICT 0x1a0 | |
df8b9702 | 109 | #define MULTIPLANE_ADDR_RESTRICT__FLAG BIT(0) |
ce082596 JR |
110 | |
111 | #define ECC_CORRECTION 0x1b0 | |
df8b9702 | 112 | #define ECC_CORRECTION__VALUE GENMASK(4, 0) |
57a4d8b5 MY |
113 | #define ECC_CORRECTION__ERASE_THRESHOLD GENMASK(31, 16) |
114 | #define MAKE_ECC_CORRECTION(val, thresh) \ | |
115 | (((val) & (ECC_CORRECTION__VALUE)) | \ | |
116 | (((thresh) << 16) & (ECC_CORRECTION__ERASE_THRESHOLD))) | |
ce082596 JR |
117 | |
118 | #define READ_MODE 0x1c0 | |
df8b9702 | 119 | #define READ_MODE__VALUE GENMASK(3, 0) |
ce082596 JR |
120 | |
121 | #define WRITE_MODE 0x1d0 | |
df8b9702 | 122 | #define WRITE_MODE__VALUE GENMASK(3, 0) |
ce082596 JR |
123 | |
124 | #define COPYBACK_MODE 0x1e0 | |
df8b9702 | 125 | #define COPYBACK_MODE__VALUE GENMASK(3, 0) |
ce082596 JR |
126 | |
127 | #define RDWR_EN_LO_CNT 0x1f0 | |
df8b9702 | 128 | #define RDWR_EN_LO_CNT__VALUE GENMASK(4, 0) |
ce082596 JR |
129 | |
130 | #define RDWR_EN_HI_CNT 0x200 | |
df8b9702 | 131 | #define RDWR_EN_HI_CNT__VALUE GENMASK(4, 0) |
ce082596 JR |
132 | |
133 | #define MAX_RD_DELAY 0x210 | |
df8b9702 | 134 | #define MAX_RD_DELAY__VALUE GENMASK(3, 0) |
ce082596 JR |
135 | |
136 | #define CS_SETUP_CNT 0x220 | |
df8b9702 | 137 | #define CS_SETUP_CNT__VALUE GENMASK(4, 0) |
1bb88666 | 138 | #define CS_SETUP_CNT__TWB GENMASK(17, 12) |
ce082596 JR |
139 | |
140 | #define SPARE_AREA_SKIP_BYTES 0x230 | |
df8b9702 | 141 | #define SPARE_AREA_SKIP_BYTES__VALUE GENMASK(5, 0) |
ce082596 JR |
142 | |
143 | #define SPARE_AREA_MARKER 0x240 | |
df8b9702 | 144 | #define SPARE_AREA_MARKER__VALUE GENMASK(15, 0) |
ce082596 JR |
145 | |
146 | #define DEVICES_CONNECTED 0x250 | |
df8b9702 | 147 | #define DEVICES_CONNECTED__VALUE GENMASK(2, 0) |
ce082596 | 148 | |
6ea9ad24 | 149 | #define DIE_MASK 0x260 |
df8b9702 | 150 | #define DIE_MASK__VALUE GENMASK(7, 0) |
ce082596 JR |
151 | |
152 | #define FIRST_BLOCK_OF_NEXT_PLANE 0x270 | |
df8b9702 | 153 | #define FIRST_BLOCK_OF_NEXT_PLANE__VALUE GENMASK(15, 0) |
ce082596 JR |
154 | |
155 | #define WRITE_PROTECT 0x280 | |
df8b9702 | 156 | #define WRITE_PROTECT__FLAG BIT(0) |
ce082596 JR |
157 | |
158 | #define RE_2_RE 0x290 | |
df8b9702 | 159 | #define RE_2_RE__VALUE GENMASK(5, 0) |
ce082596 | 160 | |
6ea9ad24 | 161 | #define MANUFACTURER_ID 0x300 |
df8b9702 | 162 | #define MANUFACTURER_ID__VALUE GENMASK(7, 0) |
ce082596 JR |
163 | |
164 | #define DEVICE_ID 0x310 | |
df8b9702 | 165 | #define DEVICE_ID__VALUE GENMASK(7, 0) |
ce082596 JR |
166 | |
167 | #define DEVICE_PARAM_0 0x320 | |
df8b9702 | 168 | #define DEVICE_PARAM_0__VALUE GENMASK(7, 0) |
ce082596 JR |
169 | |
170 | #define DEVICE_PARAM_1 0x330 | |
df8b9702 | 171 | #define DEVICE_PARAM_1__VALUE GENMASK(7, 0) |
ce082596 JR |
172 | |
173 | #define DEVICE_PARAM_2 0x340 | |
df8b9702 | 174 | #define DEVICE_PARAM_2__VALUE GENMASK(7, 0) |
ce082596 JR |
175 | |
176 | #define LOGICAL_PAGE_DATA_SIZE 0x350 | |
df8b9702 | 177 | #define LOGICAL_PAGE_DATA_SIZE__VALUE GENMASK(15, 0) |
ce082596 JR |
178 | |
179 | #define LOGICAL_PAGE_SPARE_SIZE 0x360 | |
df8b9702 | 180 | #define LOGICAL_PAGE_SPARE_SIZE__VALUE GENMASK(15, 0) |
ce082596 | 181 | |
6ea9ad24 | 182 | #define REVISION 0x370 |
df8b9702 | 183 | #define REVISION__VALUE GENMASK(15, 0) |
ce082596 JR |
184 | |
185 | #define ONFI_DEVICE_FEATURES 0x380 | |
df8b9702 | 186 | #define ONFI_DEVICE_FEATURES__VALUE GENMASK(5, 0) |
ce082596 | 187 | |
6ea9ad24 | 188 | #define ONFI_OPTIONAL_COMMANDS 0x390 |
df8b9702 | 189 | #define ONFI_OPTIONAL_COMMANDS__VALUE GENMASK(5, 0) |
ce082596 JR |
190 | |
191 | #define ONFI_TIMING_MODE 0x3a0 | |
df8b9702 | 192 | #define ONFI_TIMING_MODE__VALUE GENMASK(5, 0) |
ce082596 JR |
193 | |
194 | #define ONFI_PGM_CACHE_TIMING_MODE 0x3b0 | |
df8b9702 | 195 | #define ONFI_PGM_CACHE_TIMING_MODE__VALUE GENMASK(5, 0) |
ce082596 JR |
196 | |
197 | #define ONFI_DEVICE_NO_OF_LUNS 0x3c0 | |
df8b9702 MY |
198 | #define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS GENMASK(7, 0) |
199 | #define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE BIT(8) | |
ce082596 JR |
200 | |
201 | #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0 | |
df8b9702 | 202 | #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE GENMASK(15, 0) |
ce082596 JR |
203 | |
204 | #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0 | |
df8b9702 MY |
205 | #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE GENMASK(15, 0) |
206 | ||
207 | #define FEATURES 0x3f0 | |
208 | #define FEATURES__N_BANKS GENMASK(1, 0) | |
209 | #define FEATURES__ECC_MAX_ERR GENMASK(5, 2) | |
210 | #define FEATURES__DMA BIT(6) | |
211 | #define FEATURES__CMD_DMA BIT(7) | |
212 | #define FEATURES__PARTITION BIT(8) | |
213 | #define FEATURES__XDMA_SIDEBAND BIT(9) | |
214 | #define FEATURES__GPREG BIT(10) | |
215 | #define FEATURES__INDEX_ADDR BIT(11) | |
ce082596 JR |
216 | |
217 | #define TRANSFER_MODE 0x400 | |
df8b9702 | 218 | #define TRANSFER_MODE__VALUE GENMASK(1, 0) |
ce082596 | 219 | |
df8b9702 MY |
220 | #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) |
221 | #define INTR_EN(bank) (0x420 + (bank) * 0x50) | |
24715c74 | 222 | /* bit[1:0] is used differently depending on IP version */ |
df8b9702 MY |
223 | #define INTR__ECC_UNCOR_ERR BIT(0) /* new IP */ |
224 | #define INTR__ECC_TRANSACTION_DONE BIT(0) /* old IP */ | |
225 | #define INTR__ECC_ERR BIT(1) /* old IP */ | |
226 | #define INTR__DMA_CMD_COMP BIT(2) | |
227 | #define INTR__TIME_OUT BIT(3) | |
228 | #define INTR__PROGRAM_FAIL BIT(4) | |
229 | #define INTR__ERASE_FAIL BIT(5) | |
230 | #define INTR__LOAD_COMP BIT(6) | |
231 | #define INTR__PROGRAM_COMP BIT(7) | |
232 | #define INTR__ERASE_COMP BIT(8) | |
233 | #define INTR__PIPE_CPYBCK_CMD_COMP BIT(9) | |
234 | #define INTR__LOCKED_BLK BIT(10) | |
235 | #define INTR__UNSUP_CMD BIT(11) | |
236 | #define INTR__INT_ACT BIT(12) | |
237 | #define INTR__RST_COMP BIT(13) | |
238 | #define INTR__PIPE_CMD_ERR BIT(14) | |
239 | #define INTR__PAGE_XFER_INC BIT(15) | |
57a4d8b5 | 240 | #define INTR__ERASED_PAGE BIT(16) |
df8b9702 MY |
241 | |
242 | #define PAGE_CNT(bank) (0x430 + (bank) * 0x50) | |
243 | #define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50) | |
244 | #define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50) | |
ce082596 | 245 | |
ce082596 | 246 | #define ECC_THRESHOLD 0x600 |
df8b9702 | 247 | #define ECC_THRESHOLD__VALUE GENMASK(9, 0) |
ce082596 | 248 | |
6ea9ad24 | 249 | #define ECC_ERROR_BLOCK_ADDRESS 0x610 |
df8b9702 | 250 | #define ECC_ERROR_BLOCK_ADDRESS__VALUE GENMASK(15, 0) |
ce082596 JR |
251 | |
252 | #define ECC_ERROR_PAGE_ADDRESS 0x620 | |
df8b9702 MY |
253 | #define ECC_ERROR_PAGE_ADDRESS__VALUE GENMASK(11, 0) |
254 | #define ECC_ERROR_PAGE_ADDRESS__BANK GENMASK(15, 12) | |
ce082596 JR |
255 | |
256 | #define ECC_ERROR_ADDRESS 0x630 | |
df8b9702 MY |
257 | #define ECC_ERROR_ADDRESS__OFFSET GENMASK(11, 0) |
258 | #define ECC_ERROR_ADDRESS__SECTOR_NR GENMASK(15, 12) | |
ce082596 JR |
259 | |
260 | #define ERR_CORRECTION_INFO 0x640 | |
df8b9702 MY |
261 | #define ERR_CORRECTION_INFO__BYTEMASK GENMASK(7, 0) |
262 | #define ERR_CORRECTION_INFO__DEVICE_NR GENMASK(11, 8) | |
263 | #define ERR_CORRECTION_INFO__ERROR_TYPE BIT(14) | |
264 | #define ERR_CORRECTION_INFO__LAST_ERR_INFO BIT(15) | |
ce082596 | 265 | |
24715c74 MY |
266 | #define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10) |
267 | #define ECC_COR_INFO__SHIFT(bank) ((bank) % 2 * 8) | |
df8b9702 MY |
268 | #define ECC_COR_INFO__MAX_ERRORS GENMASK(6, 0) |
269 | #define ECC_COR_INFO__UNCOR_ERR BIT(7) | |
24715c74 | 270 | |
7de117fd MY |
271 | #define CFG_DATA_BLOCK_SIZE 0x6b0 |
272 | ||
273 | #define CFG_LAST_DATA_BLOCK_SIZE 0x6c0 | |
274 | ||
275 | #define CFG_NUM_DATA_BLOCKS 0x6d0 | |
276 | ||
277 | #define CFG_META_DATA_SIZE 0x6e0 | |
278 | ||
ce082596 | 279 | #define DMA_ENABLE 0x700 |
df8b9702 | 280 | #define DMA_ENABLE__FLAG BIT(0) |
ce082596 JR |
281 | |
282 | #define IGNORE_ECC_DONE 0x710 | |
df8b9702 | 283 | #define IGNORE_ECC_DONE__FLAG BIT(0) |
ce082596 JR |
284 | |
285 | #define DMA_INTR 0x720 | |
1aded58a | 286 | #define DMA_INTR_EN 0x730 |
df8b9702 MY |
287 | #define DMA_INTR__TARGET_ERROR BIT(0) |
288 | #define DMA_INTR__DESC_COMP_CHANNEL0 BIT(1) | |
289 | #define DMA_INTR__DESC_COMP_CHANNEL1 BIT(2) | |
290 | #define DMA_INTR__DESC_COMP_CHANNEL2 BIT(3) | |
291 | #define DMA_INTR__DESC_COMP_CHANNEL3 BIT(4) | |
292 | #define DMA_INTR__MEMCOPY_DESC_COMP BIT(5) | |
ce082596 JR |
293 | |
294 | #define TARGET_ERR_ADDR_LO 0x740 | |
df8b9702 | 295 | #define TARGET_ERR_ADDR_LO__VALUE GENMASK(15, 0) |
ce082596 JR |
296 | |
297 | #define TARGET_ERR_ADDR_HI 0x750 | |
df8b9702 | 298 | #define TARGET_ERR_ADDR_HI__VALUE GENMASK(15, 0) |
ce082596 JR |
299 | |
300 | #define CHNL_ACTIVE 0x760 | |
df8b9702 MY |
301 | #define CHNL_ACTIVE__CHANNEL0 BIT(0) |
302 | #define CHNL_ACTIVE__CHANNEL1 BIT(1) | |
303 | #define CHNL_ACTIVE__CHANNEL2 BIT(2) | |
304 | #define CHNL_ACTIVE__CHANNEL3 BIT(3) | |
ce082596 | 305 | |
ce082596 | 306 | struct denali_nand_info { |
ce082596 | 307 | struct nand_chip nand; |
1bb88666 | 308 | unsigned long clk_x_rate; /* bus interface clock rate */ |
0d3a966d | 309 | int active_bank; /* currently selected bank */ |
84457949 | 310 | struct device *dev; |
0d3a966d MY |
311 | void __iomem *reg; /* Register Interface */ |
312 | void __iomem *host; /* Host Data/Command Interface */ | |
ce082596 JR |
313 | |
314 | /* elements used by ISR */ | |
315 | struct completion complete; | |
316 | spinlock_t irq_lock; | |
c19e31d0 | 317 | uint32_t irq_mask; |
ce082596 | 318 | uint32_t irq_status; |
2a0a288e | 319 | int irq; |
66406524 | 320 | |
00fc615f MY |
321 | void *buf; |
322 | dma_addr_t dma_addr; | |
26d266e1 | 323 | int dma_avail; |
0d3a966d MY |
324 | int devs_per_cs; /* devices connected in parallel */ |
325 | int oob_skip_bytes; | |
e30b4690 | 326 | int max_banks; |
e7beeeec | 327 | unsigned int revision; |
be72a4aa | 328 | unsigned int caps; |
7de117fd | 329 | const struct nand_ecc_caps *ecc_caps; |
ce082596 JR |
330 | }; |
331 | ||
24715c74 | 332 | #define DENALI_CAP_HW_ECC_FIXUP BIT(0) |
210a2c87 | 333 | #define DENALI_CAP_DMA_64BIT BIT(1) |
24715c74 | 334 | |
7de117fd | 335 | int denali_calc_ecc_bytes(int step_size, int strength); |
2a0a288e DN |
336 | extern int denali_init(struct denali_nand_info *denali); |
337 | extern void denali_remove(struct denali_nand_info *denali); | |
338 | ||
a81b4708 | 339 | #endif /* __DENALI_H__ */ |