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82771882 PK |
1 | /* |
2 | * Freescale Integrated Flash Controller NAND driver | |
3 | * | |
4 | * Copyright 2011-2012 Freescale Semiconductor, Inc | |
5 | * | |
6 | * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/types.h> | |
82771882 | 25 | #include <linux/kernel.h> |
5af50730 | 26 | #include <linux/of_address.h> |
82771882 PK |
27 | #include <linux/slab.h> |
28 | #include <linux/mtd/mtd.h> | |
29 | #include <linux/mtd/nand.h> | |
30 | #include <linux/mtd/partitions.h> | |
31 | #include <linux/mtd/nand_ecc.h> | |
d2ae2e20 | 32 | #include <linux/fsl_ifc.h> |
82771882 PK |
33 | |
34 | #define ERR_BYTE 0xFF /* Value returned for read | |
35 | bytes when read failed */ | |
36 | #define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait | |
37 | for IFC NAND Machine */ | |
38 | ||
39 | struct fsl_ifc_ctrl; | |
40 | ||
41 | /* mtd information per set */ | |
42 | struct fsl_ifc_mtd { | |
82771882 PK |
43 | struct nand_chip chip; |
44 | struct fsl_ifc_ctrl *ctrl; | |
45 | ||
46 | struct device *dev; | |
47 | int bank; /* Chip select bank number */ | |
48 | unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */ | |
49 | u8 __iomem *vbase; /* Chip select base virtual address */ | |
50 | }; | |
51 | ||
52 | /* overview of the fsl ifc controller */ | |
53 | struct fsl_ifc_nand_ctrl { | |
54 | struct nand_hw_control controller; | |
55 | struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT]; | |
56 | ||
4454406e | 57 | void __iomem *addr; /* Address of assigned IFC buffer */ |
82771882 PK |
58 | unsigned int page; /* Last page written to / read from */ |
59 | unsigned int read_bytes;/* Number of bytes read during command */ | |
60 | unsigned int column; /* Saved column from SEQIN */ | |
61 | unsigned int index; /* Pointer to next byte to 'read' */ | |
62 | unsigned int oob; /* Non zero if operating on OOB data */ | |
63 | unsigned int eccread; /* Non zero for a full-page ECC read */ | |
64 | unsigned int counter; /* counter for the initializations */ | |
3f91e94f | 65 | unsigned int max_bitflips; /* Saved during READ0 cmd */ |
82771882 PK |
66 | }; |
67 | ||
68 | static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl; | |
69 | ||
82771882 PK |
70 | /* |
71 | * Generic flash bbt descriptors | |
72 | */ | |
73 | static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; | |
74 | static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
75 | ||
76 | static struct nand_bbt_descr bbt_main_descr = { | |
77 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
78 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
79 | .offs = 2, /* 0 on 8-bit small page */ | |
80 | .len = 4, | |
81 | .veroffs = 6, | |
82 | .maxblocks = 4, | |
83 | .pattern = bbt_pattern, | |
84 | }; | |
85 | ||
86 | static struct nand_bbt_descr bbt_mirror_descr = { | |
87 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
88 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
89 | .offs = 2, /* 0 on 8-bit small page */ | |
90 | .len = 4, | |
91 | .veroffs = 6, | |
92 | .maxblocks = 4, | |
93 | .pattern = mirror_pattern, | |
94 | }; | |
95 | ||
caf5129e BB |
96 | static int fsl_ifc_ooblayout_ecc(struct mtd_info *mtd, int section, |
97 | struct mtd_oob_region *oobregion) | |
98 | { | |
99 | struct nand_chip *chip = mtd_to_nand(mtd); | |
100 | ||
101 | if (section) | |
102 | return -ERANGE; | |
103 | ||
104 | oobregion->offset = 8; | |
105 | oobregion->length = chip->ecc.total; | |
106 | ||
107 | return 0; | |
108 | } | |
109 | ||
110 | static int fsl_ifc_ooblayout_free(struct mtd_info *mtd, int section, | |
111 | struct mtd_oob_region *oobregion) | |
112 | { | |
113 | struct nand_chip *chip = mtd_to_nand(mtd); | |
114 | ||
115 | if (section > 1) | |
116 | return -ERANGE; | |
117 | ||
118 | if (mtd->writesize == 512 && | |
119 | !(chip->options & NAND_BUSWIDTH_16)) { | |
120 | if (!section) { | |
121 | oobregion->offset = 0; | |
122 | oobregion->length = 5; | |
123 | } else { | |
124 | oobregion->offset = 6; | |
125 | oobregion->length = 2; | |
126 | } | |
127 | ||
128 | return 0; | |
129 | } | |
130 | ||
131 | if (!section) { | |
132 | oobregion->offset = 2; | |
133 | oobregion->length = 6; | |
134 | } else { | |
135 | oobregion->offset = chip->ecc.total + 8; | |
136 | oobregion->length = mtd->oobsize - oobregion->offset; | |
137 | } | |
138 | ||
139 | return 0; | |
140 | } | |
141 | ||
142 | static const struct mtd_ooblayout_ops fsl_ifc_ooblayout_ops = { | |
143 | .ecc = fsl_ifc_ooblayout_ecc, | |
144 | .free = fsl_ifc_ooblayout_free, | |
145 | }; | |
146 | ||
82771882 PK |
147 | /* |
148 | * Set up the IFC hardware block and page address fields, and the ifc nand | |
149 | * structure addr field to point to the correct IFC buffer in memory | |
150 | */ | |
151 | static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) | |
152 | { | |
4bd4ebcc | 153 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 154 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 | 155 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; |
7a654172 | 156 | struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; |
82771882 PK |
157 | int buf_num; |
158 | ||
159 | ifc_nand_ctrl->page = page_addr; | |
160 | /* Program ROW0/COL0 */ | |
cf184dc2 JS |
161 | ifc_out32(page_addr, &ifc->ifc_nand.row0); |
162 | ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0); | |
82771882 PK |
163 | |
164 | buf_num = page_addr & priv->bufnum_mask; | |
165 | ||
166 | ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2); | |
167 | ifc_nand_ctrl->index = column; | |
168 | ||
169 | /* for OOB data point to the second half of the buffer */ | |
170 | if (oob) | |
171 | ifc_nand_ctrl->index += mtd->writesize; | |
172 | } | |
173 | ||
82771882 PK |
174 | /* returns nonzero if entire page is blank */ |
175 | static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, | |
176 | u32 *eccstat, unsigned int bufnum) | |
177 | { | |
178 | u32 reg = eccstat[bufnum / 4]; | |
179 | int errors; | |
180 | ||
181 | errors = (reg >> ((3 - bufnum % 4) * 8)) & 15; | |
182 | ||
183 | return errors; | |
184 | } | |
185 | ||
186 | /* | |
187 | * execute IFC NAND command and wait for it to complete | |
188 | */ | |
189 | static void fsl_ifc_run_command(struct mtd_info *mtd) | |
190 | { | |
4bd4ebcc | 191 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 192 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 PK |
193 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; |
194 | struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl; | |
7a654172 | 195 | struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; |
82771882 PK |
196 | u32 eccstat[4]; |
197 | int i; | |
198 | ||
199 | /* set the chip select for NAND Transaction */ | |
cf184dc2 JS |
200 | ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT, |
201 | &ifc->ifc_nand.nand_csel); | |
82771882 PK |
202 | |
203 | dev_vdbg(priv->dev, | |
204 | "%s: fir0=%08x fcr0=%08x\n", | |
205 | __func__, | |
cf184dc2 JS |
206 | ifc_in32(&ifc->ifc_nand.nand_fir0), |
207 | ifc_in32(&ifc->ifc_nand.nand_fcr0)); | |
82771882 PK |
208 | |
209 | ctrl->nand_stat = 0; | |
210 | ||
211 | /* start read/write seq */ | |
cf184dc2 | 212 | ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt); |
82771882 PK |
213 | |
214 | /* wait for command complete flag or timeout */ | |
215 | wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat, | |
95d70665 | 216 | msecs_to_jiffies(IFC_TIMEOUT_MSECS)); |
82771882 PK |
217 | |
218 | /* ctrl->nand_stat will be updated from IRQ context */ | |
219 | if (!ctrl->nand_stat) | |
220 | dev_err(priv->dev, "Controller is not responding\n"); | |
221 | if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER) | |
222 | dev_err(priv->dev, "NAND Flash Timeout Error\n"); | |
223 | if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER) | |
224 | dev_err(priv->dev, "NAND Flash Write Protect Error\n"); | |
225 | ||
3f91e94f MD |
226 | nctrl->max_bitflips = 0; |
227 | ||
82771882 PK |
228 | if (nctrl->eccread) { |
229 | int errors; | |
230 | int bufnum = nctrl->page & priv->bufnum_mask; | |
231 | int sector = bufnum * chip->ecc.steps; | |
232 | int sector_end = sector + chip->ecc.steps - 1; | |
65644147 MM |
233 | __be32 *eccstat_regs; |
234 | ||
235 | if (ctrl->version >= FSL_IFC_VERSION_2_0_0) | |
236 | eccstat_regs = ifc->ifc_nand.v2_nand_eccstat; | |
237 | else | |
238 | eccstat_regs = ifc->ifc_nand.v1_nand_eccstat; | |
82771882 PK |
239 | |
240 | for (i = sector / 4; i <= sector_end / 4; i++) | |
65644147 | 241 | eccstat[i] = ifc_in32(&eccstat_regs[i]); |
82771882 PK |
242 | |
243 | for (i = sector; i <= sector_end; i++) { | |
244 | errors = check_read_ecc(mtd, ctrl, eccstat, i); | |
245 | ||
246 | if (errors == 15) { | |
247 | /* | |
248 | * Uncorrectable error. | |
d45e5316 | 249 | * We'll check for blank pages later. |
82771882 PK |
250 | * |
251 | * We disable ECCER reporting due to... | |
252 | * erratum IFC-A002770 -- so report it now if we | |
253 | * see an uncorrectable error in ECCSTAT. | |
254 | */ | |
d45e5316 BB |
255 | ctrl->nand_stat |= IFC_NAND_EVTER_STAT_ECCER; |
256 | continue; | |
82771882 PK |
257 | } |
258 | ||
259 | mtd->ecc_stats.corrected += errors; | |
3f91e94f MD |
260 | nctrl->max_bitflips = max_t(unsigned int, |
261 | nctrl->max_bitflips, | |
262 | errors); | |
82771882 PK |
263 | } |
264 | ||
265 | nctrl->eccread = 0; | |
266 | } | |
267 | } | |
268 | ||
269 | static void fsl_ifc_do_read(struct nand_chip *chip, | |
270 | int oob, | |
271 | struct mtd_info *mtd) | |
272 | { | |
d699ed25 | 273 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 | 274 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; |
7a654172 | 275 | struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; |
82771882 PK |
276 | |
277 | /* Program FIR/IFC_NAND_FCR0 for Small/Large page */ | |
278 | if (mtd->writesize > 512) { | |
cf184dc2 JS |
279 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
280 | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | | |
281 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | | |
282 | (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | | |
283 | (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT), | |
284 | &ifc->ifc_nand.nand_fir0); | |
285 | ifc_out32(0x0, &ifc->ifc_nand.nand_fir1); | |
286 | ||
287 | ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | | |
288 | (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT), | |
289 | &ifc->ifc_nand.nand_fcr0); | |
82771882 | 290 | } else { |
cf184dc2 JS |
291 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
292 | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | | |
293 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | | |
294 | (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT), | |
295 | &ifc->ifc_nand.nand_fir0); | |
296 | ifc_out32(0x0, &ifc->ifc_nand.nand_fir1); | |
82771882 PK |
297 | |
298 | if (oob) | |
cf184dc2 JS |
299 | ifc_out32(NAND_CMD_READOOB << |
300 | IFC_NAND_FCR0_CMD0_SHIFT, | |
301 | &ifc->ifc_nand.nand_fcr0); | |
82771882 | 302 | else |
cf184dc2 JS |
303 | ifc_out32(NAND_CMD_READ0 << |
304 | IFC_NAND_FCR0_CMD0_SHIFT, | |
305 | &ifc->ifc_nand.nand_fcr0); | |
82771882 PK |
306 | } |
307 | } | |
308 | ||
309 | /* cmdfunc send commands to the IFC NAND Machine */ | |
310 | static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, | |
311 | int column, int page_addr) { | |
4bd4ebcc | 312 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 313 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 | 314 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; |
7a654172 | 315 | struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; |
82771882 PK |
316 | |
317 | /* clear the read buffer */ | |
318 | ifc_nand_ctrl->read_bytes = 0; | |
319 | if (command != NAND_CMD_PAGEPROG) | |
320 | ifc_nand_ctrl->index = 0; | |
321 | ||
322 | switch (command) { | |
323 | /* READ0 read the entire buffer to use hardware ECC. */ | |
324 | case NAND_CMD_READ0: | |
cf184dc2 | 325 | ifc_out32(0, &ifc->ifc_nand.nand_fbcr); |
82771882 PK |
326 | set_addr(mtd, 0, page_addr, 0); |
327 | ||
328 | ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize; | |
329 | ifc_nand_ctrl->index += column; | |
330 | ||
331 | if (chip->ecc.mode == NAND_ECC_HW) | |
332 | ifc_nand_ctrl->eccread = 1; | |
333 | ||
334 | fsl_ifc_do_read(chip, 0, mtd); | |
335 | fsl_ifc_run_command(mtd); | |
336 | return; | |
337 | ||
338 | /* READOOB reads only the OOB because no ECC is performed. */ | |
339 | case NAND_CMD_READOOB: | |
cf184dc2 | 340 | ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr); |
82771882 PK |
341 | set_addr(mtd, column, page_addr, 1); |
342 | ||
343 | ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize; | |
344 | ||
345 | fsl_ifc_do_read(chip, 1, mtd); | |
346 | fsl_ifc_run_command(mtd); | |
347 | ||
348 | return; | |
349 | ||
82771882 | 350 | case NAND_CMD_READID: |
59fdd5b9 PK |
351 | case NAND_CMD_PARAM: { |
352 | int timing = IFC_FIR_OP_RB; | |
353 | if (command == NAND_CMD_PARAM) | |
354 | timing = IFC_FIR_OP_RBCD; | |
355 | ||
cf184dc2 JS |
356 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
357 | (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | | |
358 | (timing << IFC_NAND_FIR0_OP2_SHIFT), | |
359 | &ifc->ifc_nand.nand_fir0); | |
360 | ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT, | |
361 | &ifc->ifc_nand.nand_fcr0); | |
362 | ifc_out32(column, &ifc->ifc_nand.row3); | |
59fdd5b9 PK |
363 | |
364 | /* | |
365 | * although currently it's 8 bytes for READID, we always read | |
366 | * the maximum 256 bytes(for PARAM) | |
367 | */ | |
cf184dc2 | 368 | ifc_out32(256, &ifc->ifc_nand.nand_fbcr); |
59fdd5b9 | 369 | ifc_nand_ctrl->read_bytes = 256; |
82771882 PK |
370 | |
371 | set_addr(mtd, 0, 0, 0); | |
372 | fsl_ifc_run_command(mtd); | |
373 | return; | |
59fdd5b9 | 374 | } |
82771882 PK |
375 | |
376 | /* ERASE1 stores the block and page address */ | |
377 | case NAND_CMD_ERASE1: | |
378 | set_addr(mtd, 0, page_addr, 0); | |
379 | return; | |
380 | ||
381 | /* ERASE2 uses the block and page address from ERASE1 */ | |
382 | case NAND_CMD_ERASE2: | |
cf184dc2 JS |
383 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
384 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | | |
385 | (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT), | |
386 | &ifc->ifc_nand.nand_fir0); | |
82771882 | 387 | |
cf184dc2 JS |
388 | ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | |
389 | (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT), | |
390 | &ifc->ifc_nand.nand_fcr0); | |
82771882 | 391 | |
cf184dc2 | 392 | ifc_out32(0, &ifc->ifc_nand.nand_fbcr); |
82771882 PK |
393 | ifc_nand_ctrl->read_bytes = 0; |
394 | fsl_ifc_run_command(mtd); | |
395 | return; | |
396 | ||
397 | /* SEQIN sets up the addr buffer and all registers except the length */ | |
398 | case NAND_CMD_SEQIN: { | |
399 | u32 nand_fcr0; | |
400 | ifc_nand_ctrl->column = column; | |
401 | ifc_nand_ctrl->oob = 0; | |
402 | ||
403 | if (mtd->writesize > 512) { | |
404 | nand_fcr0 = | |
405 | (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) | | |
4af98749 PK |
406 | (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) | |
407 | (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT); | |
82771882 | 408 | |
cf184dc2 JS |
409 | ifc_out32( |
410 | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | | |
411 | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | | |
412 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | | |
413 | (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) | | |
414 | (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT), | |
415 | &ifc->ifc_nand.nand_fir0); | |
416 | ifc_out32( | |
417 | (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) | | |
418 | (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) | | |
419 | (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT), | |
420 | &ifc->ifc_nand.nand_fir1); | |
82771882 PK |
421 | } else { |
422 | nand_fcr0 = ((NAND_CMD_PAGEPROG << | |
423 | IFC_NAND_FCR0_CMD1_SHIFT) | | |
424 | (NAND_CMD_SEQIN << | |
4af98749 PK |
425 | IFC_NAND_FCR0_CMD2_SHIFT) | |
426 | (NAND_CMD_STATUS << | |
427 | IFC_NAND_FCR0_CMD3_SHIFT)); | |
82771882 | 428 | |
cf184dc2 | 429 | ifc_out32( |
0c69fb03 KP |
430 | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
431 | (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | | |
432 | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | | |
433 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | | |
434 | (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT), | |
435 | &ifc->ifc_nand.nand_fir0); | |
cf184dc2 JS |
436 | ifc_out32( |
437 | (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) | | |
438 | (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) | | |
439 | (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) | | |
440 | (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT), | |
441 | &ifc->ifc_nand.nand_fir1); | |
82771882 PK |
442 | |
443 | if (column >= mtd->writesize) | |
444 | nand_fcr0 |= | |
445 | NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT; | |
446 | else | |
447 | nand_fcr0 |= | |
448 | NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT; | |
449 | } | |
450 | ||
451 | if (column >= mtd->writesize) { | |
452 | /* OOB area --> READOOB */ | |
453 | column -= mtd->writesize; | |
454 | ifc_nand_ctrl->oob = 1; | |
455 | } | |
cf184dc2 | 456 | ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0); |
82771882 PK |
457 | set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob); |
458 | return; | |
459 | } | |
460 | ||
461 | /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ | |
462 | case NAND_CMD_PAGEPROG: { | |
463 | if (ifc_nand_ctrl->oob) { | |
cf184dc2 JS |
464 | ifc_out32(ifc_nand_ctrl->index - |
465 | ifc_nand_ctrl->column, | |
466 | &ifc->ifc_nand.nand_fbcr); | |
82771882 | 467 | } else { |
cf184dc2 | 468 | ifc_out32(0, &ifc->ifc_nand.nand_fbcr); |
82771882 PK |
469 | } |
470 | ||
471 | fsl_ifc_run_command(mtd); | |
472 | return; | |
473 | } | |
474 | ||
cf184dc2 JS |
475 | case NAND_CMD_STATUS: { |
476 | void __iomem *addr; | |
477 | ||
478 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | | |
479 | (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT), | |
480 | &ifc->ifc_nand.nand_fir0); | |
481 | ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT, | |
482 | &ifc->ifc_nand.nand_fcr0); | |
483 | ifc_out32(1, &ifc->ifc_nand.nand_fbcr); | |
82771882 PK |
484 | set_addr(mtd, 0, 0, 0); |
485 | ifc_nand_ctrl->read_bytes = 1; | |
486 | ||
487 | fsl_ifc_run_command(mtd); | |
488 | ||
489 | /* | |
490 | * The chip always seems to report that it is | |
491 | * write-protected, even when it is not. | |
492 | */ | |
cf184dc2 | 493 | addr = ifc_nand_ctrl->addr; |
21704804 | 494 | if (chip->options & NAND_BUSWIDTH_16) |
cf184dc2 | 495 | ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr); |
21704804 | 496 | else |
cf184dc2 | 497 | ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr); |
82771882 | 498 | return; |
cf184dc2 | 499 | } |
82771882 PK |
500 | |
501 | case NAND_CMD_RESET: | |
cf184dc2 JS |
502 | ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT, |
503 | &ifc->ifc_nand.nand_fir0); | |
504 | ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT, | |
505 | &ifc->ifc_nand.nand_fcr0); | |
82771882 PK |
506 | fsl_ifc_run_command(mtd); |
507 | return; | |
508 | ||
509 | default: | |
510 | dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n", | |
511 | __func__, command); | |
512 | } | |
513 | } | |
514 | ||
515 | static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip) | |
516 | { | |
517 | /* The hardware does not seem to support multiple | |
518 | * chips per bank. | |
519 | */ | |
520 | } | |
521 | ||
522 | /* | |
523 | * Write buf to the IFC NAND Controller Data Buffer | |
524 | */ | |
525 | static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) | |
526 | { | |
4bd4ebcc | 527 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 528 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 PK |
529 | unsigned int bufsize = mtd->writesize + mtd->oobsize; |
530 | ||
531 | if (len <= 0) { | |
532 | dev_err(priv->dev, "%s: len %d bytes", __func__, len); | |
533 | return; | |
534 | } | |
535 | ||
536 | if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) { | |
537 | dev_err(priv->dev, | |
538 | "%s: beyond end of buffer (%d requested, %u available)\n", | |
539 | __func__, len, bufsize - ifc_nand_ctrl->index); | |
540 | len = bufsize - ifc_nand_ctrl->index; | |
541 | } | |
542 | ||
4454406e | 543 | memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len); |
82771882 PK |
544 | ifc_nand_ctrl->index += len; |
545 | } | |
546 | ||
547 | /* | |
548 | * Read a byte from either the IFC hardware buffer | |
549 | * read function for 8-bit buswidth | |
550 | */ | |
551 | static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd) | |
552 | { | |
4bd4ebcc | 553 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 554 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
4454406e | 555 | unsigned int offset; |
82771882 PK |
556 | |
557 | /* | |
558 | * If there are still bytes in the IFC buffer, then use the | |
559 | * next byte. | |
560 | */ | |
4454406e AS |
561 | if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) { |
562 | offset = ifc_nand_ctrl->index++; | |
cf184dc2 | 563 | return ifc_in8(ifc_nand_ctrl->addr + offset); |
4454406e | 564 | } |
82771882 PK |
565 | |
566 | dev_err(priv->dev, "%s: beyond end of buffer\n", __func__); | |
567 | return ERR_BYTE; | |
568 | } | |
569 | ||
570 | /* | |
571 | * Read two bytes from the IFC hardware buffer | |
572 | * read function for 16-bit buswith | |
573 | */ | |
574 | static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd) | |
575 | { | |
4bd4ebcc | 576 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 577 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 PK |
578 | uint16_t data; |
579 | ||
580 | /* | |
581 | * If there are still bytes in the IFC buffer, then use the | |
582 | * next byte. | |
583 | */ | |
584 | if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) { | |
cf184dc2 | 585 | data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index); |
82771882 PK |
586 | ifc_nand_ctrl->index += 2; |
587 | return (uint8_t) data; | |
588 | } | |
589 | ||
590 | dev_err(priv->dev, "%s: beyond end of buffer\n", __func__); | |
591 | return ERR_BYTE; | |
592 | } | |
593 | ||
594 | /* | |
595 | * Read from the IFC Controller Data Buffer | |
596 | */ | |
597 | static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len) | |
598 | { | |
4bd4ebcc | 599 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 600 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 PK |
601 | int avail; |
602 | ||
603 | if (len < 0) { | |
604 | dev_err(priv->dev, "%s: len %d bytes", __func__, len); | |
605 | return; | |
606 | } | |
607 | ||
608 | avail = min((unsigned int)len, | |
609 | ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index); | |
4454406e | 610 | memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail); |
82771882 PK |
611 | ifc_nand_ctrl->index += avail; |
612 | ||
613 | if (len > avail) | |
614 | dev_err(priv->dev, | |
615 | "%s: beyond end of buffer (%d requested, %d available)\n", | |
616 | __func__, len, avail); | |
617 | } | |
618 | ||
82771882 PK |
619 | /* |
620 | * This function is called after Program and Erase Operations to | |
621 | * check for success or failure. | |
622 | */ | |
623 | static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
624 | { | |
d699ed25 | 625 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 | 626 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; |
7a654172 | 627 | struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; |
82771882 PK |
628 | u32 nand_fsr; |
629 | ||
630 | /* Use READ_STATUS command, but wait for the device to be ready */ | |
cf184dc2 JS |
631 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
632 | (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT), | |
633 | &ifc->ifc_nand.nand_fir0); | |
634 | ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT, | |
635 | &ifc->ifc_nand.nand_fcr0); | |
636 | ifc_out32(1, &ifc->ifc_nand.nand_fbcr); | |
82771882 PK |
637 | set_addr(mtd, 0, 0, 0); |
638 | ifc_nand_ctrl->read_bytes = 1; | |
639 | ||
640 | fsl_ifc_run_command(mtd); | |
641 | ||
cf184dc2 | 642 | nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr); |
82771882 PK |
643 | |
644 | /* | |
645 | * The chip always seems to report that it is | |
646 | * write-protected, even when it is not. | |
647 | */ | |
648 | return nand_fsr | NAND_STATUS_WP; | |
649 | } | |
650 | ||
d45e5316 BB |
651 | /* |
652 | * The controller does not check for bitflips in erased pages, | |
653 | * therefore software must check instead. | |
654 | */ | |
655 | static int check_erased_page(struct nand_chip *chip, u8 *buf) | |
656 | { | |
657 | struct mtd_info *mtd = nand_to_mtd(chip); | |
658 | u8 *ecc = chip->oob_poi; | |
659 | const int ecc_size = chip->ecc.bytes; | |
660 | const int pkt_size = chip->ecc.size; | |
661 | int i, res, bitflips = 0; | |
662 | struct mtd_oob_region oobregion = { }; | |
663 | ||
664 | mtd_ooblayout_ecc(mtd, 0, &oobregion); | |
665 | ecc += oobregion.offset; | |
666 | ||
667 | for (i = 0; i < chip->ecc.steps; ++i) { | |
668 | res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size, | |
669 | NULL, 0, | |
670 | chip->ecc.strength); | |
671 | if (res < 0) | |
672 | mtd->ecc_stats.failed++; | |
673 | else | |
674 | mtd->ecc_stats.corrected += res; | |
675 | ||
676 | bitflips = max(res, bitflips); | |
677 | buf += pkt_size; | |
678 | ecc += ecc_size; | |
679 | } | |
680 | ||
681 | return bitflips; | |
682 | } | |
683 | ||
1fbb938d BN |
684 | static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip, |
685 | uint8_t *buf, int oob_required, int page) | |
82771882 | 686 | { |
d699ed25 | 687 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 | 688 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; |
3f91e94f | 689 | struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl; |
82771882 PK |
690 | |
691 | fsl_ifc_read_buf(mtd, buf, mtd->writesize); | |
a6976cdf BN |
692 | if (oob_required) |
693 | fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
82771882 | 694 | |
d45e5316 BB |
695 | if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER) { |
696 | if (!oob_required) | |
697 | fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
698 | ||
699 | return check_erased_page(chip, buf); | |
700 | } | |
82771882 PK |
701 | |
702 | if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) | |
703 | mtd->ecc_stats.failed++; | |
704 | ||
3f91e94f | 705 | return nctrl->max_bitflips; |
82771882 PK |
706 | } |
707 | ||
708 | /* ECC will be calculated automatically, and errors will be detected in | |
709 | * waitfunc. | |
710 | */ | |
fdbad98d | 711 | static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 | 712 | const uint8_t *buf, int oob_required, int page) |
82771882 PK |
713 | { |
714 | fsl_ifc_write_buf(mtd, buf, mtd->writesize); | |
715 | fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
716 | |
717 | return 0; | |
82771882 PK |
718 | } |
719 | ||
720 | static int fsl_ifc_chip_init_tail(struct mtd_info *mtd) | |
721 | { | |
4bd4ebcc | 722 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 723 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 PK |
724 | |
725 | dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__, | |
726 | chip->numchips); | |
727 | dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__, | |
728 | chip->chipsize); | |
729 | dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__, | |
730 | chip->pagemask); | |
731 | dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__, | |
732 | chip->chip_delay); | |
733 | dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__, | |
734 | chip->badblockpos); | |
735 | dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__, | |
736 | chip->chip_shift); | |
737 | dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__, | |
738 | chip->page_shift); | |
739 | dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__, | |
740 | chip->phys_erase_shift); | |
82771882 PK |
741 | dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__, |
742 | chip->ecc.mode); | |
743 | dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__, | |
744 | chip->ecc.steps); | |
745 | dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__, | |
746 | chip->ecc.bytes); | |
747 | dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__, | |
748 | chip->ecc.total); | |
caf5129e BB |
749 | dev_dbg(priv->dev, "%s: mtd->ooblayout = %p\n", __func__, |
750 | mtd->ooblayout); | |
82771882 PK |
751 | dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags); |
752 | dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size); | |
753 | dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__, | |
754 | mtd->erasesize); | |
755 | dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__, | |
756 | mtd->writesize); | |
757 | dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__, | |
758 | mtd->oobsize); | |
759 | ||
760 | return 0; | |
761 | } | |
762 | ||
10bfa766 PK |
763 | static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv) |
764 | { | |
765 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; | |
7a654172 RD |
766 | struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs; |
767 | struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs; | |
10bfa766 PK |
768 | uint32_t csor = 0, csor_8k = 0, csor_ext = 0; |
769 | uint32_t cs = priv->bank; | |
770 | ||
771 | /* Save CSOR and CSOR_ext */ | |
7a654172 RD |
772 | csor = ifc_in32(&ifc_global->csor_cs[cs].csor); |
773 | csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext); | |
10bfa766 PK |
774 | |
775 | /* chage PageSize 8K and SpareSize 1K*/ | |
776 | csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000; | |
7a654172 RD |
777 | ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor); |
778 | ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext); | |
10bfa766 PK |
779 | |
780 | /* READID */ | |
cf184dc2 | 781 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
7a654172 RD |
782 | (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | |
783 | (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT), | |
784 | &ifc_runtime->ifc_nand.nand_fir0); | |
cf184dc2 | 785 | ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT, |
7a654172 RD |
786 | &ifc_runtime->ifc_nand.nand_fcr0); |
787 | ifc_out32(0x0, &ifc_runtime->ifc_nand.row3); | |
10bfa766 | 788 | |
7a654172 | 789 | ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr); |
10bfa766 PK |
790 | |
791 | /* Program ROW0/COL0 */ | |
7a654172 RD |
792 | ifc_out32(0x0, &ifc_runtime->ifc_nand.row0); |
793 | ifc_out32(0x0, &ifc_runtime->ifc_nand.col0); | |
10bfa766 PK |
794 | |
795 | /* set the chip select for NAND Transaction */ | |
7a654172 RD |
796 | ifc_out32(cs << IFC_NAND_CSEL_SHIFT, |
797 | &ifc_runtime->ifc_nand.nand_csel); | |
10bfa766 PK |
798 | |
799 | /* start read seq */ | |
7a654172 RD |
800 | ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, |
801 | &ifc_runtime->ifc_nand.nandseq_strt); | |
10bfa766 PK |
802 | |
803 | /* wait for command complete flag or timeout */ | |
804 | wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat, | |
95d70665 | 805 | msecs_to_jiffies(IFC_TIMEOUT_MSECS)); |
10bfa766 PK |
806 | |
807 | if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) | |
808 | printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n"); | |
809 | ||
810 | /* Restore CSOR and CSOR_ext */ | |
7a654172 RD |
811 | ifc_out32(csor, &ifc_global->csor_cs[cs].csor); |
812 | ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext); | |
10bfa766 PK |
813 | } |
814 | ||
82771882 PK |
815 | static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) |
816 | { | |
817 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; | |
7a654172 RD |
818 | struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs; |
819 | struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs; | |
82771882 | 820 | struct nand_chip *chip = &priv->chip; |
5e9fb93d | 821 | struct mtd_info *mtd = nand_to_mtd(&priv->chip); |
09691661 | 822 | u32 csor; |
82771882 PK |
823 | |
824 | /* Fill in fsl_ifc_mtd structure */ | |
5e9fb93d | 825 | mtd->dev.parent = priv->dev; |
a61ae81a | 826 | nand_set_flash_node(chip, priv->dev->of_node); |
82771882 PK |
827 | |
828 | /* fill in nand_chip structure */ | |
829 | /* set up function call table */ | |
7a654172 RD |
830 | if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)) |
831 | & CSPR_PORT_SIZE_16) | |
82771882 PK |
832 | chip->read_byte = fsl_ifc_read_byte16; |
833 | else | |
834 | chip->read_byte = fsl_ifc_read_byte; | |
835 | ||
836 | chip->write_buf = fsl_ifc_write_buf; | |
837 | chip->read_buf = fsl_ifc_read_buf; | |
82771882 PK |
838 | chip->select_chip = fsl_ifc_select_chip; |
839 | chip->cmdfunc = fsl_ifc_cmdfunc; | |
840 | chip->waitfunc = fsl_ifc_wait; | |
4a78cc64 BB |
841 | chip->onfi_set_features = nand_onfi_get_set_features_notsupp; |
842 | chip->onfi_get_features = nand_onfi_get_set_features_notsupp; | |
82771882 PK |
843 | |
844 | chip->bbt_td = &bbt_main_descr; | |
845 | chip->bbt_md = &bbt_mirror_descr; | |
846 | ||
7a654172 | 847 | ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr); |
82771882 PK |
848 | |
849 | /* set up nand options */ | |
82771882 | 850 | chip->bbt_options = NAND_BBT_USE_FLASH; |
20cd0008 | 851 | chip->options = NAND_NO_SUBPAGE_WRITE; |
82771882 | 852 | |
7a654172 RD |
853 | if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr) |
854 | & CSPR_PORT_SIZE_16) { | |
82771882 PK |
855 | chip->read_byte = fsl_ifc_read_byte16; |
856 | chip->options |= NAND_BUSWIDTH_16; | |
857 | } else { | |
858 | chip->read_byte = fsl_ifc_read_byte; | |
859 | } | |
860 | ||
861 | chip->controller = &ifc_nand_ctrl->controller; | |
d699ed25 | 862 | nand_set_controller_data(chip, priv); |
82771882 PK |
863 | |
864 | chip->ecc.read_page = fsl_ifc_read_page; | |
865 | chip->ecc.write_page = fsl_ifc_write_page; | |
866 | ||
7a654172 | 867 | csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor); |
82771882 | 868 | |
82771882 PK |
869 | switch (csor & CSOR_NAND_PGS_MASK) { |
870 | case CSOR_NAND_PGS_512: | |
caf5129e | 871 | if (!(chip->options & NAND_BUSWIDTH_16)) { |
82771882 PK |
872 | /* Avoid conflict with bad block marker */ |
873 | bbt_main_descr.offs = 0; | |
874 | bbt_mirror_descr.offs = 0; | |
875 | } | |
876 | ||
877 | priv->bufnum_mask = 15; | |
878 | break; | |
879 | ||
880 | case CSOR_NAND_PGS_2K: | |
82771882 PK |
881 | priv->bufnum_mask = 3; |
882 | break; | |
883 | ||
884 | case CSOR_NAND_PGS_4K: | |
82771882 PK |
885 | priv->bufnum_mask = 1; |
886 | break; | |
887 | ||
ebff90b2 | 888 | case CSOR_NAND_PGS_8K: |
ebff90b2 | 889 | priv->bufnum_mask = 0; |
caf5129e | 890 | break; |
ebff90b2 | 891 | |
82771882 PK |
892 | default: |
893 | dev_err(priv->dev, "bad csor %#x: bad page size\n", csor); | |
894 | return -ENODEV; | |
895 | } | |
896 | ||
897 | /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */ | |
898 | if (csor & CSOR_NAND_ECC_DEC_EN) { | |
899 | chip->ecc.mode = NAND_ECC_HW; | |
caf5129e BB |
900 | mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops); |
901 | ||
902 | /* Hardware generates ECC per 512 Bytes */ | |
903 | chip->ecc.size = 512; | |
904 | if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) { | |
905 | chip->ecc.bytes = 8; | |
906 | chip->ecc.strength = 4; | |
907 | } else { | |
908 | chip->ecc.bytes = 16; | |
909 | chip->ecc.strength = 8; | |
910 | } | |
82771882 PK |
911 | } else { |
912 | chip->ecc.mode = NAND_ECC_SOFT; | |
ff1ef350 | 913 | chip->ecc.algo = NAND_ECC_HAMMING; |
82771882 PK |
914 | } |
915 | ||
d1ab0da8 | 916 | if (ctrl->version >= FSL_IFC_VERSION_1_1_0) |
10bfa766 PK |
917 | fsl_ifc_sram_init(priv); |
918 | ||
82771882 PK |
919 | return 0; |
920 | } | |
921 | ||
922 | static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv) | |
923 | { | |
5e9fb93d | 924 | struct mtd_info *mtd = nand_to_mtd(&priv->chip); |
82771882 | 925 | |
5e9fb93d BB |
926 | nand_release(mtd); |
927 | ||
928 | kfree(mtd->name); | |
82771882 PK |
929 | |
930 | if (priv->vbase) | |
931 | iounmap(priv->vbase); | |
932 | ||
933 | ifc_nand_ctrl->chips[priv->bank] = NULL; | |
82771882 PK |
934 | |
935 | return 0; | |
936 | } | |
937 | ||
7a654172 | 938 | static int match_bank(struct fsl_ifc_global __iomem *ifc_global, int bank, |
82771882 PK |
939 | phys_addr_t addr) |
940 | { | |
7a654172 | 941 | u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr); |
82771882 PK |
942 | |
943 | if (!(cspr & CSPR_V)) | |
944 | return 0; | |
945 | if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND) | |
946 | return 0; | |
947 | ||
948 | return (cspr & CSPR_BA) == convert_ifc_address(addr); | |
949 | } | |
950 | ||
951 | static DEFINE_MUTEX(fsl_ifc_nand_mutex); | |
952 | ||
06f25510 | 953 | static int fsl_ifc_nand_probe(struct platform_device *dev) |
82771882 | 954 | { |
7a654172 | 955 | struct fsl_ifc_runtime __iomem *ifc; |
82771882 PK |
956 | struct fsl_ifc_mtd *priv; |
957 | struct resource res; | |
958 | static const char *part_probe_types[] | |
959 | = { "cmdlinepart", "RedBoot", "ofpart", NULL }; | |
960 | int ret; | |
961 | int bank; | |
962 | struct device_node *node = dev->dev.of_node; | |
5e9fb93d | 963 | struct mtd_info *mtd; |
82771882 | 964 | |
7a654172 | 965 | if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs) |
82771882 | 966 | return -ENODEV; |
7a654172 | 967 | ifc = fsl_ifc_ctrl_dev->rregs; |
82771882 PK |
968 | |
969 | /* get, allocate and map the memory resource */ | |
970 | ret = of_address_to_resource(node, 0, &res); | |
971 | if (ret) { | |
972 | dev_err(&dev->dev, "%s: failed to get resource\n", __func__); | |
973 | return ret; | |
974 | } | |
975 | ||
976 | /* find which chip select it is connected to */ | |
09691661 | 977 | for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) { |
7a654172 | 978 | if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start)) |
82771882 PK |
979 | break; |
980 | } | |
981 | ||
09691661 | 982 | if (bank >= fsl_ifc_ctrl_dev->banks) { |
82771882 PK |
983 | dev_err(&dev->dev, "%s: address did not match any chip selects\n", |
984 | __func__); | |
985 | return -ENODEV; | |
986 | } | |
987 | ||
988 | priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); | |
989 | if (!priv) | |
990 | return -ENOMEM; | |
991 | ||
992 | mutex_lock(&fsl_ifc_nand_mutex); | |
993 | if (!fsl_ifc_ctrl_dev->nand) { | |
994 | ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL); | |
995 | if (!ifc_nand_ctrl) { | |
82771882 PK |
996 | mutex_unlock(&fsl_ifc_nand_mutex); |
997 | return -ENOMEM; | |
998 | } | |
999 | ||
1000 | ifc_nand_ctrl->read_bytes = 0; | |
1001 | ifc_nand_ctrl->index = 0; | |
1002 | ifc_nand_ctrl->addr = NULL; | |
1003 | fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl; | |
1004 | ||
d45bc58d | 1005 | nand_hw_control_init(&ifc_nand_ctrl->controller); |
82771882 PK |
1006 | } else { |
1007 | ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand; | |
1008 | } | |
1009 | mutex_unlock(&fsl_ifc_nand_mutex); | |
1010 | ||
1011 | ifc_nand_ctrl->chips[bank] = priv; | |
1012 | priv->bank = bank; | |
1013 | priv->ctrl = fsl_ifc_ctrl_dev; | |
1014 | priv->dev = &dev->dev; | |
1015 | ||
1016 | priv->vbase = ioremap(res.start, resource_size(&res)); | |
1017 | if (!priv->vbase) { | |
1018 | dev_err(priv->dev, "%s: failed to map chip region\n", __func__); | |
1019 | ret = -ENOMEM; | |
1020 | goto err; | |
1021 | } | |
1022 | ||
1023 | dev_set_drvdata(priv->dev, priv); | |
1024 | ||
cf184dc2 JS |
1025 | ifc_out32(IFC_NAND_EVTER_EN_OPC_EN | |
1026 | IFC_NAND_EVTER_EN_FTOER_EN | | |
1027 | IFC_NAND_EVTER_EN_WPER_EN, | |
1028 | &ifc->ifc_nand.nand_evter_en); | |
82771882 PK |
1029 | |
1030 | /* enable NAND Machine Interrupts */ | |
cf184dc2 JS |
1031 | ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN | |
1032 | IFC_NAND_EVTER_INTR_FTOERIR_EN | | |
1033 | IFC_NAND_EVTER_INTR_WPERIR_EN, | |
1034 | &ifc->ifc_nand.nand_evter_intr_en); | |
5e9fb93d BB |
1035 | |
1036 | mtd = nand_to_mtd(&priv->chip); | |
1037 | mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start); | |
1038 | if (!mtd->name) { | |
82771882 PK |
1039 | ret = -ENOMEM; |
1040 | goto err; | |
1041 | } | |
1042 | ||
1043 | ret = fsl_ifc_chip_init(priv); | |
1044 | if (ret) | |
1045 | goto err; | |
1046 | ||
5e9fb93d | 1047 | ret = nand_scan_ident(mtd, 1, NULL); |
82771882 PK |
1048 | if (ret) |
1049 | goto err; | |
1050 | ||
5e9fb93d | 1051 | ret = fsl_ifc_chip_init_tail(mtd); |
82771882 PK |
1052 | if (ret) |
1053 | goto err; | |
1054 | ||
5e9fb93d | 1055 | ret = nand_scan_tail(mtd); |
82771882 PK |
1056 | if (ret) |
1057 | goto err; | |
1058 | ||
1059 | /* First look for RedBoot table or partitions on the command | |
1060 | * line, these take precedence over device tree information */ | |
5e9fb93d | 1061 | mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0); |
82771882 PK |
1062 | |
1063 | dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n", | |
1064 | (unsigned long long)res.start, priv->bank); | |
1065 | return 0; | |
1066 | ||
1067 | err: | |
1068 | fsl_ifc_chip_remove(priv); | |
1069 | return ret; | |
1070 | } | |
1071 | ||
1072 | static int fsl_ifc_nand_remove(struct platform_device *dev) | |
1073 | { | |
1074 | struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev); | |
1075 | ||
1076 | fsl_ifc_chip_remove(priv); | |
1077 | ||
1078 | mutex_lock(&fsl_ifc_nand_mutex); | |
1079 | ifc_nand_ctrl->counter--; | |
1080 | if (!ifc_nand_ctrl->counter) { | |
1081 | fsl_ifc_ctrl_dev->nand = NULL; | |
1082 | kfree(ifc_nand_ctrl); | |
1083 | } | |
1084 | mutex_unlock(&fsl_ifc_nand_mutex); | |
1085 | ||
1086 | return 0; | |
1087 | } | |
1088 | ||
1089 | static const struct of_device_id fsl_ifc_nand_match[] = { | |
1090 | { | |
1091 | .compatible = "fsl,ifc-nand", | |
1092 | }, | |
1093 | {} | |
1094 | }; | |
3f7f7a5f | 1095 | MODULE_DEVICE_TABLE(of, fsl_ifc_nand_match); |
82771882 PK |
1096 | |
1097 | static struct platform_driver fsl_ifc_nand_driver = { | |
1098 | .driver = { | |
1099 | .name = "fsl,ifc-nand", | |
82771882 PK |
1100 | .of_match_table = fsl_ifc_nand_match, |
1101 | }, | |
1102 | .probe = fsl_ifc_nand_probe, | |
1103 | .remove = fsl_ifc_nand_remove, | |
1104 | }; | |
1105 | ||
c69ad0ef | 1106 | module_platform_driver(fsl_ifc_nand_driver); |
82771882 PK |
1107 | |
1108 | MODULE_LICENSE("GPL"); | |
1109 | MODULE_AUTHOR("Freescale"); | |
1110 | MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver"); |