[mirror_ubuntu-zesty-kernel.git] / drivers / mtd / nand / gpio.c

/*
 * drivers/mtd/nand/gpio.c
 *
 * Updated, and converted to generic GPIO based driver by Russell King.
 *
 * Written by Ben Dooks <ben@simtec.co.uk>
 *   Based on 2.4 version by Mark Whittaker
 *
 * © 2004 Simtec Electronics
 *
 * Device driver for NAND flash that uses a memory mapped interface to
 * read/write the NAND commands and data, and GPIO pins for control signals
 * (the DT binding refers to this as "GPIO assisted NAND flash")
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/nand-gpio.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_gpio.h>

struct gpiomtd {
	void __iomem		*io_sync;
	struct nand_chip	nand_chip;
	struct gpio_nand_platdata plat;
};

static inline struct gpiomtd *gpio_nand_getpriv(struct mtd_info *mtd)
{
	return container_of(mtd_to_nand(mtd), struct gpiomtd, nand_chip);
}


#ifdef CONFIG_ARM
/* gpio_nand_dosync()
 *
 * Make sure the GPIO state changes occur in-order with writes to NAND
 * memory region.
 * Needed on PXA due to bus-reordering within the SoC itself (see section on
 * I/O ordering in PXA manual (section 2.3, p35)
 */
static void gpio_nand_dosync(struct gpiomtd *gpiomtd)
{
	unsigned long tmp;

	if (gpiomtd->io_sync) {
		/*
		 * Linux memory barriers don't cater for what's required here.
		 * What's required is what's here - a read from a separate
		 * region with a dependency on that read.
		 */
		tmp = readl(gpiomtd->io_sync);
		asm volatile("mov %1, %0\n" : "=r" (tmp) : "r" (tmp));
	}
}
#else
static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {}
#endif

static void gpio_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);

	gpio_nand_dosync(gpiomtd);

	if (ctrl & NAND_CTRL_CHANGE) {
		gpio_set_value(gpiomtd->plat.gpio_nce, !(ctrl & NAND_NCE));
		gpio_set_value(gpiomtd->plat.gpio_cle, !!(ctrl & NAND_CLE));
		gpio_set_value(gpiomtd->plat.gpio_ale, !!(ctrl & NAND_ALE));
		gpio_nand_dosync(gpiomtd);
	}
	if (cmd == NAND_CMD_NONE)
		return;

	writeb(cmd, gpiomtd->nand_chip.IO_ADDR_W);
	gpio_nand_dosync(gpiomtd);
}

static int gpio_nand_devready(struct mtd_info *mtd)
{
	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);

	return gpio_get_value(gpiomtd->plat.gpio_rdy);
}

#ifdef CONFIG_OF
static const struct of_device_id gpio_nand_id_table[] = {
	{ .compatible = "gpio-control-nand" },
	{}
};
MODULE_DEVICE_TABLE(of, gpio_nand_id_table);

static int gpio_nand_get_config_of(const struct device *dev,
				   struct gpio_nand_platdata *plat)
{
	u32 val;

	if (!dev->of_node)
		return -ENODEV;

	if (!of_property_read_u32(dev->of_node, "bank-width", &val)) {
		if (val == 2) {
			plat->options |= NAND_BUSWIDTH_16;
		} else if (val != 1) {
			dev_err(dev, "invalid bank-width %u\n", val);
			return -EINVAL;
		}
	}

	plat->gpio_rdy = of_get_gpio(dev->of_node, 0);
	plat->gpio_nce = of_get_gpio(dev->of_node, 1);
	plat->gpio_ale = of_get_gpio(dev->of_node, 2);
	plat->gpio_cle = of_get_gpio(dev->of_node, 3);
	plat->gpio_nwp = of_get_gpio(dev->of_node, 4);

	if (!of_property_read_u32(dev->of_node, "chip-delay", &val))
		plat->chip_delay = val;

	return 0;
}

static struct resource *gpio_nand_get_io_sync_of(struct platform_device *pdev)
{
	struct resource *r;
	u64 addr;

	if (of_property_read_u64(pdev->dev.of_node,
				       "gpio-control-nand,io-sync-reg", &addr))
		return NULL;

	r = devm_kzalloc(&pdev->dev, sizeof(*r), GFP_KERNEL);
	if (!r)
		return NULL;

	r->start = addr;
	r->end = r->start + 0x3;
	r->flags = IORESOURCE_MEM;

	return r;
}
#else /* CONFIG_OF */
static inline int gpio_nand_get_config_of(const struct device *dev,
					  struct gpio_nand_platdata *plat)
{
	return -ENOSYS;
}

static inline struct resource *
gpio_nand_get_io_sync_of(struct platform_device *pdev)
{
	return NULL;
}
#endif /* CONFIG_OF */

static inline int gpio_nand_get_config(const struct device *dev,
				       struct gpio_nand_platdata *plat)
{
	int ret = gpio_nand_get_config_of(dev, plat);

	if (!ret)
		return ret;

	if (dev_get_platdata(dev)) {
		memcpy(plat, dev_get_platdata(dev), sizeof(*plat));
		return 0;
	}

	return -EINVAL;
}

static inline struct resource *
gpio_nand_get_io_sync(struct platform_device *pdev)
{
	struct resource *r = gpio_nand_get_io_sync_of(pdev);

	if (r)
		return r;

	return platform_get_resource(pdev, IORESOURCE_MEM, 1);
}

static int gpio_nand_remove(struct platform_device *pdev)
{
	struct gpiomtd *gpiomtd = platform_get_drvdata(pdev);

	nand_release(nand_to_mtd(&gpiomtd->nand_chip));

	if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
		gpio_set_value(gpiomtd->plat.gpio_nwp, 0);
	gpio_set_value(gpiomtd->plat.gpio_nce, 1);

	return 0;
}

static int gpio_nand_probe(struct platform_device *pdev)
{
	struct gpiomtd *gpiomtd;
	struct nand_chip *chip;
	struct mtd_info *mtd;
	struct resource *res;
	int ret = 0;

	if (!pdev->dev.of_node && !dev_get_platdata(&pdev->dev))
		return -EINVAL;

	gpiomtd = devm_kzalloc(&pdev->dev, sizeof(*gpiomtd), GFP_KERNEL);
	if (!gpiomtd)
		return -ENOMEM;

	chip = &gpiomtd->nand_chip;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(chip->IO_ADDR_R))
		return PTR_ERR(chip->IO_ADDR_R);

	res = gpio_nand_get_io_sync(pdev);
	if (res) {
		gpiomtd->io_sync = devm_ioremap_resource(&pdev->dev, res);
		if (IS_ERR(gpiomtd->io_sync))
			return PTR_ERR(gpiomtd->io_sync);
	}

	ret = gpio_nand_get_config(&pdev->dev, &gpiomtd->plat);
	if (ret)
		return ret;

	ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_nce, "NAND NCE");
	if (ret)
		return ret;
	gpio_direction_output(gpiomtd->plat.gpio_nce, 1);

	if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) {
		ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_nwp,
					"NAND NWP");
		if (ret)
			return ret;
	}

	ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_ale, "NAND ALE");
	if (ret)
		return ret;
	gpio_direction_output(gpiomtd->plat.gpio_ale, 0);

	ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_cle, "NAND CLE");
	if (ret)
		return ret;
	gpio_direction_output(gpiomtd->plat.gpio_cle, 0);

	if (gpio_is_valid(gpiomtd->plat.gpio_rdy)) {
		ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_rdy,
					"NAND RDY");
		if (ret)
			return ret;
		gpio_direction_input(gpiomtd->plat.gpio_rdy);
		chip->dev_ready = gpio_nand_devready;
	}

	nand_set_flash_node(chip, pdev->dev.of_node);
	chip->IO_ADDR_W		= chip->IO_ADDR_R;
	chip->ecc.mode		= NAND_ECC_SOFT;
	chip->ecc.algo		= NAND_ECC_HAMMING;
	chip->options		= gpiomtd->plat.options;
	chip->chip_delay	= gpiomtd->plat.chip_delay;
	chip->cmd_ctrl		= gpio_nand_cmd_ctrl;

	mtd			= nand_to_mtd(chip);
	mtd->dev.parent		= &pdev->dev;

	platform_set_drvdata(pdev, gpiomtd);

	if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
		gpio_direction_output(gpiomtd->plat.gpio_nwp, 1);

	ret = nand_scan(mtd, 1);
	if (ret)
		goto err_wp;

	if (gpiomtd->plat.adjust_parts)
		gpiomtd->plat.adjust_parts(&gpiomtd->plat, mtd->size);

	ret = mtd_device_register(mtd, gpiomtd->plat.parts,
				  gpiomtd->plat.num_parts);
	if (!ret)
		return 0;

err_wp:
	if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
		gpio_set_value(gpiomtd->plat.gpio_nwp, 0);

	return ret;
}

static struct platform_driver gpio_nand_driver = {
	.probe		= gpio_nand_probe,
	.remove		= gpio_nand_remove,
	.driver		= {
		.name	= "gpio-nand",
		.of_match_table = of_match_ptr(gpio_nand_id_table),
	},
};

module_platform_driver(gpio_nand_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
MODULE_DESCRIPTION("GPIO NAND Driver");
Commit	Line	Data
aaf7ea20 MR	1	/*
	2	* drivers/mtd/nand/gpio.c
	3	*
	4	* Updated, and converted to generic GPIO based driver by Russell King.
	5	*
	6	* Written by Ben Dooks <ben@simtec.co.uk>
	7	* Based on 2.4 version by Mark Whittaker
	8	*
	9	* © 2004 Simtec Electronics
	10	*
c9d79c4b GS	11	* Device driver for NAND flash that uses a memory mapped interface to
	12	* read/write the NAND commands and data, and GPIO pins for control signals
	13	* (the DT binding refers to this as "GPIO assisted NAND flash")
aaf7ea20 MR	14	*
	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*
	19	*/
	20
	21	#include <linux/kernel.h>
283df420	22	#include <linux/err.h>
aaf7ea20 MR	23	#include <linux/slab.h>
	24	#include <linux/module.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/gpio.h>
	27	#include <linux/io.h>
	28	#include <linux/mtd/mtd.h>
	29	#include <linux/mtd/nand.h>
	30	#include <linux/mtd/partitions.h>
	31	#include <linux/mtd/nand-gpio.h>
775c3220 JI	32	#include <linux/of.h>
	33	#include <linux/of_address.h>
	34	#include <linux/of_gpio.h>
aaf7ea20 MR	35
	36	struct gpiomtd {
	37	void __iomem *io_sync;
aaf7ea20 MR	38	struct nand_chip nand_chip;
	39	struct gpio_nand_platdata plat;
	40	};
	41
dc2948ca BB	42	static inline struct gpiomtd gpio_nand_getpriv(struct mtd_info mtd)
	43	{
	44	return container_of(mtd_to_nand(mtd), struct gpiomtd, nand_chip);
	45	}
aaf7ea20 MR	46
	47
	48	#ifdef CONFIG_ARM
	49	/* gpio_nand_dosync()
	50	*
	51	* Make sure the GPIO state changes occur in-order with writes to NAND
	52	* memory region.
	53	* Needed on PXA due to bus-reordering within the SoC itself (see section on
	54	* I/O ordering in PXA manual (section 2.3, p35)
	55	*/
	56	static void gpio_nand_dosync(struct gpiomtd *gpiomtd)
	57	{
	58	unsigned long tmp;
	59
	60	if (gpiomtd->io_sync) {
	61	/*
	62	* Linux memory barriers don't cater for what's required here.
	63	* What's required is what's here - a read from a separate
	64	* region with a dependency on that read.
	65	*/
	66	tmp = readl(gpiomtd->io_sync);
	67	asm volatile("mov %1, %0\n" : "=r" (tmp) : "r" (tmp));
	68	}
	69	}
	70	#else
	71	static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {}
	72	#endif
	73
	74	static void gpio_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
	75	{
	76	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
	77
	78	gpio_nand_dosync(gpiomtd);
	79
	80	if (ctrl & NAND_CTRL_CHANGE) {
	81	gpio_set_value(gpiomtd->plat.gpio_nce, !(ctrl & NAND_NCE));
	82	gpio_set_value(gpiomtd->plat.gpio_cle, !!(ctrl & NAND_CLE));
	83	gpio_set_value(gpiomtd->plat.gpio_ale, !!(ctrl & NAND_ALE));
	84	gpio_nand_dosync(gpiomtd);
	85	}
	86	if (cmd == NAND_CMD_NONE)
	87	return;
	88
	89	writeb(cmd, gpiomtd->nand_chip.IO_ADDR_W);
	90	gpio_nand_dosync(gpiomtd);
	91	}
	92
aaf7ea20 MR	93	static int gpio_nand_devready(struct mtd_info *mtd)
	94	{
	95	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
18afbc54	96
c85d32d5	97	return gpio_get_value(gpiomtd->plat.gpio_rdy);
aaf7ea20 MR	98	}
aaf7ea20 MR	99
775c3220 JI	100	#ifdef CONFIG_OF
	101	static const struct of_device_id gpio_nand_id_table[] = {
	102	{ .compatible = "gpio-control-nand" },
	103	{}
	104	};
	105	MODULE_DEVICE_TABLE(of, gpio_nand_id_table);
	106
	107	static int gpio_nand_get_config_of(const struct device *dev,
	108	struct gpio_nand_platdata *plat)
	109	{
	110	u32 val;
	111
ee4f3666 AS	112	if (!dev->of_node)
	113	return -ENODEV;
	114
775c3220 JI	115	if (!of_property_read_u32(dev->of_node, "bank-width", &val)) {
	116	if (val == 2) {
	117	plat->options \|= NAND_BUSWIDTH_16;
	118	} else if (val != 1) {
	119	dev_err(dev, "invalid bank-width %u\n", val);
	120	return -EINVAL;
	121	}
	122	}
	123
	124	plat->gpio_rdy = of_get_gpio(dev->of_node, 0);
	125	plat->gpio_nce = of_get_gpio(dev->of_node, 1);
	126	plat->gpio_ale = of_get_gpio(dev->of_node, 2);
	127	plat->gpio_cle = of_get_gpio(dev->of_node, 3);
	128	plat->gpio_nwp = of_get_gpio(dev->of_node, 4);
	129
	130	if (!of_property_read_u32(dev->of_node, "chip-delay", &val))
	131	plat->chip_delay = val;
	132
	133	return 0;
	134	}
	135
	136	static struct resource gpio_nand_get_io_sync_of(struct platform_device pdev)
	137	{
103cdd85	138	struct resource *r;
775c3220 JI	139	u64 addr;
775c3220 JI	140
103cdd85	141	if (of_property_read_u64(pdev->dev.of_node,
775c3220 JI	142	"gpio-control-nand,io-sync-reg", &addr))
	143	return NULL;
	144
103cdd85 BN	145	r = devm_kzalloc(&pdev->dev, sizeof(*r), GFP_KERNEL);
	146	if (!r)
	147	return NULL;
	148
775c3220 JI	149	r->start = addr;
	150	r->end = r->start + 0x3;
	151	r->flags = IORESOURCE_MEM;
	152
	153	return r;
	154	}
	155	#else /* CONFIG_OF */
775c3220 JI	156	static inline int gpio_nand_get_config_of(const struct device *dev,
	157	struct gpio_nand_platdata *plat)
	158	{
	159	return -ENOSYS;
	160	}
	161
	162	static inline struct resource *
	163	gpio_nand_get_io_sync_of(struct platform_device *pdev)
	164	{
	165	return NULL;
	166	}
	167	#endif /* CONFIG_OF */
	168
	169	static inline int gpio_nand_get_config(const struct device *dev,
	170	struct gpio_nand_platdata *plat)
	171	{
	172	int ret = gpio_nand_get_config_of(dev, plat);
	173
	174	if (!ret)
	175	return ret;
	176
453810b7 JH	177	if (dev_get_platdata(dev)) {
453810b7 JH	178	memcpy(plat, dev_get_platdata(dev), sizeof(*plat));
775c3220 JI	179	return 0;
	180	}
	181
	182	return -EINVAL;
	183	}
	184
	185	static inline struct resource *
	186	gpio_nand_get_io_sync(struct platform_device *pdev)
	187	{
	188	struct resource *r = gpio_nand_get_io_sync_of(pdev);
	189
	190	if (r)
	191	return r;
	192
	193	return platform_get_resource(pdev, IORESOURCE_MEM, 1);
	194	}
	195
f8e81c2b	196	static int gpio_nand_remove(struct platform_device *pdev)
aaf7ea20	197	{
f8e81c2b	198	struct gpiomtd *gpiomtd = platform_get_drvdata(pdev);
aaf7ea20	199
dc2948ca	200	nand_release(nand_to_mtd(&gpiomtd->nand_chip));
aaf7ea20	201
aaf7ea20 MR	202	if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
	203	gpio_set_value(gpiomtd->plat.gpio_nwp, 0);
	204	gpio_set_value(gpiomtd->plat.gpio_nce, 1);
	205
aaf7ea20 MR	206	return 0;
	207	}
	208
f8e81c2b	209	static int gpio_nand_probe(struct platform_device *pdev)
aaf7ea20 MR	210	{
aaf7ea20 MR	211	struct gpiomtd *gpiomtd;
f8e81c2b	212	struct nand_chip *chip;
dc2948ca	213	struct mtd_info *mtd;
283df420	214	struct resource *res;
775c3220	215	int ret = 0;
aaf7ea20	216
453810b7	217	if (!pdev->dev.of_node && !dev_get_platdata(&pdev->dev))
aaf7ea20 MR	218	return -EINVAL;
aaf7ea20 MR	219
f8e81c2b	220	gpiomtd = devm_kzalloc(&pdev->dev, sizeof(*gpiomtd), GFP_KERNEL);
24e9971d	221	if (!gpiomtd)
aaf7ea20	222	return -ENOMEM;
aaf7ea20	223
f8e81c2b	224	chip = &gpiomtd->nand_chip;
aaf7ea20	225
f8e81c2b AS	226	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	227	chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
	228	if (IS_ERR(chip->IO_ADDR_R))
	229	return PTR_ERR(chip->IO_ADDR_R);
283df420	230
f8e81c2b	231	res = gpio_nand_get_io_sync(pdev);
283df420	232	if (res) {
f8e81c2b	233	gpiomtd->io_sync = devm_ioremap_resource(&pdev->dev, res);
283df420 AS	234	if (IS_ERR(gpiomtd->io_sync))
283df420 AS	235	return PTR_ERR(gpiomtd->io_sync);
aaf7ea20 MR	236	}
aaf7ea20 MR	237
f8e81c2b	238	ret = gpio_nand_get_config(&pdev->dev, &gpiomtd->plat);
775c3220	239	if (ret)
283df420	240	return ret;
aaf7ea20	241
f8e81c2b	242	ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_nce, "NAND NCE");
aaf7ea20	243	if (ret)
283df420	244	return ret;
aaf7ea20	245	gpio_direction_output(gpiomtd->plat.gpio_nce, 1);
283df420	246
aaf7ea20	247	if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) {
f8e81c2b	248	ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_nwp,
283df420	249	"NAND NWP");
aaf7ea20	250	if (ret)
283df420	251	return ret;
aaf7ea20	252	}
283df420	253
f8e81c2b	254	ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_ale, "NAND ALE");
aaf7ea20	255	if (ret)
283df420	256	return ret;
aaf7ea20	257	gpio_direction_output(gpiomtd->plat.gpio_ale, 0);
283df420	258
f8e81c2b	259	ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_cle, "NAND CLE");
aaf7ea20	260	if (ret)
283df420	261	return ret;
aaf7ea20	262	gpio_direction_output(gpiomtd->plat.gpio_cle, 0);
283df420	263
18afbc54	264	if (gpio_is_valid(gpiomtd->plat.gpio_rdy)) {
f8e81c2b	265	ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_rdy,
283df420	266	"NAND RDY");
18afbc54	267	if (ret)
283df420	268	return ret;
18afbc54	269	gpio_direction_input(gpiomtd->plat.gpio_rdy);
f8e81c2b	270	chip->dev_ready = gpio_nand_devready;
18afbc54	271	}
aaf7ea20	272
a61ae81a	273	nand_set_flash_node(chip, pdev->dev.of_node);
f8e81c2b AS	274	chip->IO_ADDR_W = chip->IO_ADDR_R;
f8e81c2b AS	275	chip->ecc.mode = NAND_ECC_SOFT;
050658c8	276	chip->ecc.algo = NAND_ECC_HAMMING;
f8e81c2b AS	277	chip->options = gpiomtd->plat.options;
	278	chip->chip_delay = gpiomtd->plat.chip_delay;
	279	chip->cmd_ctrl = gpio_nand_cmd_ctrl;
aaf7ea20	280
dc2948ca	281	mtd = nand_to_mtd(chip);
dc2948ca	282	mtd->dev.parent = &pdev->dev;
aaf7ea20	283
f8e81c2b	284	platform_set_drvdata(pdev, gpiomtd);
283df420 AS	285
	286	if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
	287	gpio_direction_output(gpiomtd->plat.gpio_nwp, 1);
	288
408bf51e MY	289	ret = nand_scan(mtd, 1);
408bf51e MY	290	if (ret)
aaf7ea20	291	goto err_wp;
aaf7ea20 MR	292
aaf7ea20 MR	293	if (gpiomtd->plat.adjust_parts)
dc2948ca	294	gpiomtd->plat.adjust_parts(&gpiomtd->plat, mtd->size);
aaf7ea20	295
dc2948ca	296	ret = mtd_device_register(mtd, gpiomtd->plat.parts,
a61ae81a	297	gpiomtd->plat.num_parts);
283df420 AS	298	if (!ret)
283df420 AS	299	return 0;
aaf7ea20 MR	300
	301	err_wp:
	302	if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
	303	gpio_set_value(gpiomtd->plat.gpio_nwp, 0);
283df420	304
aaf7ea20 MR	305	return ret;
	306	}
	307
	308	static struct platform_driver gpio_nand_driver = {
	309	.probe = gpio_nand_probe,
	310	.remove = gpio_nand_remove,
	311	.driver = {
	312	.name = "gpio-nand",
b57d43ff	313	.of_match_table = of_match_ptr(gpio_nand_id_table),
aaf7ea20 MR	314	},
	315	};
	316
2fe87aef	317	module_platform_driver(gpio_nand_driver);
aaf7ea20 MR	318
	319	MODULE_LICENSE("GPL");
	320	MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
	321	MODULE_DESCRIPTION("GPIO NAND Driver");