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aaf7ea20 MR |
1 | /* |
2 | * drivers/mtd/nand/gpio.c | |
3 | * | |
4 | * Updated, and converted to generic GPIO based driver by Russell King. | |
5 | * | |
6 | * Written by Ben Dooks <ben@simtec.co.uk> | |
7 | * Based on 2.4 version by Mark Whittaker | |
8 | * | |
9 | * © 2004 Simtec Electronics | |
10 | * | |
c9d79c4b GS |
11 | * Device driver for NAND flash that uses a memory mapped interface to |
12 | * read/write the NAND commands and data, and GPIO pins for control signals | |
13 | * (the DT binding refers to this as "GPIO assisted NAND flash") | |
aaf7ea20 MR |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | * | |
19 | */ | |
20 | ||
21 | #include <linux/kernel.h> | |
283df420 | 22 | #include <linux/err.h> |
aaf7ea20 MR |
23 | #include <linux/slab.h> |
24 | #include <linux/module.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/gpio.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/mtd/mtd.h> | |
29 | #include <linux/mtd/nand.h> | |
30 | #include <linux/mtd/partitions.h> | |
31 | #include <linux/mtd/nand-gpio.h> | |
775c3220 JI |
32 | #include <linux/of.h> |
33 | #include <linux/of_address.h> | |
34 | #include <linux/of_gpio.h> | |
aaf7ea20 MR |
35 | |
36 | struct gpiomtd { | |
37 | void __iomem *io_sync; | |
aaf7ea20 MR |
38 | struct nand_chip nand_chip; |
39 | struct gpio_nand_platdata plat; | |
40 | }; | |
41 | ||
dc2948ca BB |
42 | static inline struct gpiomtd *gpio_nand_getpriv(struct mtd_info *mtd) |
43 | { | |
44 | return container_of(mtd_to_nand(mtd), struct gpiomtd, nand_chip); | |
45 | } | |
aaf7ea20 MR |
46 | |
47 | ||
48 | #ifdef CONFIG_ARM | |
49 | /* gpio_nand_dosync() | |
50 | * | |
51 | * Make sure the GPIO state changes occur in-order with writes to NAND | |
52 | * memory region. | |
53 | * Needed on PXA due to bus-reordering within the SoC itself (see section on | |
54 | * I/O ordering in PXA manual (section 2.3, p35) | |
55 | */ | |
56 | static void gpio_nand_dosync(struct gpiomtd *gpiomtd) | |
57 | { | |
58 | unsigned long tmp; | |
59 | ||
60 | if (gpiomtd->io_sync) { | |
61 | /* | |
62 | * Linux memory barriers don't cater for what's required here. | |
63 | * What's required is what's here - a read from a separate | |
64 | * region with a dependency on that read. | |
65 | */ | |
66 | tmp = readl(gpiomtd->io_sync); | |
67 | asm volatile("mov %1, %0\n" : "=r" (tmp) : "r" (tmp)); | |
68 | } | |
69 | } | |
70 | #else | |
71 | static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {} | |
72 | #endif | |
73 | ||
74 | static void gpio_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
75 | { | |
76 | struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd); | |
77 | ||
78 | gpio_nand_dosync(gpiomtd); | |
79 | ||
80 | if (ctrl & NAND_CTRL_CHANGE) { | |
44dd1828 CL |
81 | if (gpio_is_valid(gpiomtd->plat.gpio_nce)) |
82 | gpio_set_value(gpiomtd->plat.gpio_nce, | |
83 | !(ctrl & NAND_NCE)); | |
aaf7ea20 MR |
84 | gpio_set_value(gpiomtd->plat.gpio_cle, !!(ctrl & NAND_CLE)); |
85 | gpio_set_value(gpiomtd->plat.gpio_ale, !!(ctrl & NAND_ALE)); | |
86 | gpio_nand_dosync(gpiomtd); | |
87 | } | |
88 | if (cmd == NAND_CMD_NONE) | |
89 | return; | |
90 | ||
91 | writeb(cmd, gpiomtd->nand_chip.IO_ADDR_W); | |
92 | gpio_nand_dosync(gpiomtd); | |
93 | } | |
94 | ||
aaf7ea20 MR |
95 | static int gpio_nand_devready(struct mtd_info *mtd) |
96 | { | |
97 | struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd); | |
18afbc54 | 98 | |
c85d32d5 | 99 | return gpio_get_value(gpiomtd->plat.gpio_rdy); |
aaf7ea20 MR |
100 | } |
101 | ||
775c3220 JI |
102 | #ifdef CONFIG_OF |
103 | static const struct of_device_id gpio_nand_id_table[] = { | |
104 | { .compatible = "gpio-control-nand" }, | |
105 | {} | |
106 | }; | |
107 | MODULE_DEVICE_TABLE(of, gpio_nand_id_table); | |
108 | ||
109 | static int gpio_nand_get_config_of(const struct device *dev, | |
110 | struct gpio_nand_platdata *plat) | |
111 | { | |
112 | u32 val; | |
113 | ||
ee4f3666 AS |
114 | if (!dev->of_node) |
115 | return -ENODEV; | |
116 | ||
775c3220 JI |
117 | if (!of_property_read_u32(dev->of_node, "bank-width", &val)) { |
118 | if (val == 2) { | |
119 | plat->options |= NAND_BUSWIDTH_16; | |
120 | } else if (val != 1) { | |
121 | dev_err(dev, "invalid bank-width %u\n", val); | |
122 | return -EINVAL; | |
123 | } | |
124 | } | |
125 | ||
126 | plat->gpio_rdy = of_get_gpio(dev->of_node, 0); | |
127 | plat->gpio_nce = of_get_gpio(dev->of_node, 1); | |
128 | plat->gpio_ale = of_get_gpio(dev->of_node, 2); | |
129 | plat->gpio_cle = of_get_gpio(dev->of_node, 3); | |
130 | plat->gpio_nwp = of_get_gpio(dev->of_node, 4); | |
131 | ||
132 | if (!of_property_read_u32(dev->of_node, "chip-delay", &val)) | |
133 | plat->chip_delay = val; | |
134 | ||
135 | return 0; | |
136 | } | |
137 | ||
138 | static struct resource *gpio_nand_get_io_sync_of(struct platform_device *pdev) | |
139 | { | |
103cdd85 | 140 | struct resource *r; |
775c3220 JI |
141 | u64 addr; |
142 | ||
103cdd85 | 143 | if (of_property_read_u64(pdev->dev.of_node, |
775c3220 JI |
144 | "gpio-control-nand,io-sync-reg", &addr)) |
145 | return NULL; | |
146 | ||
103cdd85 BN |
147 | r = devm_kzalloc(&pdev->dev, sizeof(*r), GFP_KERNEL); |
148 | if (!r) | |
149 | return NULL; | |
150 | ||
775c3220 JI |
151 | r->start = addr; |
152 | r->end = r->start + 0x3; | |
153 | r->flags = IORESOURCE_MEM; | |
154 | ||
155 | return r; | |
156 | } | |
157 | #else /* CONFIG_OF */ | |
775c3220 JI |
158 | static inline int gpio_nand_get_config_of(const struct device *dev, |
159 | struct gpio_nand_platdata *plat) | |
160 | { | |
161 | return -ENOSYS; | |
162 | } | |
163 | ||
164 | static inline struct resource * | |
165 | gpio_nand_get_io_sync_of(struct platform_device *pdev) | |
166 | { | |
167 | return NULL; | |
168 | } | |
169 | #endif /* CONFIG_OF */ | |
170 | ||
171 | static inline int gpio_nand_get_config(const struct device *dev, | |
172 | struct gpio_nand_platdata *plat) | |
173 | { | |
174 | int ret = gpio_nand_get_config_of(dev, plat); | |
175 | ||
176 | if (!ret) | |
177 | return ret; | |
178 | ||
453810b7 JH |
179 | if (dev_get_platdata(dev)) { |
180 | memcpy(plat, dev_get_platdata(dev), sizeof(*plat)); | |
775c3220 JI |
181 | return 0; |
182 | } | |
183 | ||
184 | return -EINVAL; | |
185 | } | |
186 | ||
187 | static inline struct resource * | |
188 | gpio_nand_get_io_sync(struct platform_device *pdev) | |
189 | { | |
190 | struct resource *r = gpio_nand_get_io_sync_of(pdev); | |
191 | ||
192 | if (r) | |
193 | return r; | |
194 | ||
195 | return platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
196 | } | |
197 | ||
f8e81c2b | 198 | static int gpio_nand_remove(struct platform_device *pdev) |
aaf7ea20 | 199 | { |
f8e81c2b | 200 | struct gpiomtd *gpiomtd = platform_get_drvdata(pdev); |
aaf7ea20 | 201 | |
dc2948ca | 202 | nand_release(nand_to_mtd(&gpiomtd->nand_chip)); |
aaf7ea20 | 203 | |
aaf7ea20 MR |
204 | if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) |
205 | gpio_set_value(gpiomtd->plat.gpio_nwp, 0); | |
44dd1828 CL |
206 | if (gpio_is_valid(gpiomtd->plat.gpio_nce)) |
207 | gpio_set_value(gpiomtd->plat.gpio_nce, 1); | |
aaf7ea20 | 208 | |
aaf7ea20 MR |
209 | return 0; |
210 | } | |
211 | ||
f8e81c2b | 212 | static int gpio_nand_probe(struct platform_device *pdev) |
aaf7ea20 MR |
213 | { |
214 | struct gpiomtd *gpiomtd; | |
f8e81c2b | 215 | struct nand_chip *chip; |
dc2948ca | 216 | struct mtd_info *mtd; |
283df420 | 217 | struct resource *res; |
775c3220 | 218 | int ret = 0; |
aaf7ea20 | 219 | |
453810b7 | 220 | if (!pdev->dev.of_node && !dev_get_platdata(&pdev->dev)) |
aaf7ea20 MR |
221 | return -EINVAL; |
222 | ||
f8e81c2b | 223 | gpiomtd = devm_kzalloc(&pdev->dev, sizeof(*gpiomtd), GFP_KERNEL); |
24e9971d | 224 | if (!gpiomtd) |
aaf7ea20 | 225 | return -ENOMEM; |
aaf7ea20 | 226 | |
f8e81c2b | 227 | chip = &gpiomtd->nand_chip; |
aaf7ea20 | 228 | |
f8e81c2b AS |
229 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
230 | chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res); | |
231 | if (IS_ERR(chip->IO_ADDR_R)) | |
232 | return PTR_ERR(chip->IO_ADDR_R); | |
283df420 | 233 | |
f8e81c2b | 234 | res = gpio_nand_get_io_sync(pdev); |
283df420 | 235 | if (res) { |
f8e81c2b | 236 | gpiomtd->io_sync = devm_ioremap_resource(&pdev->dev, res); |
283df420 AS |
237 | if (IS_ERR(gpiomtd->io_sync)) |
238 | return PTR_ERR(gpiomtd->io_sync); | |
aaf7ea20 MR |
239 | } |
240 | ||
f8e81c2b | 241 | ret = gpio_nand_get_config(&pdev->dev, &gpiomtd->plat); |
775c3220 | 242 | if (ret) |
283df420 | 243 | return ret; |
aaf7ea20 | 244 | |
44dd1828 CL |
245 | if (gpio_is_valid(gpiomtd->plat.gpio_nce)) { |
246 | ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_nce, | |
247 | "NAND NCE"); | |
248 | if (ret) | |
249 | return ret; | |
250 | gpio_direction_output(gpiomtd->plat.gpio_nce, 1); | |
251 | } | |
283df420 | 252 | |
aaf7ea20 | 253 | if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) { |
f8e81c2b | 254 | ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_nwp, |
283df420 | 255 | "NAND NWP"); |
aaf7ea20 | 256 | if (ret) |
283df420 | 257 | return ret; |
aaf7ea20 | 258 | } |
283df420 | 259 | |
f8e81c2b | 260 | ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_ale, "NAND ALE"); |
aaf7ea20 | 261 | if (ret) |
283df420 | 262 | return ret; |
aaf7ea20 | 263 | gpio_direction_output(gpiomtd->plat.gpio_ale, 0); |
283df420 | 264 | |
f8e81c2b | 265 | ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_cle, "NAND CLE"); |
aaf7ea20 | 266 | if (ret) |
283df420 | 267 | return ret; |
aaf7ea20 | 268 | gpio_direction_output(gpiomtd->plat.gpio_cle, 0); |
283df420 | 269 | |
18afbc54 | 270 | if (gpio_is_valid(gpiomtd->plat.gpio_rdy)) { |
f8e81c2b | 271 | ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_rdy, |
283df420 | 272 | "NAND RDY"); |
18afbc54 | 273 | if (ret) |
283df420 | 274 | return ret; |
18afbc54 | 275 | gpio_direction_input(gpiomtd->plat.gpio_rdy); |
f8e81c2b | 276 | chip->dev_ready = gpio_nand_devready; |
18afbc54 | 277 | } |
aaf7ea20 | 278 | |
a61ae81a | 279 | nand_set_flash_node(chip, pdev->dev.of_node); |
f8e81c2b AS |
280 | chip->IO_ADDR_W = chip->IO_ADDR_R; |
281 | chip->ecc.mode = NAND_ECC_SOFT; | |
050658c8 | 282 | chip->ecc.algo = NAND_ECC_HAMMING; |
f8e81c2b AS |
283 | chip->options = gpiomtd->plat.options; |
284 | chip->chip_delay = gpiomtd->plat.chip_delay; | |
285 | chip->cmd_ctrl = gpio_nand_cmd_ctrl; | |
aaf7ea20 | 286 | |
dc2948ca | 287 | mtd = nand_to_mtd(chip); |
dc2948ca | 288 | mtd->dev.parent = &pdev->dev; |
aaf7ea20 | 289 | |
f8e81c2b | 290 | platform_set_drvdata(pdev, gpiomtd); |
283df420 AS |
291 | |
292 | if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) | |
293 | gpio_direction_output(gpiomtd->plat.gpio_nwp, 1); | |
294 | ||
408bf51e MY |
295 | ret = nand_scan(mtd, 1); |
296 | if (ret) | |
aaf7ea20 | 297 | goto err_wp; |
aaf7ea20 MR |
298 | |
299 | if (gpiomtd->plat.adjust_parts) | |
dc2948ca | 300 | gpiomtd->plat.adjust_parts(&gpiomtd->plat, mtd->size); |
aaf7ea20 | 301 | |
dc2948ca | 302 | ret = mtd_device_register(mtd, gpiomtd->plat.parts, |
a61ae81a | 303 | gpiomtd->plat.num_parts); |
283df420 AS |
304 | if (!ret) |
305 | return 0; | |
aaf7ea20 MR |
306 | |
307 | err_wp: | |
308 | if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) | |
309 | gpio_set_value(gpiomtd->plat.gpio_nwp, 0); | |
283df420 | 310 | |
aaf7ea20 MR |
311 | return ret; |
312 | } | |
313 | ||
314 | static struct platform_driver gpio_nand_driver = { | |
315 | .probe = gpio_nand_probe, | |
316 | .remove = gpio_nand_remove, | |
317 | .driver = { | |
318 | .name = "gpio-nand", | |
b57d43ff | 319 | .of_match_table = of_match_ptr(gpio_nand_id_table), |
aaf7ea20 MR |
320 | }, |
321 | }; | |
322 | ||
2fe87aef | 323 | module_platform_driver(gpio_nand_driver); |
aaf7ea20 MR |
324 | |
325 | MODULE_LICENSE("GPL"); | |
326 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
327 | MODULE_DESCRIPTION("GPIO NAND Driver"); |