[mirror_ubuntu-eoan-kernel.git] / drivers / mtd / nand / gpio.c

/*
 * drivers/mtd/nand/gpio.c
 *
 * Updated, and converted to generic GPIO based driver by Russell King.
 *
 * Written by Ben Dooks <ben@simtec.co.uk>
 *   Based on 2.4 version by Mark Whittaker
 *
 * © 2004 Simtec Electronics
 *
 * Device driver for NAND connected via GPIO
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/nand-gpio.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_gpio.h>

struct gpiomtd {
	void __iomem		*io_sync;
	struct mtd_info		mtd_info;
	struct nand_chip	nand_chip;
	struct gpio_nand_platdata plat;
};

#define gpio_nand_getpriv(x) container_of(x, struct gpiomtd, mtd_info)


#ifdef CONFIG_ARM
/* gpio_nand_dosync()
 *
 * Make sure the GPIO state changes occur in-order with writes to NAND
 * memory region.
 * Needed on PXA due to bus-reordering within the SoC itself (see section on
 * I/O ordering in PXA manual (section 2.3, p35)
 */
static void gpio_nand_dosync(struct gpiomtd *gpiomtd)
{
	unsigned long tmp;

	if (gpiomtd->io_sync) {
		/*
		 * Linux memory barriers don't cater for what's required here.
		 * What's required is what's here - a read from a separate
		 * region with a dependency on that read.
		 */
		tmp = readl(gpiomtd->io_sync);
		asm volatile("mov %1, %0\n" : "=r" (tmp) : "r" (tmp));
	}
}
#else
static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {}
#endif

static void gpio_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);

	gpio_nand_dosync(gpiomtd);

	if (ctrl & NAND_CTRL_CHANGE) {
		gpio_set_value(gpiomtd->plat.gpio_nce, !(ctrl & NAND_NCE));
		gpio_set_value(gpiomtd->plat.gpio_cle, !!(ctrl & NAND_CLE));
		gpio_set_value(gpiomtd->plat.gpio_ale, !!(ctrl & NAND_ALE));
		gpio_nand_dosync(gpiomtd);
	}
	if (cmd == NAND_CMD_NONE)
		return;

	writeb(cmd, gpiomtd->nand_chip.IO_ADDR_W);
	gpio_nand_dosync(gpiomtd);
}

static void gpio_nand_writebuf(struct mtd_info *mtd, const u_char *buf, int len)
{
	struct nand_chip *this = mtd->priv;

	iowrite8_rep(this->IO_ADDR_W, buf, len);
}

static void gpio_nand_readbuf(struct mtd_info *mtd, u_char *buf, int len)
{
	struct nand_chip *this = mtd->priv;

	ioread8_rep(this->IO_ADDR_R, buf, len);
}

static void gpio_nand_writebuf16(struct mtd_info *mtd, const u_char *buf,
				 int len)
{
	struct nand_chip *this = mtd->priv;

	if (IS_ALIGNED((unsigned long)buf, 2)) {
		iowrite16_rep(this->IO_ADDR_W, buf, len>>1);
	} else {
		int i;
		unsigned short *ptr = (unsigned short *)buf;

		for (i = 0; i < len; i += 2, ptr++)
			writew(*ptr, this->IO_ADDR_W);
	}
}

static void gpio_nand_readbuf16(struct mtd_info *mtd, u_char *buf, int len)
{
	struct nand_chip *this = mtd->priv;

	if (IS_ALIGNED((unsigned long)buf, 2)) {
		ioread16_rep(this->IO_ADDR_R, buf, len>>1);
	} else {
		int i;
		unsigned short *ptr = (unsigned short *)buf;

		for (i = 0; i < len; i += 2, ptr++)
			*ptr = readw(this->IO_ADDR_R);
	}
}

static int gpio_nand_devready(struct mtd_info *mtd)
{
	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);

	if (gpio_is_valid(gpiomtd->plat.gpio_rdy))
		return gpio_get_value(gpiomtd->plat.gpio_rdy);

	return 1;
}

#ifdef CONFIG_OF
static const struct of_device_id gpio_nand_id_table[] = {
	{ .compatible = "gpio-control-nand" },
	{}
};
MODULE_DEVICE_TABLE(of, gpio_nand_id_table);

static int gpio_nand_get_config_of(const struct device *dev,
				   struct gpio_nand_platdata *plat)
{
	u32 val;

	if (!of_property_read_u32(dev->of_node, "bank-width", &val)) {
		if (val == 2) {
			plat->options |= NAND_BUSWIDTH_16;
		} else if (val != 1) {
			dev_err(dev, "invalid bank-width %u\n", val);
			return -EINVAL;
		}
	}

	plat->gpio_rdy = of_get_gpio(dev->of_node, 0);
	plat->gpio_nce = of_get_gpio(dev->of_node, 1);
	plat->gpio_ale = of_get_gpio(dev->of_node, 2);
	plat->gpio_cle = of_get_gpio(dev->of_node, 3);
	plat->gpio_nwp = of_get_gpio(dev->of_node, 4);

	if (!of_property_read_u32(dev->of_node, "chip-delay", &val))
		plat->chip_delay = val;

	return 0;
}

static struct resource *gpio_nand_get_io_sync_of(struct platform_device *pdev)
{
	struct resource *r = devm_kzalloc(&pdev->dev, sizeof(*r), GFP_KERNEL);
	u64 addr;

	if (!r || of_property_read_u64(pdev->dev.of_node,
				       "gpio-control-nand,io-sync-reg", &addr))
		return NULL;

	r->start = addr;
	r->end = r->start + 0x3;
	r->flags = IORESOURCE_MEM;

	return r;
}
#else /* CONFIG_OF */
static inline int gpio_nand_get_config_of(const struct device *dev,
					  struct gpio_nand_platdata *plat)
{
	return -ENOSYS;
}

static inline struct resource *
gpio_nand_get_io_sync_of(struct platform_device *pdev)
{
	return NULL;
}
#endif /* CONFIG_OF */

static inline int gpio_nand_get_config(const struct device *dev,
				       struct gpio_nand_platdata *plat)
{
	int ret = gpio_nand_get_config_of(dev, plat);

	if (!ret)
		return ret;

	if (dev->platform_data) {
		memcpy(plat, dev->platform_data, sizeof(*plat));
		return 0;
	}

	return -EINVAL;
}

static inline struct resource *
gpio_nand_get_io_sync(struct platform_device *pdev)
{
	struct resource *r = gpio_nand_get_io_sync_of(pdev);

	if (r)
		return r;

	return platform_get_resource(pdev, IORESOURCE_MEM, 1);
}

static int gpio_nand_remove(struct platform_device *dev)
{
	struct gpiomtd *gpiomtd = platform_get_drvdata(dev);

	nand_release(&gpiomtd->mtd_info);

	if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
		gpio_set_value(gpiomtd->plat.gpio_nwp, 0);
	gpio_set_value(gpiomtd->plat.gpio_nce, 1);

	return 0;
}

static int gpio_nand_probe(struct platform_device *dev)
{
	struct gpiomtd *gpiomtd;
	struct nand_chip *this;
	struct resource *res;
	struct mtd_part_parser_data ppdata = {};
	int ret = 0;

	if (!dev->dev.of_node && !dev->dev.platform_data)
		return -EINVAL;

	gpiomtd = devm_kzalloc(&dev->dev, sizeof(*gpiomtd), GFP_KERNEL);
	if (!gpiomtd) {
		dev_err(&dev->dev, "failed to create NAND MTD\n");
		return -ENOMEM;
	}

	this = &gpiomtd->nand_chip;

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	this->IO_ADDR_R = devm_ioremap_resource(&dev->dev, res);
	if (IS_ERR(this->IO_ADDR_R))
		return PTR_ERR(this->IO_ADDR_R);

	res = gpio_nand_get_io_sync(dev);
	if (res) {
		gpiomtd->io_sync = devm_ioremap_resource(&dev->dev, res);
		if (IS_ERR(gpiomtd->io_sync))
			return PTR_ERR(gpiomtd->io_sync);
	}

	ret = gpio_nand_get_config(&dev->dev, &gpiomtd->plat);
	if (ret)
		return ret;

	ret = devm_gpio_request(&dev->dev, gpiomtd->plat.gpio_nce, "NAND NCE");
	if (ret)
		return ret;
	gpio_direction_output(gpiomtd->plat.gpio_nce, 1);

	if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) {
		ret = devm_gpio_request(&dev->dev, gpiomtd->plat.gpio_nwp,
					"NAND NWP");
		if (ret)
			return ret;
	}

	ret = devm_gpio_request(&dev->dev, gpiomtd->plat.gpio_ale, "NAND ALE");
	if (ret)
		return ret;
	gpio_direction_output(gpiomtd->plat.gpio_ale, 0);

	ret = devm_gpio_request(&dev->dev, gpiomtd->plat.gpio_cle, "NAND CLE");
	if (ret)
		return ret;
	gpio_direction_output(gpiomtd->plat.gpio_cle, 0);

	if (gpio_is_valid(gpiomtd->plat.gpio_rdy)) {
		ret = devm_gpio_request(&dev->dev, gpiomtd->plat.gpio_rdy,
					"NAND RDY");
		if (ret)
			return ret;
		gpio_direction_input(gpiomtd->plat.gpio_rdy);
	}

	this->IO_ADDR_W  = this->IO_ADDR_R;
	this->ecc.mode   = NAND_ECC_SOFT;
	this->options    = gpiomtd->plat.options;
	this->chip_delay = gpiomtd->plat.chip_delay;

	/* install our routines */
	this->cmd_ctrl   = gpio_nand_cmd_ctrl;
	this->dev_ready  = gpio_nand_devready;

	if (this->options & NAND_BUSWIDTH_16) {
		this->read_buf   = gpio_nand_readbuf16;
		this->write_buf  = gpio_nand_writebuf16;
	} else {
		this->read_buf   = gpio_nand_readbuf;
		this->write_buf  = gpio_nand_writebuf;
	}

	/* set the mtd private data for the nand driver */
	gpiomtd->mtd_info.priv = this;
	gpiomtd->mtd_info.owner = THIS_MODULE;

	platform_set_drvdata(dev, gpiomtd);

	if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
		gpio_direction_output(gpiomtd->plat.gpio_nwp, 1);

	if (nand_scan(&gpiomtd->mtd_info, 1)) {
		ret = -ENXIO;
		goto err_wp;
	}

	if (gpiomtd->plat.adjust_parts)
		gpiomtd->plat.adjust_parts(&gpiomtd->plat,
					   gpiomtd->mtd_info.size);

	ppdata.of_node = dev->dev.of_node;
	ret = mtd_device_parse_register(&gpiomtd->mtd_info, NULL, &ppdata,
					gpiomtd->plat.parts,
					gpiomtd->plat.num_parts);
	if (!ret)
		return 0;

err_wp:
	if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
		gpio_set_value(gpiomtd->plat.gpio_nwp, 0);

	return ret;
}

static struct platform_driver gpio_nand_driver = {
	.probe		= gpio_nand_probe,
	.remove		= gpio_nand_remove,
	.driver		= {
		.name	= "gpio-nand",
		.of_match_table = of_match_ptr(gpio_nand_id_table),
	},
};

module_platform_driver(gpio_nand_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
MODULE_DESCRIPTION("GPIO NAND Driver");
Commit	Line	Data
aaf7ea20 MR	1	/*
	2	* drivers/mtd/nand/gpio.c
	3	*
	4	* Updated, and converted to generic GPIO based driver by Russell King.
	5	*
	6	* Written by Ben Dooks <ben@simtec.co.uk>
	7	* Based on 2.4 version by Mark Whittaker
	8	*
	9	* © 2004 Simtec Electronics
	10	*
	11	* Device driver for NAND connected via GPIO
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License version 2 as
	15	* published by the Free Software Foundation.
	16	*
	17	*/
	18
	19	#include <linux/kernel.h>
283df420	20	#include <linux/err.h>
aaf7ea20 MR	21	#include <linux/init.h>
	22	#include <linux/slab.h>
	23	#include <linux/module.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/gpio.h>
	26	#include <linux/io.h>
	27	#include <linux/mtd/mtd.h>
	28	#include <linux/mtd/nand.h>
	29	#include <linux/mtd/partitions.h>
	30	#include <linux/mtd/nand-gpio.h>
775c3220 JI	31	#include <linux/of.h>
	32	#include <linux/of_address.h>
	33	#include <linux/of_gpio.h>
aaf7ea20 MR	34
	35	struct gpiomtd {
	36	void __iomem *io_sync;
	37	struct mtd_info mtd_info;
	38	struct nand_chip nand_chip;
	39	struct gpio_nand_platdata plat;
	40	};
	41
	42	#define gpio_nand_getpriv(x) container_of(x, struct gpiomtd, mtd_info)
	43
	44
	45	#ifdef CONFIG_ARM
	46	/* gpio_nand_dosync()
	47	*
	48	* Make sure the GPIO state changes occur in-order with writes to NAND
	49	* memory region.
	50	* Needed on PXA due to bus-reordering within the SoC itself (see section on
	51	* I/O ordering in PXA manual (section 2.3, p35)
	52	*/
	53	static void gpio_nand_dosync(struct gpiomtd *gpiomtd)
	54	{
	55	unsigned long tmp;
	56
	57	if (gpiomtd->io_sync) {
	58	/*
	59	* Linux memory barriers don't cater for what's required here.
	60	* What's required is what's here - a read from a separate
	61	* region with a dependency on that read.
	62	*/
	63	tmp = readl(gpiomtd->io_sync);
	64	asm volatile("mov %1, %0\n" : "=r" (tmp) : "r" (tmp));
	65	}
	66	}
	67	#else
	68	static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {}
	69	#endif
	70
	71	static void gpio_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
	72	{
	73	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
	74
	75	gpio_nand_dosync(gpiomtd);
	76
	77	if (ctrl & NAND_CTRL_CHANGE) {
	78	gpio_set_value(gpiomtd->plat.gpio_nce, !(ctrl & NAND_NCE));
	79	gpio_set_value(gpiomtd->plat.gpio_cle, !!(ctrl & NAND_CLE));
	80	gpio_set_value(gpiomtd->plat.gpio_ale, !!(ctrl & NAND_ALE));
	81	gpio_nand_dosync(gpiomtd);
	82	}
	83	if (cmd == NAND_CMD_NONE)
	84	return;
	85
	86	writeb(cmd, gpiomtd->nand_chip.IO_ADDR_W);
	87	gpio_nand_dosync(gpiomtd);
	88	}
	89
	90	static void gpio_nand_writebuf(struct mtd_info mtd, const u_char buf, int len)
	91	{
	92	struct nand_chip *this = mtd->priv;
	93
82045362	94	iowrite8_rep(this->IO_ADDR_W, buf, len);
aaf7ea20 MR	95	}
	96
	97	static void gpio_nand_readbuf(struct mtd_info mtd, u_char buf, int len)
	98	{
	99	struct nand_chip *this = mtd->priv;
	100
82045362	101	ioread8_rep(this->IO_ADDR_R, buf, len);
aaf7ea20 MR	102	}
aaf7ea20 MR	103
aaf7ea20 MR	104	static void gpio_nand_writebuf16(struct mtd_info mtd, const u_char buf,
	105	int len)
	106	{
	107	struct nand_chip *this = mtd->priv;
	108
	109	if (IS_ALIGNED((unsigned long)buf, 2)) {
82045362	110	iowrite16_rep(this->IO_ADDR_W, buf, len>>1);
aaf7ea20 MR	111	} else {
	112	int i;
	113	unsigned short ptr = (unsigned short )buf;
	114
	115	for (i = 0; i < len; i += 2, ptr++)
	116	writew(*ptr, this->IO_ADDR_W);
	117	}
	118	}
	119
	120	static void gpio_nand_readbuf16(struct mtd_info mtd, u_char buf, int len)
	121	{
	122	struct nand_chip *this = mtd->priv;
	123
	124	if (IS_ALIGNED((unsigned long)buf, 2)) {
82045362	125	ioread16_rep(this->IO_ADDR_R, buf, len>>1);
aaf7ea20 MR	126	} else {
	127	int i;
	128	unsigned short ptr = (unsigned short )buf;
	129
	130	for (i = 0; i < len; i += 2, ptr++)
	131	*ptr = readw(this->IO_ADDR_R);
	132	}
	133	}
	134
aaf7ea20 MR	135	static int gpio_nand_devready(struct mtd_info *mtd)
	136	{
	137	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
18afbc54 AS	138
	139	if (gpio_is_valid(gpiomtd->plat.gpio_rdy))
	140	return gpio_get_value(gpiomtd->plat.gpio_rdy);
	141
	142	return 1;
aaf7ea20 MR	143	}
aaf7ea20 MR	144
775c3220 JI	145	#ifdef CONFIG_OF
	146	static const struct of_device_id gpio_nand_id_table[] = {
	147	{ .compatible = "gpio-control-nand" },
	148	{}
	149	};
	150	MODULE_DEVICE_TABLE(of, gpio_nand_id_table);
	151
	152	static int gpio_nand_get_config_of(const struct device *dev,
	153	struct gpio_nand_platdata *plat)
	154	{
	155	u32 val;
	156
	157	if (!of_property_read_u32(dev->of_node, "bank-width", &val)) {
	158	if (val == 2) {
	159	plat->options \|= NAND_BUSWIDTH_16;
	160	} else if (val != 1) {
	161	dev_err(dev, "invalid bank-width %u\n", val);
	162	return -EINVAL;
	163	}
	164	}
	165
	166	plat->gpio_rdy = of_get_gpio(dev->of_node, 0);
	167	plat->gpio_nce = of_get_gpio(dev->of_node, 1);
	168	plat->gpio_ale = of_get_gpio(dev->of_node, 2);
	169	plat->gpio_cle = of_get_gpio(dev->of_node, 3);
	170	plat->gpio_nwp = of_get_gpio(dev->of_node, 4);
	171
	172	if (!of_property_read_u32(dev->of_node, "chip-delay", &val))
	173	plat->chip_delay = val;
	174
	175	return 0;
	176	}
	177
	178	static struct resource gpio_nand_get_io_sync_of(struct platform_device pdev)
	179	{
	180	struct resource r = devm_kzalloc(&pdev->dev, sizeof(r), GFP_KERNEL);
	181	u64 addr;
	182
	183	if (!r \|\| of_property_read_u64(pdev->dev.of_node,
	184	"gpio-control-nand,io-sync-reg", &addr))
	185	return NULL;
	186
	187	r->start = addr;
	188	r->end = r->start + 0x3;
	189	r->flags = IORESOURCE_MEM;
	190
	191	return r;
	192	}
	193	#else /* CONFIG_OF */
775c3220 JI	194	static inline int gpio_nand_get_config_of(const struct device *dev,
	195	struct gpio_nand_platdata *plat)
	196	{
	197	return -ENOSYS;
	198	}
	199
	200	static inline struct resource *
	201	gpio_nand_get_io_sync_of(struct platform_device *pdev)
	202	{
	203	return NULL;
	204	}
	205	#endif /* CONFIG_OF */
	206
	207	static inline int gpio_nand_get_config(const struct device *dev,
	208	struct gpio_nand_platdata *plat)
	209	{
	210	int ret = gpio_nand_get_config_of(dev, plat);
	211
	212	if (!ret)
	213	return ret;
	214
	215	if (dev->platform_data) {
	216	memcpy(plat, dev->platform_data, sizeof(*plat));
	217	return 0;
	218	}
	219
	220	return -EINVAL;
	221	}
	222
	223	static inline struct resource *
	224	gpio_nand_get_io_sync(struct platform_device *pdev)
	225	{
	226	struct resource *r = gpio_nand_get_io_sync_of(pdev);
	227
	228	if (r)
	229	return r;
	230
	231	return platform_get_resource(pdev, IORESOURCE_MEM, 1);
	232	}
	233
810b7e06	234	static int gpio_nand_remove(struct platform_device *dev)
aaf7ea20 MR	235	{
aaf7ea20 MR	236	struct gpiomtd *gpiomtd = platform_get_drvdata(dev);
aaf7ea20 MR	237
	238	nand_release(&gpiomtd->mtd_info);
	239
aaf7ea20 MR	240	if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
	241	gpio_set_value(gpiomtd->plat.gpio_nwp, 0);
	242	gpio_set_value(gpiomtd->plat.gpio_nce, 1);
	243
aaf7ea20 MR	244	return 0;
	245	}
	246
06f25510	247	static int gpio_nand_probe(struct platform_device *dev)
aaf7ea20 MR	248	{
	249	struct gpiomtd *gpiomtd;
	250	struct nand_chip *this;
283df420	251	struct resource *res;
775c3220 JI	252	struct mtd_part_parser_data ppdata = {};
775c3220 JI	253	int ret = 0;
aaf7ea20	254
775c3220	255	if (!dev->dev.of_node && !dev->dev.platform_data)
aaf7ea20 MR	256	return -EINVAL;
aaf7ea20 MR	257
b60c7243	258	gpiomtd = devm_kzalloc(&dev->dev, sizeof(*gpiomtd), GFP_KERNEL);
283df420	259	if (!gpiomtd) {
aaf7ea20 MR	260	dev_err(&dev->dev, "failed to create NAND MTD\n");
	261	return -ENOMEM;
	262	}
	263
	264	this = &gpiomtd->nand_chip;
aaf7ea20	265
283df420 AS	266	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	267	this->IO_ADDR_R = devm_ioremap_resource(&dev->dev, res);
	268	if (IS_ERR(this->IO_ADDR_R))
	269	return PTR_ERR(this->IO_ADDR_R);
	270
	271	res = gpio_nand_get_io_sync(dev);
	272	if (res) {
	273	gpiomtd->io_sync = devm_ioremap_resource(&dev->dev, res);
	274	if (IS_ERR(gpiomtd->io_sync))
	275	return PTR_ERR(gpiomtd->io_sync);
aaf7ea20 MR	276	}
aaf7ea20 MR	277
775c3220 JI	278	ret = gpio_nand_get_config(&dev->dev, &gpiomtd->plat);
775c3220 JI	279	if (ret)
283df420	280	return ret;
aaf7ea20	281
283df420	282	ret = devm_gpio_request(&dev->dev, gpiomtd->plat.gpio_nce, "NAND NCE");
aaf7ea20	283	if (ret)
283df420	284	return ret;
aaf7ea20	285	gpio_direction_output(gpiomtd->plat.gpio_nce, 1);
283df420	286
aaf7ea20	287	if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) {
283df420 AS	288	ret = devm_gpio_request(&dev->dev, gpiomtd->plat.gpio_nwp,
283df420 AS	289	"NAND NWP");
aaf7ea20	290	if (ret)
283df420	291	return ret;
aaf7ea20	292	}
283df420 AS	293
283df420 AS	294	ret = devm_gpio_request(&dev->dev, gpiomtd->plat.gpio_ale, "NAND ALE");
aaf7ea20	295	if (ret)
283df420	296	return ret;
aaf7ea20	297	gpio_direction_output(gpiomtd->plat.gpio_ale, 0);
283df420 AS	298
283df420 AS	299	ret = devm_gpio_request(&dev->dev, gpiomtd->plat.gpio_cle, "NAND CLE");
aaf7ea20	300	if (ret)
283df420	301	return ret;
aaf7ea20	302	gpio_direction_output(gpiomtd->plat.gpio_cle, 0);
283df420	303
18afbc54	304	if (gpio_is_valid(gpiomtd->plat.gpio_rdy)) {
283df420 AS	305	ret = devm_gpio_request(&dev->dev, gpiomtd->plat.gpio_rdy,
283df420 AS	306	"NAND RDY");
18afbc54	307	if (ret)
283df420	308	return ret;
18afbc54 AS	309	gpio_direction_input(gpiomtd->plat.gpio_rdy);
18afbc54 AS	310	}
aaf7ea20	311
aaf7ea20 MR	312	this->IO_ADDR_W = this->IO_ADDR_R;
	313	this->ecc.mode = NAND_ECC_SOFT;
	314	this->options = gpiomtd->plat.options;
	315	this->chip_delay = gpiomtd->plat.chip_delay;
	316
	317	/* install our routines */
	318	this->cmd_ctrl = gpio_nand_cmd_ctrl;
	319	this->dev_ready = gpio_nand_devready;
	320
	321	if (this->options & NAND_BUSWIDTH_16) {
	322	this->read_buf = gpio_nand_readbuf16;
	323	this->write_buf = gpio_nand_writebuf16;
aaf7ea20 MR	324	} else {
	325	this->read_buf = gpio_nand_readbuf;
	326	this->write_buf = gpio_nand_writebuf;
aaf7ea20 MR	327	}
	328
	329	/* set the mtd private data for the nand driver */
	330	gpiomtd->mtd_info.priv = this;
	331	gpiomtd->mtd_info.owner = THIS_MODULE;
	332
283df420 AS	333	platform_set_drvdata(dev, gpiomtd);
	334
	335	if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
	336	gpio_direction_output(gpiomtd->plat.gpio_nwp, 1);
	337
aaf7ea20	338	if (nand_scan(&gpiomtd->mtd_info, 1)) {
aaf7ea20 MR	339	ret = -ENXIO;
	340	goto err_wp;
	341	}
	342
	343	if (gpiomtd->plat.adjust_parts)
	344	gpiomtd->plat.adjust_parts(&gpiomtd->plat,
	345	gpiomtd->mtd_info.size);
	346
775c3220 JI	347	ppdata.of_node = dev->dev.of_node;
	348	ret = mtd_device_parse_register(&gpiomtd->mtd_info, NULL, &ppdata,
	349	gpiomtd->plat.parts,
	350	gpiomtd->plat.num_parts);
283df420 AS	351	if (!ret)
283df420 AS	352	return 0;
aaf7ea20 MR	353
	354	err_wp:
	355	if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
	356	gpio_set_value(gpiomtd->plat.gpio_nwp, 0);
283df420	357
aaf7ea20 MR	358	return ret;
	359	}
	360
	361	static struct platform_driver gpio_nand_driver = {
	362	.probe = gpio_nand_probe,
	363	.remove = gpio_nand_remove,
	364	.driver = {
	365	.name = "gpio-nand",
b57d43ff	366	.of_match_table = of_match_ptr(gpio_nand_id_table),
aaf7ea20 MR	367	},
	368	};
	369
2fe87aef	370	module_platform_driver(gpio_nand_driver);
aaf7ea20 MR	371
	372	MODULE_LICENSE("GPL");
	373	MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
	374	MODULE_DESCRIPTION("GPIO NAND Driver");